Quartus II Settings File Reference Manual - Altera

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semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 

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described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying 

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ISO 

9001:2008 

Registered 

June 2012 Altera Corporation Quartus Settings File 

Reference Manual

Contents 

Chapter 1. Project-Wide Assignments 

AGGREGATE_REVISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 

AHDL_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 

AHDL_TEXT_DESIGN_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 

ASM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 

AUTO_EXPORT_VER_COMPATIBLE_DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5 

BASE_REVISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 

BASE_REVISION_PROJECT_OUTPUT_DIRECTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7 

BDF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 

BINARY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 

BSF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10 

CDF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11 

COMMAND_MACRO_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12 

CPP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13 

CPP_INCLUDE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14 

CUSP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15 

CVP_REVISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16 

C_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 

DEPENDENCY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18 

DSPBUILDER_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19 

EDIF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–20 

ELF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21 

ENABLE_COMPACT_REPORT_TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–22 

ENABLE_REDUCED_MEMORY_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–23 

EQUATION_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–24 

FLOW_DISABLE_ASSEMBLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–25 

FLOW_ENABLE_HC_COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–26 

FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27 

FLOW_ENABLE_PARALLEL_MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–28 

FLOW_ENABLE_POWER_ANALYZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–29 

FLOW_ENABLE_RTL_VIEWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–30 

FLOW_HARDCOPY_DESIGN_READINESS_CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–31 

GDF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–32 

HC_OUTPUT_DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–33 

HEX_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–34 

HEX_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–35 

HTML_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–36 

HTML_REPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–37 

INCLUDE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–38 

IPA_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–39 

IP_TOOL_ENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–40 

IP_TOOL_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–41 

IP_TOOL_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–42 

ISC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–43 

JAM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–44 

JBC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–45 

LICENSE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–46 

LMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–47 

LOGIC_ANALYZER_INTERFACE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–48 



ii Contents 

MAP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–49 

MASK_REVISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–50 

MESSAGE_DISABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–51 

MESSAGE_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–52 

MESSAGE_SUPPRESSION_RULE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–53 

MIF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–54 

MIGRATION_DIFFERENT_SOURCE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–55 

MISC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–56 

NUM_PARALLEL_PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–57 

OBJECT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–59 

OCP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–60 

PARTIAL_SRAM_OBJECT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–61 

PERSONA_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–62 

PIN_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–63 

POWER_INPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–64 

PPF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–65 

PROGRAMMER_OBJECT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–66 

PROJECT_OUTPUT_DIRECTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–67 

PROJECT_SHOW_ENTITY_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–68 

PROJECT_USE_SIMPLIFIED_NAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–69 

QARLOG_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–70 

QAR_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–71 

QIP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–72 

QSYS_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–73 

QUARTUS_PTF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–74 

QUARTUS_SBD_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–75 

QUARTUS_STANDARD_DELAY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–76 

QVAR_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–77 

QXP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–78 

RAW_BINARY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–79 

READ_OR_WRITE_IN_BYTE_ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–80 

RECONFIGURABLE_REVISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–81 

REVISION_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–82 

RUN_FULL_COMPILE_ON_DEVICE_CHANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–83 

SAVE_MIGRATION_INFO_DURING_COMPILATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–84 

SBI_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–85 

SDC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–86 

SDF_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–87 

SERIAL_BITSTREAM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–88 

SIGNALTAP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–89 

SIP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–90 

SMART_RECOMPILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–91 

SMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–92 

SOFTWARE_LIBRARY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–93 

SOPC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–94 

SOURCE_TCL_SCRIPT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–95 

SPD_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–96 

SRAM_OBJECT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–97 

SRECORDS_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–98 

SVF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–99 

SYM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–100 

SYNTHESIS_ONLY_QIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–101 

SYSTEMVERILOG_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–102 

TCL_SCRIPT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–103 

Quartus Settings File June 2012 Altera Corporation 


Contents iii 

TEMPLATE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–104 

TEXT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–105 

TEXT_FORMAT_REPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–106 

TIMING_ANALYSIS_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–107 

VCD_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–108 

VECTOR_TABLE_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–109 

VECTOR_TEXT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–110 

VECTOR_WAVEFORM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–111 

VERILOG_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–112 

VERILOG_INCLUDE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–113 

VERILOG_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–114 

VERILOG_TEST_BENCH_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–115 

VER_COMPATIBLE_DB_DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–116 

VHDL_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–117 

VHDL_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–118 

VHDL_TEST_BENCH_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–119 

VQM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–120 

ZIP_VECTOR_WAVEFORM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–121 

Chapter 2. Pin & Locations Assignments 

FAST_INPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 

FAST_OCT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 

FAST_OUTPUT_ENABLE_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 

FAST_OUTPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 

IP_DEBUG_VISIBLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8 

LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 

LOCATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10 

MAX7K_CLIQUE_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11 

MEMBER_OF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12 

PIN_CONNECT_FROM_NODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 

RESERVE_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 

SUBCLIQUE_OF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 

VIRTUAL_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 

Chapter 3. Assignment Group Assignments 

ASSIGNMENT_GROUP_EXCEPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 

ASSIGNMENT_GROUP_MEMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 

Chapter 4. Analysis & Synthesis Assignments 

ADV_NETLIST_OPT_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 

ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 

ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 

ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 

ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 

ALLOW_CHILD_PARTITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11 

ALLOW_POWER_UP_DONT_CARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12 

ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13 

ALLOW_SYNCH_CTRL_USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15 

ALLOW_XOR_GATE_USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17 

AUTO_CARRY_CHAINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18 

AUTO_CLOCK_ENABLE_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20 

AUTO_DSP_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22 

AUTO_ENABLE_SMART_COMPILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24 



iv Contents 

AUTO_GLOBAL_CLOCK_MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25 

AUTO_GLOBAL_OE_MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26 

AUTO_LCELL_INSERTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27 

AUTO_OPEN_DRAIN_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28 

AUTO_PARALLEL_EXPANDERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30 

AUTO_RAM_BLOCK_BALANCING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31 

AUTO_RAM_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33 

AUTO_RAM_TO_LCELL_CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–35 

AUTO_RESOURCE_SHARING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–37 

AUTO_ROM_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–38 

AUTO_SHIFT_REGISTER_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–40 

BLOCK_DESIGN_NAMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–42 

CLKLOCKX1_INPUT_FREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–44 

CYCLONEII_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–45 

CYCLONE_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–47 

DEVICE_FILTER_PACKAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–49 

DEVICE_FILTER_PIN_COUNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–50 

DEVICE_FILTER_SPEED_GRADE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–51 

DEVICE_FILTER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–52 

DISABLE_OCP_HW_EVAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53 

DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–54 

DONT_MERGE_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–55 

DQS_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–56 

DQS_FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–57 

DQS_SHIFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–58 

DQS_SYSTEM_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–59 

DSE_SYNTH_EXTRA_EFFORT_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–60 

DSP_BLOCK_BALANCING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–61 

EDA_DESIGN_ENTRY_SYNTHESIS_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–63 

EDA_INPUT_DATA_FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–64 

EDA_INPUT_GND_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–65 

EDA_INPUT_VCC_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–66 

EDA_LMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–67 

EDA_RUN_TOOL_AUTOMATICALLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–68 

EDA_SHOW_LMF_MAPPING_MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–69 

EDA_VHDL_LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–70 

ENABLE_IP_DEBUG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–71 

ENABLE_M512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–72 

EXTRACT_VERILOG_STATE_MACHINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–73 

EXTRACT_VHDL_STATE_MACHINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–74 

FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–75 

FORCE_SYNCH_CLEAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–76 

HDL_INITIAL_FANOUT_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–78 

HDL_MESSAGE_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–79 

HDL_MESSAGE_OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–80 

HDL_MESSAGE_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–81 

HPS_PARTITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–82 

IGNORE_CARRY_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–83 

IGNORE_CASCADE_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–84 

IGNORE_GLOBAL_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–85 

IGNORE_LCELL_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–86 

IGNORE_MAX_FANOUT_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–88 

IGNORE_ROW_GLOBAL_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–90 

IGNORE_SOFT_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–91 



Contents v 

IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–93 

IGNORE_VERILOG_INITIAL_CONSTRUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–94 

IMPLEMENT_AS_CLOCK_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–95 

IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–97 

INFER_RAMS_FROM_RAW_LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–98 

LCELL_INSERTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–99 

LIMIT_AHDL_INTEGERS_TO_32_BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–100 

MAX7000_FANIN_PER_CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–101 

MAX7000_IGNORE_LCELL_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–103 

MAX7000_IGNORE_SOFT_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–105 

MAX7000_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–106 

MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–108 

MAXII_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–109 

MAX_AUTO_GLOBAL_REGISTER_CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–111 

MAX_BALANCING_DSP_BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–113 

MAX_FANOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–115 

MAX_LABS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–117 

MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–118 

MAX_RAM_BLOCKS_M4K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–119 

MAX_RAM_BLOCKS_M512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–121 

MAX_RAM_BLOCKS_MRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–123 

MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED 

_THROUGH_MODE_SETTING_DONT_CARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–125 

MUX_RESTRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–127 

NOT_GATE_PUSH_BACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–129 

NUMBER_OF_INVERTED_REGISTERS_REPORTED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–130 

NUMBER_OF_REMOVED_REGISTERS_REPORTED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–131 

NUMBER_OF_SWEPT_NODES_REPORTED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–132 

OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–133 

OPTIMIZE_POWER_DURING_SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–135 

PARALLEL_SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–137 

PARAMETER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–138 

POWER_UP_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–139 

PRESERVE_FANOUT_FREE_NODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–141 

PRESERVE_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–142 

PRE_MAPPING_RESYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–143 

RBCGEN_CRITICAL_WARNING_TO_ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–144 

REMOVE_DUPLICATE_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–145 

REMOVE_REDUNDANT_LOGIC_CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–146 

REPORT_CONNECTIVITY_CHECKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–148 

REPORT_PARAMETER_SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–149 

REPORT_SOURCE_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–150 

RESYNTHESIS_PHYSICAL_SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–151 

RESYNTHESIS_RETIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–152 

SAFE_STATE_MACHINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–153 

SAVE_DISK_SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–154 

SEARCH_PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–155 

SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–156 

SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES . . . . . . . . . . . . . . . . . . . . . . . 4–157 

STATE_MACHINE_PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–158 

STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_ 

DETECT_SIGNAL_THRESHOLD_SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–160 

STRATIXII_CARRY_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–161 

STRATIXII_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–163 



vi Contents 

STRATIX_CARRY_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–165 

STRATIX_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–166 

STRICT_RAM_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–168 

SYNCHRONIZATION_REGISTER_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–170 

SYNTHESIS_EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–172 

SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER . . . . . . . . . . . . . . . . 4–173 

SYNTHESIS_SEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–174 

SYNTH_CLOCK_MUX_PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–175 

SYNTH_CRITICAL_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–177 

SYNTH_GATED_CLOCK_CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–179 

SYNTH_MESSAGE_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–181 

SYNTH_PROTECT_SDC_CONSTRAINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–182 

SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–184 

SYNTH_TIMING_DRIVEN_SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–186 

TOP_LEVEL_ENTITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–188 

TRUE_WYSIWYG_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–189 

USER_LIBRARIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–190 

USE_HIGH_SPEED_ADDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–191 

USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–192 

VERILOG_CONSTANT_LOOP_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–193 

VERILOG_INPUT_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–194 

VERILOG_LMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–195 

VERILOG_MACRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–196 

VERILOG_NON_CONSTANT_LOOP_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–197 

VERILOG_SHOW_LMF_MAPPING_MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–198 

VHDL_INPUT_LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–199 

VHDL_INPUT_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–200 

VHDL_LMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–201 

VHDL_SHOW_LMF_MAPPING_MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–202 

Chapter 5. Incremental Compilation Assignments 

ALLOW_MULTIPLE_PERSONAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 

AUTO_EXPORT_INCREMENTAL_COMPILATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 

IGNORE_PARTITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 

INCREMENTAL_COMPILATION_EXPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4 

INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5 

INCREMENTAL_COMPILATION_EXPORT_POST_FIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6 

INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7 

INCREMENTAL_COMPILATION_EXPORT_ROUTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8 

INPUT_PERSONA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9 

PARTITION_ALWAYS_USE_QXP_NETLIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 

PARTITION_FITTER_PRESERVATION_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11 

PARTITION_HIERARCHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12 

PARTITION_IGNORE_SOURCE_FILE_CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13 

PARTITION_IMPORT_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14 

PARTITION_IMPORT_EXISTING_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15 

PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16 

PARTITION_IMPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17 

PARTITION_IMPORT_PROMOTE_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18 

PARTITION_LAST_IMPORTED_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19 

PARTITION_NETLIST_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20 

PARTITION_PRESERVE_HIGH_SPEED_TILES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21 



Contents vii 

Chapter 6. Fitter Assignments 

ACTIVE_SERIAL_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1 

ADCE_ENABLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3 

ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER . . . . . . . . . . . . . . 6–4 

ALWAYS_ENABLE_INPUT_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5 

ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6 

ASYNC_PIPELINE_REG_REACH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7 

AUTO_C3_M9K_BIT_SKIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 

AUTO_DELAY_CHAINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9 

AUTO_GLOBAL_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11 

AUTO_GLOBAL_MEMORY_CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13 

AUTO_GLOBAL_REGISTER_CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14 

AUTO_MERGE_PLLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16 

AUTO_PACKED_REGISTERS_CYCLONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18 

AUTO_PACKED_REGISTERS_MAXII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20 

AUTO_PACKED_REGISTERS_STRATIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22 

AUTO_PACKED_REGISTERS_STRATIXII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24 

AUTO_TURBO_BIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26 

BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27 

BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES . . . . . . . . . . . . . . . . 6–28 

BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS . . . . . . . . . . . . . . . . . . . . 6–30 

BLOCK_RAM_TO_MLAB_CELL_CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–32 

C3_M9K_BIT_SKIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–33 

CDR_BANDWIDTH_PRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–34 

CKN_CK_PAIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–35 

CLAMPING_DIODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–36 

CLOCK_TO_OUTPUT_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37 

CONFIGURATION_VCCIO_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–38 

CRC_ERROR_CHECKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–40 

CRC_ERROR_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–42 

CURRENT_STRENGTH_NEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–43 

CVP_CONFDONE_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–45 

CVP_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–46 

CYCLONEIII_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–47 

CYCLONEII_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–48 

CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–49 

CYCLONEII_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–50 

CYCLONE_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–51 

D1_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–52 

D1_FINE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–53 

D2_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–54 

D3_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–55 

D4_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–56 

D4_FINE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–57 

D5_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–58 

D5_FINE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–59 

D5_OCT_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–60 

D5_OE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–61 

D6_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–62 

D6_FINE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–63 

D6_OCT_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–64 

D6_OE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–65 

D6_OE_FINE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–66 

DATA0_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–67 



viii Contents 

DCLK_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–68 

DC_CURRENT_FOR_ELECTROMIGRATION_CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–69 

DDIO_INPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–70 

DDIO_OUTPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–71 

DDIO_OUTPUT_REGISTER_DISTANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–72 

DECREASE_INPUT_DELAY_TO_INPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–73 

DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–74 

DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–75 

DEVICE_MIGRATION_LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–76 

DEVICE_TECHNOLOGY_MIGRATION_LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–77 

DPRIO_CHANNEL_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–78 

DPRIO_CRUCLK_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–79 

DPRIO_INTERFACE_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–80 

DPRIO_QUAD_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–81 

DPRIO_QUAD_PLL_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–82 

DPRIO_TX_PLL0_REFCLK_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–83 

DPRIO_TX_PLL1_REFCLK_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–84 

DPRIO_TX_PLL_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–85 

DQSB_DQS_PAIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–86 

DQSOUT_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–87 

DQS_ENABLE_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–88 

DQS_LOCAL_CLOCK_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–89 

DQ_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–90 

DQ_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–91 

DUAL_PURPOSE_CLOCK_PIN_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–92 

DUPLICATE_ATOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–93 

DYNAMIC_OCT_CONTROL_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–95 

ECO_ALLOW_ROUTING_CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–96 

ECO_OPTIMIZE_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–97 

ECO_REGENERATE_REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–98 

ENABLE_ASMI_FOR_FLASH_LOADER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–99 

ENABLE_BENEFICIAL_SKEW_OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–100 

ENABLE_BUS_HOLD_CIRCUITRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–101 

ENABLE_CRC_ERROR_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–103 

ENABLE_CVP_CONFDONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–104 

ENABLE_DEVICE_WIDE_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–105 

ENABLE_DEVICE_WIDE_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–107 

ENABLE_HOLD_BACK_OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–109 

ENABLE_INIT_DONE_OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–110 

ENABLE_NCEO_OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–112 

ENABLE_PR_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–113 

ENABLE_VREFA_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–114 

ENABLE_VREFB_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–115 

ERROR_CHECK_FREQUENCY_DIVISOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–116 

EXCLUSIVE_IO_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–118 

EXTERNAL_LVDS_RX_USES_DPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–119 

FINAL_PLACEMENT_OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–120 

FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–122 

FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–123 

FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–125 

FITTER_EARLY_TIMING_ESTIMATE_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–127 

FITTER_EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–129 

FIT_ATTEMPTS_TO_SKIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–130 

FIT_ONLY_ONE_ATTEMPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–132 



Contents ix 

FLEX10K_MAX_PERIPHERAL_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–133 

FORCE_CONFIGURATION_VCCIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–134 

FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS . . . . . . . . . . . . . . . . . . . . . 6–136 

FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–137 

FORCE_MERGE_PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–138 

FORCE_MERGE_PLL_FANOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–139 

FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–140 

GENERATE_GXB_RECONFIG_MIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–141 

GENERATE_GXB_RECONFIG_MIF_WITH_PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–142 

GLOBAL_SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–143 

GLOBAL_SIGNAL_CLKCTRL_LOCATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–145 

GNDIO_CURRENT_1PT8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–146 

GNDIO_CURRENT_2PT5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–147 

GNDIO_CURRENT_GTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–148 

GNDIO_CURRENT_GTL_PLUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–149 

GNDIO_CURRENT_LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–150 

GNDIO_CURRENT_LVTTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–151 

GNDIO_CURRENT_PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–152 

GNDIO_CURRENT_SSTL2_CLASS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–153 




GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–157 

GXB_0PPM_CLOCK_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–158 

GXB_0PPM_CLOCK_GROUP_DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–159 

GXB_0PPM_CORECLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–160 

GXB_0PPM_CORE_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–161 

GXB_CLOCK_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–162 

GXB_CLOCK_GROUP_DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–163 

GXB_RECONFIG_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–164 

GXB_RECONFIG_MIF_PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–165 

GXB_REFCLK_COUPLING_TERMINATION_SETTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–166 

HPS_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–167 

IGNORE_MODE_FOR_MERGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–168 

IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–169 

INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–170 

INCREASE_DELAY_TO_OUTPUT_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–171 

INCREASE_INPUT_CLOCK_ENABLE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–172 

INCREASE_OUTPUT_CLOCK_ENABLE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–173 

INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–174 

INCREASE_TZX_DELAY_TO_OUTPUT_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–175 

INC_PLC_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–176 

INIT_DONE_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–177 

INPUT_REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–178 

INPUT_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–179 

INSERT_ADDITIONAL_LOGIC_CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–180 

INTERNAL_SCRUBBING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–181 

IO_MAXIMUM_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–182 

IO_PLACEMENT_OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–184 

IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–186 

LVDS_DIRECT_LOOPBACK_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–188 

LVDS_RX_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–189 

M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–190 

MATCH_PLL_COMPENSATION_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–191 



x Contents 

MAX7000B_VCCIO_IOBANK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–192 

MAX7000B_VCCIO_IOBANK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–193 

MAX7000_DEVICE_IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–194 

MAX7000_ENABLE_JTAG_BST_SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–195 

MAX7000_INDIVIDUAL_TURBO_BIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–196 

MAX_CLOCKS_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–197 

MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–198 

MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION . . . . . . . . . . . . . . . . . . . . . . . 6–199 

MAX_CURRENT_FOR_ELECTROMIGRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–200 

MAX_CURRENT_FOR_VIO_ELECTROMIGRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–201 

MAX_GLOBAL_CLOCKS_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–202 

MAX_PERIPHERY_CLOCKS_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–203 

MAX_REGIONAL_CLOCKS_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–204 

MEMORY_INTERFACE_DATA_PIN_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–205 

MEM_INTERFACE_DELAY_CHAIN_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–206 

MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR . . . . . . . . . . . . . . . . . . . . . . . . . 6–207 

MIGRATION_CONSTRAIN_CORE_RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–208 

MIGRATION_DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–209 

NCEO_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–210 

NDQS_LOCAL_CLOCK_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–211 

OPTIMIZE_FOR_METASTABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–212 

OPTIMIZE_HOLD_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–213 

OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–215 

OPTIMIZE_MULTI_CORNER_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–216 

OPTIMIZE_POWER_DURING_FITTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–218 

OPTIMIZE_SSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–220 

OPTIMIZE_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–222 

OUTPUT_BUFFER_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–224 

OUTPUT_BUFFER_DELAY_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–225 

OUTPUT_ENABLE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–227 

OUTPUT_ENABLE_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–228 

OUTPUT_PIN_LOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–230 

OUTPUT_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–231 

OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–232 

PAD_TO_CORE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–233 

PAD_TO_DDIO_REGISTER_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–234 

PAD_TO_INPUT_REGISTER_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–235 

PCI_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–236 

PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING . . . . . . . . . . . . . . . . . . . . . . . 6–238 

PHYSICAL_SYNTHESIS_COMBO_LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–240 

PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–242 

PHYSICAL_SYNTHESIS_EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–244 

PHYSICAL_SYNTHESIS_LOG_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–246 

PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA . . . . . . . . . . . . . . . . . . . . . . . . 6–247 

PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–248 

PHYSICAL_SYNTHESIS_REGISTER_RETIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–250 

PLACEMENT_EFFORT_MULTIPLIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–252 

PLL_AUTO_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–254 

PLL_BANDWIDTH_PRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–255 

PLL_CHANNEL_SPACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–256 

PLL_COMPENSATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–257 

PLL_COMPENSATION_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–259 

PLL_ENFORCE_USER_PHASE_SHIFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–261 

PLL_FEEDBACK_CLOCK_SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–262 



Contents xi 

PLL_FORCE_OUTPUT_COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–263 

PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–265 

PLL_IGNORE_MIGRATION_DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–266 

PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–267 

PLL_OUTPUT_CLOCK_FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–268 

PLL_PFD_CLOCK_FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–269 

PLL_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–270 

PLL_VCO_CLOCK_FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–271 

PRESERVE_PLL_COUNTER_ORDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–272 

PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_ 

FRACTION_OF_USED_LAB_TILES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–273 

PROGRAMMABLE_POWER_TECHNOLOGY_SETTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–274 

PROGRAMMABLE_PREEMPHASIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–275 

PROGRAMMABLE_VOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–277 

PR_DONE_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–279 

PR_ERROR_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–280 

PR_READY_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–281 

QDR_D_PIN_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–282 

RESERVE_ALL_UNUSED_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–283 

RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–284 

RESERVE_ASDO_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–285 

RESERVE_DATA0_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–286 

RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . 6–288 

RESERVE_DATA1_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–289 

RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . 6–290 

RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 6–291 



RESERVE_DCLK_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–295 

RESERVE_FLASH_NCE_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–296 

RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–297 

RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–298 

RESERVE_RDYNBUSY_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–299 

ROUTER_CLOCKING_TOPOLOGY_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–300 

ROUTER_EFFORT_MULTIPLIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–301 

ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–303 

ROUTER_REGISTER_DUPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–305 

ROUTER_TIMING_OPTIMIZATION_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–307 

ROUTING_BACK_ANNOTATION_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–309 

SCE_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–310 

SDO_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–311 

SEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–312 

SLEW_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–313 

SLOW_SLEW_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–315 

STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET . . . . . . . . . . . . . . . . . . . . . . . . 6–317 

STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE . . . . . . . . . . . . . . . . . . . . . . . . 6–318 

STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE . . . . . . . . . . . . . . . . . . . . . . . . 6–319 

STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–320 

STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER . . . . . . . . . . 6–321 

STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE . . . . . . . . . 6–322 

STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE . . . . . . . 6–323 

STRATIXGX_ALLOW_POST8B10B_LOOPBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–324 

STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–325 

STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_ 



xii Contents 

SOURCE_IN_DOUBLE_DATA_WIDTH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–326 

STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–327 

STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . 6–328 

STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER . . . . . . . . . 6–329 

STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE . . . . . . . . . 6–330 

STRATIXGX_TERMINATION_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–331 

STRATIXIIGX_TERMINATION_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–332 

STRATIXIII_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–333 

STRATIXIII_MRAM_COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–334 

STRATIXIII_UPDATE_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–335 

STRATIXII_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–336 

STRATIXII_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–337 

STRATIXV_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–338 

STRATIX_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–339 

STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–340 

STRATIX_DEVICE_IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–341 

STRATIX_UPDATE_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–343 

SYNCHRONIZER_IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–344 

SYNCHRONIZER_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–346 

T11_0_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–347 

T11_1_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–348 

T11_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–349 

T11_FINE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–350 

T4_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–351 

T8_DELAY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–352 

T8_DELAY1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–353 

TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–354 

TERMINATION_CONTROL_BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–355 

TREAT_BIDIR_AS_OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–356 

TRI_STATE_SPI_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–358 

TXPMA_SLEW_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–359 

UNUSED_TSD_PINS_GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–360 

USER_START_UP_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–361 

VCCIO_CURRENT_1PT8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–363 

VCCIO_CURRENT_2PT5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–364 

VCCIO_CURRENT_GTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–365 

VCCIO_CURRENT_GTL_PLUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–366 

VCCIO_CURRENT_LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–367 

VCCIO_CURRENT_LVTTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–368 

VCCIO_CURRENT_PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–369 

VCCIO_CURRENT_SSTL2_CLASS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–370 




VCCPD_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–374 

WEAK_PULL_UP_RESISTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–375 

XCVR_ANALOG_SETTINGS_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–377 

XCVR_GT_IO_PIN_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–379 

XCVR_GT_RX_COMMON_MODE_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–380 

XCVR_GT_RX_CTLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–381 

XCVR_GT_RX_DC_GAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–382 

XCVR_GT_TX_COMMON_MODE_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–383 

XCVR_GT_TX_PRE_EMP_1ST_POST_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–384 

XCVR_GT_TX_PRE_EMP_INV_PRE_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–385 



Contents xiii 

XCVR_GT_TX_PRE_EMP_PRE_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–386 

XCVR_GT_TX_VOD_MAIN_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–387 

XCVR_IO_PIN_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–388 

XCVR_REFCLK_PIN_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–389 

XCVR_RX_ACGAIN_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–390 

XCVR_RX_ACGAIN_V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–391 

XCVR_RX_BYPASS_EQ_STAGES_234 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–392 

XCVR_RX_COMMON_MODE_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–393 

XCVR_RX_DC_GAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–394 

XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–395 

XCVR_RX_EQ_BW_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–396 

XCVR_RX_INPUT_VCM_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–397 

XCVR_RX_LINEAR_EQUALIZER_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–398 

XCVR_RX_SD_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–399 

XCVR_RX_SD_OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–400 

XCVR_RX_SD_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–401 

XCVR_RX_SD_THRESHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–402 

XCVR_RX_SEL_HALF_BW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–403 

XCVR_TX_COMMON_MODE_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–404 

XCVR_TX_PLL_RECONFIG_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–405 

XCVR_TX_PRE_EMP_1ST_POST_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–406 

XCVR_TX_PRE_EMP_2ND_POST_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–407 

XCVR_TX_PRE_EMP_2ND_POST_TAP_USER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–408 

XCVR_TX_PRE_EMP_INV_2ND_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–409 

XCVR_TX_PRE_EMP_INV_PRE_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–410 

XCVR_TX_PRE_EMP_PRE_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–411 

XCVR_TX_PRE_EMP_PRE_TAP_USER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–412 

XCVR_TX_RX_DET_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–413 

XCVR_TX_RX_DET_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–414 

XCVR_TX_RX_DET_OUTPUT_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–415 

XCVR_TX_SLEW_RATE_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–416 

XCVR_TX_VCM_CTRL_SRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–417 

XCVR_TX_VOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–418 

XCVR_TX_VOD_PRE_EMP_CTRL_SRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–419 

XCVR_VCCA_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–420 

XCVR_VCCR_VCCT_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–421 

XSTL_INPUT_ALLOW_SE_BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–422 

Chapter 7. Power Estimation Assignments 

POWER_AUTO_COMPUTE_TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 

POWER_BOARD_TEMPERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3 

POWER_BOARD_THERMAL_MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4 

POWER_DEFAULT_INPUT_IO_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5 

POWER_DEFAULT_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7 

POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9 

POWER_HPS_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10 

POWER_HPS_DYNAMIC_POWER_DUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12 

POWER_HPS_DYNAMIC_POWER_SINGLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14 

POWER_HPS_JUNCTION_TEMPERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16 

POWER_HPS_PROC_FREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–18 

POWER_HPS_STATIC_POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20 

POWER_HPS_TOTAL_POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–22 

POWER_HSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–24 

POWER_HSSI_LEFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–25 



xiv Contents 

POWER_HSSI_RIGHT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–26 

POWER_HSSI_VCCHIP_LEFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–27 

POWER_HSSI_VCCHIP_RIGHT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–28 

POWER_INPUT_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–29 

POWER_INPUT_FILE_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–31 

POWER_INPUT_SAF_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–33 

POWER_INPUT_VCD_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–34 

POWER_OCS_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–35 

POWER_OJB_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–36 

POWER_OJC_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–37 

POWER_OSA_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–38 

POWER_OUTPUT_SAF_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–39 

POWER_PRESET_COOLING_SOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–41 

POWER_READ_INPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–42 

POWER_REPORT_POWER_DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–44 

POWER_REPORT_SIGNAL_ACTIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–46 

POWER_SIGNAL_ACTIVITY_END_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–48 

POWER_SIGNAL_ACTIVITY_START_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–49 

POWER_STATIC_PROBABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–50 

POWER_TJ_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–52 

POWER_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–54 

POWER_TOGGLE_RATE_PERCENTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–56 

POWER_USE_CUSTOM_COOLING_SOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–58 

POWER_USE_DEVICE_CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–60 

POWER_USE_INPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–62 

POWER_USE_INPUT_FILES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–63 

POWER_USE_PVA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–65 

POWER_USE_TA_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–67 

POWER_VCCAUX_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–69 

POWER_VCCA_GXB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–70 

POWER_VCCA_L_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–71 

POWER_VCCA_R_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–72 

POWER_VCCCB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–73 

POWER_VCCH_GXBL_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–74 

POWER_VCCH_GXBR_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–75 

POWER_VCCH_GXB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–76 

POWER_VCCIO_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–77 

POWER_VCCL_GXB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–78 

POWER_VCCPD_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–79 

POWER_VCCR_GXBL_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–80 

POWER_VCCR_GXBR_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–81 

POWER_VCCR_GXB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–82 

POWER_VCCT_GXBL_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–83 

POWER_VCCT_GXBR_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–84 

POWER_VCCT_GXB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–85 

POWER_VCD_FILE_END_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–86 

POWER_VCD_FILE_START_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–88 

POWER_VCD_FILTER_GLITCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–90 

VCCAUX_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–92 

VCCA_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–93 

VCCA_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–94 

VCCA_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–95 

VCCA_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–96 

VCCA_PLL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–97 



Contents xv 

VCCA_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–98 

VCCA_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–99 

VCCCB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–100 

VCCD_PLL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–101 

VCCD_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–102 

VCCE_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–103 

VCCE_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–104 

VCCE_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–105 

VCCE_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–106 

VCCEH_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–107 

VCCEH_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–108 

VCCEH_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–109 

VCCHIP_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–110 

VCCHIP_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–111 

VCCHIP_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–112 

VCCHSSI_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–113 

VCCHSSI_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–114 

VCCH_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–115 

VCCH_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–116 

VCCH_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–117 

VCCH_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–118 

VCCH_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–119 

VCCINT_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–120 

VCCIO_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–121 

VCCL_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–122 

VCCL_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–123 

VCCL_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–124 

VCCL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–125 

VCCPD_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–126 

VCCPT_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–127 

VCCP_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–128 

VCCR_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–129 

VCCR_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–130 

VCCR_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–131 

VCCR_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–132 

VCCR_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–133 

VCCR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–134 

VCCT_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–135 

VCCT_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–136 

VCCT_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–137 

VCCT_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–138 

VCCT_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–139 

VCCT_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–140 

VCC_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–141 

Chapter 8. EDA Netlist Writer Assignments 

EDA_BOARD_BOUNDARY_SCAN_OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1 

EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2 

EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3 

EDA_BOARD_DESIGN_SYMBOL_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4 

EDA_BOARD_DESIGN_TIMING_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5 

EDA_BOARD_DESIGN_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6 

EDA_DESIGN_EXTRA_ALTERA_SIM_LIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7 

EDA_DESIGN_INSTANCE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8 



xvi Contents 

EDA_ENABLE_GLITCH_FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–9 

EDA_ENABLE_IPUTF_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10 

EDA_EXTRA_ELAB_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11 

EDA_FLATTEN_BUSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12 

EDA_FORMAL_VERIFICATION_ALLOW_RETIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13 

EDA_FORMAL_VERIFICATION_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–14 

EDA_FV_HIERARCHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15 

EDA_GENERATE_FUNCTIONAL_NETLIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–16 

EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT . . . . . . . . . . . . . . . . . . . . . 8–17 

EDA_GENERATE_POWER_INPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–18 

EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–19 

EDA_GENERATE_TIMING_CLOSURE_DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–20 

EDA_IBIS_MODEL_SELECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–21 

EDA_IBIS_MUTUAL_COUPLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–22 

EDA_IBIS_SPECIFICATION_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–23 

EDA_IPFS_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–24 

EDA_LAUNCH_CMD_LINE_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–25 

EDA_MAINTAIN_DESIGN_HIERARCHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–26 

EDA_MAP_ILLEGAL_CHARACTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–27 

EDA_NATIVELINK_GENERATE_SCRIPT_ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–28 

EDA_NATIVELINK_PORTABLE_FILE_PATHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–29 

EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–30 

EDA_NATIVELINK_SIMULATION_TEST_BENCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–31 

EDA_NETLIST_WRITER_OUTPUT_DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–32 

EDA_RESYNTHESIS_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–33 

EDA_RTL_SIMULATION_RUN_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–34 

EDA_RTL_SIM_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–35 

EDA_RTL_TEST_BENCH_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–36 

EDA_RTL_TEST_BENCH_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–37 

EDA_RTL_TEST_BENCH_RUN_FOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–38 

EDA_SDC_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–39 

EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED . . . . . . . . . . . . . 8–40 

EDA_SIMULATION_RUN_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–41 

EDA_SIMULATION_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–42 

EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–43 

EDA_SIMULATION_VCD_OUTPUT_TCL_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–44 

EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–45 

EDA_TEST_BENCH_DESIGN_INSTANCE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–46 

EDA_TEST_BENCH_ENABLE_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–47 

EDA_TEST_BENCH_ENTITY_MODULE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–48 

EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–49 

EDA_TEST_BENCH_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–50 

EDA_TEST_BENCH_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–51 

EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–52 

EDA_TEST_BENCH_MODULE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–53 

EDA_TEST_BENCH_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–54 

EDA_TEST_BENCH_RUN_FOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–55 

EDA_TEST_BENCH_RUN_SIM_FOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–56 

EDA_TIME_SCALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–57 

EDA_TIMING_ANALYSIS_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–58 

EDA_TRUNCATE_LONG_HIERARCHY_PATHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–59 

EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–60 

EDA_VHDL_ARCH_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–61 

EDA_WAIT_FOR_GUI_TOOL_COMPLETION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–62 



Contents xvii 

EDA_WRITER_DONT_WRITE_TOP_ENTITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–63 

EDA_WRITE_DEVICE_CONTROL_PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–64 

EDA_WRITE_NODES_FOR_POWER_ESTIMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–65 

Chapter 9. Assembler Assignments 

ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1 

AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2 

AUTO_RESTART_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3 

CLOCK_SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5 

COMPRESSION_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–6 

CONFIGURATION_CLOCK_DIVISOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7 

CONFIGURATION_CLOCK_FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8 

CYCLONEIII_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9 

CYCLONEII_M4K_COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10 

CYCLONE_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11 

DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12 

ENABLE_AUTONOMOUS_PCIE_HIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–13 

ENABLE_OCT_DONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14 

EPROM_USE_CHECKSUM_AS_USERCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–15 

GENERATE_HEX_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–16 

GENERATE_RBF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–17 

GENERATE_TTF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–18 

HARDCOPYII_POWER_ON_EXTRA_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–19 

HEXOUT_FILE_COUNT_DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–20 

HEXOUT_FILE_START_ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–21 

MAX7000S_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–22 

MAX7000_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–23 

MAX7000_USE_CHECKSUM_AS_USERCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–24 

ON_CHIP_BITSTREAM_DECOMPRESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–25 

RELEASE_CLEARS_BEFORE_TRI_STATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–26 

RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–28 

SECURITY_BIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–29 

STRATIXII_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–30 

STRATIXII_MRAM_COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–31 

STRATIX_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–32 

STRATIX_CONFIG_DEVICE_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–33 

STRATIX_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–34 

USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT . . . . . . . . . . . . . . . . . . . . . 9–36 

USE_CHECKSUM_AS_USERCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–37 

USE_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–39 

Chapter 10. Design Assistant Assignments 

ACLK_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1 

ACLK_RULE_IMSZER_ADOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2 

ACLK_RULE_NO_SZER_ACLK_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3 

ACLK_RULE_SZER_BTW_ACLK_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4 

CLK_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5 

CLK_RULE_CLKNET_CLKSPINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–6 

CLK_RULE_CLKNET_CLKSPINES_THRESHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–7 

CLK_RULE_COMB_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–8 

CLK_RULE_GATED_CLK_FANOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–9 

CLK_RULE_INPINS_CLKNET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–10 

CLK_RULE_INV_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–11 



xviii Contents 

CLK_RULE_MIX_EDGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–12 

DA_CUSTOM_RULE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–13 

DISABLE_DA_GX_RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–14 

DISABLE_DA_RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–15 

DRC_DEADLOCK_STATE_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–16 

DRC_DETAIL_MESSAGE_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–17 

DRC_FANOUT_EXCEEDING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–18 

DRC_GATED_CLOCK_FEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–19 

DRC_REPORT_FANOUT_EXCEEDING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–20 

DRC_REPORT_TOP_FANOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–21 

DRC_TOP_FANOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–22 

DRC_VIOLATION_MESSAGE_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–23 

ENABLE_DA_RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–24 

ENABLE_DRC_SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–25 

FSM_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–26 

FSM_RULE_DEADLOCK_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–27 

FSM_RULE_NO_RESET_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–28 

FSM_RULE_NO_SZER_ACLK_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–29 

FSM_RULE_UNREACHABLE_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–30 

FSM_RULE_UNUSED_TRANSITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–31 

HARDCOPY_FLOW_AUTOMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–32 

HARDCOPY_NEW_PROJECT_PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–33 

HCPY_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–34 

NONSYNCHSTRUCT_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–35 

NONSYNCHSTRUCT_RULE_COMBLOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–36 

NONSYNCHSTRUCT_RULE_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–37 

NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–38 

NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–39 

NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–40 

NONSYNCHSTRUCT_RULE_REG_LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–41 

NONSYNCHSTRUCT_RULE_RIPPLE_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–42 

NONSYNCHSTRUCT_RULE_SRLATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–43 

RESET_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–44 

RESET_RULE_COMB_ASYNCH_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–45 

RESET_RULE_IMSYNCH_ASYNCH_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–46 

RESET_RULE_IMSYNCH_EXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–47 

RESET_RULE_UNSYNCH_ASYNCH_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–48 

RESET_RULE_UNSYNCH_EXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–49 

SIGNALRACE_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–50 

SIGNALRACE_RULE_CLK_PORT_RACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–51 

SIGNALRACE_RULE_RESET_RACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–52 

SIGNALRACE_RULE_SECOND_SIGNAL_RACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–53 

SIGNALRACE_RULE_TRISTATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–54 

TIMING_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–55 

Chapter 11. Programmer Assignments 

EXCALIBUR_HEX_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1 

GENERATE_CONFIG_HEXOUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2 

GENERATE_CONFIG_ISC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3 

GENERATE_CONFIG_JAM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4 

GENERATE_CONFIG_JBC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5 

GENERATE_CONFIG_JBC_FILE_COMPRESSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–6 

GENERATE_CONFIG_SVF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–7 

GENERATE_ISC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–8 



Contents xix 

GENERATE_JAM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–9 

GENERATE_JBC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–11 

GENERATE_JBC_FILE_COMPRESSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–13 

GENERATE_SVF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–15 

ISP_CLAMP_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–17 

ISP_CLAMP_STATE_DEFAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–18 

MERGE_HEX_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–19 

Chapter 12. SignalTap II Assignments 

ENABLE_LOGIC_ANALYZER_INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1 

ENABLE_SIGNALTAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2 

STP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–3 

USE_LOGIC_ANALYZER_INTERFACE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 

USE_SIGNALTAP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5 

Chapter 13. LogicLock Region Assignments 

LL_AUTO_SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1 

LL_ENABLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–2 

LL_HEIGHT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–3 

LL_MEMBER_EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4 

LL_MEMBER_OF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 

LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 

LL_ORIGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–7 

LL_PARENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–8 

LL_PRIORITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9 

LL_RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–10 

LL_ROOT_REGION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–11 

LL_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–12 

LL_WIDTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–13 

Chapter 14. Migration Assignments 

MIGRATION_AUTO_PACKED_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–1 

MIGRATION_AUTO_PORT_SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–2 

MIGRATION_RAM_INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–3 

Chapter 15. Netlist Viewer Assignments 

RTLV_GROUP_COMB_LOGIC_IN_CLOUD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–1 

RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–2 

RTLV_GROUP_RELATED_NODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–3 

RTLV_GROUP_RELATED_NODES_TMV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–4 

RTLV_REMOVE_FANOUT_FREE_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–5 

RTLV_SIMPLIFIED_LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–6 

Chapter 16. Advanced I/O Timing Assignments 

BOARD_MODEL_EBD_FAR_END . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–1 

BOARD_MODEL_EBD_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–2 

BOARD_MODEL_EBD_SIGNAL_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–3 

BOARD_MODEL_FAR_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–4 

BOARD_MODEL_FAR_DIFFERENTIAL_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–5 

BOARD_MODEL_FAR_PULLDOWN_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–6 

BOARD_MODEL_FAR_PULLUP_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–7 

BOARD_MODEL_FAR_SERIES_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–8 

BOARD_MODEL_NEAR_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–9 



xx Contents 

BOARD_MODEL_NEAR_DIFFERENTIAL_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–10 

BOARD_MODEL_NEAR_PULLDOWN_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–11 

BOARD_MODEL_NEAR_PULLUP_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–12 

BOARD_MODEL_NEAR_SERIES_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–13 

BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–14 

BOARD_MODEL_NEAR_TLINE_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–15 

BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–16 

BOARD_MODEL_TERMINATION_V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–17 

BOARD_MODEL_TLINE_C_PER_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–18 

BOARD_MODEL_TLINE_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–19 

BOARD_MODEL_TLINE_L_PER_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–20 

ENABLE_ADVANCED_IO_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–21 

OUTPUT_IO_TIMING_ENDPOINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–22 

OUTPUT_IO_TIMING_FAR_END_VMEAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–23 

OUTPUT_IO_TIMING_NEAR_END_VMEAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–24 

PCB_LAYER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–25 

PCB_LAYERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–26 

PCB_LAYER_THICKNESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–27 

SYNCHRONOUS_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–28 

Chapter 17. TimeQuest Timing Assignments 

ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–1 

DO_COMBINED_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–2 

INPUT_TRANSITION_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–4 

MAX_CORE_JUNCTION_TEMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–5 

MIN_CORE_JUNCTION_TEMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–6 

NOMINAL_CORE_SUPPLY_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–7 

PACKAGE_SKEW_COMPENSATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–8 

PLL_EXTERNAL_FEEDBACK_BOARD_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–9 

TIMEQUEST_DO_CCPP_REMOVAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–10 

TIMEQUEST_DO_REPORT_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–12 

TIMEQUEST_MULTICORNER_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–13 

TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–15 

TIMEQUEST_REPORT_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–16 

TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . 17–17 

TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–18 

Additional Information 

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–1 

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–2 

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–2 

Assignment Value Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–3 

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–5 



AGGREGATE_REVISION 

Type 










June 2012 

Specifies an AGGREGATE revision type. 

String 

Device Support 

1. Project-Wide Assignments 

You can use this setting in projects targeting the following device families: 

■ Stratix V 

Notes 

The value of this assignment is case sensitive. 

Syntax 

set_global_assignment -name AGGREGATE_REVISION 

ISO 

9001:2008 

Registered 

Subscribe

1–2 Chapter 1: Project-Wide Assignments 

AHDL_FILE 

AHDL_FILE 

Type 

Associates an AHDL source file with this project. 

File name 


This setting can be used in projects targeting any Altera device family. 

Notes 

The value of this assignment is case sensitive.. 

Syntax 

set_global_assignment -name AHDL_FILE 



Chapter 1: Project-Wide Assignments 1–3 

AHDL_TEXT_DESIGN_OUTPUT_FILE 

AHDL_TEXT_DESIGN_OUTPUT_FILE 

Type 

Associates an AHDL Text Design Output File (.tdo) with this project. 




Notes 


Syntax 

set_global_assignment -name AHDL_TEXT_DESIGN_OUTPUT_FILE 




ASM_FILE 

ASM_FILE 

Type 

Associates an Assembly source file with this project. 




Notes 


Syntax 

set_global_assignment -name ASM_FILE 




AUTO_EXPORT_VER_COMPATIBLE_DB 

AUTO_EXPORT_VER_COMPATIBLE_DB 

Type 

Automatically exports version-compatible database files when compilation 

completes. 

Boolean 



Notes 

This assignment is not copied when you create a companion revision for HardCopy II 

devices. 

Syntax 

set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB 

Default Value 

Off 




BASE_REVISION 

BASE_REVISION 

Type 

Specifies a BASE revision type. 

String 



■ Stratix V 

Notes 


Syntax 

set_global_assignment -name BASE_REVISION 




BASE_REVISION_PROJECT_OUTPUT_DIRECTORY 

BASE_REVISION_PROJECT_OUTPUT_DIRECTORY 

Type 

Specifies the directory where project output files such as the Text-Format Report Files 

(.rpt) and Equation Files (.eqn) were saved for the base revision. By default, all project 

output files are saved in the project directory. 




Notes 


Syntax 

set_global_assignment -name BASE_REVISION_PROJECT_OUTPUT_DIRECTORY 




BDF_FILE 

BDF_FILE 

Type 

Associates a Block Design File (.bdf) with this project. 




Notes 


Syntax 

set_global_assignment -name BDF_FILE 




BINARY_FILE 

BINARY_FILE 

Type 

Associates a Binary File (.bin) with this project. 




Notes 


Syntax 

set_global_assignment -name BINARY_FILE 




BSF_FILE 

BSF_FILE 

Type 

Associates a Block Symbol File (.bsf) with this project. 




Notes 


Syntax 

set_global_assignment -name BSF_FILE 




CDF_FILE 

CDF_FILE 

Type 

Associates a Chain Description File (.cdf) with this project. 




Notes 


Syntax 

set_global_assignment -name CDF_FILE 




COMMAND_MACRO_FILE 

COMMAND_MACRO_FILE 

Type 

Associates a script file or ModelSim Macro File with this project. 




Notes 


Syntax 

set_global_assignment -name COMMAND_MACRO_FILE 




CPP_FILE 

CPP_FILE 

Type 

Associates a C++ source file with this project. 




Notes 


Syntax 

set_global_assignment -name CPP_FILE 




CPP_INCLUDE_FILE 

CPP_INCLUDE_FILE 

Type 

Associates a C++ include file with this project. 




Notes 


Syntax 

set_global_assignment -name CPP_INCLUDE_FILE 




CUSP_FILE 

CUSP_FILE 

Type 

Associates a C++ source file with this project. 




Notes 


Syntax 

set_global_assignment -name CUSP_FILE 




CVP_REVISION 

CVP_REVISION 

Type 

Specifies a CVP revision type. 

String 


This setting can be used in projects targeting the following device families: 

■ Stratix V 

Notes 


Syntax 

set_global_assignment -name CVP_REVISION 




C_FILE 

C_FILE 

Type 

Associates a C source file with this project. 




Notes 


Syntax 

set_global_assignment -name C_FILE 




DEPENDENCY_FILE 

DEPENDENCY_FILE 

Type 

Associates a Dependency file with this project. 




Notes 


Syntax 

set_global_assignment -name DEPENDENCY_FILE 




DSPBUILDER_FILE 

DSPBUILDER_FILE 

Type 

Associates a DSPBuilder source file with this project. 




Notes 


Syntax 

set_global_assignment -name DSPBUILDER_FILE 




EDIF_FILE 

EDIF_FILE 

Type 

Associates an EDIF source file with this project. 




Notes 


Syntax 

set_global_assignment -name EDIF_FILE 




ELF_FILE 

ELF_FILE 

Type 

Associates an ELF file with this project. 




Notes 


Syntax 

set_global_assignment -name ELF_FILE 




ENABLE_COMPACT_REPORT_TABLE 

ENABLE_COMPACT_REPORT_TABLE 

Type 

Allows you to view the report table in compact format. 

Boolean 



Notes 

This assignment is included in the Fitter report. 

Syntax 

set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE 

Default Value 

Off 




ENABLE_REDUCED_MEMORY_MODE 

ENABLE_REDUCED_MEMORY_MODE 

Type 

Determines whether to enable the Compiler to run in reduced memory mode. This 

assignment controls a small number of memory-intensive fitter optimizations. 

Therefore, enabling the reduced memory mode may slightly impact the performance 

of your design. 

Boolean 



Syntax 

set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE 

Default Value 

Off 




EQUATION_FILE 

EQUATION_FILE 

Type 

Associates an Equation File with this project. 




Notes 


Syntax 

set_global_assignment -name EQUATION_FILE 




FLOW_DISABLE_ASSEMBLER 

FLOW_DISABLE_ASSEMBLER 

Type 

Allows you to turn on or turn off the Assembler during compilation. 

Boolean 



Syntax 

set_global_assignment -name FLOW_DISABLE_ASSEMBLER 

Default Value 

Off 




FLOW_ENABLE_HC_COMPARE 

FLOW_ENABLE_HC_COMPARE 

Type 

Enables HardCopy Compare during compilation. 

Boolean 



■ HardCopy II 

■ HardCopy III 

■ HardCopy IV 

Syntax 

set_global_assignment -name FLOW_ENABLE_HC_COMPARE 

Default Value 

Off 




FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS 

FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS 

Type 

Allows you to run I/O assignment analysis before compilation. 

Boolean 



Syntax 

set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS 

Default Value 

Off 




FLOW_ENABLE_PARALLEL_MODULES 

FLOW_ENABLE_PARALLEL_MODULES 

Type 

Allows you to run Assembler and TimeQuest Timing Analyzer in parallel during 

compilation. 

Boolean 



Notes 


Syntax 

set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES 

Default Value 

On 




FLOW_ENABLE_POWER_ANALYZER 

FLOW_ENABLE_POWER_ANALYZER 

Type 

Allows you to turn on or turn off the Power Analyzer during compilation. 

Boolean 


You can use this setting in projects targeting any Altera device family. 

Syntax 

set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER 

Default Value 

Off 




FLOW_ENABLE_RTL_VIEWER 

FLOW_ENABLE_RTL_VIEWER 

Type 

Allows the RTL Viewer to process the schematic during design compilation. Turning 

on this option also allows you to open the RTL Viewer after the Analysis & Synthesis 

portion of design compilation completes, rather than waiting for the full compilation 

to complete. 

Boolean 



Syntax 

set_global_assignment -name FLOW_ENABLE_RTL_VIEWER 

Default Value 

Off 




FLOW_HARDCOPY_DESIGN_READINESS_CHECK 

FLOW_HARDCOPY_DESIGN_READINESS_CHECK 

Type 

Allows you to turn on or turn off the HardCopy Design Readiness Check during 

compilation. 

Boolean 



■ Arria II GZ 




■ Stratix II 

■ Stratix III 

■ Stratix IV 

Notes 


devices. 

Syntax 

set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK 

Default Value 

On 




GDF_FILE 

GDF_FILE 

Type 

Associates a GDF source file with this project. 




Notes 


Syntax 

set_global_assignment -name GDF_FILE 




HC_OUTPUT_DIR 

HC_OUTPUT_DIR 

Type 

Specifies the directory to which HardCopy handoff files should be generated. 







Notes 



devices. 

Syntax 

set_global_assignment -name HC_OUTPUT_DIR 

Default Value 

hc_output 




HEX_FILE 

HEX_FILE 

Type 

Associates a Hexadecimal (Intel-Format) File (.hex) with this project. 




Notes 


Syntax 

set_global_assignment -name HEX_FILE 




HEX_OUTPUT_FILE 

HEX_OUTPUT_FILE 

Type 

Associates a Hexadecimal (Intel-Format) Output File (.hexout) with this project. 




Notes 


Syntax 

set_global_assignment -name HEX_OUTPUT_FILE 




HTML_FILE 

HTML_FILE 

Type 

Associates an HTML File (.html) with this project. 




Notes 


Syntax 

set_global_assignment -name HTML_FILE 




HTML_REPORT_FILE 

HTML_REPORT_FILE 

Type 

Associates an HTML-Format Report File (.htm) with this project. 




Notes 


Syntax 

set_global_assignment -name HTML_REPORT_FILE 




INCLUDE_FILE 

INCLUDE_FILE 

Type 

Associates an Include File (.inc) with this project. 




Notes 


Syntax 

set_global_assignment -name INCLUDE_FILE 




IPA_FILE 

IPA_FILE 

Type 

Associates an IP Advisor file with this project. 




Notes 


Syntax 

set_global_assignment -name IPA_FILE 




IP_TOOL_ENV 

IP_TOOL_ENV 

Type 

Specifies the tool which generated the IP core. 

String 



Notes 


Syntax 

set_global_assignment -name IP_TOOL_ENV 

set_global_assignment -name IP_TOOL_ENV -entity 

set_instance_assignment -name IP_TOOL_ENV -to -entity 

 




IP_TOOL_NAME 

IP_TOOL_NAME 

Type 

Specifies the IP core name. 

String 



Notes 


Syntax 

set_global_assignment -name IP_TOOL_NAME 

set_global_assignment -name IP_TOOL_NAME -entity 

set_instance_assignment -name IP_TOOL_NAME -to -entity 

 




IP_TOOL_VERSION 

IP_TOOL_VERSION 

Type 

Specifies the IP core version. 

String 



Notes 


Syntax 

set_global_assignment -name IP_TOOL_VERSION 

set_global_assignment -name IP_TOOL_VERSION -entity 

set_instance_assignment -name IP_TOOL_VERSION -to -entity 




ISC_FILE 

ISC_FILE 

Type 

IEEE 1532 file. 




Notes 


Syntax 

set_global_assignment -name ISC_FILE 




JAM_FILE 

JAM_FILE 

Type 

Associates a Jam Standard Test and Programming Language (STAPL) Format File 

(.jam) with this project. 




Notes 


Syntax 

set_global_assignment -name JAM_FILE 




JBC_FILE 

JBC_FILE 

Type 

Associates a JAM Byte Code File (.jbc) with this project. 




Notes 


Syntax 

set_global_assignment -name JBC_FILE 




LICENSE_FILE 

LICENSE_FILE 

Type 

Associates a License File with this project. 




Notes 


Syntax 

set_global_assignment -name LICENSE_FILE 




LMF_FILE 

LMF_FILE 

Type 

Associates a Library Mapping File (.lmf) with this project. 




Notes 


Syntax 

set_global_assignment -name LMF_FILE 




LOGIC_ANALYZER_INTERFACE_FILE 

LOGIC_ANALYZER_INTERFACE_FILE 

Type 

Associates a Logic Analyzer Interface File (.lai) with this project. 




Notes 


Syntax 

set_global_assignment -name LOGIC_ANALYZER_INTERFACE_FILE 




MAP_FILE 

MAP_FILE 

Type 

Contains the byte addresses of pages and HEX data stored in the memory of an EPC4, 

EPC8, or EPC16 configuration device. 




Notes 


Syntax 

set_global_assignment -name MAP_FILE 




MASK_REVISION 

MASK_REVISION 

Type 

Specifies a MASK revision type. 

String 



■ Stratix V 

Notes 


Syntax 

set_global_assignment -name MASK_REVISION 




MESSAGE_DISABLE 

MESSAGE_DISABLE 

Type 

Tells the Compiler to suppress the specified user message(s). 

Integer 



Notes 

This assignment supports wildcards. 

Syntax 

set_global_assignment -name MESSAGE_DISABLE 

set_global_assignment -name MESSAGE_DISABLE -entity 

set_instance_assignment -name MESSAGE_DISABLE -to -entity 




MESSAGE_ENABLE 

MESSAGE_ENABLE 

Type 

Tells the Compiler to enable the specified user message(s). 

Integer 



Notes 


Syntax 

set_global_assignment -name MESSAGE_ENABLE 

set_global_assignment -name MESSAGE_ENABLE -entity 

set_instance_assignment -name MESSAGE_ENABLE -to -entity 




MESSAGE_SUPPRESSION_RULE_FILE 

MESSAGE_SUPPRESSION_RULE_FILE 

Type 

Associates a message suppression rule file with this project. 




Notes 


The name of this file is based on the project revision name. 

Syntax 

set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE 




MIF_FILE 

MIF_FILE 

Type 

Associates a Memory Initialization File (.mif) with this project. 




Notes 


Syntax 

set_global_assignment -name MIF_FILE 




MIGRATION_DIFFERENT_SOURCE_FILE 

MIGRATION_DIFFERENT_SOURCE_FILE 

Type 

Specifies a HDL source file that is different in the companion revision. This is used to 

allow setting differences between the current and companion revision. The 

companion revision has a different source file than the one specified here. 








Notes 


Syntax 

set_global_assignment -name MIGRATION_DIFFERENT_SOURCE_FILE 




MISC_FILE 

MISC_FILE 

Type 

Associates a file with this project. Files assigned to this assignment is archived by the 

Project Archive command if the ‘Project source and settings files’ file subset is 

selected. 




Notes 


Syntax 

set_global_assignment -name MISC_FILE 




NUM_PARALLEL_PROCESSORS 


Type 

Specifies the maximum number of processors allocated for parallel compilation on a 

single machine. For parallel compilation, you can use all available processors on your 

machine, or specify the number of processors you want to use. For example, if you 

have a quad-core processor machine and want to leave one processor free for other 

tasks, specify 3 as the setting of this option. A setting of 1 disables parallel 

compilation. 

String 



■ Arria GX 

■ Arria II GX 


■ Arria V 

■ Cyclone 

■ Cyclone II 

■ Cyclone III 

■ Cyclone III LS 

■ Cyclone IV E 

■ Cyclone IV GX 

■ Cyclone V 



■ MAX II 

■ MAX V 

■ Stratix 

■ Stratix GX 


■ Stratix II GX 



■ Stratix V 

Notes 






Syntax 

set_global_assignment -name NUM_PARALLEL_PROCESSORS 

Old Names 

This variable also has the following name(s) in some earlier versions of the Quartus II 

software: 

MAX_PROCESSORS_USED_FOR_MULTITHREADING 




OBJECT_FILE 

OBJECT_FILE 

Type 

Associates an Object File with this project. 




Notes 


Syntax 

set_global_assignment -name OBJECT_FILE 




OCP_FILE 

OCP_FILE 

Type 

Specifies the OpenCore Plus File (.ocp) generated by the MegaWizard Plug-In 

Manager. The Quartus II software uses this file to compile and generate an SRAM 

Object File (.sof) of the core without a license. 




Notes 


Syntax 

set_global_assignment -name OCP_FILE 




PARTIAL_SRAM_OBJECT_FILE 

PARTIAL_SRAM_OBJECT_FILE 

Type 

Associates a Partial SRAM Object File with this project. 




Notes 


Syntax 

set_global_assignment -name PARTIAL_SRAM_OBJECT_FILE 




PERSONA_FILE 

PERSONA_FILE 

Type 

Associates a Quartus II Persona with this project as a source file. 




Notes 


Syntax 

set_global_assignment -name PERSONA_FILE 




PIN_FILE 

PIN_FILE 

Type 

Associates a Pin-Out File (.pin) with this project. 




Notes 


Syntax 

set_global_assignment -name PIN_FILE 




POWER_INPUT_FILE 

POWER_INPUT_FILE 

Type 

Associates a Power Input File (.pwf) with this project. 




Notes 


Syntax 

set_global_assignment -name POWER_INPUT_FILE 




PPF_FILE 

PPF_FILE 

Type 

Specifies the name of the MegaWizard-generated Pin Planner File (.ppf) containing 

core-specific pin assignments. This file is loaded by the Pin Planner. 




Notes 


Syntax 

set_global_assignment -name PPF_FILE 




PROGRAMMER_OBJECT_FILE 

PROGRAMMER_OBJECT_FILE 

Type 

Associates a Programmer Object File (.pof) with this project. 




Notes 


Syntax 

set_global_assignment -name PROGRAMMER_OBJECT_FILE 




PROJECT_OUTPUT_DIRECTORY 

PROJECT_OUTPUT_DIRECTORY 

Type 

Specifies the directory in which to save all project output files such as the Text-Format 

Report Files (.rpt) and Equation Files (.eqn). By default, all project output files are 

saved in the project directory. 




Notes 


Syntax 

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY 




PROJECT_SHOW_ENTITY_NAME 

PROJECT_SHOW_ENTITY_NAME 

Type 

Determines whether to display the entity name for node names. 

Boolean 



Syntax 

set_global_assignment -name PROJECT_SHOW_ENTITY_NAME 

Default Value 

On 




PROJECT_USE_SIMPLIFIED_NAMES 

PROJECT_USE_SIMPLIFIED_NAMES 

Type 

Determines whether to use the simplified naming scheme. 

Boolean 



Syntax 

set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES 

Default Value 

Off 




QARLOG_FILE 

QARLOG_FILE 

Type 

Associates a Quartus II Archive Log File (.qarlog) with this project. 




Notes 


Syntax 

set_global_assignment -name QARLOG_FILE 




QAR_FILE 

QAR_FILE 

Type 

Associates a Quartus II Archive File (.qar) with this project. 




Notes 


Syntax 

set_global_assignment -name QAR_FILE 




QIP_FILE 

QIP_FILE 

Type 

Associates a Quartus II IP File (.qip) with this project. 




Notes 


Syntax 

set_global_assignment -name QIP_FILE 




QSYS_FILE 

QSYS_FILE 

Type 

Associates a Qsys System File (.qsys) with this project. 




Notes 


Syntax 

set_global_assignment -name QSYS_FILE 




QUARTUS_PTF_FILE 

QUARTUS_PTF_FILE 

Type 

Associates a Quartus II Peripheral Template File (.ptf) with this project. 




Notes 


Syntax 

set_global_assignment -name QUARTUS_PTF_FILE 




QUARTUS_SBD_FILE 

QUARTUS_SBD_FILE 

Type 

Associates a Quartus II System Build Descriptor File (.sbd) with this project. 




Notes 


Syntax 

set_global_assignment -name QUARTUS_SBD_FILE 




QUARTUS_STANDARD_DELAY_FILE 

QUARTUS_STANDARD_DELAY_FILE 

Type 

Associates a Quartus II Standard Delay File (.sdf) with this project. 




Notes 


Syntax 

set_global_assignment -name QUARTUS_STANDARD_DELAY_FILE 




QVAR_FILE 

QVAR_FILE 

Type 

Associates a Quartus II IP Variation File (.qvar) with this project. 



Syntax 


Notes 


set_global_assignment -name QVAR_FILE 




QXP_FILE 

QXP_FILE 

Type 

Associates a Quartus II Exported Partition File (.qxp) source file with this project. 




Notes 


Syntax 

set_global_assignment -name QXP_FILE 




RAW_BINARY_FILE 

RAW_BINARY_FILE 

Type 

Associates a Raw Binary File (.rbf) with this project. 




Notes 


Syntax 

set_global_assignment -name RAW_BINARY_FILE 




READ_OR_WRITE_IN_BYTE_ADDRESS 

READ_OR_WRITE_IN_BYTE_ADDRESS 

Type 

Determines whether to read or write Hexadecimal Files (.hex) in byte addressable 

mode for this project. 

Enumeration 

■ Off 

■ On 


■ Use global settings 


Syntax 

set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS 

Default Value 

Use global settings 




RECONFIGURABLE_REVISION 

RECONFIGURABLE_REVISION 

Type 

Specifies a RECONFIGURABLE revision type. 

String 



■ Stratix V 

Notes 


Syntax 

set_global_assignment -name RECONFIGURABLE_REVISION 




REVISION_TYPE 

REVISION_TYPE 

Type 

Describes the type of revision. The possible revision types are BASE, 

RECONFIGURABLE, AGGREGATE, CVP, and MASK. 

The default revision type is BASE. 

Enumeration 

■ Aggregate 

■ Base 

■ CVP 

■ Mask 


■ Reconfigurable 


■ Stratix V 

Syntax 

set_global_assignment -name REVISION_TYPE 

Default Value 

Base 




RUN_FULL_COMPILE_ON_DEVICE_CHANGE 

RUN_FULL_COMPILE_ON_DEVICE_CHANGE 

Type 

Runs Full Compilation when the device changes. 

Boolean 



Syntax 

set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE 

Default Value 

On 




SAVE_MIGRATION_INFO_DURING_COMPILATION 

SAVE_MIGRATION_INFO_DURING_COMPILATION 

Type 

Saves the migration information during compilation. 

Boolean 







Syntax 

set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION 

Default Value 

Off 

Old Names 


software: 

HARDCOPYII_SAVE_MIGRATION_INFO_DURING_COMPILATION 




SBI_FILE 

SBI_FILE 

Type 

Associates a Slave Binary Interface File (.sbi) with this project. 




Notes 


Syntax 

set_global_assignment -name SBI_FILE 




SDC_FILE 

SDC_FILE 

Type 

Associates a Synopsys Design Constraints File (.sdc) with this project. 




Notes 


Syntax 

set_global_assignment -name SDC_FILE 




SDF_OUTPUT_FILE 

SDF_OUTPUT_FILE 

Type 

Associates a Standard Delay Format Output File (.sdo) with this project. 




Notes 


Syntax 

set_global_assignment -name SDF_OUTPUT_FILE 




SERIAL_BITSTREAM_FILE 

SERIAL_BITSTREAM_FILE 

Type 

Associates a Serial Bitstream File (.sbf) with this project. 




Notes 


Syntax 

set_global_assignment -name SERIAL_BITSTREAM_FILE 




SIGNALTAP_FILE 

SIGNALTAP_FILE 

Type 

Associates a SignalTap II File (.stp) with this project. 




Notes 


Syntax 

set_global_assignment -name SIGNALTAP_FILE 




SIP_FILE 

SIP_FILE 

Type 

Associates a simulation IP with this project. 




Notes 


Syntax 

set_global_assignment -name SIP_FILE 




SMART_RECOMPILE 

SMART_RECOMPILE 

Type 

Specifies whether to use the Smart Compilation option. Turning this option on helps 

future compilations run faster. 

Boolean 



Notes 


Syntax 

set_global_assignment -name SMART_RECOMPILE 

Default Value 

Off 

Old Names 


software: 

SPEED_DISK_USAGE_TRADEOFF 




SMF_FILE 

SMF_FILE 

Type 

Associates a State Machine File (.smf) with this project. 




Notes 


Syntax 

set_global_assignment -name SMF_FILE 




SOFTWARE_LIBRARY_FILE 

SOFTWARE_LIBRARY_FILE 

Type 

Associates a software library file with this project. 




Notes 


Syntax 

set_global_assignment -name SOFTWARE_LIBRARY_FILE 




SOPC_FILE 

SOPC_FILE 

Type 

Associates a SOPC Builder Design File (.sopc) with this project. 




Notes 


Syntax 

set_global_assignment -name SOPC_FILE 




SOURCE_TCL_SCRIPT_FILE 

SOURCE_TCL_SCRIPT_FILE 

Type 

Runs Tcl Script File (.tcl). This assignment has the same effect as ‘source ’. 




Notes 


Syntax 

set_global_assignment -name SOURCE_TCL_SCRIPT_FILE 




SPD_FILE 

SPD_FILE 

Type 

Associates a Simulation Package Descriptor File (.spd) with this project. 




Notes 


Syntax 

set_global_assignment -name SPD_FILE 




SRAM_OBJECT_FILE 

SRAM_OBJECT_FILE 

Type 

Associates an SRAM Object File (.sof) with this project. 




Notes 


Syntax 

set_global_assignment -name SRAM_OBJECT_FILE 




SRECORDS_FILE 

SRECORDS_FILE 

Type 

Associates a Motorola S-Record File (.srec) with this project. 




Notes 


Syntax 

set_global_assignment -name SRECORDS_FILE 




SVF_FILE 

SVF_FILE 

Type 

Associates a Serial Vector Format File (.svf) with this project. 




Notes 


Syntax 

set_global_assignment -name SVF_FILE 




SYM_FILE 

SYM_FILE 

Type 

Associates a Symbol File (.sym) with this project. 




Notes 


Syntax 

set_global_assignment -name SYM_FILE 




SYNTHESIS_ONLY_QIP 

SYNTHESIS_ONLY_QIP 

Type 

Determines whether a Quartus II IP File (.qip) is not for simulation. 

Boolean 



Notes 


Syntax 

set_global_assignment -name SYNTHESIS_ONLY_QIP 




SYSTEMVERILOG_FILE 

SYSTEMVERILOG_FILE 

Type 

Associates a System Verilog Design File (.sv) with this project. 




Notes 


Syntax 

set_global_assignment -name SYSTEMVERILOG_FILE 




TCL_SCRIPT_FILE 

TCL_SCRIPT_FILE 

Type 

Associates a Tcl Script File (.tcl) with this project. 




Notes 


Syntax 

set_global_assignment -name TCL_SCRIPT_FILE 




TEMPLATE_FILE 

TEMPLATE_FILE 

Type 

Associates a Template File with this project. 




Notes 


Syntax 

set_global_assignment -name TEMPLATE_FILE 




TEXT_FILE 

TEXT_FILE 

Type 

Associates a Text File (.txt) with this project. 




Notes 


Syntax 

set_global_assignment -name TEXT_FILE 




TEXT_FORMAT_REPORT_FILE 

TEXT_FORMAT_REPORT_FILE 

Type 

Associates a Text-Format Report File (.rpt) with this project. 




Notes 


Syntax 

set_global_assignment -name TEXT_FORMAT_REPORT_FILE 




TIMING_ANALYSIS_OUTPUT_FILE 

TIMING_ANALYSIS_OUTPUT_FILE 

Type 

Associates a Timing Analysis Output File (.tao) with this project. 




Notes 


Syntax 

set_global_assignment -name TIMING_ANALYSIS_OUTPUT_FILE 




VCD_FILE 

VCD_FILE 

Type 

Associates a Verilog Value Change Dump File (.vcd) with this project. 




Notes 


Syntax 

set_global_assignment -name VCD_FILE 




VECTOR_TABLE_OUTPUT_FILE 

VECTOR_TABLE_OUTPUT_FILE 

Type 

Associates a Vector Table Output File (.tbl) with this project. 




Notes 


Syntax 

set_global_assignment -name VECTOR_TABLE_OUTPUT_FILE 




VECTOR_TEXT_FILE 

VECTOR_TEXT_FILE 

Type 

Associates a Vector Text File (.vec) with this project. 




Notes 


Syntax 

set_global_assignment -name VECTOR_TEXT_FILE 




VECTOR_WAVEFORM_FILE 

VECTOR_WAVEFORM_FILE 

Type 

Associates a Vector Waveform File (.vwf) with this project. 




Notes 


Syntax 

set_global_assignment -name VECTOR_WAVEFORM_FILE 




VERILOG_FILE 

VERILOG_FILE 

Type 

Associates a Verilog HDL source file (.v) with this project. 




Notes 


Syntax 

set_global_assignment -name VERILOG_FILE 




VERILOG_INCLUDE_FILE 

VERILOG_INCLUDE_FILE 

Type 

Associates a Verilog Include File (.v) with this project. 




Notes 


Syntax 

set_global_assignment -name VERILOG_INCLUDE_FILE 

Old Names 


software: 

VERILOG_VH_FILE 




VERILOG_OUTPUT_FILE 

VERILOG_OUTPUT_FILE 

Type 

Associates a Verilog Output File (.vo) with this project. 




Notes 


Syntax 

set_global_assignment -name VERILOG_OUTPUT_FILE 




VERILOG_TEST_BENCH_FILE 

VERILOG_TEST_BENCH_FILE 

Type 

Associates a Verilog HDL Test Bench File (.vt) with this project. 




Notes 


Syntax 

set_global_assignment -name VERILOG_TEST_BENCH_FILE 




VER_COMPATIBLE_DB_DIR 

VER_COMPATIBLE_DB_DIR 

Type 

Specifies the directory to which version-compatible database files should be saved. 




Notes 



devices. 

Syntax 

set_global_assignment -name VER_COMPATIBLE_DB_DIR 

Default Value 

export_db 




VHDL_FILE 

VHDL_FILE 

Type 

Associates a VHDL Source File (.vhd) with this project. 




Notes 


Syntax 

set_global_assignment -name VHDL_FILE 




VHDL_OUTPUT_FILE 

VHDL_OUTPUT_FILE 

Type 

Associates a VHDL Output File (.vho) with this project. 




Notes 


Syntax 

set_global_assignment -name VHDL_OUTPUT_FILE 




VHDL_TEST_BENCH_FILE 

VHDL_TEST_BENCH_FILE 

Type 

Associates a VHDL Test Bench File (.vht) with this project. 




Notes 


Syntax 

set_global_assignment -name VHDL_TEST_BENCH_FILE 




VQM_FILE 

VQM_FILE 

Type 

Associates a structural Verilog HDL source file (.v) with this project. 




Notes 


Syntax 

set_global_assignment -name VQM_FILE 




ZIP_VECTOR_WAVEFORM_FILE 


Type 

Associates a Compressed Vector Waveform File (.cvwf) with this project. 




Notes 


Syntax 

set_global_assignment -name ZIP_VECTOR_WAVEFORM_FILE 







FAST_INPUT_REGISTER 

Type 










June 2012 

2. Pin & Locations Assignments 

Implements an input register in a cell that has a fast, direct connection from an I/O 

pin. If such a fast, direct connection from the I/O pin is not available on the I/O cell 

hardware, this option instructs the Fitter to lock the input register in the logic array 

black (LAB) adjacent to the I/O cell feeding it. Turning on the Fast Input Register 

option can help maximize I/O timing performance, for example, by permitting fast 

setup times. Turning this option off for a particular signal prevents the Fitter from 

implementing the signal automatically in an I/O cell or locking down the input 

register in the LAB adjacent to the I/O cell. This option is ignored if it is applied to 

anything other than a register or an input or bidirectional pin that feeds a register. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





ISO 

9001:2008 

Registered 

Subscribe

2–2 Chapter 2: Pin & Locations Assignments 

FAST_INPUT_REGISTER 

■ MAX V 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

■ Stratix 






■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name FAST_INPUT_REGISTER -to -entity 



Chapter 2: Pin & Locations Assignments 2–3 

FAST_OCT_REGISTER 

FAST_OCT_REGISTER 

Type 

Implements an on-chip termination (OCT) register in a cell that has a fast, direct 

connection to an I/O pin. Turning on the Fast OCT Register option can help 

maximize I/O timing performance, for example, by permitting fast clock-to-output 

times. Turning this option off for a particular signal prevents the Fitter from 

implementing the signal automatically in an I/O cell. This option is ignored if it is 

applied to anything other than a register or an output or bidirectional pin fed by a 

register. 

Boolean 









■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name FAST_OCT_REGISTER -to -entity 




FAST_OUTPUT_ENABLE_REGISTER 


Type 

Implements an output enable register in a cell that has a fast, direct connection to an 

I/O pin. If such a fast, direct connection to the I/O pin is not available in the I/O cell 

hardware, this option instructs the Fitter to lock the output enable register in the LAB 

adjacent to the I/O cell it is feeding.Turning on the Fast Output Enable Register 

option can help maximize I/O timing performance, for example, by permitting fast 

clock-to-output times. Turning this option off for a particular signal prevents the Fitter 

from implementing the signal automatically in an I/O cell or locking down the output 

enable register in the LAB adjacent to the I/O cell. This option is ignored if it is 

applied to anything other than a register or an output or bidirectional pin fed by a 

register. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER -to -entity 

 




FAST_OUTPUT_REGISTER 


Type 

Implements an output register in a cell that has a fast, direct connection to an I/O pin. 

If such a fast, direct connection to the I/O pin is not available in the I/O cell 

hardware, this option instructs the Fitter to lock the output register in the LAB 

adjacent to the I/O cell it is feeding.Turning on the Fast Output Register option can 

help maximize I/O timing performance, for example, by permitting fast clock-tooutput 

times. Turning this option off for a particular signal prevents the Fitter from 

implementing the signal automatically in an I/O cell or locking down the output 

register in the LAB adjacent to the I/O cell. This option is ignored if it is applied to 

anything other than a register or an output or bidirectional pin fed by a register. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name FAST_OUTPUT_REGISTER -to -entity 

 




IP_DEBUG_VISIBLE 

IP_DEBUG_VISIBLE 

Type 

When assigned to an Encrypted IP node, this option directs the Quartus II software to 

display the node in the Node Finder. 

Boolean 



Syntax 

set_instance_assignment -name IP_DEBUG_VISIBLE -to -entity 




LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT 

LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT 

Type 

Allows the specified I/O pin to ignore security constraints. 

Boolean 



Notes 



devices. 

The value of this assignment must be a node name. 

Syntax 

set_instance_assignment -name LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT -to 

-entity 




LOCATION 

LOCATION 

Type 

Assigns a location on the device for the current node(s) and/or pin(s). 

Location 



Notes 


Syntax 

set_location_assignment -to 

Example 

set_location_assignment -to dst LOC 




MAX7K_CLIQUE_TYPE 

MAX7K_CLIQUE_TYPE 

Type 

Specifies the type of a clique. 

Enumeration 

■ LAB 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Syntax 

set_global_assignment -name MAX7K_CLIQUE_TYPE -entity - 

section_id 

Default Value 

LAB, requires section identifier and entity name 




MEMBER_OF 

MEMBER_OF 

Type 

Assigns one or more currently selected nodes and/or entities to a clique, which is a 

group of functions that the Compiler attempts to place together in the same area. You 

must also assign a name to the clique. A clique assignment allows you to group all 

logic on a speed-critical path to help achieve optimum performance. 

String 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_instance_assignment -name MEMBER_OF -to -entity - 

section_id 




PIN_CONNECT_FROM_NODE 

PIN_CONNECT_FROM_NODE 

Type 

Directs the Compiler to generate a device pin with the specified name and connect the 

device pin to an internal signal. 

String 



Notes 


Syntax 

set_instance_assignment -name PIN_CONNECT_FROM_NODE -to 




RESERVE_PIN 

RESERVE_PIN 

Type 

Reserves the pin in one of the following seven states: 

■ As an input that is tri-stated 

■ As an output that drives ground 

■ As an output that drives VCC 

■ As an output that drives an unspecified signal 

■ As SignalProbe output 

■ As a voltage reference (VREF) 

■ As bidirectional 

The As VREF setting is not appropriate for all device families. For more information 

about V REF support, refer to the device data sheet. 

Enumeration 

■ As SignalProbe output 

■ As VREF 


■ As bidirectional 

■ As input tri-stated 

■ As output driving VCC 

■ As output driving an unspecified signal 

■ As output driving ground 


Syntax 

set_instance_assignment -name RESERVE_PIN -to 

set_global_assignment -name RESERVE_PIN 

Old Names 


software: 

RESERVED_PIN 




SUBCLIQUE_OF 

SUBCLIQUE_OF 

Type 

Specifies that the current clique is a member of another clique. 

String 



Notes 


Syntax 

set_instance_assignment -name SUBCLIQUE_OF -to -entity - 

section_id 




VIRTUAL_PIN 

VIRTUAL_PIN 

Type 

Specifies whether an I/O element in a lower-level design entity can be temporarily 

mapped to a logic element and not to a pin during compilation. The virtual pin is then 

implemented as a LUT. This option should be specified only for I/O elements that 

become nodes when imported to the top-level design. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Notes 





VIRTUAL_PIN 

Syntax 

set_instance_assignment -name VIRTUAL_PIN -to -entity 

 




VIRTUAL_PIN 



ASSIGNMENT_GROUP_EXCEPTION 

Type 










June 2012 

3. Assignment Group Assignments 

Defines a node or nodes to be excluded as an exception to a previously added 

member. The node can be an instance name or a wildcard representing multiple 

instance names. 

String 



Notes 


Syntax 

set_global_assignment -name ASSIGNMENT_GROUP_EXCEPTION -section_id 

 

ISO 

9001:2008 

Registered 

Subscribe

3–2 Chapter 3: Assignment Group Assignments 

ASSIGNMENT_GROUP_MEMBER 

ASSIGNMENT_GROUP_MEMBER 

Type 

Defines an element of a group. The element can be an instance name or a wildcard 

representing multiple instance names 

String 



Notes 


Syntax 

set_global_assignment -name ASSIGNMENT_GROUP_MEMBER -section_id 



ADV_NETLIST_OPT_ALLOWED 

Type 










June 2012 

4. Analysis & Synthesis Assignments 

Specifies whether the Compiler should perform advanced netlist optimizations, such 

as gate-level retiming or physical synthesis, on the specified node or entity. 

You can choose one of the following settings: 

■ Always Allow—Allows the Compiler to alter the node or entity, even if doing so 

affects the timing or performance of the design. Altera does not recommend using 

this setting. 

■ Never Allow—Prevents the Compiler from altering the node or entity. 

■ Default—Allows the Compiler to duplicate, move, or change the synthesis of the 

node or entity, or allows register retiming during netlist optimization, only if 

doing so does not negatively affect the timing or performance of the design. 

You can use this option to preserve I/O timing on specific pins and registers in a 

design in which you want to perform netlist optimization. This option is also useful 

for preserving the synthesis of a specific node or entity, for example, preserving the 

name of a register. 

This option can be assigned to individual nodes or design entities only. 

Enumeration 

■ Always Allow 

■ Default 


■ Never Allow 


■ Arria GX 



■ Arria V 

■ Cyclone 


ISO 

9001:2008 

Registered 

Subscribe

4–2 Chapter 4: Analysis & Synthesis Assignments 

ADV_NETLIST_OPT_ALLOWED 





■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Syntax 

set_global_assignment -name ADV_NETLIST_OPT_ALLOWED -entity 

 

set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED -to -entity 

 

Example 

set_instance_assignment -name adv_netlist_opt_allowed "always allow" -to 

reg 



Chapter 4: Analysis & Synthesis Assignments 4–3 

ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP 


Type 

Specifies whether to perform WYSIWYG primitive resynthesis during synthesis. This 

option uses the setting specified in the Optimization Technique logic option. 

This option is useful for resynthesizing some or all of the WYSIWYG primitives in the 

design for better area or performance. 

This option defaults to Off. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP 

set_instance_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP -to 

-entity 

Example 

set_global_assignment -name adv_netlist_opt_synth_wysiwyg_remap on 

set_instance_assignment -name adv_netlist_opt_synth_wysiwyg_remap on -to 

foo 

Default Value 

Off 




ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION 


Type 

Allows the Compiler to infer RAMs of any size, even if they do not meet the current 

minimum requirements. 

This option is useful for minimizing the area of a design that is close to the device 

limit. 

This option can be used as a project-wide option, or assigned to a design entity. 


Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 




■ Stratix 






■ Stratix V 

Notes 

This assignment is included in the Analysis & Synthesis report. 





Syntax 

set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION 

set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION -entity 

 

set_instance_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION -to 

-entity 

Example 

set_global_assignment -name allow_any_ram_size_for_recognition off 

set_instance_assignment -name allow_any_ram_size_for_recognition off -to 

foo 

Default Value 

Off 




ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION 


Type 

Allows the Compiler to infer ROMs of any size even if the ROMs do not meet the 

design’s current minimum size requirements. 


limit. 



Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 




■ Stratix 






■ Stratix V 

Notes 






Syntax 

set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION 

set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION -entity 

 

set_instance_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION -to 

-entity 

Example 

set_global_assignment -name allow_any_rom_size_for_recognition off 

set_instance_assignment -name allow_any_rom_size_for_recognition off -to 

foo 

Default Value 

Off 




ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION 


Type 

Allows the Compiler to infer shift registers of any size even if they do not meet the 

design's current minimum size requirements. 


limit. 



Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 




■ Stratix 






■ Stratix V 

Notes 






Syntax 

set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION 

 

set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION 

-entity 

set_instance_assignment -name 

ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION -to -entity 

Example 

set_global_assignment -name allow_any_shift_register_size_for_recognition 

off 


allow_any_shift_register_size_for_recognition off -to foo 

Default Value 

Off 




ALLOW_CHILD_PARTITIONS 

ALLOW_CHILD_PARTITIONS 

Type 

Specifies whether or not an instance or a section of design hierarchy can contain user 

partitions. 

A logic option that allows you to control whether or not an instance or entity can have 

child partitions. 

This option is useful to prevent a hierarchy from being partitioned. If applied globally, 

this option can also be used to prevent any user partitions from being created. 

Boolean 



Syntax 

set_global_assignment -name ALLOW_CHILD_PARTITIONS -entity 

 

set_instance_assignment -name ALLOW_CHILD_PARTITIONS -to -entity 

 

Example 

set_global_assignment -name allow_child_partitions off 

set_instance_assignment -name allow_child_partitions off -to "sub:inst" 




ALLOW_POWER_UP_DONT_CARE 

ALLOW_POWER_UP_DONT_CARE 

Type 

Causes registers that do not have a Power-Up Level logic option setting to power up 

with a don't care logic level (X). A Power-Up Don't Care setting allows the Compiler 

to change the power-up level of a register to minimize the area of the design. 

This option is useful for allowing the Compiler to change the power-up level of a 

register to minimize the area of the design. 

This option can be used as a project-wide option only. 

This option is turned on by default. 

Boolean 



Notes 


Syntax 

set_global_assignment -name ALLOW_POWER_UP_DONT_CARE 

Example 

set_global_assignment -name allow_power_up_dont_care off 

Default Value 

On 

See Also 

■ “POWER_UP_LEVEL” on page 4–139 




ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES 


Type 

Allows the Compiler to take shift registers from different hierarchies of your design 

and place the shift registers in the same RAM. 

Merging shift registers across hierarchies is good for logic utilization, as it allows 

more shift registers to be put in RAM, and it allows the different shift registers to 

share the same external counter logic. However, merging shift registers across 

hierarchies can be bad for timing as it pulls together registers from different unrelated 

hierarchies. 

When this option is set to Auto, the Compiler decides whether it wants to merge shift 

registers across hierarchies based on resource availability, timing and the 

Optimization Technique setting. When the option is set to On, shift registers are 

merged across hierarchies as much as possible. When the option is set to Off, shift 

registers are not be merged across hierarchies at all. This option is ignored when the 

Auto Shift Register Replacement setting is set to Off. 



Enumeration 

■ Always 

■ Auto 

■ Off 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 









■ MAX V 

■ Stratix 






■ Stratix V 

Notes 



Syntax 

set_global_assignment -name 

ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES 


ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES -entity 

 


ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES -to -entity 

Example 


allow_shift_register_merging_across_hierarchies off 


allow_shift_register_merging_across_hierarchies off -to foo 

Default Value 

Auto 




ALLOW_SYNCH_CTRL_USAGE 


Type 

Allows the Compiler to utilize synchronous clear and/or synchronous load signals in 

normal mode logic cells. Turning on this option helps to reduce the total number of 

logic cells used in the design, but might negatively impact the fitting since 

synchronous control signals are shared by all the logic cells in a LAB. 

This option is useful for finding areas of the design that can be implemented more 

efficiently with synchronous clear and/or synchronous load signals in normal mode 

logic cells, and as a result, minimize the number of logic cells used in the design. 


Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE 

set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE -entity 

 

set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE -to -entity 

 

Example 

set_global_assignment -name allow_synch_ctrl_usage off 

set_instance_assignment -name allow_synch_ctrl_usage off -to foo 

Default Value 

On 




ALLOW_XOR_GATE_USAGE 

ALLOW_XOR_GATE_USAGE 

Type 

Allows the Compiler to use the XOR gate that exists in a macrocell (that is, in an 

embedded cell within an Embedded System Block [ESB] that is set to use Product 

Term mode). This option is ignored if you select LUT or ROM as the setting for the 

Technology Mapper option. 

This option is ignored if it is assigned to anything other than a design entity. The 

Allow XOR Gate Usage option is also ignored if you select LUT or ROM as the setting 

for the Technology Mapper option. This option can be set in the Assignment Editor 

in the Assignments menu, the Analysis & Synthesis Settings page, or the Fitter 

Settings page of the Settings dialog box in the Assignments menu. This option is 

available for APEX 20K, APEX 20KC, APEX 20KE, APEX II, Excalibur, MAX 3000, 

MAX 7000A, MAX 7000AE, MAX 7000B, and MAX 7000S devices. 


Boolean 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_global_assignment -name ALLOW_XOR_GATE_USAGE 

set_global_assignment -name ALLOW_XOR_GATE_USAGE -entity 

 

set_instance_assignment -name ALLOW_XOR_GATE_USAGE -to -entity 

 

Example 

set_instance_assignment -name allow_xor_gate_usage off -to clock 

Default Value 

On 




AUTO_CARRY_CHAINS 


Type 

Allows the Compiler to create carry chains automatically by inserting CARRY_SUM 

buffers into the design. This option is also required to recognize carry chains in any 

design containing MAX+PLUS II-style CARRY buffers. The length of the chains is 

controlled with the Carry Chain Length option. If this option is turned off, CARRY 

buffers are ignored, but CARRY_SUM buffers are unaffected. The Auto Carry Chains 

option is ignored if you select Product Term or ROM as the setting for the Technology 

Mapper option. 


Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name AUTO_CARRY_CHAINS 

set_global_assignment -name AUTO_CARRY_CHAINS -entity 

 

set_instance_assignment -name AUTO_CARRY_CHAINS -to -entity 

Default Value 

On 




AUTO_CLOCK_ENABLE_RECOGNITION 


Type 

Allows the Compiler to find logic that feeds a register and move the logic to the 

register’s clock enable input port. 

This option can bet set to Off on individual registers or design entities to solve fitting 

and performance issues with designs that have many clock enables generated by 

Analysis & Synthesis. 


Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 





Notes 



Syntax 

set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION 

set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION -entity 

set_instance_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION -to - 

entity 

Example 

set_global_assignment -name auto_clock_enable_replacement off 

set_instance_assignment -name auto_clock_enable_replacement off -to reg 

Default Value 

On 




AUTO_DSP_RECOGNITION 


Type 

Allows the Compiler to find a multiply-accumulate function or a multiply-add 

function that can be replaced with the altmult_accum or the altmult_add 

megafunction. 


efficiently, and as a result, minimizing the area and maximizing the speed of the 

design. 



Boolean 



■ Arria GX 



■ Arria V 





■ Cyclone V 




■ Stratix 






■ Stratix V 

Notes 







Syntax 

set_global_assignment -name AUTO_DSP_RECOGNITION 

set_global_assignment -name AUTO_DSP_RECOGNITION -entity 

 

set_instance_assignment -name AUTO_DSP_RECOGNITION -to -entity 

 

Example 

set_global_assignment -name auto_dsp_recognition off 

set_instance_assignment -name auto_dsp_recognition off -to foo 

Default Value 

On 




AUTO_ENABLE_SMART_COMPILE 

AUTO_ENABLE_SMART_COMPILE 

Type 

Specifies whether the SignalTap II Logic Analyzer should perform a smart 

compilation if conditions exist in which you use incremental routing with the 

SignalTap II Logic Analyzer. 

Boolean 



Syntax 

set_global_assignment -name AUTO_ENABLE_SMART_COMPILE 




AUTO_GLOBAL_CLOCK_MAX 

AUTO_GLOBAL_CLOCK_MAX 

Type 

Allows the Compiler to choose the signal that feeds the most clock inputs to flipflops 

as a global clock signal that is made available throughout the device on the global 

routing paths. If you want to prevent the Compiler from automatically selecting a 

particular signal as global clock, set the Global Signal option to Off on that signal. 



Boolean 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Syntax 

set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX 

set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX -entity 

 

set_instance_assignment -name AUTO_GLOBAL_CLOCK_MAX -to -entity 

 

Example 

set_global_assignment -name auto_global_clock_max off 

set_instance_assignment -name auto_global_clock_max off -to foo 

Default Value 

On 

Old Names 


software: 

Auto Global Clock -- MAX 7000B/7000AE/3000A/7000S/7000A 




AUTO_GLOBAL_OE_MAX 

AUTO_GLOBAL_OE_MAX 

Type 

Allows the Compiler to choose the signal that feeds the most TRI buffers as a global 

output enable signal that is made available throughout the device on the global 


particular signal as global output enable, set the Global Signal option to Off on that 

signal. 



Boolean 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Syntax 

set_global_assignment -name AUTO_GLOBAL_OE_MAX 

set_global_assignment -name AUTO_GLOBAL_OE_MAX -entity 

 

set_instance_assignment -name AUTO_GLOBAL_OE_MAX -to -entity 

Example 

set_global_assignment -name auto_global_oe_max off 

set_instance_assignment -name auto_global_oe_max off -to foo 

Default Value 

On 

Old Names 


software: 

Auto Global Output Enable -- MAX 7000B/7000AE/3000A/7000S/7000A 




AUTO_LCELL_INSERTION 

AUTO_LCELL_INSERTION 

Type 

Allows the Compiler to insert macrocells into the design. This option is ignored if it is 

assigned to anything other than a design entity. If you want to prevent the Compiler 

from automatically inserting macrocells into the design, set the Auto Logic Cell 

Insertion option to Off on that signal. 



Boolean 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_global_assignment -name AUTO_LCELL_INSERTION 

set_global_assignment -name AUTO_LCELL_INSERTION -entity 

 

set_instance_assignment -name AUTO_LCELL_INSERTION -to -entity 

 

Example 

set_global_assignment -name auto_lcell_insertion off 

set_instance_assignment -name auto_lcell_insertion off -to foo 

Default Value 

On 




AUTO_OPEN_DRAIN_PINS 


Type 

Allows the Compiler to automatically convert a tri-state buffer with a strong low data 

input into the equivalent open-drain buffer. 

This option cannot be used with a netlists that are synthesized with third-party 

synthesis tools. To use this option, you must turn on the Perform WYSIWYG 

Primitive Resynthesis logic option. 



Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name AUTO_OPEN_DRAIN_PINS 

set_global_assignment -name AUTO_OPEN_DRAIN_PINS -entity 

 

set_instance_assignment -name AUTO_OPEN_DRAIN_PINS -to -entity 

 

Example 

set_global_assignment -name auto_open_drain_pins off 

set_instance_assignment -name auto_open_drain_pins off -to foo 

Default Value 

On 




AUTO_PARALLEL_EXPANDERS 

AUTO_PARALLEL_EXPANDERS 

Type 

Allows the Compiler to automatically create chains of parallel expander product 

terms. Parallel expanders are available in macrocells, that is, embedded cells within 

an Embedded System Block [ESB] that is set to use Product Term mode. The length of 

the chains is controlled with the Parallel Expander Chain Length option. The Auto 

Parallel Expanders option is ignored if you select LUT or ROM as the setting for the 

Technology Mapper option. 

This option can be set in the Assignment Editor in the Assignments menu, the 

Analysis & Synthesis Settings page, or the Fitter Settings page of the Settings dialog 

box in the Assignments menu. This option is available for APEX 20K, APEX 20KC, 

APEX 20KE, APEX II, Excalibur, MAX 3000, MAX 7000AE, MAX 7000B, and MAX 

7000S devices. 


Boolean 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_global_assignment -name AUTO_PARALLEL_EXPANDERS 

set_global_assignment -name AUTO_PARALLEL_EXPANDERS -entity 

 

set_instance_assignment -name AUTO_PARALLEL_EXPANDERS -to -entity 

 

Example 

set_instance_assignment -name auto_parallel_expanders on -to clock 

Default Value 

On 




AUTO_RAM_BLOCK_BALANCING 


Type 

Enables the Compiler to automatically use different memory types when using auto 

RAM blocks and allows the Compiler to use different RAM partitions with the same 

memory types. 



design. During design fitting, a megafunction may use a RAM partition that cannot fit 

in the design due to unbalanced use of RAM resources. The logic option allows the 

Compiler to dynamically change RAM partitions and balance resource usage when 

using different RAM block types. 



Boolean 



■ Arria GX 



■ Cyclone 








■ Stratix 






Notes 






Syntax 

set_global_assignment -name AUTO_RAM_BLOCK_BALANCING 

Example 

set_global_assignment -name auto_ram_block_balancing off 

Default Value 

On 




AUTO_RAM_RECOGNITION 


Type 

Allows the Compiler to find a set of registers and logic that can be replaced with the 

altsyncram or the lpm_ram_dp megafunction. Turning on this option may change the 

functionality of the design. 



design. 



Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 




■ Stratix 






■ Stratix V 





Notes 



Syntax 

set_global_assignment -name AUTO_RAM_RECOGNITION 

set_global_assignment -name AUTO_RAM_RECOGNITION -entity 

 

set_instance_assignment -name AUTO_RAM_RECOGNITION -to -entity 

 

Example 

set_global_assignment -name auto_ram_recognition off 

set_instance_assignment -name auto_ram_recognition off -to foo 

Default Value 

On 




AUTO_RAM_TO_LCELL_CONVERSION 


Type 

Allows the Compiler to convert small RAM blocks into logic cells. 

Boolean 



■ Arria GX 



■ Cyclone 









■ Stratix 






Notes 


Syntax 

set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION 

set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION -entity 

set_instance_assignment -name AUTO_RAM_TO_LCELL_CONVERSION -to - 

entity 





Default Value 

Off 




AUTO_RESOURCE_SHARING 

AUTO_RESOURCE_SHARING 

Type 

Allows the Compiler to share hardware resources among many similar, but mutually 

exclusive, operations in your HDL source code. If you enable this option, the 

Compiler will merge compatible addition, subtraction, and multiplication operations. 

By merging operations, this may reduce the area required by your design. Because 

resource sharing introduces extra muxing and control logic on each shared resource, it 

may negatively impact the final f max of your design. 

Boolean 



Notes 


Syntax 

set_global_assignment -name AUTO_RESOURCE_SHARING 

set_global_assignment -name AUTO_RESOURCE_SHARING -entity 

 

set_instance_assignment -name AUTO_RESOURCE_SHARING -to -entity 

 

Default Value 

Off 




AUTO_ROM_RECOGNITION 


Type 

Allows the Compiler to find logic that can be replaced with the altsyncram or the 

lpm_rom megafunction. Turning on this option may change the power-up state of the 

design. 



design. 



Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 




■ Stratix 






■ Stratix V 





Notes 



Syntax 

set_global_assignment -name AUTO_ROM_RECOGNITION 

set_global_assignment -name AUTO_ROM_RECOGNITION -entity 

 

set_instance_assignment -name AUTO_ROM_RECOGNITION -to -entity 

 

Example 

set_global_assignment -name auto_rom_recognition off 

set_instance_assignment -name auto_rom_recognition off -to foo 

Default Value 

On 




AUTO_SHIFT_REGISTER_RECOGNITION 


Type 

Allows the Compiler to find a group of shift registers of the same length that can be 

replaced with the altshift_taps megafunction. The shift registers must all use the same 

clock and clock enable signals, must not have any other secondary signals, and must 

have equally spaced taps that are at least three registers apart. 



design. 



Enumeration 

■ Always 

■ Auto 

■ Off 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 



Syntax 

set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION 

set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION -entity 

 

set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION -to - 

entity 

Example 

set_global_assignment -name auto_shift_register_recognition off 

set_instance_assignment -name auto_shift_register_recognition off -to foo 

Default Value 

Auto 




BLOCK_DESIGN_NAMING 


Type 

Specifies the naming scheme used for the block design. This option is ignored if it is 

assigned to anything other than a design entity. 

The following three settings are available: 

■ MAX+PLUS II—This option specifies the naming scheme used in previous 

versions of the Quartus II software. 

■ Quartus II—This option specifies the new naming scheme on block designs. When 

a bus is split, the resulted pins are named with a base name followed by square 

brackets, with indicies between the bracket pair. 

■ Auto—This option informs the Quartus II software to use the naming scheme that 

is specified by the source file. 

This option is useful if your design contains design files that are generated by the 

Quartus II software versions 7.2 and earlier. You can use this option to specify which 

naming scheme you want the Quartus II software to use on the specified design entity. 

This option can be used as a project-wide option, or assigned to a block design entity. 

This option defaults to Auto. 

Enumeration 

■ Auto 

■ MaxPlusII 

■ QuartusII 



Notes 


Syntax 

set_global_assignment -name BLOCK_DESIGN_NAMING -entity 

 

set_instance_assignment -name BLOCK_DESIGN_NAMING -to -entity 

set_global_assignment -name BLOCK_DESIGN_NAMING 

Example 

set_global_assignment -name block_design_naming MaxPlusII 

set_instance_assignment -name block_design_naming MaxPlusII -to top 





Default Value 

Auto 




CLKLOCKX1_INPUT_FREQ 

CLKLOCKX1_INPUT_FREQ 

Type 

Creates an internal ClockLock phase-locked loop (PLL) and specifies its frequency. 

Turning this option on is equivalent to instantiating an altclklock megafunction with 

either of its ClockBoost parameters set to a value of 1. The CLKLOCKx1 Input 

Frequency option is provided primarily for backward compatibility with MAX+PLUS 

II designs. Altera recommends using the MegaWizard Plug-In Manager to instantiate 

PLLs in new designs. This option is ignored if it is assigned to anything other than an 

input pin or to a device that does not have the PLL feature. 

Frequency 



■ Arria GX 



■ Cyclone 









■ Stratix 






Syntax 

set_instance_assignment -name CLKLOCKX1_INPUT_FREQ -to -entity 

 




CYCLONEII_OPTIMIZATION_TECHNIQUE 


Type 

Specifies the overall optimization goal for Analysis & Synthesis, that is, whether to 

attempt to maximize performance, minimize logic usage, or balance high 

performance with minimal logic usage during compilation. 

You can select one of the following settings: 

■ Area—The Compiler makes the design as small as possible in order to minimize 

resource usage 

■ Speed—The Compiler chooses a design implementation that has the fastest f max 

■ Balanced—The Compiler chooses a design implementation that balances high 

performance with minimal logic usage 


This option defaults to Balanced. 

Enumeration 

■ Area 

■ Balanced 

■ Speed 








Notes 


Syntax 

set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE 

set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE -entity 

 

set_instance_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE -to - 

entity 

Example 

set_global_assignment -name cycloneii_optimization_technique speed 





Default Value 

Balanced 

Old Names 


software: 

Optimization Technique -- Cyclone II/Cyclone III 




CYCLONE_OPTIMIZATION_TECHNIQUE 


Type 

Specifies the overall optimization goal for Analysis & Synthesis, that is, whether to 

attempt to maximize performance, minimize logic usage, or balance high 

performance with minimal logic usage during compilation. 




■ Speed—The Compiler chooses a design implementation that has the fastest f max 





Enumeration 

■ Area 

■ Balanced 

■ Speed 



■ Cyclone 

Notes 


Syntax 

set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE 

set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE -entity 

set_instance_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE -to - 

entity 

Example 

set_global_assignment -name cyclone_optimization_technique speed 

Default Value 

Balanced 





Old Names 


software: 

Optimization Technique -- Cyclone 




DEVICE_FILTER_PACKAGE 

DEVICE_FILTER_PACKAGE 

Type 

Package filter for available devices. 

String 



Syntax 

set_global_assignment -name DEVICE_FILTER_PACKAGE 

Default Value 

Any 




DEVICE_FILTER_PIN_COUNT 

DEVICE_FILTER_PIN_COUNT 

Type 

Pin count filter for available devices. 

String 



Syntax 

set_global_assignment -name DEVICE_FILTER_PIN_COUNT 

Default Value 

Any 




DEVICE_FILTER_SPEED_GRADE 

DEVICE_FILTER_SPEED_GRADE 

Type 

Speed grade filter for available devices. 

String 



Syntax 

set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 

Default Value 

Any 




DEVICE_FILTER_VOLTAGE 

DEVICE_FILTER_VOLTAGE 

Type 

Voltage filter for available devices. 

String 



Syntax 

set_global_assignment -name DEVICE_FILTER_VOLTAGE 




DISABLE_OCP_HW_EVAL 

DISABLE_OCP_HW_EVAL 

Type 

Turns off OpenCore Plus hardware evaluation feature. 

Boolean 



Notes 


Syntax 

set_global_assignment -name DISABLE_OCP_HW_EVAL 

Default Value 

Off 




DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES 

DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES 

Type 

Specifies whether registers that are in different hierarchies are allowed to be merged if 

their inputs are the same. 

Enumeration 

■ Auto 

■ Off 

■ On 



Notes 


Syntax 

set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES 

 

Default Value 

Auto 




DONT_MERGE_REGISTER 

DONT_MERGE_REGISTER 

Type 

When set to On, this option prevents the specified register from merging with other 

registers, and prevents other registers from merging with the specified register. 

You can use this option to instruct the Compiler to use the user-specified timing 

constraints on the register during synthesis. For example, if the register has a 

multicycle constraint, this option prevents the Compiler from merging other registers 

into the specified register, avoiding unintended timing and functional effects. 

This option is different from Preserve Register logic option because it does not 

prevent a register with constant drivers or a redundant register from being removed. 

In addition, this option prevents other registers from merging with the specified 

register. 

This option is ignored if the register does not drive anything or if it has constant 

drivers, in which case the register is removed during synthesis. 

This option is ignored if it is applied to anything other than a register or a design 

entity containing registers. 

Boolean 



Notes 


Syntax 

set_global_assignment -name DONT_MERGE_REGISTER -entity 

 

set_instance_assignment -name DONT_MERGE_REGISTER -to -entity 

Example 

set_instance_assignment -name dont_merge_register on -to foo 




DQS_DELAY 

DQS_DELAY 

Type 

Increases the propagation delay from a DQS I/O pin to the interior of the device. This 

option is used to center-align the DQS signal to the DQ data signals and should be 

selected to ensure the desired setup and hold margins across process, voltage, and 

temperature ranges. 

Time 



■ Cyclone 





Syntax 

set_instance_assignment -name DQS_DELAY -to -entity 

 




DQS_FREQUENCY 

DQS_FREQUENCY 

Type 

Specifies the DQS system clock frequency by which data is transferred between a 

device and an external RAM that uses double data rate (DDR). You can specify the 

desired frequency setting. 

Frequency 



■ Cyclone 






■ Stratix 


Syntax 

set_instance_assignment -name DQS_FREQUENCY -to -entity 

 




DQS_SHIFT 

DQS_SHIFT 

Type 

Specifies the interval of arrival between the DQ data signals and DQS signal during 

data transfer between a device and an external RAM that uses DDR. This option is 

ignored if it is applied to anything other than pins intended for use with the dedicated 

DDR SDRAM interface. 

Enumeration 


■ Phase of 0 degrees 




■ Stratix 


Syntax 

set_instance_assignment -name DQS_SHIFT -to -entity 

 




DQS_SYSTEM_CLOCK 

DQS_SYSTEM_CLOCK 

Type 

Specifies the clock input used as a frequency reference for a DQS I/O pin. The clock is 

the pin that drives the DDIO circuitry for the dedicated DDR SDRAM interface. 

String 



■ Stratix 


Notes 


Syntax 

set_instance_assignment -name DQS_SYSTEM_CLOCK -to -entity 




DSE_SYNTH_EXTRA_EFFORT_MODE 

DSE_SYNTH_EXTRA_EFFORT_MODE 

Type 

Specifies the Design Space Explorer synthesis extra effort mode. 

Enumeration 

■ MODE_1 

■ MODE_2 

■ MODE_3 

■ MODE_4 

■ MODE_5 


■ MODE_DEFAULT 


Syntax 

set_global_assignment -name DSE_SYNTH_EXTRA_EFFORT_MODE 




DSP_BLOCK_BALANCING 


Type 

Allows you to control the conversion of certain DSP block slices during DSP block 

balancing. 

This option is useful for controlling the DSP block balancer when it produces results 

that conflict with your design, such as converting DSP block slices that you do not 

want to be converted. 


■ Auto 

■ Off 

■ DSP blocks 

■ Logic Elements 

■ Simple Multipliers 

■ Width 18-bit Multipliers 

■ Simple 18-bit Multipliers 


Enumeration 

■ Auto 

■ DSP blocks 

■ Logic Elements 

■ Off 


■ Simple 18-bit Multipliers 

■ Simple Multipliers 

■ Width 18-bit Multipliers 


■ Arria GX 



■ Arria V 










■ Cyclone V 




■ Stratix 






■ Stratix V 

Notes 


Syntax 

set_global_assignment -name DSP_BLOCK_BALANCING -entity 

 

set_instance_assignment -name DSP_BLOCK_BALANCING -to -entity 

set_global_assignment -name DSP_BLOCK_BALANCING 

Example 

set_global_assignment -name dsp_block_balancing "dsp blocks" 

set_instance_assignment -name dsp_block_balancing "logic elements" -to 

mult0 

Default Value 

Auto 




EDA_DESIGN_ENTRY_SYNTHESIS_TOOL 

EDA_DESIGN_ENTRY_SYNTHESIS_TOOL 

Type 

Specifies the third-party EDA tool used for design entry/synthesis 

String 



Notes 


Syntax 

set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL 

set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL -entity 

 

Default Value 

None 




EDA_INPUT_DATA_FORMAT 

EDA_INPUT_DATA_FORMAT 

Type 

Specifies the format of the input data read from other EDA design entry/synthesis 

tools. 

String 



Syntax 

set_global_assignment -name EDA_INPUT_DATA_FORMAT -section_id 

set_global_assignment -name EDA_INPUT_DATA_FORMAT -entity - 

section_id 

Default Value 

None, requires section identifier 




EDA_INPUT_GND_NAME 

EDA_INPUT_GND_NAME 

Type 

Specifies the global high signal used in the files generated by the EDA synthesis tool, 

which is GND. 

String 



Syntax 

set_global_assignment -name EDA_INPUT_GND_NAME -section_id 

set_global_assignment -name EDA_INPUT_GND_NAME -entity - 

section_id 

Default Value 

GND, requires section identifier 




EDA_INPUT_VCC_NAME 

EDA_INPUT_VCC_NAME 

Type 

Specifies the global power-down signal. 

String 



Syntax 

set_global_assignment -name EDA_INPUT_VCC_NAME -section_id 

set_global_assignment -name EDA_INPUT_VCC_NAME -entity - 

section_id 

Default Value 

VCC, requires section identifier 




EDA_LMF_FILE 

EDA_LMF_FILE 

Type 

Specifies the default Library Mapping File (.lmf) for the current compilation. 




Notes 


Syntax 

set_global_assignment -name EDA_LMF_FILE -section_id 

 

set_global_assignment -name EDA_LMF_FILE -entity -section_id 

 




EDA_RUN_TOOL_AUTOMATICALLY 

EDA_RUN_TOOL_AUTOMATICALLY 

Type 

Runs the third-party EDA tool automatically from Quartus II when a design is 

compiled. 

Boolean 



Syntax 

set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY -section_id 

 

set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY -entity -section_id 

Default Value 

Off, requires section identifier 




EDA_SHOW_LMF_MAPPING_MESSAGES 

EDA_SHOW_LMF_MAPPING_MESSAGES 

Type 

Determines whether to display messages describing the mappings used in the Library 

Mapping File (.lmf). 

Boolean 



Syntax 

set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES -section_id 

 

set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES -entity -section_id 

Default Value 





EDA_VHDL_LIBRARY 

EDA_VHDL_LIBRARY 

Type 

Specifies the logical name of a user-defined VHDL design library, which is a physical 

name. 

String 



Notes 


Syntax 

set_instance_assignment -name EDA_VHDL_LIBRARY -to -section_id 

 

set_instance_assignment -name EDA_VHDL_LIBRARY -to -entity -section_id 




ENABLE_IP_DEBUG 

ENABLE_IP_DEBUG 

Type 

Make certain nodes (for example, important registers, pins, and state machines) 

visible for all the MegaCore functions in a design. You can use a MegaCore function’s 

nodes to effectively debug the megafunction, particularly when using the 

megafunction with the SignalTap II Logic Analyzer. The Node Finder, using SignalTap 

II Logic Analyzer filters, displays all the nodes that Analysis & Synthesis makes 

visible. When making the debugging nodes visible, Analysis & Synthesis can change 

the f max and number of logic cells in MegaCore functions. 

Boolean 



Notes 


Syntax 

set_global_assignment -name ENABLE_IP_DEBUG 

Default Value 

Off 




ENABLE_M512 

ENABLE_M512 

Type 

Enables the Compiler to use M512 memory blocks in a design. Because HardCopy II 

designs do not support M512 memory blocks, this option is useful when you migrate 

a compiled Stratix II design to a HardCopy II design. 



Boolean 



■ Arria GX 

■ Cyclone 



■ MAX V 

■ Stratix 




Notes 


Syntax 

set_global_assignment -name ENABLE_M512 

Example 

set_global_assignment -name enable_m512 off 




EXTRACT_VERILOG_STATE_MACHINES 

EXTRACT_VERILOG_STATE_MACHINES 

Type 

Allows the Compiler to extract state machines from Verilog Design Files (.v). The 

Compiler optimizes state machines using special techniques to reduce area and/or 

improve performance. If set to Off, the Compiler extracts and optimizes state 

machines in Verilog Design Files (.v) as regular logic. 

This option is useful for preventing automatic state machine optimizations to 

manually optimized logic. 



Boolean 



Notes 


Syntax 

set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES 

Example 

set_global_assignment -name extract_verilog_state_machines off 

Default Value 

On 

See Also 

■ “STATE_MACHINE_PROCESSING” on page 4–158 

■ “EXTRACT_VHDL_STATE_MACHINES” on page 4–74 




EXTRACT_VHDL_STATE_MACHINES 

EXTRACT_VHDL_STATE_MACHINES 

Type 

Allows the Compiler to extract state machines from VHDL Design Files (.vhd). The 

Compiler optimizes state machines using special techniques to reduce area and/or 

improve performance. If set to Off, the Compiler extracts and optimizes state 

machines in VHDL Design Files (.vhd) as regular logic. 

This option is useful for preventing automatic state machine optimizations to 

manually optimized logic. 



Boolean 



Notes 


Syntax 

set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES 

Example 

set_global_assignment -name extract_vhdl_state_machines off 

Default Value 

On 

See Also 


■ “EXTRACT_VERILOG_STATE_MACHINES” on page 4–73 




FAMILY 

FAMILY 

Type 

Specifies the device family to use for compilation. 

String 



C 

Notes 



Syntax 

set_global_assignment -name FAMILY 

Default Value 

Cyclone IV GX 




FORCE_SYNCH_CLEAR 


Type 

Forces the Compiler to use synchronous clear signals in normal mode logic cells. 

Turning on this option helps to reduce the total number of logic cells used in the 

design, but might negatively impact the fitting since synchronous control signals are 

shared by all the logic cells in a LAB. 


Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name FORCE_SYNCH_CLEAR 

set_global_assignment -name FORCE_SYNCH_CLEAR -entity 

 

set_instance_assignment -name FORCE_SYNCH_CLEAR -to -entity 

Example 

set_global_assignment -name force_synch_clear on 

set_instance_assignment -name force_synch_clear on -to foo 

Default Value 

Off 

See Also 

■ “ALLOW_SYNCH_CTRL_USAGE” on page 4–15 




HDL_INITIAL_FANOUT_LIMIT 

HDL_INITIAL_FANOUT_LIMIT 

Type 

Directs the Quartus II Integrated Synthesis to check the initial fan-out of each net in 

the netlist immediately after elaboration but prior to any netlist optimizations. If the 

fan-out for a net in the post-elaboration netlist exceeds the specified limit, the Quartus 

II Integrated Synthesis issues a warning. The post-elaboration netlist is the initial 

netlist created by elaborating a single entity in your HDL source. Later synthesis and 

fitter optimizations may reduce or increase the fan-out of the nets in the netlist. 

This option is useful for identifying high-fanout signals early in the design process. 

This option is ignored if applied to anything other than an entity or an instance of an 

entity. 

Integer 



Syntax 

set_global_assignment -name HDL_INITIAL_FANOUT_LIMIT -entity 

 

set_instance_assignment -name HDL_INITIAL_FANOUT_LIMIT -to -entity 

 

Example 

set_instance_assignment -name hdl_initial_fanout_limit 100 -to foo 




HDL_MESSAGE_LEVEL 

HDL_MESSAGE_LEVEL 

Type 

Specifies the type of HDL messages you want to view, including messages that 

display processing errors in the HDL source code. 

■ Level1—Allows you to view only the most important HDL messages. 

■ Level2—Allows you to view most HDL messages, including warning and 

information based messages. 

■ Level3—Allows you to view all HDL messages, including warning and 

information based messages and alerts about potential design problems or lint 

errors. 

Enumeration 

■ Level1 

■ Level2 

■ Level3 



Notes 


Syntax 

set_global_assignment -name HDL_MESSAGE_LEVEL 

Default Value 

Level2 




HDL_MESSAGE_OFF 

HDL_MESSAGE_OFF 

Type 

Specifies the list of HDL message IDs you want to turn off for this project. 

Integer 


The value must be from 10000 to 11000 


Notes 


Syntax 

set_global_assignment -name HDL_MESSAGE_OFF 




HDL_MESSAGE_ON 

HDL_MESSAGE_ON 

Type 

Specifies the list of HDL message IDs you want to turn on for this project. 

Integer 


The value must be from 10000 to 11000 


Notes 


Syntax 

set_global_assignment -name HDL_MESSAGE_ON 




HPS_PARTITION 

HPS_PARTITION 

Type 

Specifies whether an entity or instance is a special-purpose partition that models the 

internals of the Hard Processor System (HPS). 

Boolean 



Syntax 

set_global_assignment -name HPS_PARTITION -entity 

set_instance_assignment -name HPS_PARTITION -to -entity 

 

Example 

set_instance_assignment -name hps_partition on -entity hps 




IGNORE_CARRY_BUFFERS 

IGNORE_CARRY_BUFFERS 

Type 

Ignores CARRY_SUM buffers that are instantiated in the design. The Ignore CARRY 

Buffers option is ignored if it is applied to anything other than an individual 

CARRY_SUM buffer or to a design entity containing CARRY_SUM buffers. This 

option also applies to MAX+PLUS II-style CARRY buffers. 


Boolean 



Notes 


Syntax 

set_global_assignment -name IGNORE_CARRY_BUFFERS 

set_global_assignment -name IGNORE_CARRY_BUFFERS -entity 

 

set_instance_assignment -name IGNORE_CARRY_BUFFERS -to -entity 

 

Example 

set_global_assignment -name ignore_carry_buffers on 

set_instance_assignment -name ignore_carry_buffers on -to foo 

Default Value 

Off 




IGNORE_CASCADE_BUFFERS 

IGNORE_CASCADE_BUFFERS 

Type 

Ignores CASCADE buffers that are instantiated in the design. This option is ignored if 

it is applied to anything other than an individual CASCADE buffer or a design entity 

containing CASCADE buffers. 


Boolean 



Notes 


Syntax 

set_global_assignment -name IGNORE_CASCADE_BUFFERS 

set_global_assignment -name IGNORE_CASCADE_BUFFERS -entity 

 

set_instance_assignment -name IGNORE_CASCADE_BUFFERS -to -entity 

 

Example 

set_global_assignment -name ignore_cascade_buffers on 

set_instance_assignment -name ignore_cascade_buffers on -to foo 

Default Value 

Off 




IGNORE_GLOBAL_BUFFERS 

IGNORE_GLOBAL_BUFFERS 

Type 

Ignores GLOBAL buffers that are instantiated in the design. This option is ignored if it 

is applied to anything other than an individual GLOBAL buffer or a design entity 

containing GLOBAL buffers. 

Boolean 



Notes 


Syntax 

set_global_assignment -name IGNORE_GLOBAL_BUFFERS 

set_global_assignment -name IGNORE_GLOBAL_BUFFERS -entity 

 

set_instance_assignment -name IGNORE_GLOBAL_BUFFERS -to -entity 

 

Default Value 

Off 




IGNORE_LCELL_BUFFERS 


Type 

Ignores LCELL buffers that are instantiated in the design. This option is ignored if it is 

applied to anything other than an individual LCELL buffer or a design entity 

containing LCELL buffers. 


Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Notes 






Syntax 

set_global_assignment -name IGNORE_LCELL_BUFFERS 

set_global_assignment -name IGNORE_LCELL_BUFFERS -entity 

 

set_instance_assignment -name IGNORE_LCELL_BUFFERS -to -entity 

 

Example 

set_global_assignment -name ignore_lcell_buffers on 

set_instance_assignment -name ignore_lcell_buffers on -to foo 

Default Value 

Off 




IGNORE_MAX_FANOUT_ASSIGNMENTS 


Type 

Directs the Compiler to ignore the Maximum Fan-Out assignments on a node, an 

entity, or the whole design. For HCII migration, the Maximum Fan-Out assignments 

can cause mismatches in Revision Compare. One can remove the Maximum Fan-Out 

assignments from the project but it is inconvenient/impossible as some assignments 

are embedded in the HDL sources. One should turn on this assignment to direct 

Quartus II to ignore the Maximum Fan-Out assignments. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS 

set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS -entity 

set_instance_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS -to - 

entity 

Default Value 

Off 




IGNORE_ROW_GLOBAL_BUFFERS 

IGNORE_ROW_GLOBAL_BUFFERS 

Type 

Ignores ROW GLOBAL buffers that are instantiated in the design. This option is 

ignored if it is applied to anything other than an individual GLOBAL buffer or a 

design entity containing GLOBAL buffers. 

Boolean 



Notes 


Syntax 

set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS 

set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS -entity 

set_instance_assignment -name IGNORE_ROW_GLOBAL_BUFFERS -to -entity 

 

Default Value 

Off 




IGNORE_SOFT_BUFFERS 


Type 

Ignores SOFT buffers that are instantiated in the design. This option is ignored if it is 

applied to anything other than an individual SOFT buffer or a design entity 

containing SOFT buffers. 


Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Notes 






Syntax 

set_global_assignment -name IGNORE_SOFT_BUFFERS 

set_global_assignment -name IGNORE_SOFT_BUFFERS -entity 

 

set_instance_assignment -name IGNORE_SOFT_BUFFERS -to -entity 

Example 

set_global_assignment -name ignore_soft_buffers off 

set_instance_assignment -name ignore_soft_buffers off -to foo 

Default Value 

On 




IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF 

IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF 

Type 

Instructs Analysis & Synthesis to ignore all translate_off or synthesis_off 

synthesis directives in your Verilog and VHDL design files. You can use this option to 

disable these synthesis directives and include previously ignored code during 

elaboration. 

You can use this option to compile code that was previously ignored by third-party 

synthesis tools, for example, megafunction declarations that were treated as blackboxes 

in other tools but that may be compiled in the Quartus II software. 


Boolean 



Notes 


Syntax 

set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF 

Example 

set_global_assignment -name ignore_translate_off_and_synthesis_off on 

Default Value 

Off 




IGNORE_VERILOG_INITIAL_CONSTRUCTS 

IGNORE_VERILOG_INITIAL_CONSTRUCTS 

Type 

Instructs Analysis & Synthesis to ignore initial constructs and variable declaration 

assignments in your Verilog HDL design files. By default, Analysis & Synthesis 

derives power-up conditions for your design by elaborating these constructs. This 

option is provided for backwards compatibility with previous versions of the Quartus 

II software that ignored these constructs by default. You can use this option to restore 

the previous behavior of your design in the current version of the software. 


Boolean 



Notes 


Syntax 

set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS 

set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS -entity 

 

set_instance_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS -to - 

entity 

Example 

set_global_assignment -name ignore_verilog_initial_constructs off 

Default Value 

Off 




IMPLEMENT_AS_CLOCK_ENABLE 


Type 

Specifies that this node should function as a clock enable signal for one or more 

registers. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Notes 






Syntax 

set_instance_assignment -name IMPLEMENT_AS_CLOCK_ENABLE -to -entity 

 




IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL 

IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL 

Type 

Implements the output of a primitive in a logic cell. You can apply this option to a 

logic function that would not ordinarily be implemented in a logic cell, typically a 

combinatorial function such as an AND2 gate. Implementing the output of a primitive 

a logic cell makes it possible to observe its output in simulation and timing analysis. 

However, because an additional logic cell is used, overall device utilization will 

increase. This option does not insert an additional logic cell on a function that is 

already implemented in a logic cell, such as a flipflop. This option is ignored if it is 

applied to anything other than a primitive. 

This option can be assigned to an individual node only. 

Boolean 



Syntax 

set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL -to - 

entity 

Example 

set_instance_assignment -name implement_as_output_of_logic_cell on -to foo 




INFER_RAMS_FROM_RAW_LOGIC 

INFER_RAMS_FROM_RAW_LOGIC 

Type 

Instructs the Compiler to infer RAM from registers and multiplexers. Some HDL 

patterns that differ from Altera RAM templates are initially converted into logic. 

However, these structures function as RAM and, because of that, the Compiler may 

create an altsyncram megafunction instance for them at a later stage when this 

assignment is on. With this assignment on, the Compiler may use more device RAM 

resources and less LABs. 



Boolean 



Notes 


Syntax 

set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC 

set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC -entity 

set_instance_assignment -name INFER_RAMS_FROM_RAW_LOGIC -to -entity 

 

Example 

set_global_assignment -name infer_rams_from_raw_logic off 

set_instance_assignment -name infer_rams_from_raw_logic off -to foo 

Default Value 

On 




LCELL_INSERTION 

LCELL_INSERTION 

Type 

Allows you to insert one or more logic cells between two nodes without changing the 

design files. The value you assign this option is the number of logic cells you want to 

insert. The inserted logic cell(s) act as a simple buffer and do not alter the functionality 

of the design. For more detailed information, go to Quartus II online help. 

Integer 



■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Syntax 

set_instance_assignment -name LCELL_INSERTION -to -entity 

set_instance_assignment -name LCELL_INSERTION -from -to - 

entity 




LIMIT_AHDL_INTEGERS_TO_32_BITS 

LIMIT_AHDL_INTEGERS_TO_32_BITS 

Type 

Specifies whether an AHDL-based design should have a limit on integer size of 32 

bits. This option is provided for backward compatibility with pre-2000.09 releases of 

the Quartus software, which do not support integers larger than 32 bits in AHDL. 

Boolean 



Notes 


Syntax 

set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS 

Default Value 

Off 




MAX7000_FANIN_PER_CELL 


Type 

Specifies the maximum fan-in per macrocell. Legal integer values, in percentage 

terms, range from 20 through 100. 

You can use this option to improve the fitting of a design. The Maximum Fan-in Per 

Macrocell option allows you to spread routing resources and reduce congestion in a 

design. 


This option defaults to 100. 

Integer 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_global_assignment -name MAX7000_FANIN_PER_CELL 

set_global_assignment -name MAX7000_FANIN_PER_CELL -entity 

 

set_instance_assignment -name MAX7000_FANIN_PER_CELL -to -entity 

 

Example 

set_global_assignment -name max7000_fanin_per_cell 20 

set_instance_assignment -name max7000_fanin_per_cell 20 -to foo 

Default Value 

100 

Old Names 


software: 





Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A 




MAX7000_IGNORE_LCELL_BUFFERS 


Type 

Ignores LCELL buffers that are instantiated in the design. This option is ignored if it is 

applied to anything other than an individual LCELL buffer or a design entity 

containing LCELL buffers. 


Enumeration 

■ Auto 

■ Off 

■ On 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS 

set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS -entity 

set_instance_assignment -name MAX7000_IGNORE_LCELL_BUFFERS -to - 

entity 

Example 

set_global_assignment -name max7000_ignore_lcell_buffers on 

set_instance_assignment -name max7000_ignore_lcell_buffers on -to foo 

Default Value 

AUTO 

Old Names 


software: 





Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A 




MAX7000_IGNORE_SOFT_BUFFERS 

MAX7000_IGNORE_SOFT_BUFFERS 

Type 

Ignores SOFT buffers that are instantiated in the design. This option is ignored if it is 

applied to anything other than an individual SOFT buffer or a design entity 

containing SOFT buffers. 


Boolean 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS 

set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS -entity 

set_instance_assignment -name MAX7000_IGNORE_SOFT_BUFFERS -to -entity 

 

Example 

set_global_assignment -name max7000_ignore_soft_buffers on 

set_instance_assignment -name max7000_ignore_soft_buffers on -to foo 

Default Value 

Off 

Old Names 


software: 

Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A 




MAX7000_OPTIMIZATION_TECHNIQUE 


Type 

Specifies the overall optimization goal for Analysis & Synthesis, which is to maximize 

performance, minimize logic usage, or balance high performance with minimal logic 

usage during compilation.You can select one of the following settings: 



resource usage. 

■ Speed—The Compiler chooses a design implementation that has the fastest f max. 


performance with minimal logic usage. 


This option defaults to Speed. 

Enumeration 

■ Area 

■ Balanced 

■ Speed 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE 

set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE -entity 

set_instance_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE -to - 

entity 

Example 

set_global_assignment -name max7000_optimization_technique balanced 





Default Value 

Speed 

Old Names 


software: 

Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A 




MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 

MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 

Type 

Specifies the maximum allowable length of a chain of Compiler-synthesized parallel 

expander product terms. 



Integer 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 

set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH -entity 

 

set_instance_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH -to 

-entity 

Example 

set_global_assignment -name max7000_parallel_expander_chain_length 3 

Default Value 

4 

Old Names 


software: 

Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A 




MAXII_OPTIMIZATION_TECHNIQUE 


Type 



usage during compilation.You can select one of the following settings: 



■ Speed—The Compiler chooses a design implementation that has the fastest f max. 





Enumeration 

■ Area 

■ Balanced 

■ Speed 




■ MAX V 

Notes 


Syntax 

set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE 

set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE -entity 

set_instance_assignment -name MAXII_OPTIMIZATION_TECHNIQUE -to - 

entity 

Example 

set_global_assignment -name maxii_optimization_technique speed 

Default Value 

Balanced 





Old Names 


software: 

Optimization Technique -- MAX II 

TSUNAMI_OPTIMIZATION_TECHNIQUE 




MAX_AUTO_GLOBAL_REGISTER_CONTROLS 


Type 

Allows the Compiler to choose the signals that feed the most control signal inputs to 

flipflops (excluding clock signals) as global signals that are made available 

throughout the device on the global routing paths. Depending on the target device 

family, these control signals can include asynchronous clear and load, synchronous 

clear and load, clock enable, and preset signals. This option is ignored if it is assigned 

to anything other than a design entity. If you want to prevent the Compiler from 

automatically selecting a particular signal as global register control signal, set the 

Global Signal option to Off on that signal. 



Boolean 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Syntax 

set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS 

set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS -entity 

 

set_instance_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS -to - 

entity 

Example 

set_global_assignment -name max_auto_global_register_controls off 

set_instance_assignment -name max_auto_global_register_controls off -to 

foo 

Default Value 

On 

Old Names 


software: 





Auto Global Register Control Signals -- MAX 7000B/7000AE/3000A/7000S/7000A 




MAX_BALANCING_DSP_BLOCKS 


Type 

Allows you to specify the maximum number of DSP blocks that the DSP block 

balancer will assume exist in the current device for each partition. This option 

overrides the usual method of using the maximum number of DSP blocks the current 

device supports. For HardCopy II devices, the number of DSP blocks represents the 

number of DSP blocks used in the equivalent Stratix II device. This option is useful for 

HardCopy II device migration, where the number of DSP blocks that can be 

implemented in a HardCopy II device is more than the number of DSP blocks that can 

be implemented in its equivalent Stratix II device. This option is also useful in 

incremental compilation to set different DSP block usage limits for different 

partitions. 

You can use this option as a project-wide option or on a specific partition by setting 

the assignment on the instance name of the partition root. The assignment on a 

partition overrides the global assignment, if any, for that particular partition. 

Integer 



■ Arria GX 



■ Arria V 






■ Cyclone V 




■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name MAX_BALANCING_DSP_BLOCKS 

set_instance_assignment -name MAX_BALANCING_DSP_BLOCKS -to -entity 

 

Example 

set_global_assignment -name max_balancing_dsp_blocks 4 

set_instance_assignment -name max_balancing_dsp -to 

"my_partition_root_entity:my_partition_root_entity_inst" 

Default Value 

-1 (Unlimited) 




MAX_FANOUT 

MAX_FANOUT 

Type 

Directs the Compiler to control the number of destinations the specified node feeds so 

the fan-out count does not exceed the value specified as the maximum number of fanout 

allowed from the node. 

You can use this option to reduce the load of critical signals, which improves 

performance. 

This option is ignored if it is applied to anything other than a register or a logic cell 

buffer, or a design entity that contains registers or logic cell buffers. 

Integer 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 




MAX_FANOUT 

Notes 


Syntax 

set_global_assignment -name MAX_FANOUT -entity 

set_instance_assignment -name MAX_FANOUT -to -entity 

 

Example 

set_instance_assignment -name max_fanout 10 -to foo 




MAX_LABS 

MAX_LABS 

Type 

Allows you to specify the maximum number of LABs that Analysis & Synthesis may 

use for a device. This option overrides the usual method of using the maximum 

number of LABs the current device supports, when the value is non-negative and is 

less than the maximum number of LABs available on the current device. 

This option is ignored when the value is greater than the maximum number of LABs 

available on the current device. 

You can use this option in incremental compilation to set different lab usage limits for 

different partitions. 

You can use this option as a project-wide option or on a specific partition by setting 



You can use this option for device migration. 

Integer 



Notes 


Syntax 

set_global_assignment -name MAX_LABS 

set_instance_assignment -name MAX_LABS -to -entity 

 

Example 

set_global_assignment -name max_labs 100 

Default Value 





MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS 

MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS 

Type 

Allows you to specify the maximum number of registers that Analysis & Synthesis 

can use for conversion of uninferred RAMs. You can use this option as a project-wide 

option or on a specific partition by setting the assignment on the instance name of the 

partition root. 

The assignment on a partition overrides the global assignment (if any) for that 

particular partition. 

This option prevents synthesis from causing long compilations and running out of 

memory when many registers are used for uninferred RAMs. Instead of continuing 

the compilation, the Quartus II software issues an error and exits. 

Integer 



Notes 


Syntax 

set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS 

 

set_instance_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS 

-to -entity 

Example 

set_global_assignment -name max_number_of_registers_from_uninferred_rams 

2048 

Default Value 





MAX_RAM_BLOCKS_M4K 


Type 

Allows you to specify the maximum number of M4K, M9K, M20K, or M10K memory 

blocks that the Compiler may use for a device. This option overrides the usual 

method of using the maximum number of M4K, M9K, M20K, or M10K memory 

blocks the current device supports, when the value is non-negative and is less than 

the maximum number of M4K, M9K, M20K, or M10K memory blocks available on the 

current device. 

This option is also useful in incremental compilation to set different M4K, M9K, 

M20K, or M10K memory block usage limits for different partitions. 

This option can be used as a project-wide option or on a specific partition by setting 


partition overrides the global assignment (if any) for that particular partition. 

This option is useful for device migration. 

Integer 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name MAX_RAM_BLOCKS_M4K 

set_instance_assignment -name MAX_RAM_BLOCKS_M4K -to -entity 

Example 

set_global_assignment -name max_ram_blocks_m4k 4 

Default Value 


See Also 

■ “MAX_RAM_BLOCKS_M512” on page 4–121 

■ “MAX_RAM_BLOCKS_MRAM” on page 4–123 




MAX_RAM_BLOCKS_M512 


Type 

Allows you to specify the maximum number of M512 memory blocks that the 

Compiler may use for a device. This option overrides the usual method of using the 

maximum number of M512 memory blocks the current device supports, when the 

value is non-negative and is less than the maximum number of M512 memory blocks 

available on the current device. 

This option is also useful in incremental compilation to set different M512 memory 

block usage limits for different partitions. 





Integer 



■ Arria GX 

■ Cyclone 



■ MAX V 

■ Stratix 




Notes 


Syntax 

set_global_assignment -name MAX_RAM_BLOCKS_M512 

set_instance_assignment -name MAX_RAM_BLOCKS_M512 -to -entity 

Example 

set_global_assignment -name max_ram_blocks_m512 4 





Default Value 


See Also 

■ “MAX_RAM_BLOCKS_M4K” on page 4–119 

■ “MAX_RAM_BLOCKS_MRAM” on page 4–123 




MAX_RAM_BLOCKS_MRAM 


Type 

Allows you to specify the maximum number of M-RAM or M144K memory blocks 

that the Compiler may use for a device. This option overrides the usual method of 

using the maximum number of M-RAM or M144K memory blocks the selected device 

supports, when the value is non-negative and is less than the maximum number of M- 

RAM or M144K memory blocks available on the current device. 

This option is also useful in incremental compilation to set different M-RAM or 

M144K memory block usage limits for different partitions. 



partition overrides the global assignment (if any) for that particular partition. 


Integer 



■ Arria GX 



■ Cyclone 





■ MAX V 

■ Stratix 






Notes 


Syntax 

set_global_assignment -name MAX_RAM_BLOCKS_MRAM 





set_instance_assignment -name MAX_RAM_BLOCKS_MRAM -to -entity 

Example 

set_global_assignment -name max_ram_blocks_mram 4 

Default Value 


See Also 

■ “MAX_RAM_BLOCKS_M512” on page 4–121 

■ “MAX_RAM_BLOCKS_M4K” on page 4–119 




MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED _THROUGH_MODE_SETTING_DONT_CARE 

MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED 

_THROUGH_MODE_SETTING_DONT_CARE 

Type 

Allows you to specify whether you want the TimeQuest Timing Analyzer to evaluate 

timing constraints between the write and the read operation of the MLAB memory 

block. Performing a write and read operation simultaneously at the same address 

might result in metastability because no timing constraints between those operations 

exist by default. Turning on this option introduces timing constraints between the 

write and read operation on the MLAB memory block and thereby avoids 

metastability issues; however, turning on this option degrades the performance of the 

MLAB memory blocks. If your design does not perform write and read operations 

simultaneously at the same address you do not need to set this option. 

Boolean 





■ Arria V 

■ Cyclone V 





■ Stratix V 

Notes 



Syntax 


MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_ 

CARE -entity 



CARE -to -entity 



CARE 




MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED _THROUGH_MODE_SETTING_DONT_CARE 

Default Value 

Off 




MUX_RESTRUCTURE 


Type 

Allows the Compiler to reduce the number of logic elements required to implement 

multiplexers in a design. You can use this option if your design contains buses of 

fragmented multiplexers. This option restructures multiplexers more efficiently for 

area, allowing the design to implement multiplexers with a reduced number of logic 

elements. 

The following three settings are available: 

■ On—Allows the Compiler to minimize your design area. This setting decreases 

logic element usage but may negatively affect design clock speed (f MAX). 

■ Off—Multiplexer restructuring is disabled in the design. This setting does not 

decrease logic element usage and does not affect design clock speed (f MAX). 

■ Auto—Allows the Quartus II software to determine whether multiplexer 

restructuring should be enabled. The Quartus II software uses other synthesis 

settings, for example, the Optimization Technique option, to determine if 

multiplexer restructuring should be applied to the design. This setting decreases 

logic element usage but may negatively affect design clock speed ( fMAX). 

The Restructure Multiplexers option works on entire trees of multiplexers. 

Multiplexers may arise in different parts of the design through VHDL or Verilog 

constructs such as “if”, “case”, or “?:”. When multiplexers from one part of the design 

feed multiplexers in another part of the design, trees of multiplexers are formed. The 

Restructure Multiplexers option identifies buses of multiplexer trees that have a 

similar structure. Multiplexer buses occur most often as a result of multiplexing 

together vectors in Verilog, or array types such as STD_LOGIC_VECTOR in VHDL. 

When turned on, the Restructure Multiplexers option optimizes the structure of each 

multiplexer bus for the target device to reduce the overall number of logic elements 

used in the design. 

You can use this option as a project-wide option, or assigned to a design entity. 


Enumeration 

■ Auto 

■ Off 

■ On 



■ Arria GX 



■ Arria V 





■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Notes 


Syntax 

set_global_assignment -name MUX_RESTRUCTURE 

set_global_assignment -name MUX_RESTRUCTURE -entity 

set_instance_assignment -name MUX_RESTRUCTURE -to -entity 

Example 

set_global_assignment -name mux_restructure off 

set_instance_assignment -name mux_restructure on -to accel 

Default Value 

Auto 




NOT_GATE_PUSH_BACK 

NOT_GATE_PUSH_BACK 

Type 

Allows the Compiler to push an inversion (that is, a NOT gate) back through a 

register and implement it on that register's data input if it is necessary to implement 

the design. If this option is turned on, a register may power up to an active-high state, 

so it may need to be explicitly cleared during initial operation of the device. This 

option is ignored if it is applied to anything other than an individual register or a 

design entity containing registers. If it is applied to an output pin that is directly fed 

by a register, it is automatically transferred to that register. 


Boolean 



Notes 


Syntax 

set_global_assignment -name NOT_GATE_PUSH_BACK -entity 

 

set_instance_assignment -name NOT_GATE_PUSH_BACK -to -entity 

set_global_assignment -name NOT_GATE_PUSH_BACK 

Example 

set_global_assignment -name not_gate_push_back off 

set_instance_assignment -name not_gate_push_back off -to reg 

Default Value 

On 




NUMBER_OF_INVERTED_REGISTERS_REPORTED 

NUMBER_OF_INVERTED_REGISTERS_REPORTED 

Type 

Allows you to specify the maximum number of inverted registers that the Synthesis 

Report should display. 

Legal values are integers starting from 0. The value of 0 means that there is no report 

panel about inverted registers in the Synthesis report. 

The default value is 100. 


Integer 



Notes 


Syntax 

set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 

Example 

set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 200 

Default Value 

100 




NUMBER_OF_REMOVED_REGISTERS_REPORTED 

NUMBER_OF_REMOVED_REGISTERS_REPORTED 

Type 

Allows you to specify the maximum number of removed registers that the Synthesis 

Report should display. 

Legal values are integers starting from 0. The value of 0 means that there will be no 

report panel about removed registers in the Synthesis report. 

The default value is 5000. 


Integer 



Notes 


Syntax 

set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 

Example 

set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 200 

Default Value 

5000 




NUMBER_OF_SWEPT_NODES_REPORTED 

NUMBER_OF_SWEPT_NODES_REPORTED 

Type 

Allows you to specify the maximum number of swept nodes that the Synthesis Report 

displays. A swept node is any node which was eliminated from your design because 

the Quartus II software found the node to be unnecessary. 

Integer 



Notes 


Syntax 

set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 

Example 

set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 200 

Default Value 

5000 




OPTIMIZATION_TECHNIQUE 


Type 



usage during compilation. 




■ Speed—The Compiler chooses a design implementation that has the fastest f MAX. 





This option is applicable to Stratix IV and Stratix V. 

Enumeration 

■ Area 

■ Balanced 

■ Speed 





■ Arria V 

■ Cyclone V 



■ Stratix V 

Notes 


Syntax 

set_global_assignment -name OPTIMIZATION_TECHNIQUE 

set_global_assignment -name OPTIMIZATION_TECHNIQUE -entity 

 





set_instance_assignment -name OPTIMIZATION_TECHNIQUE -to -entity 

 

Example 

set_global_assignment -name optimization_technique speed 

Default Value 

Balanced 

Old Names 


software: 

Optimization Technique -- Stratix IV 




OPTIMIZE_POWER_DURING_SYNTHESIS 


Type 

Controls the power-driven compilation setting of Analysis & Synthesis. This option 

determines how aggressively Analysis & Synthesis optimizes the design for power. If 

this option is set to Off, Analysis & Synthesis does not perform any power 

optimizations. If this option is set to Normal compilation, Analysis & Synthesis 

performs power optimizations as long as they are not expected to reduce design 

performance. When this option is set to Extra effort, Analysis & Synthesis performs 

additional power optimizations which may reduce design performance. 


This option defaults to Normal compilation. 

Enumeration 

■ Extra effort 

■ Normal compilation 

■ Off 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS 

set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS -entity 

 

set_instance_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS -to - 

entity 

Example 

set_global_assignment -name optimize_power_during_synthesis off 

Default Value 

Normal compilation 




PARALLEL_SYNTHESIS 

PARALLEL_SYNTHESIS 

Type 

Enables or disables parallel synthesis. 

This option is used as a project-wide option. 


Boolean 



Notes 


Syntax 

set_global_assignment -name PARALLEL_SYNTHESIS 

Example 

set_global_assignment -name parallel_synthesis on 

Default Value 

On 




PARAMETER 

PARAMETER 

Type 

Assigns an attribute that determines the logic created or used to implement the 

function, for example, the width of a bus. Parameters are characteristics that 

determine the size, behavior, or silicon implementation of a function. Parameter 

values are inherited from project defaults or higher hierarchical levels unless you 

make explicit assignments to individual nodes. Parameters are also overridden by 

explicit logic synthesis and fitting options. 

String 



Notes 


Syntax 

set_parameter 

set_parameter -entity 




POWER_UP_LEVEL 


Type 

Causes a register to power up with the specified logic level, either High (1) or Low (0). 

If this option is specified for an input pin, it is automatically transferred to the register 

that is driven by the pin if the following conditions are present: 

■ There is no intervening logic, other than inversion, between the pin and the 

register 

■ The input pin drives the data input of the register 

■ The input pin does not fan-out to any other logic 

If this option is specified for an output or bidirectional pin, it is automatically 

transferred to the register that feeds the pin if the following conditions are present: 

■ There is no intervening logic, other than inversion, between the register and the 

pin 

■ The register does not fan-out to any other logic 

You can assign this option to any register, or to a pin with any logic configuration 

other than those previously described. You can also assign this option to a design 

entity containing registers if you want to set the power level for all registers in the 

design entity. In order for the register to power up with the specified logic level, the 

Compiler may perform NOT Gate Push-Back on the register. 

You can assign this option to any register, registered logic cell WYSIWYG primitive, or 

to a pin with any logic configuration other than those described above. If this option is 

assigned to a registered logic cell WYSIWYG primitive, you must turn on the Perform 

WYSIWYG Primitive Resynthesis logic option for it to take effect. You can also 

assign this option to a design entity containing registers if you want to set the power 

level for all registers in the design entity. In order for the register to power up with the 

specified logic level, the Compiler may perform NOT Gate Push-Back on the register. 

Enumeration 

■ High 

■ Low 



Notes 


Syntax 

set_global_assignment -name POWER_UP_LEVEL -entity 

set_instance_assignment -name POWER_UP_LEVEL -to -entity 





Example 

set_instance_assignment -name power_up_level low -to foo 

See Also 

■ “ALLOW_POWER_UP_DONT_CARE” on page 4–12 




PRESERVE_FANOUT_FREE_NODE 

PRESERVE_FANOUT_FREE_NODE 

Type 

Prevents a register that has no fan-out from being removed during synthesis. 

A logic option that specifies that the register should be preserved in the design even 

when it becomes fan-out free. 

Boolean 



■ Arria GX 



■ Arria V 






■ Cyclone V 








■ Stratix V 

Syntax 

set_instance_assignment -name PRESERVE_FANOUT_FREE_NODE -to -entity 

 

Example 

set_instance_assignment -name preserve_fanout_free_node on -to reg 




PRESERVE_REGISTER 

PRESERVE_REGISTER 

Type 

Prevents a register from minimizing away during synthesis and prevents sequential 

netlist optimizations. Sequential netlist optimizations can eliminate redundant 

registers and registers with constant drivers. 

This option is useful for preserving a register so you can observe it during Simulation. 

It is also useful for creating a preliminary version of the design in which secondary 

signals are not specified. This option is ignored if the register does not drive anything, 

in which case, the register will be removed by the netlist optimization. 

This option is ignored if it is applied to anything other than a register or a design 

entity that contains registers. 

Boolean 



Notes 


Syntax 

set_global_assignment -name PRESERVE_REGISTER -entity 

 

set_instance_assignment -name PRESERVE_REGISTER -to -entity 

Example 

set_instance_assignment -name preserve_register on -to foo 




PRE_MAPPING_RESYNTHESIS 

PRE_MAPPING_RESYNTHESIS 

Type 

Specifies that the Quartus II software should perform a resynthesis optimization step 

immediately before technology mapping. The On setting increases design 

performance, which increases design clock speed (f MAX) but may also slightly increase 

logic element usage and compilation time. The Off selection disables this 

optimization. 

Boolean 



Syntax 

set_global_assignment -name PRE_MAPPING_RESYNTHESIS 

Default Value 

Off 




RBCGEN_CRITICAL_WARNING_TO_ERROR 

RBCGEN_CRITICAL_WARNING_TO_ERROR 

Type 

Converts the critical warning of the Quartus II software to error. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR 

Default Value 

On 




REMOVE_DUPLICATE_REGISTERS 

REMOVE_DUPLICATE_REGISTERS 

Type 

Removes a register if it is identical to another register. If two registers generate the 

same logic, the second register is deleted and the first register fans out to the 

destination of the second register. Also, if the deleted register has different logic 

option assignments, they are ignored. You can use this option to prevent the Compiler 

from removing duplicate registers that you have used deliberately. Perform this by 

setting the option to Off. This option is ignored if it is applied to anything other than 

an individual register or a design entity containing registers. 

This option is ignored if it is assigned to anything other than an individual register or 

a design entity containing registers. 


Boolean 



Notes 



Syntax 

set_global_assignment -name REMOVE_DUPLICATE_REGISTERS 

set_global_assignment -name REMOVE_DUPLICATE_REGISTERS -entity 

set_instance_assignment -name REMOVE_DUPLICATE_REGISTERS -to -entity 

 

Example 

set_global_assignment -name remove_duplicate_registers off 

set_instance_assignment -name remove_duplicate_registers off -to foo 

Default Value 

On 

Old Names 


software: 

DUPLICATE_REGISTER_EXTRACTION 




REMOVE_REDUNDANT_LOGIC_CELLS 


Type 

Removes redundant LCELL primitives or WYSIWYG primitives. Turning this option 

on optimizes a circuit for area and speed. This option is ignored if it is applied to 

anything other than a design entity. 


Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Notes 






Syntax 

set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -entity 

set_instance_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -to - 

entity 

set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS 

Example 

set_global_assignment -name remove_redundant_logic_cells on 

set_instance_assignment -name remove_redundant_logic_cells on -to node 

Default Value 

Off 




REPORT_CONNECTIVITY_CHECKS 

REPORT_CONNECTIVITY_CHECKS 

Type 

Specifies whether the synthesis report should include the panels in the Connectivity 

Checks folder 

Boolean 



Notes 


Syntax 

set_global_assignment -name REPORT_CONNECTIVITY_CHECKS 

Default Value 

On 




REPORT_PARAMETER_SETTINGS 

REPORT_PARAMETER_SETTINGS 

Type 

Specifies whether the synthesis report should include the panels in the Parameter 

Settings by Entity Instance folder 

Boolean 



Notes 


Syntax 

set_global_assignment -name REPORT_PARAMETER_SETTINGS 

Default Value 

On 

Old Names 


software: 

SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT 




REPORT_SOURCE_ASSIGNMENTS 

REPORT_SOURCE_ASSIGNMENTS 

Type 

Specifies whether the synthesis report should include the panels in the Source 

Assignments folder 

Boolean 



Notes 


Syntax 

set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS 

Default Value 

On 




RESYNTHESIS_PHYSICAL_SYNTHESIS 

RESYNTHESIS_PHYSICAL_SYNTHESIS 

Type 

Specifies the physical synthesis level for resynthesis. 

Enumeration 

■ Advanced 

■ Normal 



Notes 


Syntax 

set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS -section_id 

 

set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS -entity -section_id 

Default Value 

Normal, requires section identifier 




RESYNTHESIS_RETIMING 

RESYNTHESIS_RETIMING 

Type 

Specifies the paths on which retiming is performed, which are all paths, register-toregister 

paths only, or none. 

Enumeration 

■ Core 

■ Full 

■ Off 



Notes 


Syntax 

set_global_assignment -name RESYNTHESIS_RETIMING -section_id 

set_global_assignment -name RESYNTHESIS_RETIMING -entity - 

section_id 

Default Value 

Full, requires section identifier 




SAFE_STATE_MACHINE 

SAFE_STATE_MACHINE 

Type 

Directs the Compiler to implement state machines that can recover gracefully from an 

illegal state. 

This option can be applied globally or to a specific entity or node. 

Implementation of such safe state machines can result in some area increase. 


Boolean 



Notes 


Syntax 

set_global_assignment -name SAFE_STATE_MACHINE -entity 

 

set_instance_assignment -name SAFE_STATE_MACHINE -to -entity 

set_global_assignment -name SAFE_STATE_MACHINE 

Example 

set_global_assignment -name safe_state_machine on 

set_instance_assignment -name safe_state_machine on -to foo 

Default Value 

Off 

See Also 







SAVE_DISK_SPACE 

SAVE_DISK_SPACE 

Type 

Saves disk space by reducing the number of node names available for entering 

assignments, simulation, timing analysis, reporting, and others. 

Boolean 



Notes 


Syntax 

set_global_assignment -name SAVE_DISK_SPACE 

Default Value 

On 




SEARCH_PATH 

SEARCH_PATH 

Type 

Specifies the path name of a user-defined library. 

String 



Notes 


Syntax 

set_global_assignment -name SEARCH_PATH 




SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL 

SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL 

Type 

Allows the Compiler to find a group of shift registers of the same length that can be 

replaced with the altshift_taps megafunction. The shift registers must all use the same 

aclr signals, must not have any other secondary signals, and must have equally 

spaced taps that are at least three registers apart. To use this option, you must turn on 

the Auto Shift Register Replacement logic option. 



Boolean 



Notes 


Syntax 

set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL 

set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL -entity 

 

set_instance_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL -to 

-entity 

Example 

set_global_assignment -name shift_register_recognition_aclr_signal off 

set_instance_assignment -name shift_register_recognition_aclr_signal off - 

to foo 

Default Value 

On 




SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES 

SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES 

Type 

Allows the Compiler to skip the fitting stage during smart recompilation when design 

changes may affect timing requirements. This option is available only for changes to 

Cyclone, Stratix, and Stratix GX PLL parameters, and Stratix GX gigabit transceiver 

block parameters. 

Boolean 



Syntax 


SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES 

Default Value 

Off 




STATE_MACHINE_PROCESSING 


Type 

Specifies the processing style used to compile a state machine. You can use your own 

‘User-Encoded’ style, or select ‘One-Hot’, ‘Minimal Bits’, ‘Gray’, ‘Johnson’, 

‘Sequential’ or ‘Auto’ (Compiler-selected) encoding. 

The following settings are available: 

■ Auto—Allows the Compiler to choose the best encoding for the state machine 

■ Minimal Bits—Uses the minimal number of bits to encode the state machine 

■ One-Hot—Encodes the state machine in the one-hot style 

■ User-Encoded—Encodes the state machine in the manner that you specified 

■ Gray—Encodes the state machine in the Gray style 

■ Johnson—Encodes the state machine in the Johnson style 

■ Sequential—Encode the state machine in the sequential binary style. 


Enumeration 

■ Auto 

■ Gray 

■ Johnson 

■ Minimal Bits 

■ One-Hot 

■ Sequential 


■ User-Encoded 


Notes 


Syntax 

set_global_assignment -name STATE_MACHINE_PROCESSING -entity 

 

set_instance_assignment -name STATE_MACHINE_PROCESSING -to -entity 

 

set_global_assignment -name STATE_MACHINE_PROCESSING 





Example 

set_global_assignment -name state_machine_processing "one-hot" 

set_instance_assignment -name state_machine_processing "one-hot" -to foo 

Default Value 

Auto 

See Also 






STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_ DETECT_SIGNAL_THRESHOLD_SELECT 

STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_ 

DETECT_SIGNAL_THRESHOLD_SELECT 

Type 

Directs the Compiler to not modify the Force Signal Detect and Signal Threshold 

Select parameters on gigabit transceiver block receiver channels. 

Boolean 



■ Arria GX 



Syntax 


STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT 

 

Default Value 

Off 




STRATIXII_CARRY_CHAIN_LENGTH 


Type 

Specifies the maximum allowable length of a chain of both user-entered and 

Compiler-synthesized CARRY_SUM buffers. Carry chains that exceed this length are 

broken into separate chains. This option also applies to MAX+PLUS II-style CARRY 

buffers. 

Integer 



■ Arria GX 



■ Arria V 

■ Cyclone V 








■ Stratix V 

Notes 


Syntax 

set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 

set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH -entity 

set_instance_assignment -name STRATIXII_CARRY_CHAIN_LENGTH -to - 

entity 

Default Value 

70 





Old Names 


software: 

ARMSTRONG_CARRY_CHAIN_LENGTH 

Carry Chain Length -- Stratix II/Stratix III 




STRATIXII_OPTIMIZATION_TECHNIQUE 


Type 







■ Speed—The Compiler chooses a design implementation that has the fastest f MAX 





This option is applicable to Arria GX, HardCopy II, Stratix II, Stratix II GX, and Stratix 

III devices. 

Enumeration 

■ Area 

■ Balanced 

■ Speed 



■ Arria GX 






Notes 


Syntax 

set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE 

set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE -entity 

 

set_instance_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE -to - 

entity 





Example 

set_global_assignment -name stratixii_optimization_technique speed 

Default Value 

Balanced 

Old Names 


software: 

ARMSTRONG_OPTIMIZATION_TECHNIQUE 

Optimization Technique -- Stratix II/III/HardCopy II/Stratix II GX/Arria GX 




STRATIX_CARRY_CHAIN_LENGTH 

STRATIX_CARRY_CHAIN_LENGTH 

Type 

Specifies the maximum allowable length of a chain of both user-entered and 

Compiler-synthesized CARRY_SUM buffers. Carry chains that exceed this length are 

broken into separate chains. This option also applies to MAX+PLUS II-style CARRY 

buffers. 

Integer 



■ Cyclone 







■ MAX V 

■ Stratix 


Notes 


Syntax 

set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 

set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH -entity 

set_instance_assignment -name STRATIX_CARRY_CHAIN_LENGTH -to -entity 

 

Default Value 

70 

Old Names 


software: 

Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III 




STRATIX_OPTIMIZATION_TECHNIQUE 


Type 







■ Speed—The Compiler chooses a design implementation that has the fastest f MAX 





This option is applicable to Stratix and Stratix GX devices. 

Enumeration 

■ Area 

■ Balanced 

■ Speed 



■ Stratix 


Notes 


Syntax 

set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE 

set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE -entity 

set_instance_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE -to - 

entity 

Example 

set_global_assignment -name stratix_optimization_technique speed 

Default Value 

Balanced 





Old Names 


software: 

Optimization Technique -- Stratix/Stratix GX 

YEAGER_OPTIMIZATION_TECHNIQUE 




STRICT_RAM_RECOGNITION 


Type 

When you set this option to On, the Compiler is only allowed to replace RAM if the 

hardware matches the design exactly. 


Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 




■ Stratix 






■ Stratix V 

Notes 


Syntax 

set_global_assignment -name STRICT_RAM_RECOGNITION 





set_global_assignment -name STRICT_RAM_RECOGNITION -entity 

 

set_instance_assignment -name STRICT_RAM_RECOGNITION -to -entity 

 

Example 

set_global_assignment -name strict_ram_recognition on 

set_global_assignment -name strict_ram_recognition on -to foo 

Default Value 

Off 




SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 


Type 

This setting specifies the maximum number of registers in a row to be considered as a 

synchronization chain. Synchronization chains are sequences of registers with the 

same clock, no fanout in between, such that the first register is fed by a pin, or by logic 

in another clock domain. These registers are considered for metastability analysis 

(available for some families), and are also protected from optimizations such as 

retiming. When gate-level retiming is turned on, these registers are not moved. The 

default length is set to two. 

Integer 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 





Notes 



Syntax 

set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 

set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH -entity 

 

set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH -to 

-entity 

Old Names 


software: 

ADV_NETLIST_OPT_METASTABLE_REGS 




SYNTHESIS_EFFORT 

SYNTHESIS_EFFORT 

Type 

Controls the synthesis trade-off between compilation speed and performance and 

area. The default is Auto, which means synthesis goes through all its steps. You can 

select Fast, which means synthesis skips a number of steps which makes it 

approximately 30% faster, but at the cost of performance and area. Altera 

recommends that you only use Fast when the Fitter early timing estimate flow is used. 

This is because the Fast synthesis results produces a netlist that is slightly harder for 

the Fitter to route, thus making the Fitter slower, which cancels out the speed-up of 

synthesis. The Fitter early timing estimate runtime is not affected by the synthesis 

effort level. 

Enumeration 

■ Auto 

■ Fast 



Notes 


Syntax 

set_global_assignment -name SYNTHESIS_EFFORT 

Example 

set_global_assignment -name synthesis_effort fast 

Default Value 

Auto 




SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER 

SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER 

Type 

When this option is set to On, synthesis keeps the synchronous clear or preset 

behavior when remapping the I/O WYSIWYG primitives (from other device families) 

using the DDIO INPUT feature to the targeted device family. 

For example, the DDIO INPUT of the Stratix III device family behaves differently 

from Stratix II when you use synchronous clear or preset behavior. For the Stratix III 

device family, the synchronous clear or preset behavior affects all three registers, 

while it only affects the two capture registers in Stratix II. 

Boolean 



Syntax 


SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER -entity 


SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER -to -entity 

 


SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER 

Example 


synthesis_keep_synch_clear_preset_behavior_in_unmapper on 


synthesis_keep_synch_clear_preset_behavior_in_unmapper on -to foo 




SYNTHESIS_SEED 

SYNTHESIS_SEED 

Type 

Specifies the seed that Synthesis uses to randomly do synthesis in a slightly different 

way. This seed can be used when a design is close to meeting requirements, in order to 

get a slightly different result. The value can be any non-negative integer value. 

Changing the starting value may or may not produce better results. 

Integer 



Notes 


Syntax 

set_global_assignment -name SYNTHESIS_SEED 

Default Value 

1 




SYNTH_CLOCK_MUX_PROTECTION 


Type 

Causes the multiplexers in the clock network to be decomposed to 2 to 1 multiplexer 

trees, and protected from being merged with, or transferred to, other logic. This 

option helps the TimeQuest timing analyzer to understand clock behavior. 

A clock multiplexer can cause glitches. Altera recommends that you use a clock 

control block instead. 



Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION 

Example 

set_global_assignment -name synth_clock_mux_protection off 

Default Value 

On 




SYNTH_CRITICAL_CLOCK 


Type 

Specifies that all combinational logic in the given clock domain, or between the given 

clock domains, should be mapped with optimization technique speed. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Notes 






Syntax 

set_instance_assignment -name SYNTH_CRITICAL_CLOCK -to -entity 

 

set_instance_assignment -name SYNTH_CRITICAL_CLOCK -from -to - 

entity 

Example 

set_instance_assignment -name synth_critical_clock on -to clock 

set_instance_assignment -name synth_critical_clock on -from clk1 -to clk2 




SYNTH_GATED_CLOCK_CONVERSION 


Type 

Automatically converts gated clocks in the design to use clock enable pins if clock 

enable pins are not used in the original design. Clock gating logic can contain AND, 

OR, MUX, and NOT gates. Turning on this option may increase memory use and 

overall run time. You must use the TimeQuest Timing Analyzer for timing analysis, 

and you must define all base clocks in Synopsys Design Constraints File (.sdc) format. 

You can use this option for ASIC prototyping flow on FPGA, and only works with the 

TimeQuest timing analyzer. For more information, refer to Quartus II Development 

Software Handbook on the Altera website. 

This option may cause memory usage and run time increase. 



Boolean 



■ Arria GX 



■ Arria V 






■ Cyclone V 








■ Stratix V 





Notes 


Syntax 

set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION -entity 

set_instance_assignment -name SYNTH_GATED_CLOCK_CONVERSION -to - 

entity 

set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION 

Example 

set_global_assignment -name synth_gated_clock_conversion on 

set_instance_assignment -name synth_gated_clock_conversion on -to foo 

Default Value 

Off 




SYNTH_MESSAGE_LEVEL 

SYNTH_MESSAGE_LEVEL 

Type 

Specifies the type of Analysis & Synthesis messages you want to view. Setting this 

option to Low allows you to view only the most important Analysis & Synthesis 

messages. Setting this option to Medium allows you to view most Analysis & 

Synthesis messages, but hides the detailed messages in Analysis & Synthesis report. 

Setting this option to High allows you to view all Analysis & Synthesis messages. 

Enumeration 

■ High 

■ Low 

■ Medium 



Notes 


Syntax 

set_global_assignment -name SYNTH_MESSAGE_LEVEL 

Default Value 

Medium 




SYNTH_PROTECT_SDC_CONSTRAINT 


Type 

Causes SDC constraint checking in register merging. It helps to maintain the validity 

of SDC constraints through compilation. 

This option is useful for maintaining the validity of SDC constraints through 

compilation. 

This option may cause memory usage and run time increase. 



Boolean 



■ Arria GX 



■ Arria V 






■ Cyclone V 








■ Stratix V 

Notes 






Syntax 

set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT 

Example 

set_global_assignment -name synth_protect_sdc_constraint on 

Default Value 

Off 




SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM 


Type 

Specifies whether Analysis & Synthesis is allowed to use information about the device 

and design resources to decide which logical RAMs, ROMs, and shift-registers to infer 

from your HDL. 

You can use this option when regular synthesis infers more RAMs, ROMs, and shiftregisters 

to be implemented in block RAM than the device can fit. Resource-aware 

inference tries to estimate the required number of RAM blocks and registers for your 

design, and makes inference decisions based on the available device resources. 

This option can only be used for Cyclone, Cyclone II, Cyclone III, Cyclone III LS, 

Cyclone IV, Arria II GX, Stratix III, HardCopy III, Stratix IV and HardCopy IV 

families. It is ignored for other families. 

When you set this option to on, Altera recommends that you specify a device for the 

design. If no device is specified, then the RAM, ROM, and shift-register inference is 

not resource-aware. 



Boolean 





■ Arria V 

■ Cyclone 






■ Cyclone V 




■ Stratix 








■ Stratix V 

Notes 


Syntax 

set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM 

 

Example 

set_global_assignment -name synth_resource_aware_inference_for_block_ram 

on 




SYNTH_TIMING_DRIVEN_SYNTHESIS 


Type 

Allows the Quartus II Synthesis to use timing information during synthesis to 

optimize the design. 

When you turn this option on, the Quartus II Synthesis runs timing analysis to obtain 

timing information about the netlist, and optimizes the netlist accordingly. It also 

automatically applies the SDC Constraint Protection logic option. 

You can use this option when regular synthesis does not optimize the circuit well for 

the given timing constraints. When you set the Timing-Driven Synthesis option to 

on, you can expect Synthesis to perform better at the cost of some ALUTs and/or 

registers. Runtime and peak memory slightly increases as well. 

This option can only be used for Cyclone II, Cyclone III, Cyclone III LS, Cyclone IV, 

Arria II GX, Stratix II, HardCopy II, Stratix III, HardCopy III, Stratix IV and HardCopy 

IV families. It is ignored for other families. It is also ignored when the Synthesis Effort 

is set to Fast. Appropriate warnings are given when the option is ignored. 

When you set this option to on, Altera recommends that you specify a device for the 

design. If no device is specified, timing-driven synthesis automatically uses the 

smallest device in the family that satisfies design constraints like speed grade and 

package. It gives an error when no valid device can be found. 



Boolean 



■ Arria GX 



■ Arria V 






■ Cyclone V 












■ Stratix V 

Notes 


Syntax 

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS 

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -entity 

set_instance_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -to - 

entity 

Example 

set_global_assignment -name synth_timing_driven_synthesis on 




TOP_LEVEL_ENTITY 

TOP_LEVEL_ENTITY 

Type 

Specifies the full hierarchichal path of the entity that is the focus of the current 

compilation or simulation. 

String 



Notes 



Syntax 

set_global_assignment -name TOP_LEVEL_ENTITY 

Old Names 


software: 

FOCUS_ENTITY_NAME 




TRUE_WYSIWYG_FLOW 

TRUE_WYSIWYG_FLOW 

Type 

Specifies that the Quartus II software should not try to optimize this WYSIWYG 

design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name TRUE_WYSIWYG_FLOW 

Default Value 

Off 




USER_LIBRARIES 

USER_LIBRARIES 

Type 

Specifies the pathnames of user-defined libraries. 

String 



Notes 


Syntax 

set_global_assignment -name USER_LIBRARIES 




USE_HIGH_SPEED_ADDER 

USE_HIGH_SPEED_ADDER 

Type 

Directs the Compiler whether to use high speed adder circuitry to implement 

arithmetic functions or not. This option is useful for improving the performance of 

the design when set to On and minimizing the total number of HCells used in the 

design when set to Off. 

This option applies to HardCopy series devices only. 

This option defaults to Auto, which has the same behavior as On when the 

Optimization Technique is set to Speed or Balanced, and as Off when the 

Optimization Technique is set to Area. 

Enumeration 

■ Auto 

■ Off 

■ On 






Notes 


Syntax 

set_global_assignment -name USE_HIGH_SPEED_ADDER 

set_global_assignment -name USE_HIGH_SPEED_ADDER -entity 

 

set_instance_assignment -name USE_HIGH_SPEED_ADDER -to -entity 

 

Example 

set_global_assignment -name use_high_speed_adder off 

Default Value 

Auto 




USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING 

USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING 

Type 

Directs the Compiler to use LogicLock constraints during DSP and RAM balancing, 

thus helping the balancer to make better balancing decisions. 


Boolean 



Notes 


Syntax 

set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING 

Example 

set_global_assignment -name use_logiclock_constraints_in_balancing on 

Default Value 

On 




VERILOG_CONSTANT_LOOP_LIMIT 

VERILOG_CONSTANT_LOOP_LIMIT 

Type 

Defines the iteration limit for Verilog loops with loop conditions that evaluate to 

compile-time constants on each loop iteration. For example, such loops would have 

loop conditions that depend only on loop variables and constant expressions. If a loop 

condition refers to an input to the current module or to another variable other than a 

loop-variable, then the loop condition is most likely a non-constant loop condition, 

which has a separate limit in the Quartus II software. This logic option exists 

primarily to catch potential infinite loops before they exhaust memory or trap the 

software in an actual infinite loop. In general, you should only increase the value of 

this option, unless you are trying to identify a loop that requires excessive amounts of 

logic and therefore exhausts the memory available to the Quartus II software. If you 

decrease the value of this logic option, you may receive errors for loops that 

previously passed synthesis. 



Integer 



Notes 


Syntax 

set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 

set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -entity 

set_instance_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -to -entity 

 

Example 

set_global_assignment -name verilog_constant_loop_limit 3000 

Default Value 

5000 




VERILOG_INPUT_VERSION 

VERILOG_INPUT_VERSION 

Type 

Specifies the language dialect to use when processing Verilog Design Files, which are 

Verilog-1995 (IEEE Std. 1364-1995), Verilog-2001 (IEEE Std. 1364-2001), or 

SystemVerilog-2005 (IEEE Std. 1800-2005). Verilog 2001 is the default dialect. 

Enumeration 


■ SystemVerilog_2005 

■ Verilog_1995 

■ Verilog_2001 


Notes 


Syntax 

set_global_assignment -name VERILOG_INPUT_VERSION 

Default Value 

Verilog_2001 




VERILOG_LMF_FILE 

VERILOG_LMF_FILE 

Type 





Notes 



Syntax 

set_global_assignment -name VERILOG_LMF_FILE 




VERILOG_MACRO 

VERILOG_MACRO 

Type 

Defines Verilog HDL macro - same as `define directive. 

String 



Notes 


Syntax 

set_global_assignment -name VERILOG_MACRO 




VERILOG_NON_CONSTANT_LOOP_LIMIT 

VERILOG_NON_CONSTANT_LOOP_LIMIT 

Type 

Defines the iteration limit for Verilog loops with loop conditions that depend on 

inputs to the current module or on non-loop variables. When the loop condition does 

not evaluate to a constant true or false, the Quartus II software must create extra logic 

to account for the potential exit from the loop. This logic may accumulate over a 

number of iterations and exhaust the available memory. Eventually, the loop 

condition must evaluate to a constant false to terminate the loop. Otherwise, the 

Quartus II software exhausts the available memory or generate an error. This logic 

option exists primarily to catch potential infinite loops before they exhaust memory or 

trap the software in an actual infinite loop. In general, you should only increase the 

value of this option, unless you are trying to identify a loop that requires excessive 

amounts of logic and therefore exhausts the memory available to the Quartus II 

software. If you decrease the value of this logic option, you may receive errors for 

loops that previously passed synthesis. 



Integer 



Notes 


Syntax 

set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 

set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT -entity 

 

set_instance_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT -to - 

entity 

Example 

set_global_assignment -name verilog_non_constant_loop_limit 3000 

Default Value 

250 




VERILOG_SHOW_LMF_MAPPING_MESSAGES 

VERILOG_SHOW_LMF_MAPPING_MESSAGES 

Type 



Boolean 



Notes 


Syntax 

set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES 




VHDL_INPUT_LIBRARY 

VHDL_INPUT_LIBRARY 

Type 

Specifies the logical name of a user-defined VHDL design library, which is a physical 

name. 

String 



Notes 


Syntax 

set_instance_assignment -name VHDL_INPUT_LIBRARY -to 




VHDL_INPUT_VERSION 

VHDL_INPUT_VERSION 

Type 

Specifies the language dialect to use when processing VHDL Design Files, which are 

VHDL-1987 (IEEE Std 1076-1987), VHDL-1993 (IEEE Std 1076-1993) or VHDL-2008 

(IEEE Std 1076-2008). VHDL-1993 is the default dialect. 

Enumeration 

■ VHDL_1987 

■ VHDL_1993 

■ VHDL_2008 



Notes 


Syntax 

set_global_assignment -name VHDL_INPUT_VERSION 

Default Value 

VHDL_1993 




VHDL_LMF_FILE 

VHDL_LMF_FILE 

Type 





Notes 



Syntax 

set_global_assignment -name VHDL_LMF_FILE 




VHDL_SHOW_LMF_MAPPING_MESSAGES 

VHDL_SHOW_LMF_MAPPING_MESSAGES 

Type 



Boolean 



Notes 


Syntax 

set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES 



ALLOW_MULTIPLE_PERSONAS 

Type 










June 2012 

5. Incremental Compilation Assignments 

Specifies if this partition represents a reconfigurable part of the design that can have 

mulitple personas (implementations). 

Boolean 



■ Stratix V 

Notes 


devices. 

Syntax 

set_global_assignment -name ALLOW_MULTIPLE_PERSONAS -entity 

-section_id 

set_instance_assignment -name ALLOW_MULTIPLE_PERSONAS -to -entity 

-section_id 

Default Value 

Off, requires section identifier and entity name 

ISO 

9001:2008 

Registered 

Subscribe

5–2 Chapter 5: Incremental Compilation Assignments 

AUTO_EXPORT_INCREMENTAL_COMPILATION 

AUTO_EXPORT_INCREMENTAL_COMPILATION 

Type 

Automatically exports the project as a design partition. 

Boolean 



■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 


devices. 

Syntax 

set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION 

Default Value 

Off 



Chapter 5: Incremental Compilation Assignments 5–3 

IGNORE_PARTITIONS 

IGNORE_PARTITIONS 

Type 

Specifies whether the Compiler should ignore partition assignments in the project. 

Boolean 



Notes 


devices. 

Syntax 

set_global_assignment -name IGNORE_PARTITIONS 

Default Value 

Off 




INCREMENTAL_COMPILATION_EXPORT_FILE 

INCREMENTAL_COMPILATION_EXPORT_FILE 

Type 

Specifies the path to the exported file. The file must have a Quartus II Exported 

Partition File (.qxp) extension. 




■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 



devices. 

Syntax 

set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_FILE 




INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME 

INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME 

Type 

Specifies the name of the partition that contains the design hierarchy to be exported. 

The root partition is exported if this assignment is not specified. 

String 



■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 



devices. 

Syntax 

set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME 




INCREMENTAL_COMPILATION_EXPORT_POST_FIT 

INCREMENTAL_COMPILATION_EXPORT_POST_FIT 

Type 

Specifies whether the exported Quartus II Exported Partition File (.qxp) contains the 

post-fit netlist 

Boolean 



Notes 


devices. 

Syntax 

set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_POST_FIT 

 




INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH 

INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH 

Type 

Specifies whether the exported Quartus II Exported Partition File (.qxp) contains the 

post-synthesis netlist. 

Boolean 



Notes 


devices. 

Syntax 

set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH 

 




INCREMENTAL_COMPILATION_EXPORT_ROUTING 

INCREMENTAL_COMPILATION_EXPORT_ROUTING 

Type 

Specifies whether the post-fit netlist exported to the Quartus II Exported Partition File 

(.qxp) contains routing information. 

Boolean 



■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 


devices. 

Syntax 

set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_ROUTING 




INPUT_PERSONA 

INPUT_PERSONA 

Type 

Specifies the input persona file to use for this partition. 




■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 



devices. 

Syntax 

set_global_assignment -name INPUT_PERSONA -entity - 

section_id 

set_instance_assignment -name INPUT_PERSONA -to -entity 

-section_id 




PARTITION_ALWAYS_USE_QXP_NETLIST 

PARTITION_ALWAYS_USE_QXP_NETLIST 

Type 

Specifies whether to always use the netlist in the Quartus II Exported Partition File 

(.qxp) associated with the partition, either because the Quartus II Exported Partition 

File (.qxp) is imported into the partition, or is specified as a source file for the 

partition. Setting defaults to Off. 

Boolean 



Notes 


devices. 

Syntax 

set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST -entity 

-section_id 

set_instance_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST -to - 

entity -section_id 

Default Value 





PARTITION_FITTER_PRESERVATION_LEVEL 

PARTITION_FITTER_PRESERVATION_LEVEL 

Type 

Specifies the amount of data to reuse when you specify to reuse the post-fit netlist of 

this partition. 

Enumeration 


■ COMPATIBLE_PLACEMENT 

■ COMPATIBLE_PLACEMENT_AND_ROUTING 

■ NETLIST_ONLY 

■ PLACEMENT 

■ PLACEMENT_AND_ROUTING 

■ PLACEMENT_AND_ROUTING_AND_HIGH_SPEED_TILES 


■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 


devices. 

Syntax 

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL -entity 

-section_id 

set_instance_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL -to 

-entity -section_id 




PARTITION_HIERARCHY 

PARTITION_HIERARCHY 

Type 

The target of the assignment specifies the hierarchy path of the entity instance for the 

partition. The value of the assignment specifies the base output filename for writing 

intermediary atom netlists. Altera recommends that you rely on the default output 

filenames generated by the Quartus II software. If you decide to provide your own 

filenames, you must ensure their uniqueness among partitions. 




■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 


Syntax 

set_global_assignment -name PARTITION_HIERARCHY -entity - 

section_id 

set_instance_assignment -name PARTITION_HIERARCHY -to -entity -section_id 

set_global_assignment -name PARTITION_HIERARCHY -entity 

 

set_instance_assignment -name PARTITION_HIERARCHY -to -entity 

Old Names 


software: 

INCREMENTAL_DESIGN_PARTITION 




PARTITION_IGNORE_SOURCE_FILE_CHANGES 

PARTITION_IGNORE_SOURCE_FILE_CHANGES 

Type 

Specifies whether to use the requested post-synthesis or post-fit netlist when it is 

available, even when source file changes are present. Setting defaults to Off. 

Boolean 



Notes 


devices. 

Syntax 

set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES -entity 

-section_id 

set_instance_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES -to 


Default Value 





PARTITION_IMPORT_ASSIGNMENTS 

PARTITION_IMPORT_ASSIGNMENTS 

Type 

Specifies whether LogicLock or non-LogicLock assignments should be imported. If 

set to FALSE, only the netlist will be imported. 

Boolean 



■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 


devices. 

Syntax 

set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS -entity -section_id 

set_instance_assignment -name PARTITION_IMPORT_ASSIGNMENTS -to - 


Default Value 

On, requires section identifier and entity name 




PARTITION_IMPORT_EXISTING_ASSIGNMENTS 

PARTITION_IMPORT_EXISTING_ASSIGNMENTS 

Type 

Specifies the way existing and conflicting non-LogicLock region assignments should 

be handled during import. 

Enumeration 


■ REPLACE_CONFLICTING 

■ SKIP_CONFLICTING 


■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 


devices. 

Syntax 

set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS -entity 

-section_id 

set_instance_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS -to 


Default Value 

REPLACE_CONFLICTING, requires section identifier and entity name 




PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS 

PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS 

Type 

Specifies the way existing and conflicting LogicLock region assignments should be 

handled during import. 

Enumeration 


■ REPLACE_CONFLICTING 

■ SKIP_CONFLICTING 

■ UPDATE_CONFLICTING 


■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 


devices. 

Syntax 

set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS - 


set_instance_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS 

-to -entity -section_id 

Default Value 

REPLACE_CONFLICTING, requires section identifier and entity name 




PARTITION_IMPORT_FILE 

PARTITION_IMPORT_FILE 

Type 

Specifies the name of the file from which to import the contents for the partition. This 

setting is only used during importation. 




■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 



devices. 

Syntax 

set_global_assignment -name PARTITION_IMPORT_FILE -entity - 

section_id 

set_instance_assignment -name PARTITION_IMPORT_FILE -to -entity 

-section_id 




PARTITION_IMPORT_PROMOTE_ASSIGNMENTS 

PARTITION_IMPORT_PROMOTE_ASSIGNMENTS 

Type 

Specifies whether assignments should be promoted to all instances of the imported 

entity. 

Boolean 



■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 


devices. 

Syntax 

set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS -entity 

-section_id 

set_instance_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS -to 


Default Value 





PARTITION_LAST_IMPORTED_FILE 

PARTITION_LAST_IMPORTED_FILE 

Type 

Specifies the name of the file from which the partition was last imported. This 

assignment is for purely informational purpose only. 




■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 



devices. 

Syntax 

set_global_assignment -name PARTITION_LAST_IMPORTED_FILE -entity -section_id 

set_instance_assignment -name PARTITION_LAST_IMPORTED_FILE -to - 





PARTITION_NETLIST_TYPE 

PARTITION_NETLIST_TYPE 

Type 

Specifies the type of netlist to use for this partition during the next compilation. 

Enumeration 

■ Auto 

■ EMPTY 

■ IMPORTED 

■ IMPORT_BASED_POST_FIT 

■ POST_FIT 

■ POST_FIT_WITH_ROUTING 

■ POST_SYNTH 

■ SOURCE 


■ STRICT_POST_FIT 


■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Notes 


devices. 

Syntax 

set_global_assignment -name PARTITION_NETLIST_TYPE -entity - 

section_id 

set_instance_assignment -name PARTITION_NETLIST_TYPE -to -entity 

-section_id 




PARTITION_PRESERVE_HIGH_SPEED_TILES 


Type 

Specifies whether to preserve the high-speed tiles in the post-fit netlist, if applicable. 

Boolean 



Notes 


devices. 

Syntax 

set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES -entity 

-section_id 

set_instance_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES -to 


Default Value 








ACTIVE_SERIAL_CLOCK 

Type 










June 2012 

6. Fitter Assignments 

Specifies the clock source for Fast Active Serial Programming. You can select an 

internal oscillator clock or an external clock as the clock source for Fast Active Serial 

programming. If you choose an external clock as the source, you can control exactly 

when the device enters user mode. The external clock is provided through the CLKUSR 

pin and you should enable user-supplied start-up clock (CLKUSR) option. The default is 

to use an internal oscillator clock of 40 MHz for Arria II GX and Cyclone IV devices, 

and 100 MHz for Stratix V and Arria V devices. 

Enumeration 

■ CLKUSR 


■ FREQ_100MHz 

■ FREQ_12_5MHz 







■ Arria V 


■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_global_assignment -name ACTIVE_SERIAL_CLOCK 

ISO 

9001:2008 

Registered 

Subscribe

6–2 Chapter 6: Fitter Assignments 

ACTIVE_SERIAL_CLOCK 

Example 

set_global_assignment -name active_serial_clock "CLKUSR" 

See Also 

■ “USER_START_UP_CLOCK” on page 6–361 



Chapter 6: Fitter Assignments 6–3 

ADCE_ENABLED 

ADCE_ENABLED 

Type 

Disables the Adaptive Dispersion Compensation Engine (ADCE) on a physical media 

attachment (PMA) direct channel for RX PMA. Setting this option to Off disables the 

ADCE. Setting this option to Auto leaves the ADCE setting unchanged. The default 

value is Auto. 

Enumeration 

■ Auto 

■ Off 






Syntax 

set_global_assignment -name ADCE_ENABLED 

set_instance_assignment -name ADCE_ENABLED -to 

Default Value 

Auto 




ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER 

ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER 

Type 

Specifies whether the Fitter allows input pins with LVTTL or LVCMOS I/O standards 

to be placed inside an I/O bank with a lower V CCIO voltage than the voltage specified 

by the pins. Overdriving the I/O bank results in higher leakage current, which can 

cause the design to not function as intended. 

Boolean 



■ Arria GX 

■ Cyclone 




■ MAX V 

■ Stratix 




Syntax 


ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER 

Default Value 

Off 




ALWAYS_ENABLE_INPUT_BUFFERS 

ALWAYS_ENABLE_INPUT_BUFFERS 

Type 

Enables input buffers on all I/O pins including output pins. This option is required 

for the SAMPLE/PRELOAD JTAG instruction to function correctly on output pins. 

Turning on this option consumes more power. 

Boolean 



■ Arria GX 




■ MAX V 



Notes 


Syntax 

set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS 

Default Value 

Off 




ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK 

ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK 

Type 

Allows the automatic asynchronous signal pipelining algorithm to run on the 

specified asynchronous signal even if it feeds synchronous inputs. However, turning 

this option On can change circuit functionality. This option is intended for advanced 

users 

Boolean 



Syntax 

set_global_assignment -name ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK - 

entity 

set_instance_assignment -name ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK -to 

-entity 




ASYNC_PIPELINE_REG_REACH 

ASYNC_PIPELINE_REG_REACH 

Type 

Specify the maximum number of LABs that the asynchronous signal sourcing at the 

To register can go across before a new pipeline register is inserted. This requirement 

might not be met for all pipeline stages, when, due to congestion or over-filled LABs, 

the register cannot be placed at the desired location. 

Integer 



Syntax 

set_global_assignment -name ASYNC_PIPELINE_REG_REACH -entity 

 

set_instance_assignment -name ASYNC_PIPELINE_REG_REACH -to -entity 

 




AUTO_C3_M9K_BIT_SKIP 

AUTO_C3_M9K_BIT_SKIP 

Type 

Directs the Fitter to skip certain bitlines in Cyclone III (including LS) M9K blocks that 

may be susceptible to read bit error when used in affected modes. The Standard 

setting reserves the necessary M9K bitlines to ensure correct operation for all devices 

within the selected temperature range. The Auto setting applies the necessary bitline 

reservation to additional modes (×16 or ×18) to provide extra margin. The Maximum 

setting applies the most conservative bitline reservation required for industrial 

temperature ranges regardless of the targeted device settings. Enabling any of these 

options can increase the number of M9K blocks required to implement the design. 

You can override this global setting for each memory instance in the Assignment 

Editor to customize the solution. Certain RAM modes may not be supported for 

commercial temperature range devices when the Standard or Auto setting is applied. 

The Fitter issues an error for these cases. You can implement RAM cells by making an 

instance assignment with the Maximum setting, in which case additional M9K blocks 

may be used. For more information, refer to the Cyclone III Device Family Errata Sheet. 

Enumeration 

■ Auto 

■ Maximum 

■ Off 

■ Standard 





Notes 


Syntax 

set_global_assignment -name AUTO_C3_M9K_BIT_SKIP 

Default Value 

Off 




AUTO_DELAY_CHAINS 


Type 

Allows the Fitter to choose the optimal delay chain to meet tsu and tco timing 

requirements for all I/O elements. Turning on this option may reduce the number of 

tsu violations while introducing a minimal number of th violations. Turning on this 

option does not override delay chain settings on individual nodes. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Notes 






Syntax 

set_global_assignment -name AUTO_DELAY_CHAINS 

Default Value 

On 




AUTO_GLOBAL_CLOCK 


Type 

Allows the Compiler to choose the signal that feeds the most clock inputs to flipflops 

as a global clock signal that is made available throughout the device on the global 


particular signal as global clock, set the Global Signal option to Off on that signal. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 

■ EPC1 

■ EPC2 

■ Enhanced Configuration Devices 

■ FLEX10KB 

■ FLEX8000 





■ MAX V 

■ MAX9000 

■ Stratix 










■ Stratix V 

Notes 



Syntax 

set_global_assignment -name AUTO_GLOBAL_CLOCK 

set_global_assignment -name AUTO_GLOBAL_CLOCK -entity 

 

set_instance_assignment -name AUTO_GLOBAL_CLOCK -to -entity 

Default Value 

On 




AUTO_GLOBAL_MEMORY_CONTROLS 

AUTO_GLOBAL_MEMORY_CONTROLS 

Type 

Allows the Compiler to choose the signals that feed the most write enable and read 

enable inputs to memories as global write enable and read enable signals that are 

made available throughout the device on the global routing paths. If you want to 

prevent the Compiler from automatically selecting a particular signal as global 

memory control signal, set the Global Signal option to Off on that signal. 

Boolean 



■ Arria GX 

■ Cyclone 




■ Stratix 




Notes 



Syntax 

set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS 

set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS -entity 

set_instance_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS -to -entity 

 

Default Value 

Off 




AUTO_GLOBAL_REGISTER_CONTROLS 


Type 

Allows the Compiler to choose the signals that feed the most control signal inputs to 

flipflops (excluding clock signals) as global signals that are made available 

throughout the device on the global routing paths. Depending on the target device 

family, these control signals can include asynchronous clear and load, synchronous 

clear and load, clock enable, and preset signals.If you want to prevent the Compiler 

from automatically selecting a particular signal as global register control signal, set 

the Global Signal option to Off on that signal. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 

■ EPC1 

■ EPC2 


■ FLEX10KB 

■ FLEX8000 





■ MAX V 

■ MAX9000 

■ Stratix 










■ Stratix V 

Notes 



Syntax 

set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS 

set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS -entity 

set_instance_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS -to - 

entity 

Default Value 

On 




AUTO_MERGE_PLLS 


Type 

Allows the Compiler to automatically find and merge together two compatible phaselocked 

loops (PLL) driven by the same clock source, reducing the total number of 

PLLs used in a design. 

Boolean 



■ Arria GX 



■ Cyclone 









■ Stratix 






Notes 



Syntax 

set_global_assignment -name AUTO_MERGE_PLLS 

set_global_assignment -name AUTO_MERGE_PLLS -entity 





set_instance_assignment -name AUTO_MERGE_PLLS -to -entity 

Default Value 

On 




AUTO_PACKED_REGISTERS_CYCLONE 


Type 

Allows the Compiler to automatically implement a register and a combinational 

function in the same logic cell, or to implement registers using I/O cells or RAM 

blocks instead of logic cells. This option controls how aggressively the Fitter combines 

registers with other function blocks in order to reduce logic element count. If this 

option is set to Off, the Fitter does not attempt to place a pair of logic functions in a 

single logic cell; however, logic cells specified during synthesis to perform both a 

combinational and a sequential function are maintained. If this option is set to 

Normal, the Fitter places both a combinational and a sequential operation in a logic 

cell when it is expected that the placement does not affect design performance. When 

this option is set to Minimize Area, the Fitter aggressively combines unrelated 

sequential and combinational functions that are not part of an arithmetic or register 

cascade chain into a single logic cell in order to reduce the logic cell count, even at the 

expense of design performance. When this option is set to Minimize Area with 

Chains, the Fitter even more aggressively combines sequential and combinational 

functions that are part of arithmetic or register cascade chains or that can be converted 

to register cascade chains. When this setting is Auto, the fitter attempts to achieve the 

best performance while maintaining a fit for the design in the specified device. The 

fitter will combine all combinational and sequential functions that are deemed to 

benefit circuit speed. In addition, more aggressive combinations of unrelated 

combinational and sequential functions are performed to the extent required to 

reduce the area of the design in order to achieve a fit in the specified device. If this 

option is set to any value but Off, registers are merged with I/O cells to improve I/O 

timing, and with RAM blocks to reduce logic cell count or improve timing when 

possible. 

Enumeration 

■ Auto 

■ Minimize Area 

■ Minimize Area with Chains 

■ Normal 

■ Off 



■ Cyclone 

Notes 



Syntax 

set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE 





set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE -entity 

set_instance_assignment -name AUTO_PACKED_REGISTERS_CYCLONE -to - 

entity 

Default Value 

Auto 

Old Names 


software: 

AUTO_PACKED_REG_CYCLONE 

Auto Packed Registers -- Cyclone 




AUTO_PACKED_REGISTERS_MAXII 


Type 


function in the same logic cell. This option controls how aggressively the Fitter 

combines registers with other function blocks in order to reduce logic element count. 

If this option is set to Off, the Fitter does not attempt to place a pair of logic functions 

in a single logic cell; however, logic cells specified during synthesis to perform both a 





sequential and combinational functions into a single logic cell in order to reduce the 

logic cell count, even at the expense of design performance. When this option is set to 

Minimize Area with Chains, the Fitter even more aggressively combines sequential 

and combinational functions that are part of arithmetic or register cascade chains or 

that can be converted to register cascade chains. When this setting is Auto, the Fitter 

attempts to achieve the best performance while maintaining a fit for the design in the 

specified device. The Fitter combines all combinational and sequential functions that 

are deemed to benefit circuit speed. In addition, more aggressive combinations of 

unrelated combinational and sequential functions are performed to the extent 

required to reduce the area of the design in order to achieve a fit in the specified 

device. 

Enumeration 

■ Auto 



■ Normal 

■ Off 




■ MAX V 

Notes 


Syntax 

set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII 

set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII -entity 





set_instance_assignment -name AUTO_PACKED_REGISTERS_MAXII -to -entity 

 

Default Value 

Auto 

Old Names 


software: 

AUTO_PACKED_REGISTERS_TSUNAMI 

Auto Packed Registers -- MAX II 




AUTO_PACKED_REGISTERS_STRATIX 


Type 


function in the same logic cell, or to implement registers using I/O cells, RAM blocks, 

or DSP blocks instead of logic cells. This option controls how aggressively the Fitter 

combines registers with other function blocks in order to reduce logic element count. 

If this option is set to Off, the Fitter does not attempt to place a pair of logic functions 

in a single logic cell; however, logic cells specified during synthesis to perform both a 





sequential and combinational functions into a single logic cell in order to reduce the 

logic cell count, even at the expense of design performance. When this option is set to 

Minimize Area with Chains, the Fitter even more aggressively combines sequential 

and combinational functions that are part of arithmetic or register cascade chains or 

that can be converted to register cascade chains. When this setting is Auto, the fitter 

attempts to achieve the best performance while maintaining a fit for the design in the 

specified device. The Fitter combines all combinational and sequential functions that 

are deemed to benefit circuit speed. In addition, more aggressive combinations of 

unrelated combinational and sequential functions are performed to the extent 

required to reduce the area of the design in order to achieve a fit in the specified 

device. If this option is set to any value but Off, registers are merged with I/O cells to 

improve I/O timing, and with DSP blocks and RAM blocks to reduce logic cell count 

or improve timing when possible. 

Enumeration 

■ Auto 



■ Normal 

■ Off 



■ Stratix 


Notes 



Syntax 

set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX 





set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX -entity 

set_instance_assignment -name AUTO_PACKED_REGISTERS_STRATIX -to - 

entity 

Default Value 

Auto 

Old Names 


software: 

AUTO_MODIFIED_PACKED_REGISTERS 

Auto Packed Registers -- Stratix/Stratix GX 




AUTO_PACKED_REGISTERS_STRATIXII 


Type 

Allows the Compiler to combine a register and a combinational function, or to 

implement registers using I/O cells, RAM blocks, or DSP blocks instead of logic cells. 

This option controls how aggressively the Fitter combines registers with other 

function blocks to reduce the area of the design. Generally, the Auto or Sparse Auto 

settings should be used for this option. The other options limit the flexibility of the 

Fitter to combine registers with other function blocks and can result in no fits. When 

Auto, the default setting is selected, the Fitter attempts to achieve the best 

performance with good area. If necessary, additional logic is combined to reduce the 

area of the design so that it can fit within the selected device. When this setting is 

Sparse Auto, the Fitter attempts to achieve the highest performance with possibly 

increased area, but without exceeding the logic capacity of the device. If this option is 

set to Off, the Fitter does not combine registers with other functions. The Off setting 

severely increases the area of the design and may cause a no fit. If this option is set to 

Sparse, the Fitter combines functions in a way which improves performance for many 

designs. If this option is set to Normal, the Fitter combines functions that are expected 

to maximize design performance and reduce area. When this option is set to 

Minimize Area, the Fitter aggressively combines unrelated functions to reduce the 

area required for placing the design, at the expense of performance. When this option 

is set to Minimize Area with Chains, the Fitter even more aggressively combines 

functions that are part of register cascade chains or can be converted to register 

cascade chains. If this option is set to any value but Off, registers are combined with 

I/O cells to improve I/O timing (as long as the Optimize IOC Register Placement 

For Timing option allows it), and with DSP blocks and RAM blocks to reduce the area 

required for placing the design or to improve timing when possible. 

Enumeration 

■ Auto 



■ Normal 

■ Off 

■ Sparse 

■ Sparse Auto 



■ Arria GX 



■ Arria V 










■ Cyclone V 








■ Stratix V 

Notes 



Syntax 

set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII 

set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII -entity 

 

set_instance_assignment -name AUTO_PACKED_REGISTERS_STRATIXII -to - 

entity 

Default Value 

Auto 

Old Names 


software: 

AUTO_PACKED_REGISTERS_ARMSTRONG 

Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX 




AUTO_TURBO_BIT 

AUTO_TURBO_BIT 

Type 

Controls the speed versus power usage trade-off for a macrocell. If you set the Turbo 

Bit option to on, the speed of the macrocell increases; if you set this option to Off, its 

power consumption decreases; if you choose the Auto setting, the Compiler chooses 

the most appropriate setting for the design. 

Enumeration 

■ Auto 

■ Off 

■ On 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_global_assignment -name AUTO_TURBO_BIT 

set_global_assignment -name AUTO_TURBO_BIT -entity 

set_instance_assignment -name AUTO_TURBO_BIT -to -entity 

Default Value 

On 




BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE 

BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE 

Type 

Directs the Compiler to base the Pin-Out File (.pin) and floorplan package views on 

the largest selected SameFrame device. 

Boolean 



Syntax 

set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE 

Default Value 

Off 




BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES 


Type 

Controls whether RAMs implemented in MLAB cells must have equivalent pause 

read capabilities as RAMs implemented in block RAM. Pausing a read is the ability to 

keep around the last read value when reading is disabled. Allowing differences in 

paused read capabilities provides the Fitter more flexibility in implementing RAMs 

using MLAB cells. If you set this option to Don’t Care, the RAMs may convert RAMs 

to MLAB cells even if the Fitter does not have the equivalent paused read capabilities 

to a block RAM implementation. The Fitter also sends an information message 

notifying you of RAMs with different paused read capabilities. If you set this option 

to Care, the Fitter does not convert RAMs to MLAB cells unless the RAMs have the 

equivalent paused read capabilities to a block RAM implementation. To allow the 

Fitter the most flexibility in deciding which RAMs are implemented using MLAB 

cells, set this option to Don’t Care. 

Enumeration 

■ Care 

■ Don’t Care 





■ Arria V 

■ Cyclone V 





■ Stratix V 

Notes 


Syntax 


BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES 


BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES -entity 






BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES -to -entity 

 

Default Value 

Care 




BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS 


Type 

Controls whether RAMs implemented in MLAB cells must have equivalent power up 

conditions as RAMs implemented in block RAM. Power up conditions occur when 

the device is powered up or globally reset. Allowing non-equivalent power up 

conditions provides the Fitter more flexibility in implementing RAMs using MLAB 

cells. If you set this option to Auto, the Fitter may convert RAMs to MLAB cells even 

if the RAMs do not have the equivalent power up conditions to a block RAM 

implementation. The Fitter also sends a warning message notifying you of RAMs with 

non-equivalent power up conditions. If you set this option to Don’t Care, the same 

behavior as Auto applies, but the warning message is an information message 

instead. If you set this option to Care, the Fitter does not convert RAMs to MLAB cells 

unless the RAMs have the equivalent power up conditions to a block RAM 

implementation. To allow the Fitter the most flexibility in deciding which RAMs are 

implemented using MLAB cells, set this option to Auto or Don’t Care. 

Enumeration 

■ Auto 

■ Care 

■ Don’t Care 





■ Arria V 

■ Cyclone V 





■ Stratix V 

Notes 


Syntax 


BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS 






BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS -entity 

 


BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS -to -entity 

Default Value 

Auto 




BLOCK_RAM_TO_MLAB_CELL_CONVERSION 

BLOCK_RAM_TO_MLAB_CELL_CONVERSION 

Type 

Controls whether the fitter is able to convert RAMs to use LAB locations when those 

RAMs use Auto as the selected block type. If this option is changed to Off, only 

MLAB cells in the design or RAM cells with a block type setting of MLAB uses LAB 

locations to implement memory. 

Boolean 









■ Stratix V 

Notes 


Syntax 

set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION 

set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION -entity 

 

set_instance_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION -to - 

entity 

Default Value 

On 




C3_M9K_BIT_SKIP 

C3_M9K_BIT_SKIP 

Type 

Directs the Fitter to skip certain bitlines in Cyclone III M9K blocks when 

implementing the specificed RAM or ROM cell. The default remapping behavior is 

determined by the overall RAM Bit Reservation Fitter setting, accessible from the 

More Fitter Settings page of the Settings dialog box. This setting can be used to 

override that behavior for a specified RAM. For more information about the values for 

the setting, refer to the description of the global setting. 

Enumeration 

■ Auto 

■ Maximum 

■ Off 





Notes 


Syntax 

set_instance_assignment -name C3_M9K_BIT_SKIP -to -entity 




CDR_BANDWIDTH_PRESET 

CDR_BANDWIDTH_PRESET 

Type 

Specifies the CDR (clock data recovery) bandwidth preset setting. 

Enumeration 

■ Auto 

■ High 

■ Low 

■ Medium 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name CDR_BANDWIDTH_PRESET -to -entity 

 




CKN_CK_PAIR 

CKN_CK_PAIR 

Type 

Specifies the pairing of a CKn pin to a CK pin. The I/O pin of a CK CKn pair must be 

placed on a differential pin pair. This option is ignored if is assigned to anything other 

than an I/O pad, input buffer, or output buffer. 

Boolean 



Notes 


Syntax 

set_instance_assignment -name CKN_CK_PAIR -from -to -entity 

 




CLAMPING_DIODE 

CLAMPING_DIODE 

Type 

Turns on the clamping diode of a pin. The clamping diode can be turned on to limit 

overshoot voltage for a pin in input operation. The clamping diode is turned on by 

default for 3.0-V PCI/PCI-X I/O standards. The clamping diode is turned off by 

default for 3.3-V LVTTL/LVCMOS I/O standards. This option is ignored if it is 

applied to anything other than a pin or a top-level design entity. 

Boolean 





■ Arria V 

■ Cyclone V 





Notes 



Syntax 

set_global_assignment -name CLAMPING_DIODE -entity 

set_instance_assignment -name CLAMPING_DIODE -to -entity 

set_global_assignment -name CLAMPING_DIODE 

Example 

set_instance_assignment -name CLAMPING_DIODE ON -to pin 

Default Value 

Off 




CLOCK_TO_OUTPUT_DELAY 

CLOCK_TO_OUTPUT_DELAY 

Type 

Specifies the propagation delay to the output or bidirectional pin from the output 

register implemented in an I/O cell. This is an advanced option that should be used 

only after you have compiled a project, checked the I/O timing, and determined that 

the timing is unsatisfactory. For detailed information on how to use this option, refer 

to the data sheet for the device family. This option is off by default. This option is 

ignored if it is applied to anything other than an output or bidirectional pin. 

Integer 



■ Arria GX 










Notes 


Syntax 

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY -to -entity 

 




CONFIGURATION_VCCIO_LEVEL 


Type 

Specifies the V CCIO voltage of the configuration pins for the current configuration 

scheme on the target device. 

Some configuration schemes support multiple configuration voltage levels. This 

option allows you to specify a configuration voltage level. 

The Fitter produces warnings if the configuration voltage level is not consistent with 

the V CCIO after the I/O placement. 

You can use the FORCE_CONFIGURATION_VCCIO option to force the V CCIO voltage 

of the configuration pins to be the same as the configuration device I/O voltage. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 








■ Stratix V 

Syntax 

set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 

Example 

set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V 





Default Value 

Auto 

See Also 

■ “FORCE_CONFIGURATION_VCCIO” on page 6–134 




CRC_ERROR_CHECKING 


Type 

Specifies error detection CRC usage for the selected device. If error detection CRC is 

turned on, the device checks the validity of the programming data in the device. Any 

changes in the data while the device is in operation generates an error. 

Using this feature in Stratix, Cyclone, or Stratix GX devices causes a reduction in 

device speed. 

Enabling this option puts the dual-purpose CRCERROR pin into configuration mode. 

Boolean 



■ Arria GX 



■ Cyclone 









■ Stratix 






Syntax 

set_global_assignment -name CRC_ERROR_CHECKING 

Example 

set_global_assignment -name CRC_ERROR_CHECKING ON 





Default Value 

Off 

Old Names 


software: 

STRATIX_CRC_ERROR_CHECKING 

YEAGER_CRC_ERROR_CHECKING 

See Also 

■ “CRC_ERROR_OPEN_DRAIN” on page 6–42 

■ “ERROR_CHECK_FREQUENCY_DIVISOR” on page 6–116 




CRC_ERROR_OPEN_DRAIN 

CRC_ERROR_OPEN_DRAIN 

Type 

Specifies whether the Open-Drain feature on the CRC Error pin should be enabled or 

not. 

Using this feature decouples the voltage level of the CRCERROR pin from V CCIO. 

A pull-up resistor must be connected to the pin when this feature is enabled. 

Boolean 



■ Arria V 




■ Cyclone V 



■ Stratix V 

Syntax 

set_global_assignment -name CRC_ERROR_OPEN_DRAIN 

Example 

set_global_assignment -name crc_error_open_drain on 

set_global_assignment -name crc_error_open_drain off 

See Also 






CURRENT_STRENGTH_NEW 


Type 

Sets the drive strength of a pin. Specify a number (in mA), MIN, or MAX for output or 

bidirectional pins that support programmable drive strength. Refer to the family data 

sheet for which drive strengths are allowed for each I/O standard. This option is 


This option specifies a current strength setting for the single-ended output buffer of a 

pin. Since an input-only pin does not use single-ended output buffer, this option is 

ignored on such pin. This option is not supported on a pin with I/O standard which 

uses true differential output buffer such as LVDS. Some differential I/O standards are 

implemented with two single-ended output buffers and therefore this option may be 

supported. Refer to the family data sheet for which I/O standards support 

programmable drive strengths. This option can only be supported on pin locations 

that support programmable drive strength. Dedicated programming pins, such as 

TDO, do not support programmable drive strength. If output termination is enabled 

on a pin, then this current strength assignment should not be used on the pin. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name CURRENT_STRENGTH_NEW -to -entity 

 

Example 

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to output_pin 

Old Names 


software: 

CURRENT_STRENGTH 

See Also 

■ “IO_STANDARD” on page 6–186 

■ “OUTPUT_TERMINATION” on page 6–231 




CVP_CONFDONE_OPEN_DRAIN 

CVP_CONFDONE_OPEN_DRAIN 

Type 

Specify open drain on the CvP_CONFDONE pin should be enabled or not. 

Using this feature decouples the voltage level of the CvP_CONFDONE pin from V CCIO. 


Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN 

Example 

set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN on 

set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN off 

Default Value 

On 

Old Names 


software: 

CVPCIE_CONFDONE_OPEN_DRAIN 

See Also 

■ “ENABLE_CVP_CONFDONE” on page 6–104 




CVP_MODE 

CVP_MODE 

Type 

Specifies the configuration mode for Configuration via Protocol (CvP). 

Enumeration 

■ Off 


■ Power up and subsequent core configuration 

■ Subsequent core reconfiguration 


■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name CVP_MODE 

Example 

set_global_assignment -name CVP_MODE "Power up and subsequent core 

configuration" 

Default Value 

Off 

Old Names 


software: 

CVPCIE_MODE 




CYCLONEIII_CONFIGURATION_SCHEME 

CYCLONEIII_CONFIGURATION_SCHEME 

Type 

The method used to load data into the device. Up to four configuration schemes are 

available, depending on the selected device: Passive Serial (PS); Fast Passive Parallel 

(FPP), Active Parallel (AP) and Active Serial (AS). 

Enumeration 







Syntax 

set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME 

Example 

set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active 

Serial" 

Default Value 

Active Serial 




CYCLONEII_CONFIGURATION_SCHEME 

CYCLONEII_CONFIGURATION_SCHEME 

Type 

The method used to load data into the device. Two configuration schemes are 

available: Passive Serial (PS) and Active Serial (AS). 

Enumeration 

■ Active Serial 


■ Passive Serial 



Syntax 

set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME 

Default Value 

Active Serial 




CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION 

CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION 

Type 

Specifies how the nCEO pin should be used when the device is operating in user mode 

after configuration is complete. The nCEO pin can be reserved as dedicated nCEO 

programming pin or a regular I/O pin. 

Enumeration 


■ Use as programming pin 

■ Use as regular IO 








Syntax 

set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION 

 

Example 

set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION 

"Use as programming pin" 

Default Value 

Use as programming pin 




CYCLONEII_TERMINATION 

CYCLONEII_TERMINATION 

Type 

Allows the Compiler to configure the on-chip termination (OCT) and impedance 

matching for an I/O pin. OCT helps to prevent signal reflections and maintain signal 

integrity. This option is ignored if it is applied to anything other than an I/O pin. 

Enumeration 

■ Off 


■ Series 25 Ohms 

■ Series 50 Ohms 



Notes 


Syntax 

set_instance_assignment -name CYCLONEII_TERMINATION -to -entity 

 

Old Names 


software: 

Termination -- CYCLONE II 




CYCLONE_CONFIGURATION_SCHEME 

CYCLONE_CONFIGURATION_SCHEME 

Type 

The method used to load data into the device. Two configuration schemes are 

available: Passive Serial (PS) and Active Serial (AS). 

Enumeration 





■ Cyclone 

Syntax 

set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME 

Default Value 

Active Serial 




D1_DELAY 

D1_DELAY 

Type 

Specifies the propagation delay for D1 Delay Cell. This is an advanced option that 

should be used only after you have compiled a project, checked the I/O timing, and 

determined that the timing is unsatisfactory. For detailed information on how to use 

this option, refer to the data sheet for the device family. This option is ignored if it is 

applied to anything other than an input or bidirectional pin. 

Integer 




■ Arria V 

■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name D1_DELAY -to -entity 

 

Old Names 


software: 

T1_DELAY 




D1_FINE_DELAY 

D1_FINE_DELAY 

Type 

Enable the fine delay resolution on D1 Delay. 

Boolean 



Notes 


Syntax 

set_instance_assignment -name D1_FINE_DELAY -to -entity 

 

Old Names 


software: 

T1_FINE_DELAY 




D2_DELAY 

D2_DELAY 

Type 






Integer 








■ Stratix V 

Notes 


Syntax 


 

Old Names 


software: 

T2_DELAY 




D3_DELAY 

D3_DELAY 

Type 






Integer 




■ Arria V 

■ Cyclone V 





■ Stratix V 

Notes 


Syntax 


 

set_instance_assignment -name D3_DELAY -from -to -entity 

 

Old Names 


software: 

T3_DELAY 




D4_DELAY 

D4_DELAY 

Type 






Integer 




■ Arria V 

■ Cyclone V 





■ Stratix V 

Notes 


Syntax 


 

Old Names 


software: 

T7_DELAY 




D4_FINE_DELAY 

D4_FINE_DELAY 

Type 


Boolean 



Notes 


Syntax 


 

Old Names 


software: 

T7_FINE_DELAY 




D5_DELAY 

D5_DELAY 

Type 





applied to anything other than an output or bidirectional pin. 

Integer 




■ Arria V 

■ Cyclone V 





■ Stratix V 

Notes 


Syntax 


 

Old Names 


software: 

T9_DELAY 




D5_FINE_DELAY 

D5_FINE_DELAY 

Type 


Boolean 



Notes 


Syntax 


 

Old Names 


software: 

T9_FINE_DELAY 




D5_OCT_DELAY 

D5_OCT_DELAY 

Type 

Specifies the propagation delay for D5 OCT Delay Cell. This is an advanced option 

that should be used only after you have compiled a project, checked the I/O timing, 

and determined that the timing is unsatisfactory. For detailed information on how to 

use this option, refer to the data sheet for the device family. This option is ignored if it 

is applied to anything other than an input or bidirectional pin. 

Integer 




■ Arria V 

■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name D5_OCT_DELAY -to -entity 

 

Old Names 


software: 

T9_OCT_DELAY 




D5_OE_DELAY 

D5_OE_DELAY 

Type 

Specifies the propagation delay for D5 Output-Enable Delay Cell. Use this advanced 

option only after you have compiled a project, checked the I/O timing, and 

determined that the timing is unsatisfactory. For more information about this option, 

refer to the data sheet for the device family. This option is ignored if it is applied to 

anything other than an output or bidirectional pin. 

Integer 



Notes 


Syntax 

set_instance_assignment -name D5_OE_DELAY -to -entity 

 

Old Names 


software: 

T9_OE_DELAY 




D6_DELAY 

D6_DELAY 

Type 





applied to anything other than an output or bidirectional pin. 

Integer 








■ Stratix V 

Notes 


Syntax 


 

Old Names 


software: 

T10_DELAY 




D6_FINE_DELAY 

D6_FINE_DELAY 

Type 


Boolean 



Notes 


Syntax 


 

Old Names 


software: 

T10_FINE_DELAY 




D6_OCT_DELAY 

D6_OCT_DELAY 

Type 

Specifies the propagation delay for D6 OCT Delay Cell. This is an advanced option 

that should be used only after you have compiled a project, checked the I/O timing, 

and determined that the timing is unsatisfactory. For detailed information on how to 

use this option, refer to the data sheet for the device family. This option is ignored if it 

is applied to anything other than an input or bidirectional pin. 

Integer 








■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name D6_OCT_DELAY -to -entity 

 

Old Names 


software: 

T10_OCT_DELAY 




D6_OE_DELAY 

D6_OE_DELAY 

Type 

Specifies the propagation delay for D6 Output-Enable Delay Cell. This is an advanced 

option that should be used only after you have compiled a project, checked the I/O 

timing, and determined that the timing is unsatisfactory. For detailed information on 

how to use this option, refer to the data sheet for the device family. This option is 


Integer 



Notes 


Syntax 

set_instance_assignment -name D6_OE_DELAY -to -entity 

 

Old Names 


software: 

T10_OE_DELAY 




D6_OE_FINE_DELAY 

D6_OE_FINE_DELAY 

Type 

Enable the fine delay resolution on D6 Output-Enable Delay. 

Boolean 



Notes 


Syntax 

set_instance_assignment -name D6_OE_FINE_DELAY -to -entity 

Old Names 


software: 

T10_OE_FINE_DELAY 




DATA0_PIN 

DATA0_PIN 

Type 

Specifies the Data[0] configuration pin. 

Boolean 







Notes 


Syntax 

set_instance_assignment -name DATA0_PIN -to 




DCLK_PIN 

DCLK_PIN 

Type 

Specifies the DCLK configuration pin. 

Boolean 







Notes 


Syntax 

set_instance_assignment -name DCLK_PIN -to 




DC_CURRENT_FOR_ELECTROMIGRATION_CHECK 

DC_CURRENT_FOR_ELECTROMIGRATION_CHECK 

Type 

Specifies the maximum amount of DC current, in mA, allowed when the Fitter checks 

for electromigration violations. 

Integer 



■ Arria GX 

■ Cyclone 








■ MAX V 

■ Stratix 




Syntax 

set_instance_assignment -name DC_CURRENT_FOR_ELECTROMIGRATION_CHECK -to 




DDIO_INPUT_REGISTER 

DDIO_INPUT_REGISTER 

Type 

Directs the Compiler to perform special placement and routing of the specified 

register to prevent register packing of the input registers into the IO registers. This is 

used for registers involved in DDR memory interfaces. A setting of High designates 

the input register that gets set on the rising edge of the clock; a setting of Low 

designates the input register that gets set on the falling edge of the clock. 

Enumeration 

■ High 

■ Low 

■ Off 



■ Cyclone 






Notes 


Syntax 

set_instance_assignment -name DDIO_INPUT_REGISTER -to -entity 




DDIO_OUTPUT_REGISTER 

DDIO_OUTPUT_REGISTER 

Type 


register to provide a glitch-free output. This is used for registers involved in DDR 

memory interfaces. A setting of High designates the output register used when the 

output mux select is 1; a setting of Low designates the output register used when the 

output mux select is 0. 

Enumeration 

■ High 

■ Low 

■ Off 



■ Cyclone 


Notes 


Syntax 

set_instance_assignment -name DDIO_OUTPUT_REGISTER -to -entity 

 




DDIO_OUTPUT_REGISTER_DISTANCE 

DDIO_OUTPUT_REGISTER_DISTANCE 

Type 

Directs the Fitter to place the DDIO output registers (and output mux) that feed this 

I/O pin in a location whose LAB distance is specified by this option. This option is 

ignored if applied to an input pin or if applied to an output or bidir pin that is not fed 

by a DDIO Output configuration. 

Integer 




Notes 


Syntax 

set_instance_assignment -name DDIO_OUTPUT_REGISTER_DISTANCE -to - 

entity 




DECREASE_INPUT_DELAY_TO_INPUT_REGISTER 

DECREASE_INPUT_DELAY_TO_INPUT_REGISTER 

Type 

Decreases the propagation delay from an input pin to the data input of the input 

register implemented in the I/O cell associated with the pin. This is an advanced 




ignored if it is applied to anything other than an input or bidirectional pin. 

Enumeration 

■ Off 

■ On 



■ Cyclone 

■ MAX7000B 

■ Stratix 


Notes 


Syntax 

set_instance_assignment -name DECREASE_INPUT_DELAY_TO_INPUT_REGISTER -to 

-entity 




DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER 

DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER 

Type 

Decreases the propagation delay from the interior of the device to the data input of 

the output register implemented in an I/O cell. This is an advanced option that 




applied to anything other an output or bidirectional pin that is associated with an 

output register implemented in an I/O cell. 

Enumeration 

■ Off 

■ On 



■ Stratix 


Notes 


Syntax 

set_instance_assignment -name DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER -to 

-entity 

Old Names 


software: 

DELAY_SETTING_TO_CORE_TO_OUTPUT_REGISTER 




DEVICE 

DEVICE 

Type 

Specifies the device to use. 

String 



Notes 



Syntax 

set_global_assignment -name DEVICE 

Default Value 

Auto 




DEVICE_MIGRATION_LIST 

DEVICE_MIGRATION_LIST 

Type 

Specifies the list of devices intended for possible future migration. The Compiler 

constrains the resource usage to migratable resources across all devices in the 

migration list. 

String 



Notes 



Syntax 

set_global_assignment -name DEVICE_MIGRATION_LIST 




DEVICE_TECHNOLOGY_MIGRATION_LIST 

DEVICE_TECHNOLOGY_MIGRATION_LIST 

Type 

Specifies the selected technology migration devices for the current device. 

String 



Notes 



Syntax 

set_global_assignment -name DEVICE_TECHNOLOGY_MIGRATION_LIST 




DPRIO_CHANNEL_NUM 

DPRIO_CHANNEL_NUM 

Type 

RX or TX channel number for DPRIO logic. 

Integer 




Syntax 

set_instance_assignment -name DPRIO_CHANNEL_NUM -to -entity 




DPRIO_CRUCLK_NUM 

DPRIO_CRUCLK_NUM 

Type 

Logical RX CRU clock number. 

Integer 




Syntax 

set_instance_assignment -name DPRIO_CRUCLK_NUM -to -entity 




DPRIO_INTERFACE_REG 

DPRIO_INTERFACE_REG 

Type 

Interface I/O register of DPRIO logic. 

Boolean 




Syntax 

set_instance_assignment -name DPRIO_INTERFACE_REG -to -entity 




DPRIO_QUAD_NUM 

DPRIO_QUAD_NUM 

Type 

RX/TX quad number for DPRIO logic. 

Integer 




Syntax 

set_instance_assignment -name DPRIO_QUAD_NUM -to -entity 




DPRIO_QUAD_PLL_NUM 

DPRIO_QUAD_PLL_NUM 

Type 

Logical CMU PLL number in a quad. 

Integer 




Syntax 

set_instance_assignment -name DPRIO_QUAD_PLL_NUM -to -entity 




DPRIO_TX_PLL0_REFCLK_NUM 


Type 

Logical TX PLL0 REFCLK number. 

Integer 




Syntax 

set_instance_assignment -name DPRIO_TX_PLL0_REFCLK_NUM -to -entity 

 






Type 

Logical TX PLL1 REFCLK number. 

Integer 




Syntax 

set_instance_assignment -name DPRIO_TX_PLL1_REFCLK_NUM -to -entity 

 




DPRIO_TX_PLL_NUM 

DPRIO_TX_PLL_NUM 

Type 

Logical TX PLL number. 

Integer 




Syntax 

set_instance_assignment -name DPRIO_TX_PLL_NUM -to -entity 




DQSB_DQS_PAIR 

DQSB_DQS_PAIR 

Type 

Specifies the pairing of a DQSn pin to a DQS pin. The I/O pin of a DQS must be placed 

in the DQS pin location of a DQS group; the I/O pin of a DQSn must be placed in the DQSn 

pin location of the same DQS group. This option is ignored if is assigned to anything 

other than an I/O pad, input buffer, or output buffer. 

Boolean 













Notes 


Syntax 

set_instance_assignment -name DQSB_DQS_PAIR -from -to -entity 

 

Example 

set_instance_assignment -name DQSB_DQS_PAIR ON -from mem_dqs_n[0] -to 

mem_dqs[0] 

See Also 

■ “DQ_GROUP” on page 6–90 

■ “MEMORY_INTERFACE_DATA_PIN_GROUP” on page 6–205 




DQSOUT_DELAY_CHAIN 

DQSOUT_DELAY_CHAIN 

Type 

Set the propagation delay on the DQSBUS signal from the DQS pin. This is an advanced 




ignored if it is applied to anything other than a DQ pin. 

Integer 



■ Arria GX 





Notes 


Syntax 

set_instance_assignment -name DQSOUT_DELAY_CHAIN -to -entity 




DQS_ENABLE_DELAY_CHAIN 

DQS_ENABLE_DELAY_CHAIN 

Type 

Set the propagation delay on the DQS enable signal for the DQS pin. This is an advanced 




ignored if it is applied to anything other than a DQS pin. 

Integer 




Notes 


Syntax 

set_instance_assignment -name DQS_ENABLE_DELAY_CHAIN -to -entity 

 




DQS_LOCAL_CLOCK_DELAY_CHAIN 

DQS_LOCAL_CLOCK_DELAY_CHAIN 

Type 

Set the propagation delay on the DQS signal to the input register of the target pin. This 

is an advanced option that should be used only after you have compiled a project, 

checked the I/O timing, and determined that the timing is unsatisfactory. For detailed 

information on how to use this option, refer to the data sheet for the device family. 

This option is ignored if it is applied to anything other than a DQ or DQS pin. 

Integer 



■ Arria GX 





Notes 


Syntax 

set_instance_assignment -name DQS_LOCAL_CLOCK_DELAY_CHAIN -to -entity 

 




DQ_GROUP 

DQ_GROUP 

Type 

Specifies the grouping from a DQS pin to its associated DQ pins and the width (4, 9, 18, 

or 36) of the group. Setting this option allows the Fitter to view the pins as a DQS/DQ 

pin group. I/O pins of a DQ pin group must be placed in the DQ pin locations of a single 

DQS group. This option is ignored if is assigned to anything other than an I/O pad, 

input buffer, or output buffer. 

Integer 





■ Arria V 





■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name DQ_GROUP -from -to -entity 

 

Example 

set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[0..7] 

See Also 

■ “DQSB_DQS_PAIR” on page 6–86 

■ “MEMORY_INTERFACE_DATA_PIN_GROUP” on page 6–205 




DQ_PIN 

DQ_PIN 

Type 

Designates the specified pin as an DQ I/O pin. 

Boolean 




Notes 


Syntax 

set_instance_assignment -name DQ_PIN -to -entity 




DUAL_PURPOSE_CLOCK_PIN_DELAY 

DUAL_PURPOSE_CLOCK_PIN_DELAY 

Type 

Specifies the propagation delay from a dual-purpose clock pin to its fan-out 

destinations that are routed on the global clock network. Legal integer values range 

from 0 through 63 for Cyclone and Cyclone II device families and from 0 through 11 

for Cyclone III, where 0 is the setting with the least delay and 63 is the setting with the 

most delay. This is an advanced option that should be used only after you have 

compiled a project, checked the I/O timing, and determined that the timing is 

unsatisfactory. For detailed information on how to use this option, refer to the data 

sheet for the device family. This option is ignored if it is applied to anything other 

than an input or bidirectional pin, or if the pin is user assigned to a non-dual-purpose 

clock pin location. 

Integer 



■ Cyclone 






Notes 


Syntax 

set_instance_assignment -name DUAL_PURPOSE_CLOCK_PIN_DELAY -to - 

entity 




DUPLICATE_ATOM 


Type 

Directs the Compiler to duplicate the source node, and uses the new duplicate node to 

fan out to the destination node; the original source node no longer fans out to the 

destination node. Use the Value field to specify the name of the duplicate node. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Notes 








Syntax 

set_instance_assignment -name DUPLICATE_ATOM -from -to -entity 

 




DYNAMIC_OCT_CONTROL_GROUP 

DYNAMIC_OCT_CONTROL_GROUP 

Type 

Assigns a dynamic termination control group number for the specified node. Turning 

on this option directs the Fitter to view the specified nodes as a dynamic termination 

control group so as to place them next to each other to share the termination control 

routing resource. This is only applicable for bidirectional pins. 

This option is deprecated and should no longer be used. 

String 






Notes 


Syntax 

set_instance_assignment -name DYNAMIC_OCT_CONTROL_GROUP -to -entity 

 




ECO_ALLOW_ROUTING_CHANGES 

ECO_ALLOW_ROUTING_CHANGES 

Type 

This option controls whether the Fitter moves items in a design to ensure that new 

ECO signals get routed. 

Boolean 



■ Cyclone 

■ Stratix 


Syntax 

set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES 

Default Value 

Off 




ECO_OPTIMIZE_TIMING 

ECO_OPTIMIZE_TIMING 

Type 

Controls whether the fitter optimizes to meet the user's maximum delay timing 

requirements (for example, clock cycle time, T SU, T CO) during ECO compiles. By 

default, this option is set to off. Turning it on can improve timing performance at the 

cost of compilation time. 

Enumeration 

■ Off 

■ On 



Notes 


Syntax 

set_global_assignment -name ECO_OPTIMIZE_TIMING 

Default Value 

Off 




ECO_REGENERATE_REPORT 

ECO_REGENERATE_REPORT 

Type 

Controls whether the fitter report is regenerated during ECO compiles. By default, 

this option is set to off. 

Enumeration 

■ Off 

■ On 



Notes 


Syntax 

set_global_assignment -name ECO_REGENERATE_REPORT 

Default Value 

Off 




ENABLE_ASMI_FOR_FLASH_LOADER 

ENABLE_ASMI_FOR_FLASH_LOADER 

Type 

Enables Active Serial Memory Interface (ASMI) for Flash Loader IP blocks. 

Boolean 




Syntax 

set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER 

Default Value 

Off 




ENABLE_BENEFICIAL_SKEW_OPTIMIZATION 

ENABLE_BENEFICIAL_SKEW_OPTIMIZATION 

Type 

Allows the Fitter to insert skew on globally routed clock signals to improve the 

performance of the design. 

Boolean 





■ Arria V 





■ Cyclone V 



■ Stratix V 

Notes 



Syntax 

set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION 

set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -to 

-entity 

Default Value 

On 




ENABLE_BUS_HOLD_CIRCUITRY 


Type 

Enables bus-hold circuitry during device operation. If you turn this option on, a pin 

retains its last logic level when it is not driven, and does not go to a high impedance 

logic level. The Enable Bus-Hold Circuitry option should not be simultaneously with 

the Weak Pull-Up Resistor option. This option is ignored if it is applied to anything 

other than a pin. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Notes 



Syntax 

set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY 

set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY -entity 

set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY -to -entity 

 

Example 

set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to pin 

Default Value 

Off 




ENABLE_CRC_ERROR_PIN 

ENABLE_CRC_ERROR_PIN 

Type 

Specifies error detection CRC and CRC_ERROR pin usage for the selected device. If 

error detection CRC is turned on, the device checks the validity of the programming 

data in the device. Any changes in the data while the device is in operation generates 

an error. 

Enabling this option would put the dual-purpose CRCERROR pin into configuration 

mode. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name ENABLE_CRC_ERROR_PIN 

Example 

set_global_assignment -name ENABLE_CRC_ERROR_PIN ON 

Default Value 

Off 

See Also 






ENABLE_CVP_CONFDONE 

ENABLE_CVP_CONFDONE 

Type 

Enable the CvP_CONFDONE pin, which indicates that the device finished core 

programming in Configuration via Protocol mode. If this option is turned off, the 

CvP_CONFDONE pin is disabled when the device operates in user mode and is available 

as a user I/O pin. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name ENABLE_CVP_CONFDONE 

Example 

set_global_assignment -name ENABLE_CVP_CONFDONE ON 

Default Value 

Off 

Old Names 


software: 

ENABLE_CVPCIE_CONFDONE 

See Also 

■ “CVP_CONFDONE_OPEN_DRAIN” on page 6–45 




ENABLE_DEVICE_WIDE_OE 


Type 

Enables the DEV_OE pin when the device is in user mode. If this option is turned on, all 

outputs on the chip operate normally. When the pin is disabled, all outputs are tristated. 

If this option is turned off, the DEV_OE pin is disabled when the device operates 

in user mode and is available as a user I/O pin. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Syntax 

set_global_assignment -name ENABLE_DEVICE_WIDE_OE 





Example 

set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON 

Default Value 

Off 

Old Names 


software: 

ENABLE_CHIP_WIDE_OE 




ENABLE_DEVICE_WIDE_RESET 


Type 

Enables the DEV_CLRn pin, which allows all registers of the device to be reset by an 

external source. If this option is turned off, the DEV_CLRn pin is disabled when the 

device operates in user mode and is available as a user I/O pin. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Syntax 

set_global_assignment -name ENABLE_DEVICE_WIDE_RESET 





Example 

set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON 

Default Value 

Off 

Old Names 


software: 

ENABLE_CHIP_WIDE_RESET 




ENABLE_HOLD_BACK_OFF 

ENABLE_HOLD_BACK_OFF 

Type 

Enables the Fitter to successfully fit a design despite infeasible hold constraints. 

Enumeration 

■ Off 

■ On 




Syntax 

set_global_assignment -name ENABLE_HOLD_BACK_OFF 

Default Value 

On 




ENABLE_INIT_DONE_OUTPUT 


Type 

Enables the INIT_DONE pin, which allows you to externally monitor when 

initialization is completed and the device is in user mode. If this option is turned off, 

the INIT_DONE pin is disabled when the device operates in user mode and is available 


Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 




■ Stratix 






■ Stratix V 

Syntax 

set_global_assignment -name ENABLE_INIT_DONE_OUTPUT 





Example 

set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF 

Default Value 

Off 

Old Names 


software: 

Enable INIT_DONE Output 

See Also 

■ “INIT_DONE_OPEN_DRAIN” on page 6–177 




ENABLE_NCEO_OUTPUT 

ENABLE_NCEO_OUTPUT 

Type 

Enables the nCEO pin. This pin should be connected to the nCE of the succeeding device 

when multiple devices are being programmed. If this option is turned off, the nCEO 

pin is disabled when the device operates in user mode and is available as a user I/O 

pin. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name ENABLE_NCEO_OUTPUT 

Example 

set_global_assignment -name ENABLE_NCEO_OUTPUT OFF 

Default Value 

Off 




ENABLE_PR_PINS 

ENABLE_PR_PINS 

Type 

Enable the PR_REQUEST, PR_READY, PR_ERROR and PR_DONE pins. These pins are needed 

for supporting partial reconfiguration with external host or external scrubbing. An 

external host uses the PR_REQUEST pin to request partial reconfiguration or external 

scrubbing, the PR_READY pin to determine if the device is ready to receive 

programming data, the PR_ERROR pin to externally monitor programming error, and 

the PR_DONE pin to indicate that the device has finished programming. If this option is 

turned off, these functionalities are disabled when the device operates in user mode 

and these pins are available as user I/O pins. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name ENABLE_PR_PINS 

Example 

set_global_assignment -name ENABLE_PR_PINS ON 

Default Value 

Off 

See Also 

■ “PR_READY_OPEN_DRAIN” on page 6–281 

■ “PR_ERROR_OPEN_DRAIN” on page 6–280 

■ “PR_DONE_OPEN_DRAIN” on page 6–279 




ENABLE_VREFA_PIN 

ENABLE_VREFA_PIN 

Type 

Enable the circuitry for input voltage reference pins A. 

Boolean 



■ MAX7000B 

Syntax 

set_global_assignment -name ENABLE_VREFA_PIN 

Default Value 

Off 

Old Names 


software: 

Enable VREFA pin 




ENABLE_VREFB_PIN 

ENABLE_VREFB_PIN 

Type 

Enables the circuitry for input voltage reference pins B. 

Boolean 



■ MAX7000B 

Syntax 

set_global_assignment -name ENABLE_VREFB_PIN 

Default Value 

Off 

Old Names 


software: 

Enable VREFB pin 




ERROR_CHECK_FREQUENCY_DIVISOR 


Type 

Specifies the divide value of the internal clock, which determines the frequency of the 

CRC. The divide value must be a power of two. Refer to the device handbook to find 

the frequency of the internal clock for the selected device. 

Integer 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 




■ Stratix 






■ Stratix V 

Syntax 

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 

Example 

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 16 





See Also 

■ “CRC_ERROR_CHECKING” on page 6–40 




EXCLUSIVE_IO_GROUP 

EXCLUSIVE_IO_GROUP 

Type 

Assigns an exclusive group number for the specified I/O. I/Os with the different 

exclusive group number cannot share the same bank. 

Integer 



■ Arria GX 



■ Arria V 






■ Cyclone V 








■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name EXCLUSIVE_IO_GROUP -to -entity 

Example 

set_instance_assignment -name "EXCLUSIVE_IO_GROUP" -to pin 




EXTERNAL_LVDS_RX_USES_DPA 

EXTERNAL_LVDS_RX_USES_DPA 

Type 

Indicates that this LVDS Transmitter pin is connected to an external LVDS Receiver 

that uses DPA. 

Boolean 




Notes 



Syntax 

set_instance_assignment -name EXTERNAL_LVDS_RX_USES_DPA -to -entity 

 




FINAL_PLACEMENT_OPTIMIZATION 


Type 

Specifies whether the Fitter performs final placement optimizations. Performing final 

placement optimizations may improve timing and routability, but may also require 

longer compilation time. The default setting of Automatically can be used with the 

Auto Fit Fitter Effort Level (also the default) to let the Fitter decide whether these 

optimizations should run based on the routability and timing requirements of the 

design. 

Enumeration 

■ Always 

■ Automatically 

■ Never 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION 

Default Value 

Automatically 




FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 

FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 

Type 

Allows timing analysis to add extra short path guardband on a specific node during 

fitting. 

Integer 





Syntax 

set_global_assignment -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 

set_global_assignment -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND -entity 

 

set_instance_assignment -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND -to 

-entity 




FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION 


Type 

Specifies whether the Fitter aggressively optimizes for routability. Performing 

aggressive routability optimizations may decrease design speed, but may also reduce 

routing wire usage and routing time. The default setting of Automatically lets the 

Fitter decide whether to perform these optimizations based on the routability and 

timing requirements of the design. 

Enumeration 

■ Always 

■ Automatically 

■ Never 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION 

 

Default Value 

Automatically 




FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 


Type 

Specifies the amount of worst-case slack margin the Fitter should try to maintain 

when the FITTER_EFFORT option is set to Auto Fit. If the design is likely to have at 

least this much slack on every path, the Fitter reduces optimization effort to reduce 

compilation time. Otherwise, its behavior is the same as it is with the Standard Fit 

setting for the FITTER_EFFORT option. 

Time 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 





Syntax 

set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 

 

Default Value 

0ns 




FITTER_EARLY_TIMING_ESTIMATE_MODE 


Type 

Controls the type of early timing estimate produced by the Early Timing Estimate 

feature. The Realistic setting estimates the average results expected from a Standard 

Fit compile, the Optimistic setting estimates the best case final timing, and the 

Pessimistic setting estimates the worst case final timing. 

Enumeration 

■ Optimistic 

■ Pessimistic 

■ Realistic 



■ Arria GX 



■ Cyclone 










■ MAX V 

■ Stratix 






Syntax 

set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE 





Default Value 

Realistic 




FITTER_EFFORT 

FITTER_EFFORT 

Type 

Controls the trade-off between performance and compilation speed of the Fitter. The 

Auto Fit setting adjusts the Fitter optimization effort to minimize compilation time 

while still achieving the design timing requirements. The 

FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN option can be used to 

request that Auto Fit apply sufficient optimization effort to achieve additional timing 

margin. The Standard Fit setting uses maximum effort regardless of the requirements 

of the design, leading to higher compilation time and more margin on easier designs. 

For difficult designs, the Auto Fit and Standard Fit settings both use maximum effort. 

The Fast Fit setting decreases optimization effort to reduce compilation time, which 

may degrade design performance. 

Enumeration 

■ Auto Fit 

■ Fast Fit 

■ Standard Fit 



Notes 


Syntax 

set_global_assignment -name FITTER_EFFORT 

Default Value 

Auto Fit 




FIT_ATTEMPTS_TO_SKIP 


Type 

Controls how many fit attempts the Fitter skips. In subsequent fit attempts, the Fitter 

uses higher effort to improve design routability at the expense of longer compilation 

times. Use this setting to force the Fitter directly into a second or third fit attempt, 

which will save time when it is known that multiple attempts are needed. This setting 

causes the same amount of additional effort to be applied but does not guarantee an 

identical result to what would be achieved if all fit attempts were performed. For 

some families, the Fitter will not perform a third fit attempt automatically due to the 

long compilation time and possible timing quality degradation. However, a third fit 

attempt can still be forced to run by setting this value to 2. 

Integer 


The value must be between these two numbers, inclusive: 0, 2 


■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 

Default Value 

0.0 




FIT_ONLY_ONE_ATTEMPT 

FIT_ONLY_ONE_ATTEMPT 

Type 

Controls how many fitting attempts the Fitter tries to get a fit. When this option is off 

(default), the Fitter tries a maximum of three placement and routing attempts, with 

each successive attempt increasing the placement effort and hence increasing 

compilation times. These additional attempts are used only if previous attempts failed 

to fit the design. Setting this option restricts the Fitter to using only the first of these 

three attempts. 

Boolean 



Notes 


Syntax 

set_global_assignment -name FIT_ONLY_ONE_ATTEMPT 

Default Value 

Off 




FLEX10K_MAX_PERIPHERAL_OE 

FLEX10K_MAX_PERIPHERAL_OE 

Type 

Sets the limit on the number of peripheral OE buses that can be used. 

Integer 



Syntax 

set_global_assignment -name FLEX10K_MAX_PERIPHERAL_OE 




FORCE_CONFIGURATION_VCCIO 


Type 

Forces the V CCIO voltage of the configuration pins to be the same as the configuration 

device I/O voltage. 

In some device families, the V CCIO of some banks power both general purpose I/Os 

and configuration pins. 

Turning on this option forces the Fitter to produce an I/O placement in such a way 

that the V CCIO would be consistent with the selected configuration voltage. 

Fitter produces placement errors if such I/O placement cannot be found. 

Boolean 



■ Arria GX 



■ Arria V 





■ Cyclone V 








■ Stratix V 

Syntax 

set_global_assignment -name FORCE_CONFIGURATION_VCCIO 

Example 

set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON 





Default Value 

Off 

See Also 

■ “CONFIGURATION_VCCIO_LEVEL” on page 6–38 




FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS 

FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS 

Type 

Directs the Fitter to treat periphery placement warnings as errors. As a result, the 

Fitter attempts to find a placement for the design that corrects these warnings. If the 

Fitter cannot fit the design, an error message is displayed instead of the original 

warning message. 

Boolean 



Notes 


Syntax 


FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS 

Default Value 

Off 




FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION 

FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION 

Type 

Directs the Fitter to implement the specified node using the fractured mode of the 

ALM. This assignment only applies to nodes with a specific location assignment. 

Boolean 



■ Arria GX 







Notes 


Syntax 

set_instance_assignment -name FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION -to 

-entity 




FORCE_MERGE_PLL 

FORCE_MERGE_PLL 

Type 

Forces the slave PLL to be merged with the master PLL. This option should be used 

only for two compatible PLLs driven by the same clock source. 

Boolean 













Notes 



Syntax 

set_instance_assignment -name FORCE_MERGE_PLL -from -to - 

entity 




FORCE_MERGE_PLL_FANOUTS 

FORCE_MERGE_PLL_FANOUTS 

Type 

Forces the fanouts of the slave PLL clock output to be merged into the master PLL 

clock output. This option should be used only for static PLL clock outputs. 

Boolean 



■ Arria GX 














Notes 



Syntax 

set_instance_assignment -name FORCE_MERGE_PLL_FANOUTS -from -to 

-entity 




FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION 

FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION 

Type 

Directs the Fitter to implement the specified node using the non-fractured mode of the 

ALM. This assignment only applies to nodes with a specific location assignment. 

Boolean 



■ Arria GX 







Notes 


Syntax 

set_instance_assignment -name FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION 

-to -entity 




GENERATE_GXB_RECONFIG_MIF 

GENERATE_GXB_RECONFIG_MIF 

Type 

Generates a gigabit transceiver block reconfiguration Memory Initialization File (.mif) 

for each used gigabit transceiver block Transmitter and Receiver channel pair (Stratix 

II GX and Arria GX) or each ALTGX megafunction instance (Stratix IV, Arria II GX 

and Cyclone IV GX). Reprogramming using this Memory Initialization File (.mif) 

reconfigures the gigabit transceiver block channel. 

Boolean 



■ Arria GX 







Notes 


Syntax 

set_global_assignment -name GENERATE_GXB_RECONFIG_MIF 

Default Value 

Off 




GENERATE_GXB_RECONFIG_MIF_WITH_PLL 

GENERATE_GXB_RECONFIG_MIF_WITH_PLL 

Type 

Generates a gigabit transceiver block reconfiguration Memory Initialization File (.mif) 

with PLL data for each used gigabit transceiver block Transmitter and Receiver 

channel pair. Reprogramming using this Memory Initialization File (.mif) 

reconfigures the entire gigabit transceiver block channel. 

Boolean 




Notes 


Syntax 

set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL 

Default Value 

Off 




GLOBAL_SIGNAL 

GLOBAL_SIGNAL 

Type 

Specifies whether the signal should be routed using global routing paths. Global 

signals can be both pin- and logic-driven, and can be any signal in the design. Turning 

this option on for a pin or a single-output logic function signal is equivalent to feeding 

the signal through a GLOBAL buffer. Turning this option off for a particular signal 

will prevent any of the Auto Global options from using the signal as an automatic 

global signal. 

Enumeration 

■ Dual-Fast Regional Clock 

■ Dual-Regional Clock 

■ Fast Regional Clock 

■ Global Clock 

■ Off 

■ On 


■ Periphery Clock 

■ Regional Clock 


■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 

■ EPC1 

■ EPC2 


■ FLEX10KB 

■ FLEX8000 




GLOBAL_SIGNAL 





■ MAX V 

■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

■ MAX9000 

■ Stratix 






■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name GLOBAL_SIGNAL -to -entity 

 

set_instance_assignment -name GLOBAL_SIGNAL -from -to -entity 

 




GLOBAL_SIGNAL_CLKCTRL_LOCATION 

GLOBAL_SIGNAL_CLKCTRL_LOCATION 

Type 

Specifies the CLKCTRL that the signal should be routed using global routing paths. The 

value to use is the same as that used for location assignments of Clock Control/Clock 

Enable Blocks. 

String 



■ Arria GX 















Notes 


devices. 


Syntax 

set_instance_assignment -name GLOBAL_SIGNAL_CLKCTRL_LOCATION -to - 

entity 

set_instance_assignment -name GLOBAL_SIGNAL_CLKCTRL_LOCATION -from 

-to -entity 




GNDIO_CURRENT_1PT8V 


Type 

For user to override GNDIO current of 1.8-V I/O standard. The original current is 

2mA. 

Integer 



Syntax 

set_global_assignment -name GNDIO_CURRENT_1PT8V 






Type 

For user to override GNDIO current of 2.5-V I/O standard. The original current is 

2mA. 

Integer 



Syntax 

set_global_assignment -name GNDIO_CURRENT_2PT5V 




GNDIO_CURRENT_GTL 

GNDIO_CURRENT_GTL 

Type 

Overrides the GNDIO current of a GTL I/O standard. Not supported in MAX7000. 

Integer 



Syntax 

set_global_assignment -name GNDIO_CURRENT_GTL 




GNDIO_CURRENT_GTL_PLUS 

GNDIO_CURRENT_GTL_PLUS 

Type 

Overrides the GNDIO current of a GTL+ I/O standard. The original current is 50 mA. 

Integer 



Syntax 

set_global_assignment -name GNDIO_CURRENT_GTL_PLUS 




GNDIO_CURRENT_LVCMOS 

GNDIO_CURRENT_LVCMOS 

Type 

Overrides the GNDIO current of an LVCMOS I/O standard. The original current is 2 

mA. 

Integer 



Syntax 

set_global_assignment -name GNDIO_CURRENT_LVCMOS 




GNDIO_CURRENT_LVTTL 

GNDIO_CURRENT_LVTTL 

Type 

Overrides the GNDIO current of an LVTTL I/O standard. The original current is 4 

mA. 

Integer 



Syntax 

set_global_assignment -name GNDIO_CURRENT_LVTTL 




GNDIO_CURRENT_PCI 

GNDIO_CURRENT_PCI 

Type 

Overrides the GNDIO current of a PCI I/O standard. The original current is 4 mA. 

Integer 



Syntax 

set_global_assignment -name GNDIO_CURRENT_PCI 




GNDIO_CURRENT_SSTL2_CLASS1 


Type 

Overrides the GNDIO current of a SSTL2_CLASS1 I/O standard. The original current 

is 14 mA. 

Integer 



Syntax 

set_global_assignment -name GNDIO_CURRENT_SSTL2_CLASS1 






Type 


is 21 mA. 

Integer 



Syntax 







Type 


is 18 mA. 

Integer 



Syntax 







Type 


is 25 mA. 

Integer 



Syntax 





GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME 

GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME 

Type 

Controls whether the Fitter tries to achieve a zero hold time for I/O pins that feed 

globally clocked registers at the fast corner and in stringent operating conditions even 

if a design does not contain timing assignments. When this option is set to On, the 

Fitter preserves zero hold time for I/O pins feeding globally clocked registers at the 

fast corner and in stringent operating conditions. This setting may cause violations of 

t SU or t PD timing constraints. When this option is set to Off, the Fitter optimizes a 

design to meet user timing assignments only. When this option is set to When Tsu and 

Tpd Constraints Permit, the Fitter preserves zero hold time for I/O pins feeding 

globally clocked registers at the fast corner and in stringent operating conditions only 

if this can be done without violating tSU or tPD timing constraints. You can use this 

option to automatically meet I/O hold time requirements in the fast corner without 

specifying any extra timing constraints. 

Enumeration 

■ Off 

■ On 


■ When Tsu and Tpd Constraints Permit 



■ MAX V 

Notes 


Syntax 

set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME 

 

Default Value 

On 




GXB_0PPM_CLOCK_GROUP 

GXB_0PPM_CLOCK_GROUP 

Type 

Specifies a group of gigabit transceiver block core clocks that have zero parts per 

million (ppm) difference. The clock driver source specified in the gigabit transceiver 

block 0 ppm clock group driver must have a difference of 0 ppm compared with all 

clocks specified in the gigabit transceiver block 0 ppm clock group. You must connect 

the specified clock driver to all specified destinations in the gigabit transceiver block 0 

ppm clock group. Do not reconfigure the gigabit transceiver block 0 PPM clock group 

driver differently from other clocks in the gigabit transceiver block 0 ppm clock 

group, and do not disable the gigabit transceiver block 0 ppm clock group driver 

source when the destination gigabit transceiver block receiver or transmitter is 

listening to the signal. Follow the Altera High Speed I/O Applications Technical 

Support recommendations when using this assignment. 

Integer 



■ Arria GX 


Notes 


Syntax 

set_instance_assignment -name GXB_0PPM_CLOCK_GROUP -to -entity 

 




GXB_0PPM_CLOCK_GROUP_DRIVER 

GXB_0PPM_CLOCK_GROUP_DRIVER 

Type 

Specifies core clocks that have zero PPM difference. Follow the Altera High Speed I/O 

Applications Technical Support recommendations when using this assignment. 

Integer 



■ Arria GX 


Notes 


Syntax 

set_instance_assignment -name GXB_0PPM_CLOCK_GROUP_DRIVER -to -entity 

 




GXB_0PPM_CORECLK 

GXB_0PPM_CORECLK 

Type 

Specifies core clocks that have zero PPM difference. Follow the Altera High Speed I/O 

Applications Technical Support recommendations when using this assignment. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name GXB_0PPM_CORECLK -to -entity 




GXB_0PPM_CORE_CLOCK 

GXB_0PPM_CORE_CLOCK 

Type 

Specifies two GXB core clocks that have zero (0) PPM difference. The core clock driver 

for the assignment source GXB must have a difference of 0 PPM compared with the 

core clock of the assignment destination GXB. Do not reconfigure the GXB 0 PPM 

clock group driver differently from other clocks it is 0 PPM-linked to and do not bring 

down the GXB 0 PPM clock source when the destination GXB receiver or transmitter 

is listening to the signal. Follow the Altera High Speed I/O Applications Technical 

Support recommendations when using this assignment. 

Boolean 








Notes 


Syntax 

set_instance_assignment -name GXB_0PPM_CORE_CLOCK -from -to - 

entity 




GXB_CLOCK_GROUP 

GXB_CLOCK_GROUP 

Type 

Specifies gigabit transceiver block core clock groups to be merged after compilation. 

All specified gigabit transceiver block transmitters in the gigabit transceiver block 

shared clock group are driven by the clock source specified in the gigabit transceiver 

block shared clock group driver. All clocks in the gigabit transceiver block shared 

clock group and gigabit transceiver block clock group driver must be configured in 

the same manner. When the destination GXB transmitter is listening to a signal such 

as gxb_powerdown, do not disable the gigabit transceiver block shared clock group 

driver source. Follow the Altera High Speed I/O Applications Technical Support 

recommendations when using this assignment. 

Integer 



■ Arria GX 


Notes 


Syntax 

set_instance_assignment -name GXB_CLOCK_GROUP -to -entity 




GXB_CLOCK_GROUP_DRIVER 

GXB_CLOCK_GROUP_DRIVER 

Type 

Specifies the gigabit transceiver block core clock driver that drives all core clocks in a 

gigabit transceiver block shared clock group after compilation. All gigabit transceiver 

block transmitters specified in the gigabit transceiver block shared clock group are 

driven by the clock source specified in the gigabit transceiver block shared clock 

group driver. Do not reconfigure the gigabit transceiver block shared clock group 

driver differently from other clocks in the gigabit transceiver block shared clock 

group, and do not bring down the gigabit transceiver block shared clock group driver 

source when the destination gigabit transceiver block transmitter is listening to the 

signal. Follow the Altera High Speed I/O Applications Technical Support 

recommendations when using this assignment. 

Integer 



■ Arria GX 


Notes 


Syntax 

set_instance_assignment -name GXB_CLOCK_GROUP_DRIVER -to -entity 

 




GXB_RECONFIG_GROUP 

GXB_RECONFIG_GROUP 

Type 

Specifies whether gigabit transceiver block transceiver channels with Dynamic 

Reconfiguration can be placed in the same physical channel. Gigabit transceiver block 

receivers and transmitters are not placed into the same physical channel when 

Dynamic Reconfiguration setting is turned On unless they are in the same 

reconfiguration group. Gigabit transceiver block receivers and transmitters can be 

assigned to the same group if the following conditions are met: the gigabit transceiver 

block receivers and transmitters are dynamically reconfigured at the same time, and 

the gigabit transceiver block receivers and transmitters are kept in reset until the 

dynamic reconfiguration of both is complete. 

Integer 



■ Arria GX 


Notes 


Syntax 

set_instance_assignment -name GXB_RECONFIG_GROUP -to -entity 




GXB_RECONFIG_MIF_PLL 

GXB_RECONFIG_MIF_PLL 

Type 

Includes PLL information in the gigabit transceiver block reconfiguration channel 

data. 

Boolean 




Notes 


Syntax 

set_instance_assignment -name GXB_RECONFIG_MIF_PLL -to -entity 

 




GXB_REFCLK_COUPLING_TERMINATION_SETTING 

GXB_REFCLK_COUPLING_TERMINATION_SETTING 

Type 

Allows the Compiler to configure the AC/DC coupling and on-chip termination 

(OCT) for a Stratix II GX gigabit transceiver block REFCLK input pin. Use DC coupling 

external termination value only with the HCSL I/O standard on the PCI-Express 

protocol. This option is ignored if it is applied to anything other than an input pin. 

Enumeration 


■ DC coupling external termination 

■ OCT 100 Ohms 



■ Arria GX 


Notes 


Syntax 

set_instance_assignment -name GXB_REFCLK_COUPLING_TERMINATION_SETTING -to 

-entity 




HPS_IO 

HPS_IO 

Type 

Flags an I/O in the user netlist as one that is intended to be owned by a HPS block. 

Boolean 



■ Arria V 

■ Cyclone V 

Notes 


Syntax 

set_instance_assignment -name HPS_IO -to -entity 

Example 

set_instance_assignment -name HPS_IO ON -to output_pin 




IGNORE_MODE_FOR_MERGE 

IGNORE_MODE_FOR_MERGE 

Type 

Ignores the mode of the PLL when the Fitter attempts to merge PLLs, therefore 

allowing PLLs with different modes to be merged. 

Boolean 




Notes 



Syntax 

set_global_assignment -name IGNORE_MODE_FOR_MERGE 

set_global_assignment -name IGNORE_MODE_FOR_MERGE -entity 

 

set_instance_assignment -name IGNORE_MODE_FOR_MERGE -to -entity 

 

Default Value 

Off 




IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE 

IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE 

Type 

Allows you to specify the MLAB memory blocks implementation mode. MLAB 

memory blocks are implemented in 32-bit deep mode or 64-bit deep mode. Turning 

on this option forces MLAB memory blocks to be implemented in 16-bit deep mode. 

This leads to significantly shorter delays and may speed up the overall design 

performance if the MLAB memory block is on the critical path. However, it also 

requires twice as many MLAB blocks to implement a given logical memory. 

Boolean 



■ Stratix V 

Notes 



Syntax 

set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE -entity 

 

set_instance_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE -to 

-entity 

set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE 

Default Value 

Off 




INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN 

INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN 

Type 

Increases the propagation delay to the output enable pin from internal logic or the 

output enable register implemented in an I/O cell. This is an advanced option that 




applied to anything other than an output enable pin. 

Enumeration 

■ Off 

■ On 



■ Stratix 


Notes 


Syntax 

set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN -to 

-entity 




INCREASE_DELAY_TO_OUTPUT_PIN 

INCREASE_DELAY_TO_OUTPUT_PIN 

Type 

Increases the propagation delay to the output or bidirectional pin from the output 

register implemented in an I/O cell. This is an advanced option that should be used 



to the data sheet for the device family. This option is off by default. This option is 


Enumeration 

■ Off 

■ On 



■ Cyclone 

■ Stratix 


Notes 


Syntax 

set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_PIN -to - 

entity 




INCREASE_INPUT_CLOCK_ENABLE_DELAY 

INCREASE_INPUT_CLOCK_ENABLE_DELAY 

Type 

Increases the propagation delay from the interior of the device to the clock enable 

input of an output register. This is an advanced option that should be used only after 

you compile a project, check the I/O timing, and determine that the timing is 

unsatisfactory. This option is ignored if it is applied to anything other than an I/O cell 

that has an input register with a clock enable signal. For detailed information on how 

to use this option, refer to the respective device family data sheet. 

Enumeration 

■ Large 

■ Off 

■ On 

■ Small 



■ Stratix 


Notes 


Syntax 

set_instance_assignment -name INCREASE_INPUT_CLOCK_ENABLE_DELAY -to - 

entity 




INCREASE_OUTPUT_CLOCK_ENABLE_DELAY 

INCREASE_OUTPUT_CLOCK_ENABLE_DELAY 

Type 


input of an output register. This is an advanced option that should be used only after 

you compile a project, check the I/O timing, and determine that the timing is 

unsatisfactory. This option is ignored if it is applied to anything other than an I/O cell 

that has an output register with a clock enable signal. For detailed information on 

how to use this option, refer to the respective device family data sheet. 

Enumeration 

■ Large 

■ Off 

■ On 

■ Small 



■ Stratix 


Notes 


Syntax 

set_instance_assignment -name INCREASE_OUTPUT_CLOCK_ENABLE_DELAY -to 

-entity 




INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY 

INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY 

Type 


input of an output enable register. This is an advanced option that should be used 

only after you compile a project, check the I/O timing, and determine that the timing 

is unsatisfactory. This option is ignored if it is applied to anything other than an I/O 

cell that has an output enable register with a clock enable signal. For detailed 

information on how to use this option, refer to the respective device family data sheet. 

Enumeration 

■ Large 

■ Off 

■ On 

■ Small 



■ Stratix 


Notes 


Syntax 

set_instance_assignment -name INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY - 

to -entity 

Old Names 


software: 

INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAYR 




INCREASE_TZX_DELAY_TO_OUTPUT_PIN 

INCREASE_TZX_DELAY_TO_OUTPUT_PIN 

Type 

Supports zero bus-turnaround (ZBT) by increasing the propagation delay of the 

falling edge of the output enable signal. This option allows a device to quickly release 

control and slowly take control of a bus. Turning the Increase tzx Delay to Output 

Pin option on prevents bus contention between ZBT SRAM devices. This option is 


Enumeration 

■ Off 

■ On 



■ Stratix 


Notes 


Syntax 

set_instance_assignment -name INCREASE_TZX_DELAY_TO_OUTPUT_PIN -to - 

entity 

Old Names 


software: 

ZBT_OE_FALLING_EDGE_DELAY 




INC_PLC_MODE 

INC_PLC_MODE 

Type 

Directs the Quartus II software to run in Incremental Placement Mode. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name INC_PLC_MODE 




INIT_DONE_OPEN_DRAIN 

INIT_DONE_OPEN_DRAIN 

Type 

Specifies whether the Open-Drain feature on the INIT_DONE pin should be enabled or 

not. 

Using this feature decouples the voltage level of the INIT_DONE pin from V CCIO. 


Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name INIT_DONE_OPEN_DRAIN 

Example 

set_global_assignment -name init_done_open_drain on 

set_global_assignment -name init_done_open_drain off 

Default Value 

On 

See Also 

■ “ENABLE_INIT_DONE_OUTPUT” on page 6–110 




INPUT_REFERENCE 

INPUT_REFERENCE 

Type 

Allows you to specify the VREF pin for the I/O standard being used by an I/O pin. 

This option is ignored if it is applied to anything other than the I/O standard being 

used by an I/O pin. 

Enumeration 

■ As VREFA 

■ As VREFB 

■ Off 



■ MAX7000B 

Syntax 

set_instance_assignment -name INPUT_REFERENCE -to -entity 




INPUT_TERMINATION 

INPUT_TERMINATION 

Type 



integrity. This option is ignored if it is applied to anything other than an I/O pad, 

input buffer, or output buffer. This option should be applied to an I/O pad or input 

buffer of an I/O in bidirectional or input mode. A bidirectional I/O may also have an 

output termination assignment. 

String 





■ Arria V 


■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name INPUT_TERMINATION -to -entity 

Example 

set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH 

CALIBRATION" -to pin_name 

See Also 





INSERT_ADDITIONAL_LOGIC_CELL 

INSERT_ADDITIONAL_LOGIC_CELL 

Type 

Allows the Compiler to insert an additional logic cell after the output(s) of the logic 

function to which it is applied, provided that the function is implemented as one logic 

cell. This option allows you to insert logic cells for routing purposes without adding 

LCELL primitives to the design. If this option is applied to a mega- or macrofunction, 

it operates on all outputs of the function. This option is ignored if it is applied to a 

logic function that is not already implemented in a macrocell(s). For example, if it is 

applied to an AND gate, it does not force the AND gate to be the output of a logic cell. 

Boolean 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Syntax 

set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL -to - 

entity 




INTERNAL_SCRUBBING 

INTERNAL_SCRUBBING 

Type 

Specifies internal scrubbing usage for the selected device. If internal scrubbing is 

turned on, the device corrects single error or double adjacent error within the core 

configuration memory while the device is still running. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name INTERNAL_SCRUBBING 

Example 

set_global_assignment -name INTERNAL_SCRUBBING ON 

Default Value 

Off 




IO_MAXIMUM_TOGGLE_RATE 


Type 

Specifies the toggle rate of this node. You can specify the desired frequency setting. 

This option is ignored if it is applied to anything other than pins. This option can be 

used to direct the Fitter in its toggle-rate checking while allowing a single-ended pin 

to be placed closer to a differential pin. This assignment is used to analyze signal 

integrity under worst case conditions (highest possible toggle rate). A different 

assignment, Power Toggle Rate, is used to specify the expected time-averaged toggle 

rate rather than worst-case toggle rate, and is used by the Power Analyzer to estimate 

time-averaged power consumption. Use the Synchronizer Toggle Rate if you want to 

configure the data rates used for Metastability Reporting in the TimeQuest timing 

analyzer. 

Frequency 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE -to -entity 

 

Old Names 


software: 

TOGGLE RATE 

TOGGLE_RATE 




IO_PLACEMENT_OPTIMIZATION 


Type 

Specifies whether the Fitter optimizes the location of I/Os that do not already have 

pin locations assigned to them. Performing IO placement optimizations may improve 

I/O timing, f MAX, and fitting, but may also require longer compilation time. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Syntax 

set_global_assignment -name IO_PLACEMENT_OPTIMIZATION 





Default Value 

On 




IO_STANDARD 

IO_STANDARD 

Type 

Specifies the I/O standard of a pin. Different device families support different I/O 

standards, and restrictions apply to placing pins with different I/O standards 

together. For more information, refer to the respective device family data sheet. This 

option is ignored if it is applied to anything other than a pin or a top-level design 

entity. 

This option specifies an I/O standard of a pin. If a pin does not have this option, the 

Quartus II software automatically assigns an I/O standard to the pin, based on the 

global device option STRATIX_DEVICE_IO_STANDARD (or its device value), or 

derived from the netlist (for example, using differential output buffer implies that 

differential I/O standard is used). You should specify this option explicitly because 

I/O standard affects placement, timing and power. This option also implies what 

other I/O options are supported such as current strength, slew rate, termination, preemphasis 

and VOD. This option is always honored. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX7000B 

■ Stratix 





IO_STANDARD 





■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name IO_STANDARD -to 

Example 

set_instance_assignment -name IO_STANDARD LVDS -to pin 

See Also 

■ “STRATIX_DEVICE_IO_STANDARD” on page 6–341 

■ “CURRENT_STRENGTH_NEW” on page 6–43 

■ “SLEW_RATE” on page 6–313 


■ “INPUT_TERMINATION” on page 6–179 

■ “PROGRAMMABLE_PREEMPHASIS” on page 6–275 

■ “PROGRAMMABLE_VOD” on page 6–277 




LVDS_DIRECT_LOOPBACK_MODE 

LVDS_DIRECT_LOOPBACK_MODE 

Type 

Enable the LVDS Direct Loop Mode on a True Differential output pin. This assignment 

should only apply from an input pin to an output pin and both of them should have 

True Differential I/O standard. When this feature is enabled, data coming in from the 

adjacent RX pair gets looped back to the TX pair. This feature can be used to verify the 

Tx and Rx buffer by checking the data transmit and received. This option is ignored if 

it is applied to anything other than a pin or a top-level design entity. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name LVDS_DIRECT_LOOPBACK_MODE -from -to 

-entity 

Example 

set_instance_assignment -name LVDS_DIRECT_LOOPBACK_MODE ON -from 

true_diff_in_pin_p -to true_diff_out_pin_p 

See Also 





LVDS_RX_REGISTER 

LVDS_RX_REGISTER 

Type 


register for LVDS receiver interfaces. 

Enumeration 

■ High 

■ Low 

■ Off 







Notes 


Syntax 

set_instance_assignment -name LVDS_RX_REGISTER -to -entity 




M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY 

M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY 

Type 

Allows you to specify whether the M144K memory block read operations depend 

upon the read clock’s duty cycle. When M144K memory blocks are driven by a read 

clock with a very narrow pulse, they can go into a locked, inactive state. Turning on 

this option allows the M144K memory blocks to operate dependent upon the read 

clock’s duty cycle to prevent the memory blocks from going into to an inactive state; 

however, turning on this option may degrade the performance of the M144K blocks. 

Enumeration 

■ Off 

■ On 






Notes 



Syntax 

set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY - 

entity 

set_instance_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY 

-to -entity 

set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY 

 

Default Value 

Off 




MATCH_PLL_COMPENSATION_CLOCK 

MATCH_PLL_COMPENSATION_CLOCK 

Type 

Allows you to specify a PLL output clock feeding a clock network as a compensation 

target for a PLL in NORMAL or SOURCE_SYNCHRONOUS mode. This configures 

the PLL to match its feedback path to the target’s clock network. This option is 

ignored if it is applied to anything other than a PLL output clock. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK -to - 

entity 




MAX7000B_VCCIO_IOBANK1 


Type 

Specifies the default I/O Bank1 Voltage to be used for pins on the target device. 

String 



■ MAX7000B 

Notes 


Syntax 

set_global_assignment -name MAX7000B_VCCIO_IOBANK1 






Type 

Specifies the default I/O Bank2 Voltage to be used for pins on the target device. 

String 



■ MAX7000B 

Notes 


Syntax 

set_global_assignment -name MAX7000B_VCCIO_IOBANK2 




MAX7000_DEVICE_IO_STANDARD 

MAX7000_DEVICE_IO_STANDARD 

Type 

Specifies the default I/O standard to be used for pins on the target device. 

String 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_global_assignment -name MAX7000_DEVICE_IO_STANDARD 




MAX7000_ENABLE_JTAG_BST_SUPPORT 

MAX7000_ENABLE_JTAG_BST_SUPPORT 

Type 

Enables JTAG boundary-scan test (BST) support. 

Boolean 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Syntax 

set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT 

Default Value 

On 




MAX7000_INDIVIDUAL_TURBO_BIT 

MAX7000_INDIVIDUAL_TURBO_BIT 

Type 

Controls the speed versus power usage trade-off for a macrocell. If the Turbo Bit is on, 

the macrocell’s speed increases; if it is off, its power consumption decreases. 

Boolean 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_global_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT -entity 

set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT -to - 

entity 

Old Names 


software: 

Turbo Bit -- MAX 7000B/7000AE/3000A/7000S/7000A 




MAX_CLOCKS_ALLOWED 

MAX_CLOCKS_ALLOWED 

Type 

Specifies the maximum number of clocks of any type (for example, global clock, 

regional clock) that can be used by the design. A value of -1 means that the Fitter can 

use all the clocks supported by the device. 

Integer 



■ Arria GX 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name MAX_CLOCKS_ALLOWED 

Default Value 





MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION 

MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION 

Type 

Specifies the number of consecutive horizontal output or bidirectional pins 

considered in the current-density computation for electromigration when the Fitter 

checks for electromigration violations. 

Integer 



■ Arria GX 

■ Cyclone 








■ MAX V 

■ Stratix 




Syntax 

set_global_assignment -name MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION 

 




MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION 

MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION 

Type 

Specifies the number of consecutive vertical output or bidirectional pins considered in 

the current-density computation for electromigration when the Fitter checks for 

electromigration violations. 

Integer 



■ Arria GX 

■ Cyclone 








■ MAX V 

■ Stratix 




Syntax 


MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION 




MAX_CURRENT_FOR_ELECTROMIGRATION 

MAX_CURRENT_FOR_ELECTROMIGRATION 

Type 

Specifies the maximum amount of DC current, in mA, allowed on horizontal output 

or bidirectional pins when the Fitter checks for electromigration violations. 

Integer 



■ Arria GX 

■ Cyclone 








■ MAX V 

■ Stratix 




Syntax 

set_global_assignment -name MAX_CURRENT_FOR_ELECTROMIGRATION 




MAX_CURRENT_FOR_VIO_ELECTROMIGRATION 

MAX_CURRENT_FOR_VIO_ELECTROMIGRATION 

Type 

Specifies the maximum amount of DC current, in mA, allowed on vertical output or 

bidirectional pins when the Fitter checks for electromigration violations. 

Integer 



■ Arria GX 

■ Cyclone 








■ MAX V 

■ Stratix 




Syntax 

set_global_assignment -name MAX_CURRENT_FOR_VIO_ELECTROMIGRATION 




MAX_GLOBAL_CLOCKS_ALLOWED 

MAX_GLOBAL_CLOCKS_ALLOWED 

Type 

Specifies the maximum number of global clocks that can be used by the design. A 

value of -1 means that the Fitter can use all the global clocks supported by the device. 

Integer 



■ Arria GX 















■ Stratix V 

Notes 


Syntax 

set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED 

Default Value 





MAX_PERIPHERY_CLOCKS_ALLOWED 

MAX_PERIPHERY_CLOCKS_ALLOWED 

Type 

Specifies the maximum number of periphery clocks that can be used by the design. A 

value of -1 means that the Fitter can use all the periphery clocks supported by the 

device. 

Integer 









■ Stratix V 

Notes 


Syntax 

set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED 

Default Value 





MAX_REGIONAL_CLOCKS_ALLOWED 

MAX_REGIONAL_CLOCKS_ALLOWED 

Type 

Specifies the maximum number of regional clocks that can be used by the design. A 

value of -1 means that the Fitter can use all the regional clocks supported by the 

device. 

Integer 



■ Arria GX 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED 

Default Value 





MEMORY_INTERFACE_DATA_PIN_GROUP 

MEMORY_INTERFACE_DATA_PIN_GROUP 

Type 

Specifies the group width (4, 9, 18, or 36), and associates a pin with another pin. 

Turning on this option allows the Fitter to view the pins as part of the same memory 

interface pin group. I/O pins of this pin group must be placed in the DQ pin locations 

of a single DQS group. This option is ignored if is assigned to anything other than an 

I/O pad, input buffer, or output buffer. 

Integer 













Notes 


Syntax 

set_instance_assignment -name MEMORY_INTERFACE_DATA_PIN_GROUP -from 

-to -entity 

Example 

set_instance_assignment -name MEMORY_INTERFACE_DATA_PIN_GROUP 4 -from 

mem_clk[0] -to mem_clk_n[0] 

See Also 

■ “DQSB_DQS_PAIR” on page 6–86 

■ “DQ_GROUP” on page 6–90 




MEM_INTERFACE_DELAY_CHAIN_CONFIG 

MEM_INTERFACE_DELAY_CHAIN_CONFIG 

Type 

Changes Quartus II Fitter behavior regarding delay chain configurations on memory 

interface pins. This option is ignored if is assigned to anything other than an I/O pad, 

input buffer, or output buffer. 

Enumeration 


■ Fitter_optimized 

■ Flexible_timing 

■ Macro_timing 


Notes 


Syntax 

set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG -to - 

entity 




MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR 

MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR 

Type 

Allows merging of HSSI TX PLLs if their reset input are driven by registers that have 

the same asynchronous clear input. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 


MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR -to -entity 




MIGRATION_CONSTRAIN_CORE_RESOURCES 

MIGRATION_CONSTRAIN_CORE_RESOURCES 

Type 

Limits the Compiler to only use those core resources which are also available in the 

target migration device. 

Boolean 



■ Arria GX 






Syntax 

set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES 

Default Value 

On 




MIGRATION_DEVICES 

MIGRATION_DEVICES 

Type 

Shows the selected migration devices for the target device. 

String 



Notes 



devices. 

Syntax 

set_global_assignment -name MIGRATION_DEVICES 




NCEO_OPEN_DRAIN 

NCEO_OPEN_DRAIN 

Type 

Specify whether the Open-Drain feature on the nCEO pin should be enabled or not. 

Using this feature decouples the voltage level of the nCEO pin from V CCIO. 

You must connect a pull-up resistor to the pin when this feature is enabled. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name NCEO_OPEN_DRAIN 

Example 

set_global_assignment -name nceo_open_drain on 

set_global_assignment -name nceo_open_drain off 

Default Value 

On 

See Also 

■ “ENABLE_NCEO_OUTPUT” on page 6–112 




NDQS_LOCAL_CLOCK_DELAY_CHAIN 

NDQS_LOCAL_CLOCK_DELAY_CHAIN 

Type 

Sets the propagation delay on the NDQS signal to the input register of the target pin. 

This is an advanced option that should be used only after you have compiled a 

project, checked the I/O timing, and determined that the timing is unsatisfactory. For 

detailed information on how to use this option, refer to the data sheet for the device 

family. This option is ignored if it is applied to anything other than a DQ or DQS pin. 

Integer 



■ Arria GX 





Notes 


Syntax 

set_instance_assignment -name NDQS_LOCAL_CLOCK_DELAY_CHAIN -to - 

entity 




OPTIMIZE_FOR_METASTABILITY 

OPTIMIZE_FOR_METASTABILITY 

Type 

Improves the reliability of the design by increasing its Mean Time Between Failures 

(MTBF). When this setting is enabled, the Fitter aims to increase the output setup 

slacks of synchronizer registers in the design, which can exponentially increase the 

design MTBF. This option takes effect only if the TimeQuest timing analyzer is being 

used for timing-driven compilation. Use the TimeQuest analyzer 

report_metastability command to review the synchronizers detected in your design 

and to produce MTBF estimates. 

Enumeration 

■ Off 

■ On 





■ Arria V 





■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name OPTIMIZE_FOR_METASTABILITY 

Default Value 

On 




OPTIMIZE_HOLD_TIMING 


Type 

Allows the Fitter to optimize hold time by adding delay to the appropriate paths. The 

Optimize Timing option must be turned on in order for this option to work. If you 

use the TimeQuest timing analyzer and specify the I/O Paths and Minimum tpd 

Paths setting, all assignments involving I/O pins are optimized. Specifying the All 

Paths setting directs the Fitter to optimize the hold time of all paths. Turning off this 

option directs the Fitter not to optimize the hold time of any paths. 

Enumeration 

■ All Paths 

■ IO Paths and Minimum TPD Paths 

■ Off 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name OPTIMIZE_HOLD_TIMING 




OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING 

OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING 

Type 

Controls whether the Fitter optimizes I/O pin timing by automatically packing 

registers into I/Os to minimize I/O -> register and register -> I/O delays. If you 

enable the Normal option, the Fitter opportunistically packs registers into I/Os that 

should improve I/O timing. If you enable the Pack All I/O Registers, the Fitter 

aggressively tries to pack any registers connected to input, output or output enable 

pins into I/Os unless prevented by user constraints or other legality restrictions. By 

default, this option is set to Normal. This option requires the Optimize Timing option 

to be enabled for it to work. 

Enumeration 

■ Normal 

■ Off 


■ Pack All IO Registers 


Notes 


Syntax 

set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING 

 

Default Value 

Normal 




OPTIMIZE_MULTI_CORNER_TIMING 


Type 

Controls whether the Fitter optimizes a design to meet timing requirements at all 

process corners and operating conditions. The Optimize Timing logic option must be 

enabled for this option to work. If you turn this setting off, designs are optimized to 

meet timing only at the slow timing process corner and operating condition. When 

you turn this option on, designs are optimized to meet timing at all corners and 

operating conditions; as a result, turning on this option helps create a design 

implementation that is more robust across process, temperature, and voltage 

variations. Turning on this option does not enable multi-corner timing analysis. To 

enable multi-corner timing analysis, go to the TimeQuest Timing Analyzer page of 

the Settings dialog box. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 

■ EPC1 

■ EPC2 


■ FLEX10KB 

■ FLEX8000 





■ MAX V 





■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

■ MAX9000 

■ Stratix 






■ Stratix V 

Notes 


Syntax 

set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING 

Old Names 


software: 

OPTIMIZE_FAST_CORNER_TIMING 

Optimize Fast-Corner Timing 




OPTIMIZE_POWER_DURING_FITTING 


Type 

Controls the power-driven compilation setting of the Fitter. This option determines 

how aggressively the Fitter optimizes the design for power. If you set this option to 

Off, the Fitter does not perform any power optimizations. If you set this option to 

Normal compilation, the Fitter performs power optimizations which should not 

impact design performance or increase compile time. If you set this option to Extra 

effort, the Fitter performs additional power optimizations which may affect design 

performance and/or increase compile time. For the best results with Extra Effort 

power optimization during fitting, you should specify a Signal Activity File (.saf) that 

lists the toggle rate of each signal in the design. To generate the most accurate .saf, use 

a gate-level simulation, with glitch filtering, of the compiled design. Specify this .saf 

as an input to the Power Analyzer in the PowerPlay Power Analysis Settings, and 

recompile the design with Extra Effort PowerPlay Power Optimization during fitting. 

The signal activities (toggle rates) in the .saf help guide the Fitter to reduce power. 

Enumeration 



■ Off 



■ Arria GX 



■ Arria V 






■ Cyclone V 





■ MAX V 









■ Stratix V 

Notes 


Syntax 

set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING 

set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING -entity 

set_instance_assignment -name OPTIMIZE_POWER_DURING_FITTING -to - 

entity 

Default Value 





OPTIMIZE_SSN 

OPTIMIZE_SSN 

Type 

Controls the Simultaneous Switching Noise (SSN) optimization setting of the Fitter. 

This option determines how aggressively the Fitter optimizes the design for SSN. If 

this option is set to Off, the Fitter does not perform any SSN optimizations. If this 

option is set to Normal compilation, the Fitter performs SSN optimizations which 

should not impact design performance. When this option is set to Extra effort, the 

Fitter performs aggressive SSN optimizations which may affect design performance. 

Enumeration 



■ Off 





■ Arria V 





■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name OPTIMIZE_SSN 

Default Value 

Off 




OPTIMIZE_SSN 

Old Names 


software: 

OPTIMIZE_SIGNAL_INTEGRITY 




OPTIMIZE_TIMING 


Type 

Controls whether the Fitter optimizes to meet maximum delay timing requirements 

(for example, clock cycle time). By default, this option is set to Normal compilation. 

Turning it off can help fit designs that have extremely high interconnect requirements 

and can also reduce compilation time, although at the expense of significant timing 

performance (since the Fitter ignores the timing requirements of the design). If this 

option is off, other Fitter timing optimization options have no effect (such as 

Optimize Hold Timing). 

Enumeration 


■ Off 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name OPTIMIZE_TIMING 

Default Value 


Old Names 


software: 

OPTIMIZE_INTERNAL_TIMING 

USE_TIMING_DRIVEN_COMPILATION 




OUTPUT_BUFFER_DELAY 

OUTPUT_BUFFER_DELAY 

Type 

Specifies the delay value (in ps) for the Programmable Output Buffer Delay. Turning 

on this feature should improve the output duty cycle at the cost of worse timing 

across the output buffer. 

Integer 




■ Arria V 

■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name OUTPUT_BUFFER_DELAY -to -entity 

Example 

set_instance_assignment -name OUTPUT_BUFFER_DELAY 50 -to pin 



See Also 

■ “OUTPUT_BUFFER_DELAY_CONTROL” on page 6–225 




OUTPUT_BUFFER_DELAY_CONTROL 


Type 

Specifies the edges for the Programmable Output Buffer Delay. Turning on this 

feature should improve the output duty cycle at the cost of worse timing across the 

output buffer. 

Enumeration 

■ Both Edges 

■ Negative Edge 

■ Off 


■ Positive Edge 



■ Arria V 

■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name OUTPUT_BUFFER_DELAY_CONTROL -to -entity 

 

Example 

set_instance_assignment -name OUTPUT_BUFFER_DELAY_CONTROL "Both Edges" -to 

pin 

Old Names 


software: 

STRATIXII_OUTPUT_DUTY_CYCLE_CONTROL 





See Also 

■ “OUTPUT_BUFFER_DELAY” on page 6–224 




OUTPUT_ENABLE_DELAY 

OUTPUT_ENABLE_DELAY 

Type 

Specifies the propagation delay to the output enable pin from internal logic or the 

output enable register implemented in an I/O cell. This is an advanced option that 




applied to anything other than an output pin or bidirectional pin. 

Integer 



■ Arria GX 









Notes 


Syntax 

set_instance_assignment -name OUTPUT_ENABLE_DELAY -to -entity 




OUTPUT_ENABLE_GROUP 


Type 

Assigns an output enable group number for the specified node. Turning on this option 

directs the Fitter to view the specified nodes as an output enable group so as not to 

violate the requirements for the maximum number of pins driving out of a VREF 

group when a voltage-referenced input pin or bidirectional pin is present. For 

bidirectional pins, the Fitter determines all possible pins that may potentially drive 

out when any bidirectional pin is driving in by looking at the output enable of all the 

bidirectional pins in the VREF group. This behavior can result in the VREF group 

exceeding the maximum number of outputs and result in a no fit. Turning on the 

Output Enable Group option allows you to specify an output enable group for 

specific pins, thus allowing you to specify which pins in the design are driving in and 

out at the same time. The Fitter only considers pins as potential outputs when they are 

in separate output enable groups or when they are not in an output enable group; by 

specifying an output enable group, you can lower the total number of outputs in the 

VREF group when any pin is driving in. As a result, the Fitter does not count all of the 

potential outputs of the bidirectional pins and the number of outputs in the VREF 

group remains in the legal range. You should turn on this option when the Fitter 

cannot detect the output enable group of the pins in the VREF group, for example 

when the output enables come from a state machine or complex logic. For detailed 

information on the number of outputs supported by a VREF group, refer to the 

respective device family data sheet. 

Integer 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 









■ MAX V 

■ Stratix 






■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name OUTPUT_ENABLE_GROUP -to -entity 

Example 

set_instance_assignment -name OUTPUT_ENABLE_GROUP 2 -to output_pin[0] 

set_instance_assignment -name OUTPUT_ENABLE_GROUP 2 -to output_pin[1] 




OUTPUT_PIN_LOAD 

OUTPUT_PIN_LOAD 

Type 

Specifies the capacitive load, in picofarads (pF), on output pins for each I/O standard. 

These settings affect FPGA pins only. To specify board trace, termination, and 

capacitive load parameters for use with Advanced I/O Timing, use the Board Trace 

Model tab. Capacitive loading is ignored if applied to anything other than an output 

or bidirectional pin, or if Advanced I/O Timing is enabled. 

Integer 




■ Arria GX 

■ Cyclone 




■ MAX V 

■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 




Notes 

This assignment is copied to any duplicated nodes 

Syntax 

set_instance_assignment -name OUTPUT_PIN_LOAD -to -entity 

set_global_assignment -name OUTPUT_PIN_LOAD -section_id 




OUTPUT_TERMINATION 

OUTPUT_TERMINATION 

Type 



integrity. This option is ignored if it is applied to anything other than an I/O pad, 

input buffer, or output buffer. This option should be applied to an I/O pad or output 

buffer of an I/O in bidirectional or output mode. A bidirectional I/O may also have 

an input termination assignment. 

String 





■ Arria V 





■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name OUTPUT_TERMINATION -to -entity 

Example 

set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH 

CALIBRATION" -to pin_name 

See Also 





OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS 

OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS 

Type 

Specifies whether you want the Fitter to use default electromigration values, or if you 

want to specify maximum consecutive output and maximum current values. 

Boolean 



■ Arria GX 

■ Cyclone 







■ Stratix 




Syntax 

set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS 

 

Default Value 

Off 




PAD_TO_CORE_DELAY 

PAD_TO_CORE_DELAY 

Type 

Specifies the propagation delay from an input or bidirectional pin to logic and 

embedded cells within the device. This is an advanced option that should be used 



to the data sheet for the device family. This option is ignored if it is applied to 

anything other than an input or bidirectional pin. 

Integer 



■ Arria GX 









■ MAX V 



Notes 


Syntax 

set_instance_assignment -name PAD_TO_CORE_DELAY -to -entity 

set_instance_assignment -name PAD_TO_CORE_DELAY -from -to - 

entity 




PAD_TO_DDIO_REGISTER_DELAY 

PAD_TO_DDIO_REGISTER_DELAY 

Type 

Specifies the propagation delay from an input pin to the data input of the DDIO low 

capture input register in the I/O cell associated with the pin. This is an advanced 




ignored if it is applied to anything other than an input or bidirectional pin that uses 

DDIO functionality. 

Integer 




Notes 


Syntax 

set_instance_assignment -name PAD_TO_DDIO_REGISTER_DELAY -to -entity 

 




PAD_TO_INPUT_REGISTER_DELAY 

PAD_TO_INPUT_REGISTER_DELAY 

Type 

Specifies the propagation delay from an input pin to the data input of the input 

register implemented in the I/O cell associated with the pin. This is an advanced 




ignored if it is applied to anything other than an input or bidirectional pin. 

Integer 



■ Arria GX 










Notes 


Syntax 

set_instance_assignment -name PAD_TO_INPUT_REGISTER_DELAY -to -entity 

 




PCI_IO 

PCI_IO 

Type 

Turns on PCI compatibility for a pin. For example, when the VCCIO of an EP20K400 

device operates at 3.3 V and PCI I/O is turned on for a pin, the Compiler clamps the 

pin’s signal to the VCCIO value, thus making the pin 3.3-V PCI-compliant. This 

option is ignored if it is applied to anything other than a pin or a top-level design 

entity. 

Boolean 



■ Arria GX 

■ Cyclone 








■ MAX V 

■ Stratix 




Notes 



Syntax 

set_global_assignment -name PCI_IO -entity 

set_instance_assignment -name PCI_IO -to -entity 

set_global_assignment -name PCI_IO 

Example 

set_instance_assignment -name PCI_IO ON -to pin 




PCI_IO 

Default Value 

Off 




PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING 


Type 

Specifies that the Quartus II software should perform automatic insertion of pipeline 

stages for asynchronous clear and asynchronous load signals during fitting to increase 

circuit performance. This option is useful for asynchronous signals that are failing 

recovery and removal timing because they feed registers using a high-speed clock. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 



■ MAX V 

■ Stratix 






■ Stratix V 

Notes 







Syntax 


PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING 


PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING -entity 

 


PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING -to -entity 

Default Value 

Off 




PHYSICAL_SYNTHESIS_COMBO_LOGIC 


Type 

Specifies that the Quartus II software should perform physical synthesis 

optimizations on combinational logic during synthesis and fitting to increase circuit 

performance. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Notes 







Syntax 

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC 

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC -entity 

set_instance_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC -to - 

entity 

Default Value 

Off 




PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA 


Type 

Specifies that the Fitter should perform physical synthesis optimizations on 

combinational logic during fitting to achieve a fit. 

Boolean 



■ Arria GX 



■ Arria V 






■ Cyclone V 





■ Stratix V 

Notes 



Syntax 

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA 

 

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA - 

entity 

set_instance_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA -to 

-entity 





Default Value 

Off 




PHYSICAL_SYNTHESIS_EFFORT 


Type 

Specifies the amount of effort, in terms of compile time, physical synthesis should use. 

Compared to the Default setting, a setting of Extra uses extra compile time to try to 

gain extra circuit performance. Conversely, a setting of Fast uses less compile time 

but may reduce the performance gain that physical synthesis is able to achieve. 

Enumeration 

■ Extra 

■ Fast 

■ Normal 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT 

Default Value 

Normal 

Old Names 


software: 

PHYSICAL_SYNTHESIS_EXTRA_EFFORT 




PHYSICAL_SYNTHESIS_LOG_FILE 

PHYSICAL_SYNTHESIS_LOG_FILE 

Type 

Specifies the log file that lists all the physical synthesis operations performed in a 

previous compile that need to be reproduced. This log should be generated during a 

Stratix II compile with physical synthesis on, and in which a Hardcopy II device is 

specified for migration. When the design is migrated to Hardcopy II, this log file 

allows the original physical synthesis operations performed on the Stratix II device to 

be replicated on the Hardcopy II device. 

String 





Syntax 

set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE 

Default Value 

Off 




PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA 

PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA 

Type 

Specifies that the Fitter should perform physical synthesis optimizations on logic and 

registers, specifically allowing the mapping of logic and registers into unused 

memory blocks during fitting to achieve a fit. 

Boolean 



■ Arria GX 












Notes 



Syntax 


PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA 


PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA -entity 

 


PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA -to -entity 

Default Value 

Off 




PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION 


Type 

Specifies that the Fitter should perform physical synthesis optimizations on registers, 

specifically allowing register duplication, during fitting to increase circuit 

performance. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 



■ MAX V 

■ Stratix 






■ Stratix V 

Notes 







Syntax 

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION 

 

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION - 

entity 

set_instance_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION -to 

-entity 

Default Value 

Off 




PHYSICAL_SYNTHESIS_REGISTER_RETIMING 


Type 

Specifies that the Quartus II software should perform physical synthesis 

optimizations on registers, specifically allowing register retiming, during synthesis 

and fitting to increase circuit performance. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Notes 







Syntax 

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING 

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING -entity 

 

set_instance_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING -to 

-entity 

Default Value 

Off 




PLACEMENT_EFFORT_MULTIPLIER 


Type 

Controls how much time the Fitter spends in placement. The default value is 1.0 and 

legal values must be greater than 0. Specifying a floating-point number allows you to 

control the placement effort. A higher value increases CPU time but may improve 

placement quality. For example, a value of 4 increases fitting time by approximately 2 

to 4 times but may increase quality. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 

■ EPC1 

■ EPC2 


■ FLEX10KB 

■ FLEX8000 





■ MAX V 

■ MAX9000 

■ Stratix 










■ Stratix V 

Notes 


devices. 


Syntax 

set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 

Default Value 

1.0 




PLL_AUTO_RESET 

PLL_AUTO_RESET 

Type 

Causes the PLL to self-reset automatically on loss of lock. The lock time of a PLL is 

defined as the amount of time required by the PLL to attain the target frequency and 

phase relationship after device power-up, after a change in the PLL output frequency, 

or after resetting the PLL. 

A PLL might lose lock for a number of reasons, such as the following causes: 

■ Excessive jitter on the reference clock. For PLL input jitter specification, refer to the 

DC and Switching Characteristics chapter in the relevant device handbook. 

■ Excessive switching noise on the clock inputs of the PLL. 

■ Excessive noise from the power supply can cause high output jitter and possible 

loss of lock. 

■ A glitch or stopping of the input clock to the PLL. 

■ Resetting the PLL by asserting the reset port of the PLL. 

■ An attempt to reconfigure the PLL might cause the M counter, N counter, or phase 

shift to change, which causes the PLL to lose lock. However, changes to the postscale 

counters do not affect the PLL locked signal. 

■ PLL reference clock frequency drifts outside the lock range specification. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name PLL_AUTO_RESET -to -entity 




PLL_BANDWIDTH_PRESET 

PLL_BANDWIDTH_PRESET 

Type 

Specifies the PLL bandwidth preset setting. 

Enumeration 

■ Auto 

■ High 

■ Low 

■ Medium 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name PLL_BANDWIDTH_PRESET -to -entity 

 




PLL_CHANNEL_SPACING 

PLL_CHANNEL_SPACING 

Type 

Specifies the PLL channel spacing. The PLL channel spacing is the frequency 

difference between successive oscillations of the feedback clock into the phase 

frequency detector. 

Frequency 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name PLL_CHANNEL_SPACING -to -entity 




PLL_COMPENSATE 


Type 

Allows you to specify an output pin as a compensation target for a PLL in 

ZERO_DELAY_BUFFER or EXTERNAL_FEEDBACK mode, or an input pin or a 

group of input pins as compensation targets for a PLL in SOURCE_SYNCHRONOUS 

mode. If assigned to an output pin, the pin must be fed by the external clock output 

port of a PLL in a Stratix, Hardcopy Stratix or Cyclone device, or the compensated 

clock output port of a PLL in other devices. Any other output pins fed by the same 

PLL generally are not delay compensated, especially if they have different I/O 

standards. If assigned to an input pin or a group of input pins, the input pins must 

drive input registers that are clocked by the compensated clock output port of a PLL 

in SOURCE_SYNCHRONOUS mode. This option is ignored if it is applied to 

anything other than an output or input pin as described previously. 

Boolean 



■ Arria GX 



■ Arria V 






■ Cyclone V 




■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_instance_assignment -name PLL_COMPENSATE -to -entity 




PLL_COMPENSATION_MODE 


Specifies the routing path of the PLL feedback clock and adjusts the delay chains in 

the PLL. 

■ Direct—The aim of this setting is to produce the smallest possible jitter at the PLL 

output. You can perform this by minimizing the length of the feedback path by not 

compensating for anything. 

■ External Feedback—The goal is to have the clock edge at the clock output pin to 

occur earlier than the clock edge at the clock input (reference) pin, by the amount 

of board trace delay placed between the clock output pin and the external 

feedback input pin. In this mode what needs to be compensated for within the 

FPGA is any difference in delay between the two paths: 

■ Clock Input Pin to the PLL PFD input 

■ External Feedback Input Pin to the PLL PFD input 

■ LVDS—The aim of this setting is to maintain the same data and clock timing 

relationship seen at the pins at the internal SERDES capture register. Thus, this 

mode ideally compensates for the delay of the LVDS clock network, plus any 

differences in delay between the following two paths: 

■ Data Pin to SERDES capture register 

■ Clock Input Pin to SERDES capture register 

The compensation mimic path is designed to mimic the clock and data delay of the 

receiver side. 

■ Normal—The aim of this setting is to have the clock edge at an IOE or LE register 

to occur at the same time that it does at the Clock Input Pin. Thus, this mode 

ideally compensates for the clock network used and the delay from the Clock 

Input Pin to the PLL PFD input. Since you are unable to compensate for the delay 

in the first stage of the input buffer, you must use a delay chain for compensation. 

■ Source Synchronous—The aim of this setting is to maintain the same data and 

clock timing relationship seen at the pins at any IOE register. Thus, this mode 

ideally compensates for the delay of the clock network used, including any 

differences in delay between the following two paths: 

■ Data Pin to IOE register input 

■ Clock Input Pin to PLL PFD input 

There is a delay cell block in the feedback path to compensate for the timing 

differences between the SE and DIFF input delay in the IO register and wire delay. 

■ Zero Delay Buffer—The goal is to have zero delay between a clock edge at the 

clock input pin and the clock output pin. This consumes a clock output pin to 

provide the output buffer delay compensation. Thus this mode ideally 

compensates for the delay from the clock input pin to the PLL PFD input, plus the 

delay from the PLL output to the clock output pin. 

If the input clock and feedback buffers use different IO standard, we need to 

compensate the delay different by using delay chain. 





Type 

Enumeration 

■ Direct 

■ External Feedback 

■ LVDS 

■ Normal 


■ Source Synchronous 

■ Zero Delay Buffer 


■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name PLL_COMPENSATION_MODE -to -entity 

 




PLL_ENFORCE_USER_PHASE_SHIFT 

PLL_ENFORCE_USER_PHASE_SHIFT 

Type 

Ensures that phase shift requirements are given higher priority. 

Boolean 













Notes 


Syntax 

set_instance_assignment -name PLL_ENFORCE_USER_PHASE_SHIFT -to - 

entity 




PLL_FEEDBACK_CLOCK_SIGNAL 

PLL_FEEDBACK_CLOCK_SIGNAL 

Type 

Allows you to specify whether PLL feedback clock signal should be routed using 

global or regional routing paths in the PLL conversion code to fractional PLL. 

Enumeration 


■ Global Clock 

■ Regional Clock 


■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name PLL_FEEDBACK_CLOCK_SIGNAL -to -entity 

 




PLL_FORCE_OUTPUT_COUNTER 


Type 

Forces which counter to use for a particular PLL clock output. By default, the 

Compiler automatically determines the best counter to use based on clock usage and 

other routing conflicts, but can be overridden with this option. Using this option can 

cause clock routing problems, as the clock router cannot rotate counters to resolve 

conflicts. Also refer to option “PRESERVE_PLL_COUNTER_ORDER” on page 6–272. 

Enumeration 

■ C0 

■ C1 

■ C2 

■ C3 

■ C4 

■ C5 

■ C6 

■ C7 

■ C8 

■ C9 



■ Arria GX 



















Notes 


Syntax 

set_instance_assignment -name PLL_FORCE_OUTPUT_COUNTER -to -entity 

 




PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY 

PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY 

Type 

Forces which counter to use for a particular PLL clock output. By default, the 

Compiler automatically determines the best counter to use based on clock usage and 

other routing conflicts, but can be overridden with this option. Using this option can 

cause clock routing problems, as the clock router cannot rotate counters to resolve 

conflicts. Also refer to option “PRESERVE_PLL_COUNTER_ORDER” on page 6–272. 

Enumeration 

■ C0 

■ C1 

■ C2 

■ C3 

■ C4 

■ C5 

■ C6 

■ C7 

■ C8 

■ C9 








Notes 


Syntax 

set_instance_assignment -name PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY -to 

-entity 




PLL_IGNORE_MIGRATION_DEVICES 

PLL_IGNORE_MIGRATION_DEVICES 

Type 

Forces the Compiler to ignore the migration devices when calculating the PLL 

settings. Normally, the PLL is configured to work for all migration devices in addition 

to the current device. When this option is enabled, the Compiler ignores the PLL 

constraints for the migration devices, and only considers the PLL constraints from the 

current device. 

Boolean 



■ Arria GX 















Notes 


Syntax 

set_instance_assignment -name PLL_IGNORE_MIGRATION_DEVICES -to - 

entity 




PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING 

PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING 

Type 

Allows the Fitter to set the phase shift of a PLL output counter, and hence the phase 

shift of its generated clock, to improve timing for all edges affected by this clock. 

Apply multicycle timing exceptions to paths between the generated clock and other 

clocks in the design to avoid timing violations. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING -to 

-entity 




PLL_OUTPUT_CLOCK_FREQUENCY 

PLL_OUTPUT_CLOCK_FREQUENCY 

Type 

Specifies the output clock frequency of the PLL. 

Frequency 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name PLL_OUTPUT_CLOCK_FREQUENCY -to -entity 

 




PLL_PFD_CLOCK_FREQUENCY 

PLL_PFD_CLOCK_FREQUENCY 

Type 

Specifies the phase frequency detector (PFD) clock frequency. 

Frequency 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name PLL_PFD_CLOCK_FREQUENCY -to -entity 

 




PLL_TYPE 

PLL_TYPE 

Type 

Specifies a specific PLL implementation to target. 

Enumeration 

■ ATX 

■ CMU 

■ fPLL 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name PLL_TYPE -to -entity 

 




PLL_VCO_CLOCK_FREQUENCY 

PLL_VCO_CLOCK_FREQUENCY 

Type 

Specifies the voltage controlled oscillator (VCO) output clock frequency. 

Frequency 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name PLL_VCO_CLOCK_FREQUENCY -to -entity 

 




PRESERVE_PLL_COUNTER_ORDER 

PRESERVE_PLL_COUNTER_ORDER 

Type 

Preserves the order of PLL clock outputs used when selecting corresponding output 

counters. For example, a clk0 output uses a C0 counter and a clk2 output uses a C2 

counter. Turning this option can cause clock routing problems, as the clock router 

cannot rotate counters to resolve conflicts. 

Boolean 



■ Arria GX 



■ Cyclone 









■ Stratix 






Notes 


Syntax 

set_instance_assignment -name PRESERVE_PLL_COUNTER_ORDER -to -entity 

 




PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_ FRACTION_OF_USED_LAB_TILES 

PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_ 

FRACTION_OF_USED_LAB_TILES 

Type 

Sets an upper limit on the fraction of the LAB tiles used by your design that can be 

high-speed. Legal values must be between 0.0 and 1.0. The default value is 1.0. A 

value of 1.0 means that there is no restriction on the number of high-speed tiles, and 

the Fitter uses the minimum number needed to meet the timing requirements of your 

design. Specifying a value lower than 1.0 might degrade timing quality, because some 

timing critical resources might be forced into low-power mode. 

String 






■ Stratix V 

Notes 


Syntax 


PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 

Default Value 

1.0 




PROGRAMMABLE_POWER_TECHNOLOGY_SETTING 

PROGRAMMABLE_POWER_TECHNOLOGY_SETTING 

Type 

Controls how the Fitter configures tiles to operate in high-speed mode or low-power 

mode. Automatic specifies that the Fitter should try to minimize power without 

sacrificing timing performance. Minimize Power Only specifies that the Fitter should 

set the maximum number of tiles to operate in low-power mode. Force All Tiles with 

Failing Timing Paths to High Speed specifies that the Fitter should ensure that all 

paths that are failing timing are set to high-speed mode. For designs that meet timing, 

the behavior of this setting should be similar to the Automatic setting. For designs 

that fail timing, all paths with negative slack is put in high-speed mode. This does not 

likely increase the speed of the design. Although it may increase static power 

consumption, it may assist in determining which logic paths need to be re-designed in 

order to close timing. 

Enumeration 

■ Automatic 


■ Force All Tiles with Failing Timing Paths to High Speed 

■ Minimize Power Only 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING 

Default Value 

Force All Tiles with Failing Timing Paths to High Speed 




PROGRAMMABLE_PREEMPHASIS 


Type 

Implements control of programmable pre-emphasis, which helps compensate for high 

frequency losses. This option is ignored if it is applied to anything other than an 

output or bidirectional pin, or a top-level design entity containing output or 

bidirectional pins. 

This option specifies a pre-emphasis setting for the true differential output buffer of a 

pin. Since an input-only pin does not use true differential output buffer, this option is 


uses single-ended output buffer such as LVTTL. Some differential I/O standards are 

implemented with two single-ended output buffers and therefore this option cannot 

be supported. Please refer to the family data sheet for which I/O standards support 

programmable pre-emphasis. This option can only be supported on pin locations that 

support programmable pre-emphasis. Dedicated programming pins, such as TDO, 

do not support programmable pre-emphasis. 0 is the slowest pre-emphasis value. 

The higher the value the stronger the pre-emphasis. The highest pre-emphasis value is 

family dependent. A pin using this option should also use IO_STANDARD option. 

Integer 






■ Arria V 





■ Cyclone V 





■ Stratix V 

Notes 







Syntax 

set_global_assignment -name PROGRAMMABLE_PREEMPHASIS -entity 

 

set_instance_assignment -name PROGRAMMABLE_PREEMPHASIS -to -entity 

 

set_global_assignment -name PROGRAMMABLE_PREEMPHASIS 

Example 

set_instance_assignment -name PROGRAMMABLE_PREEMPHASIS 0 -to pin 

See Also 





PROGRAMMABLE_VOD 


Type 

Implements control of programmable VOD. This option is ignored if it is applied to 

anything other than an output or bidirectional pin, or a top-level design entity 

containing output or bidirectional pins. 

This option specifies a VOD setting for the true differential output buffer of a pin. 

Since an input-only pin does not use true differential output buffer, this option is 


uses single-ended output buffer such as LVTTL. Some differential I/O standards are 

implemented with two single-ended output buffers and therefore this option cannot 

be supported. Please refer to the family data sheet for which I/O standards support 

programmable VOD. This option can only be supported on pin locations that support 

programmable VOD. Dedicated programming pins, such as TDO, do not support 

programmable VOD. 0 is the slowest VOD value. The higher the value the higher the 

differential output voltage. The highest VOD value is family dependent. A pin using 

this option should also use IO_STANDARD option. 

Integer 






■ Arria V 


■ Cyclone V 





■ Stratix V 

Notes 



Syntax 

set_global_assignment -name PROGRAMMABLE_VOD -entity 

set_instance_assignment -name PROGRAMMABLE_VOD -to -entity 





set_global_assignment -name PROGRAMMABLE_VOD 

Example 

set_instance_assignment -name PROGRAMMABLE_PREEMPHASIS 0 -to pin 

See Also 





PR_DONE_OPEN_DRAIN 

PR_DONE_OPEN_DRAIN 

Type 

Specifies whether the Open-Drain feature on the PR_DONE pin should be enabled or 

not. 

Using this feature decouples the voltage level of the PR_DONE pin from V CCIO. 


Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name PR_DONE_OPEN_DRAIN 

Example 

set_global_assignment -name pr_done_open_drain on 

set_global_assignment -name pr_done_open_drain off 

Default Value 

On 

See Also 

■ “ENABLE_PR_PINS” on page 6–113 




PR_ERROR_OPEN_DRAIN 

PR_ERROR_OPEN_DRAIN 

Type 

Specifies whether the Open-Drain feature on the PR_ERROR pin should be enabled or 

not. 

Using this feature decouples the voltage level of the PR_ERROR pin from V CCIO. 


Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name PR_ERROR_OPEN_DRAIN 

Example 

set_global_assignment -name pr_error_open_drain on 

set_global_assignment -name pr_error_open_drain off 

Default Value 

On 

See Also 





PR_READY_OPEN_DRAIN 

PR_READY_OPEN_DRAIN 

Type 

Specifies whether the Open-Drain feature on the PR_READY pin should be enabled or 

not. 

Using this feature decouples the voltage level of the PR_READY pin from V CCIO. 


Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name PR_READY_OPEN_DRAIN 

Example 

set_global_assignment -name pr_ready_open_drain on 

set_global_assignment -name pr_ready_open_drain off 

Default Value 

On 

See Also 





QDR_D_PIN_GROUP 

QDR_D_PIN_GROUP 

Type 

Assigns a quad data rate (QDR) D (data) output pin group number to a specified pin. 

Turning on this option allows the Fitter to view pins as a QDR D output pin group. 

I/O pins of a QDR D output pin group must be placed in the DQ pin locations of a 

single DQS group. This option is ignored if is assigned to anything other than an I/O 

pin. 

Integer 




Notes 


Syntax 

set_instance_assignment -name QDR_D_PIN_GROUP -to -entity 




RESERVE_ALL_UNUSED_PINS 

RESERVE_ALL_UNUSED_PINS 

Type 

Reserves all unused pins on the target device in one of 5 states: as inputs that are tristated, 

as outputs that drive ground, as outputs that drive an unspecified signal, as 

input tri-stated with bus-hold, or as input tri-stated with weak pull-up. 

Enumeration 



■ As input tri-stated with bus-hold 

■ As input tri-stated with weak pull-up 




■ Arria GX 

■ Cyclone 




■ MAX V 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 




Syntax 

set_global_assignment -name RESERVE_ALL_UNUSED_PINS 

Default Value 

As output driving ground 

Old Names 


software: 

RESERVED_ALL_UNUSED_PINS 




RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP 

RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP 

Type 

Reserves all unused pins on the target device in one of 5 states: as inputs that are tristated, 

as outputs that drive ground, as outputs that drive an unspecified signal, as 

input tri-stated with bus-hold, or as input tri-stated with weak pull-up. 

Enumeration 



■ As input tri-stated with bus-hold 

■ As input tri-stated with weak pull-up 






■ Arria V 





■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP 

Default Value 

As input tri-stated with weak pull-up 




RESERVE_ASDO_AFTER_CONFIGURATION 

RESERVE_ASDO_AFTER_CONFIGURATION 

Type 

Specifies how the ASDO pin should be used when the device is operating in user 

mode after configuration is complete. Depending on the current device and 

configuration scheme, the ASDO pin can be reserved as a regular I/O pin, as an input 

that is tri-stated, as an output that drives ground, or as an output that drives an 

unspecified signal. If this pin is reserved as a regular I/O pin, the ASDO pin can be 

used as an ordinary I/O pin after configuration. 

Enumeration 





■ Arria GX 

■ Cyclone 





Syntax 

set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION 

Example 

set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS 

REGULAR IO" 

Old Names 


software: 

RESERVE_SDO_AFTER_CONFIGURATION 




RESERVE_DATA0_AFTER_CONFIGURATION 


Type 

Specifies how the Data[0] pin should be used when the device is operating in user 


configuration scheme, the Data[0] pin can be reserved as a regular I/O pin, as an 

input that is tri-stated, as an output that drives ground, as an output that drives an 

unspecified signal, or compiler configured. If the Data[0] pin is reserved as a regular 

I/O pin, the Data[0] pin can be used as an ordinary I/O pin after configuration. If the 

Data[0] pin is only used to interface with external memory for configuration, the 

Data[0] pin should be reserved as compiler configured. 

Enumeration 





■ Compiler configured 



■ Arria GX 









■ Stratix 






■ Stratix V 





Syntax 

set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION 

Example 

set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS 

REGULAR IO" 

Default Value 

As input tri-stated 




RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION 


Type 

Specifies how the Data[15..8] pins should be used when the device is operating in user 

mode after configuration is complete. 

Depending on the current device and configuration scheme, these pins can be 

reserved as regular I/O pins, as inputs that are tri-stated, as outputs that drive 

ground, or as outputs that drive an unspecified signal. If this pin is reserved as a 

regular I/O pin, the Data[15..8] pins can be used as ordinary I/O pins after 

configuration. 

Enumeration 







■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 


RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION 

Example 


RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "USE AS REGULAR IO" 

Default Value 

Use as regular IO 






Type 

Specifies how the Data[1]/ASDO pin should be used when the device is operating in 

user mode after configuration is complete. Depending on the current device and 

configuration scheme, this pin can be reserved as a regular I/O pin, as an input that is 

tri-stated, as an output that drives ground, as an output that drives an unspecified 

signal, or compiler configured. If the Data[1]/ASDO pin is reserved as a regular I/O 

pin, the Data[1]/ASDO pin can be used as an ordinary I/O pin after configuration. If 

the Data[1]/ASDO pin is only used to interface with external memory for 

configuration, the Data[1]/ASDO pin should be reserved as compiler configured. 

Enumeration 












Syntax 

set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION 

Example 

set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS 

REGULAR IO" 

Default Value 







Type 

Specifies how the Data[31..16] pins should be used when the device is operating in 

user mode after configuration is complete. 

Depending on the current device and configuration scheme, these pins can be 

reserved as regular I/O pins, as inputs that are tri-stated, as outputs that drive 

ground, or as outputs that drive an unspecified signal. If this pin is reserved as a 

regular I/O pin, the Data[31..16] pins can be used as ordinary I/O pins after 

configuration. 

Enumeration 







■ Stratix V 

Syntax 



Example 



Default Value 







Type 



configuration scheme, these pins can be reserved as regular I/O pins, as inputs that 

are tri-stated, as outputs that drive ground, or as outputs that drive an unspecified 

signal. If this pin is reserved as a regular I/O pin, the Data[7..1] pins can be used as 

ordinary I/O pins after configuration. 

Enumeration 







■ Arria GX 






■ Stratix 






■ Stratix V 

Syntax 



Example 







Default Value 







Type 




are tri-stated, as outputs that drive ground, as outputs that drive an unspecified 

signal, or compiler configured. If the Data[7..2] pins are reserved as a regular I/O 

pins, the Data[7..2] pins can be used as ordinary I/O pins after configuration. If 

Data[7..2] pins are only used to interface with external memory for configuration, the 

Data[7..2] pins should be reserved as compiler configured. 

Enumeration 












Syntax 



Example 



Default Value 







Type 




are tri-stated, as outputs that drive ground, as outputs that drive an unspecified 

signal. If the Data[7..5] pins are reserved as a regular I/O pins, the Data[7..5] pins can 

be used as ordinary I/O pins after configuration. 

Enumeration 







■ Arria V 

■ Cyclone V 

Syntax 



Example 



Default Value 





RESERVE_DCLK_AFTER_CONFIGURATION 

RESERVE_DCLK_AFTER_CONFIGURATION 

Type 

Specifies how the DCLK pin should be used when the device is operating in user 


configuration scheme, the DCLK pin can be reserved as a regular I/O pin, as a 

dedicated programming pin, or compiler configured. If this pin is reserved as a 

regular I/O pin, the DCLK pin can be used as an ordinary output pin after 

configuration. If the DCLK pin is only used to interface with external memory for 

configuration, the DCLK pin should be reserved as compiler configured. 

Enumeration 



■ Use as programming pin 







Syntax 

set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION 

Example 

set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS 

REGULAR IO" 

Default Value 

Use as programming pin 




RESERVE_FLASH_NCE_AFTER_CONFIGURATION 

RESERVE_FLASH_NCE_AFTER_CONFIGURATION 

Type 

Specifies how the FLASH_nCE/nCSO pin should be used when the device is 

operating in user mode after configuration is complete. Depending on the current 

device and configuration scheme, this pin can be reserved as a regular I/O pin, as an 

input that is tri-stated, as an output that drives ground, as an output that drives an 

unspecified signal, or compiler configured. If the FLASH_nCE/nCSO pin is reserved 

as a regular I/O pin, the FLASH_nCE/nCSO pin can be used as an ordinary I/O pin 

after configuration. If the FLASH_nCE/nCSO pin is only used to interface with 

external memory for configuration, the FLASH_nCE/nCSO pin should be reserved as 

compiler configured. 

Enumeration 












Syntax 

set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION 

Example 

set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS 

REGULAR IO" 

Default Value 





RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION 

RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION 

Type 

Specifies how the nWS, nRS, nCS, and CS pins should be used when the device is 

operating in user mode after configuration is complete. Depending on the current 

device and configuration scheme, these pins can be reserved as regular I/O pins, as 

inputs that are tri-stated, as outputs that drive ground, or as outputs that drive an 

unspecified signal. If this pin is reserved as a regular I/O pin, the nWS, nRS, nCS, and 

CS pins can be used as ordinary I/O pins after configuration. 

Enumeration 







■ Arria GX 


■ Stratix 




Syntax 

set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION 

 

Default Value 





RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION 

RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION 

Type 

Specifies how the Data[15..8], PADD[23..0], NRESET, NAVD, NOE and NWE pins 

should be used when the device is operating in user mode after configuration is 

complete. Depending on the current device and configuration scheme, these pins can 

be reserved as regular I/O pins, as inputs that are tri-stated, as outputs that drive 

ground, as outputs that drive an unspecified signal, or compiler configured. If these 

pins are reserved as regular I/O pins, they can be used as ordinary I/O pins after 

configuration. If these pins are only used to interface with external memory for 

configuration, these pins should be reserved as compiler configured. 

Enumeration 










Syntax 

set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION 

 

Example 

set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "USE 

AS REGULAR IO" 

Default Value 


Old Names 


software: 

RESERVE_OTHER_APF_PINS_AFTER_CONFIGURATION 




RESERVE_RDYNBUSY_AFTER_CONFIGURATION 

RESERVE_RDYNBUSY_AFTER_CONFIGURATION 

Type 

Specifies how the RDYnBUSY pin should be used when the device is operating in user 


configuration scheme, the RDYnBUSY pin can be reserved as a regular I/O pin, as an 

input that is tri-stated, as an output that drives ground, or as an output that drives an 

unspecified signal. If this pin is reserved as a regular I/O pin, the RDYnBUSY pin can 

be used as an ordinary I/O pin after configuration. 

Enumeration 







■ Arria GX 


■ Stratix 




Syntax 

set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION 

Default Value 





ROUTER_CLOCKING_TOPOLOGY_ANALYSIS 

ROUTER_CLOCKING_TOPOLOGY_ANALYSIS 

Type 

Directs the router to perform an analysis of the design's clocking topology and adjust 

the optimization approach on paths with significant clock skew. Enabling this option 

may improve hold timing at the cost of increased compile time. 

Boolean 





■ Arria V 





■ Cyclone V 



■ Stratix V 

Notes 


devices. 


Syntax 

set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS 

Default Value 

Off 




ROUTER_EFFORT_MULTIPLIER 


Type 

Controls how quickly the router tries to find a valid solution. The default value is 1.0 

and legal values must be greater than or equal to 0.25. Values higher than 1.0 may 

improve routing quality at the expense of run-time on difficult-to-route circuits. 

Values lower than 1.0 can reduce router run-time, but usually reduces routing quality 

slightly. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 

■ EPC1 

■ EPC2 


■ FLEX10KB 

■ FLEX8000 


■ MAX V 

■ MAX9000 

■ Stratix 










■ Stratix V 

Notes 


devices. 


Syntax 

set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 

Default Value 

1.0 




ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION 


Type 

Allows the Fitter to automatically insert buffer logic cells between two nodes without 

altering the functionality of the design. Buffer logic cells are created from unused logic 

cells in the device. This option also allows the Fitter to duplicate a logic cell within a 

LAB when there are unused logic cells available in a LAB. Using this option can 

increase compilation time. The default setting of Auto allows these operations to run 

when the design requires them to fit the design, or the performance of the design can 

be improved by this optimization with a nominal compilation time increase. 

Enumeration 

■ Auto 

■ Off 

■ On 



■ Arria GX 



■ Arria V 

■ Cyclone 





■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION 

 

Default Value 

Auto 




ROUTER_REGISTER_DUPLICATION 


Type 

Allows the Fitter to automatically duplicate registers within a LAB containing empty 

logic cells. This option does not alter the functionality of the design. The Auto 

Register Duplication option is also ignored if you select OFF as the setting for the 

Logic Cell Insertion -- Logic Duplication logic option. Turning on this option can 

allow the Logic Cell Insertion -- Logic Duplication logic option to improve a design's 

routability, but can make formal verification of a design more difficult. 

Enumeration 

■ Auto 

■ Off 

■ On 



■ Arria GX 



■ Arria V 

■ Cyclone 





■ Cyclone V 





■ MAX V 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name ROUTER_REGISTER_DUPLICATION 

Default Value 

Auto 




ROUTER_TIMING_OPTIMIZATION_LEVEL 


Type 

Controls how aggressively the router tries to meet timing requirements. Setting this 

option to Maximum can increase design speed slightly, at the cost of increased 

compile time. Setting this option to Minimum can reduce compile time, at the cost of 

slightly reduced design speed. The default value is Normal. 

Enumeration 

■ Maximum 

■ Minimum 

■ Normal 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 

■ EPC1 

■ EPC2 


■ FLEX10KB 

■ FLEX8000 


■ MAX V 

■ MAX9000 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL 

Default Value 

Normal 




ROUTING_BACK_ANNOTATION_MODE 

ROUTING_BACK_ANNOTATION_MODE 

Type 

If this option is turned on, that is, Normal, it allows the router to read routing 

constraints for the design from a Routing Constraints File (.rcf). 

Enumeration 

■ Advanced 

■ Normal 

■ Off 



Notes 


devices. 

Syntax 

set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE 




SCE_PIN 

SCE_PIN 

Type 

Specifies the SCE configuration pin. 

Boolean 







Notes 


Syntax 

set_instance_assignment -name SCE_PIN -to 




SDO_PIN 

SDO_PIN 

Type 

Specifies the SDO configuration pin. 

Boolean 







Notes 


Syntax 

set_instance_assignment -name SDO_PIN -to 




SEED 

SEED 

Type 

Specifies the starting value the Fitter uses when randomly determining the initial 

placement for the current design. The value can be any non-negative integer value. 

Changing the starting value may or may not produce better fitting. Specify a starting 

value only if the Fitter is not meeting timing requirements by a small amount. The 

Design Space Explorer tool lets you sweep many seed values easily to find the best 

value for a given project. Modifying the design or the Quartus II software settings 

even slightly usually changes which seed is best for the design. 

Integer 



Notes 


devices. 


Syntax 

set_global_assignment -name SEED 

Default Value 

1 

Old Names 


software: 

INITIAL_PLACEMENT_CONFIGURATION 




SLEW_RATE 

SLEW_RATE 

Type 

Implements control of low-to-high/high-to-low transitions on output pins to help 

reduce switching noise. When a large number of output pins switch simultaneously, 

pins that use the lower Slew Rate option help reduce switching noise. This option is 

ignored if it is applied to anything other than an output or bidirectional pin, or a toplevel 

design entity containing output or bidirectional pins. Note that using this option 

may increase the delay for output or bidir pins, which can affect slack on t CO paths for 

the pins this is applied to. 

This option specifies a slew rate setting for the single-ended output buffer of a pin. 

Since an input-only pin does not use single-ended output buffer, this option is ignored 

on such pin. This option is not supported on a pin with I/O standard which uses true 

differential output buffer such as LVDS. Some differential I/O standards are 

implemented with two single-ended output buffers and therefore this option may be 

supported. Please refer to the family data sheet for which I/O standards support 

programmable slew rate. This option can only be supported on pin locations that 

support programmable slew rate. Dedicated programming pins, such as TDO, do not 

support programmable slew rate. Please refer to the family data sheet for which 

current strength and output termination settings support programmable slew rate. 

Output termination with Calibration usually requires highest slew rate setting. 0 is 

the slowest slew rate value. The higher the value the faster the slew rate. The highest 

slew rate value is family dependent. A pin using this option should also use 

IO_STANDARD option. 

Integer 






■ Arria V 





■ Cyclone V 








SLEW_RATE 

■ Stratix V 

Notes 



Syntax 

set_global_assignment -name SLEW_RATE -entity 

set_instance_assignment -name SLEW_RATE -to -entity 

 

set_global_assignment -name SLEW_RATE 

Example 

set_instance_assignment -name SLEW_RATE 0 -to pin 

See Also 


■ “CURRENT_STRENGTH_NEW” on page 6–43 





SLOW_SLEW_RATE 


Type 

Implements slow low-to-high or high-to-low transitions on output pins to help reduce 

switching noise. When a large number of output pins switch simultaneously, pins that 

use the Slow Slew Rate option help reduce switching noise. This option is ignored if 

it is applied to anything other than an output or bidirectional pin, or a top-level 

design entity containing output or bidirectional pins. Note that using this option 

increases the delay for output or bidir pins, which can affect slack on t CO paths for the 

pins to which you apply this option. 

Boolean 



■ Cyclone 

■ EPC1 

■ EPC2 


■ FLEX10KB 

■ FLEX8000 


■ MAX V 

■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

■ MAX9000 

■ Stratix 


Notes 



Syntax 

set_global_assignment -name SLOW_SLEW_RATE -entity 

set_instance_assignment -name SLOW_SLEW_RATE -to -entity 





set_global_assignment -name SLOW_SLEW_RATE 

Default Value 

Off 




STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET 

STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET 

Type 

Allows the Compiler to enable netlist placements and routing where the dedicated 

reference clock pad in a quad, that has a gigabit transceiver block Transmitter PLL 

with its pll_reset or pllenable signal connected or has only Receivers which have 

their rxanalogreset signals connected, to feed other quads or core logic. Also allows 

the Compiler to enable netlist placements where a gigabit transceiver block 

Transmitter PLL exists in a quad that has only receivers which have their 

rxanalogreset signals connected. 

Boolean 




Syntax 

set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET 

 

Default Value 

Off 




STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE 

STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE 

Type 

Enables the double data width (channel widths of 16 and 20) GIGE mode operation of 

gigabit transceiver block Receiver and Transmitter channels. 

Boolean 




Syntax 

set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE 

 

Default Value 

Off 




STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE 

STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE 

Type 

Enables GIGE configurations of gigabit transceiver block Receiver and Transmitter 

channels to operate at other data rates than 1.25 Gbps. 

Boolean 




Syntax 

set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE 

 

Default Value 

Off 




STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B 

STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B 

Type 

Enables GIGE configurations of gigabit transceiver block Receiver and Transmitter 

channels where the 8B10B decoder and encoder are not used 

Boolean 




Syntax 

set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B 

Default Value 

Off 




STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER 

STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCH 

ER 

Type 

Enables GIGE configurations of gigabit transceiver block Receiver channels with the 

coreclk selected at the rate matching FIFO. 

Boolean 




Syntax 


STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER 

Default Value 

Off 




STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE 

STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOU 

RCE 

Type 

Allows GIGE configurations of gigabit transceiver block Receiver channels where the 

coreclk input is fed from another source than the gigabit transceiver block Transmitter 

PLL in the same quad. 

Boolean 




Syntax 


STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE 

Default Value 

Off 




STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE 

STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_M 

ODE 

Type 

Enables the double data width (channel widths of 16 and 20) parallel loopback mode 

operation of gigabit transceiver block Receiver and Transmitter channels. 

Boolean 




Syntax 


STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE 

Default Value 

Off 




STRATIXGX_ALLOW_POST8B10B_LOOPBACK 

STRATIXGX_ALLOW_POST8B10B_LOOPBACK 

Type 

Allows Post 8B10B parallel loopback configurations of gigabit transceiver block 

Receiver and Transmitter channels. 

Boolean 




Syntax 

set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK 

Default Value 

Off 




STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK 

STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK 

Type 

Allows reverse parallel loopback configurations of gigabit transceiver block Receiver 

and Transmitter channels. 

Boolean 




Syntax 

set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK 

 

Default Value 

Off 




STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_ SOURCE_IN_DOUBLE_DATA_WIDTH_MODE 

STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_ 

SOURCE_IN_DOUBLE_DATA_WIDTH_MODE 

Type 

Enables the gigabit transceiver block Receiver coreclk input to be sourced from a 

different signal than the clkout output from the same gigabit transceiver block 

Receiver channel, while in double data width mode (channel widths of 16 or 20). 

Boolean 




Syntax 


STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_ 

MODE 

Default Value 

Off 




STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS 

STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS 

Type 

Directs the Compiler to allow the use of I/O pins that couple onto the gigabit 

transceiver block I/O banks. 

Boolean 




Syntax 

set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS 

Default Value 

Off 




STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE 

STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE 

Type 

Enables single data width (channel width of 8) XAUI mode operation of gigabit 

transceiver block Receiver and Transmitter channels 

Boolean 




Syntax 

set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE 

 

Default Value 

Off 




STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER 

STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCH 

ER 

Type 

Enables XAUI configurations of gigabit transceiver block Receiver channels with the 

coreclk selected at the rate matching FIFO. 

Boolean 




Syntax 


STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER 

Default Value 

Off 




STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE 

STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOU 

RCE 

Type 

Allows XAUI configurations of gigabit transceiver block Receiver channels where the 

coreclk input is fed from another source than the gigabit transceiver block 

Transmitter PLL in the same quad. 

Boolean 




Syntax 


STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE 

Default Value 

Off 




STRATIXGX_TERMINATION_VALUE 

STRATIXGX_TERMINATION_VALUE 

Type 

Allows the Compiler to configure the on-chip termination (OCT) for a Stratix GX 

gigabit transceiver block receiver channel input pin, gigabit transceiver block 

transmitter channel output pin, gigabit transceiver block transmitter PLL clock input 

pin, or gigabit transceiver block receiver channel clock input pin. 

Enumeration 




■ Off 




Notes 


Syntax 

set_instance_assignment -name STRATIXGX_TERMINATION_VALUE -to -entity 

 




STRATIXIIGX_TERMINATION_VALUE 

STRATIXIIGX_TERMINATION_VALUE 

Type 

Allows the Compiler to configure the on-chip termination (OCT) for a Stratix II GX 

gigabit transceiver block receiver channel input pin or gigabit transceiver block 

transmitter channel output pin. 

Enumeration 




■ Off 



■ Arria GX 


Notes 


Syntax 

set_instance_assignment -name STRATIXIIGX_TERMINATION_VALUE -to - 

entity 




STRATIXIII_CONFIGURATION_SCHEME 

STRATIXIII_CONFIGURATION_SCHEME 

Type 

The method used to load data into the device. Three configuration schemes are 

available: Passive Serial (PS); Fast Passive Parallel (FPP) and Active Serial (AS). 

Enumeration 



■ Fast Passive Parallel 









Syntax 

set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME 

Example 

set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Active 

Serial" 

Default Value 

Passive Serial 

Old Names 


software: 

STRATIXIV_CONFIGURATION_SCHEME 




STRATIXIII_MRAM_COMPATIBILITY 

STRATIXIII_MRAM_COMPATIBILITY 

Type 

Directs the Quartus II software to produce programming files that are compatible 

with all silicon revisions. Refer to the Stratix III Device Handbook for more details. 

Boolean 




Notes 


Syntax 

set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY 

Default Value 

On 




STRATIXIII_UPDATE_MODE 

STRATIXIII_UPDATE_MODE 

Type 

Specifies the configuration mode used with the configuration scheme for configuring 

the device. 

Enumeration 

■ Remote 

■ Standard 





■ Arria V 









■ Stratix V 

Syntax 

set_global_assignment -name STRATIXIII_UPDATE_MODE 

Example 

set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE 

Default Value 

Standard 




STRATIXII_CONFIGURATION_SCHEME 

STRATIXII_CONFIGURATION_SCHEME 

Type 

The method used to load data into the device. Four configuration schemes are 

available: Passive Parallel Asynchronous (PPA); Passive Serial (PS); Fast Passive 

Parallel (FPP) and Active Serial (AS). 

Enumeration 




■ Passive Parallel Asynchronous 



■ Arria GX 




Syntax 

set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME 

Default Value 


Old Names 


software: 

STRATIX_II_CONFIGURATION_SCHEME 




STRATIXII_TERMINATION 

STRATIXII_TERMINATION 

Type 




Enumeration 

■ Differential 

■ Off 


■ Parallel 50 Ohms with Calibration 

■ Series 25 Ohms with Calibration 

■ Series 25 Ohms without Calibration 

■ Series 50 Ohms with Calibration 

■ Series 50 Ohms without Calibration 


■ Arria GX 




Notes 


Syntax 

set_instance_assignment -name STRATIXII_TERMINATION -to -entity 

 

Old Names 


software: 

Termination -- Stratix II/Stratix II GX/HardCopy II 




STRATIXV_CONFIGURATION_SCHEME 

STRATIXV_CONFIGURATION_SCHEME 

Type 

The method used to configure a device with a design. Up to six configuration schemes 

are available, depending on the selected device: Passive Serial (PS), Passive Parallel x8 

(PPx8), Passive Parallel ×16 (PP×16), Passive Parallel ×32 (PP×32), Active Serial ×1 

(AS×1) and Active Serial ×4 (AS×4). 

Enumeration 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Syntax 

set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME 

Example 

set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial" 

Default Value 





STRATIX_CONFIGURATION_SCHEME 

STRATIX_CONFIGURATION_SCHEME 

Type 

The method used to load data into the device. Three configuration schemes are 

available: Passive Parallel Asynchronous (PPA); Passive Serial (PS); and Fast Passive 

Parallel (FPP). 

Enumeration 



■ Passive Parallel Asynchronous 




■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name STRATIX_CONFIGURATION_SCHEME 

Default Value 





STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS 

STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS 

Type 

Decreases the propagation delay from an input or bidirectional pin to logic and 

embedded cells within the device. This is an advanced option that should be used 



to the data sheet for the device family. This option is ignored if it is applied to 

anything other than an input or bidirectional pin. 

Enumeration 

■ Large 

■ Medium 

■ Off 

■ On 

■ Small 



■ Cyclone 

■ Stratix 


Notes 


Syntax 


STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS -to -entity 


STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS -from -to - 

entity 

Old Names 


software: 

Decrease Input Delay to Internal Cells -- Stratix/Stratix GX/Cyclone 

YEAGER_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS 




STRATIX_DEVICE_IO_STANDARD 


Type 

Specifies the default I/O standard to be used for pins on the target device. This option 

is ignored on a pin with IO_STANDARD assignment. This option is also ignored if 

the netlist disagrees with the option. You should specify the IO_STANARD 

assignment for all pins in the design. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Notes 







Syntax 

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD 

Example 

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.2 V" 

Old Names 


software: 

YEAGER_DEVICE_IO_STANDARD 

See Also 





STRATIX_UPDATE_MODE 

STRATIX_UPDATE_MODE 

Type 

Specifies the configuration mode used with the configuration scheme for configuring 

the device. 

Enumeration 

■ Local 

■ Remote 

■ Standard 



■ Arria GX 


■ Stratix 




Syntax 

set_global_assignment -name STRATIX_UPDATE_MODE 

Default Value 

Standard 

Old Names 


software: 

YEAGER_UPDATE_MODE 




SYNCHRONIZER_IDENTIFICATION 


Type 

Specifies how the TimeQuest timing analyzer identifies registers as being part of a 

synchronization register chain for metastability analysis. A synchronization register 

chain is a sequence of registers with the same clock with no fan-out in between, which 

is driven by a pin or logic from another clock domain. If you set this option to Off, the 

TimeQuest analyzer does not identify the specified registers, or the registers in the 

specified entity, as synchronization registers. If you set the option to Auto, the 

TimeQuest analyzer identifies valid synchronization registers that are part of a chain 

with more than one register that contains no combinational logic. If you set this option 

to Forced if Asynchronous, the TimeQuest analyzer identifies synchronization 

register chains if the software detects an asynchronous signal transfer, even if there is 

combinational logic or only one register in the chain. If you set this option to Forced, 

then the specified register, or all registers within the specified entity, are identified as 

synchronizers. You should not apply the Forced option to the entire design, because 

doing so identifies all registers in the design as synchronizers. Registers that are 

identified as synchronizers are optimized for improved Mean Time Between Failure 

(MTBF) as long as the Optimize Design for the Metastability option is turned on. If a 

synchronization register chain is identified with the Forced or Forced if 

Asynchronous option, then the TimeQuest analyzer reports the metastability MTBF 

for the chain. MTBF is not reported for automatically-detected register chains; you can 

use the Auto setting to generate a report of possible synchronization chains in your 

design. If a synchronization register chain is identified with the Forced or Forced if 

Asynchronous option, then the TimeQuest analyzer reports the metastability MTBF 

for the chain when it meets the design timing requirements. 

Enumeration 

■ Auto 

■ Forced 

■ Forced If Asynchronous 

■ Off 





■ Arria V 





■ Cyclone V 









■ Stratix V 

Notes 



Syntax 

set_global_assignment -name SYNCHRONIZER_IDENTIFICATION 

set_global_assignment -name SYNCHRONIZER_IDENTIFICATION -entity 

set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION -to -entity 

 

Default Value 

Off 

Old Names 


software: 

ANALYZE_METASTABILITY 




SYNCHRONIZER_TOGGLE_RATE 

SYNCHRONIZER_TOGGLE_RATE 

Type 

Specifies the toggle rate of this register. The units for this value are in transitions per 

second, and must be positive. This is used when calculating the Mean Time Between 

Failures (MTBF) of a synchronizer chain in the Metastability Report. This only applies 

when the TimeQuest analyzer is used. You can specify the desired frequency setting 

on the first register of a synchronizer chain, and this will determine the data rate used 

in the MTBF estimation. There are two other assignments associated with toggle 

rates. The I/O Maximum Toggle Rate is only used for pins, and specifies the worstcase 

toggle rates used for signal integrity purposes. The Power Toggle Rate 

assignment is used to specify the expected time-averaged toggle rate, and is used by 

the Power Analyzer to estimate time-averaged power consumption. 

Integer 



Notes 


Syntax 

set_instance_assignment -name SYNCHRONIZER_TOGGLE_RATE -to -entity 

 




T11_0_DELAY 

T11_0_DELAY 

Type 

Specifies the propagation delay for the gated T11 delay cell. Use this advanced option 


the timing is unsatisfactory. For more information about using this advanced option, 

refer to the data sheet for the targeted device family. The software ignores this option 

if you apply the option to other pins other than an input or bidirectional pin. 

Integer 



■ Arria V 

■ Cyclone V 

Notes 


Syntax 

set_instance_assignment -name T11_0_DELAY -to -entity 

 




T11_1_DELAY 

T11_1_DELAY 

Type 

Specifies the propagation delay for the ungated T11 delay cell. Use this advanced 

option only after you have compiled a project, checked the I/O timing, and 

determined that the timing is unsatisfactory. For more information about using this 

option, refer to the data sheet for the device family. The software ignores this option if 

you apply this option to any pins other than an input or bidirectional pin. 

Integer 



■ Arria V 

■ Cyclone V 

Notes 


Syntax 

set_instance_assignment -name T11_1_DELAY -to -entity 

 




T11_DELAY 

T11_DELAY 

Type 

Specifies the propagation delay for T11 Delay Cell. This is an advanced option that 





Integer 








■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name T11_DELAY -to -entity 

 






Type 

Enable the fine delay resolution on T11 Delay (DQS post-amble delay cell). 

Boolean 



Notes 


Syntax 

set_instance_assignment -name T11_FINE_DELAY -to -entity 




T4_DELAY 

T4_DELAY 

Type 

Specifies the propagation delay for T4 Delay Cell (output register to switch mux). This 

is an advanced option that should be used only after you have compiled a project, 

checked the I/O timing, and determined that the timing is unsatisfactory. For detailed 

information on how to use this option, refer to the data sheet for the device family. 

This option is ignored if it is applied to anything other than an input or bidirectional 

pin. 

Integer 








■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name T4_DELAY -to -entity 

 




T8_DELAY0 

T8_DELAY0 

Type 






Integer 








■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name T8_DELAY0 -to -entity 

 




T8_DELAY1 

T8_DELAY1 

Type 






Integer 








■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name T8_DELAY1 -to -entity 

 




TERMINATION 

TERMINATION 

Type 




Enumeration 

■ Differential 

■ Off 



■ Stratix 


Notes 


Syntax 

set_instance_assignment -name TERMINATION -to -entity 

Old Names 


software: 

Termination -- Stratix / Stratix GX / HardCopy Stratix / Mercury 

YEAGER_OCT_AND_IMPEDANCE_MATCHING 




TERMINATION_CONTROL_BLOCK 

TERMINATION_CONTROL_BLOCK 

Type 

Specifies the control block used for calibrated on-chip termination (OCT) and 

impedance matching for an I/O pin. OCT helps to prevent signal reflections and 

maintain signal integrity. This option is ignored if it is applied to anything other than 

an I/O pad, input buffer, or output buffer. This option should only be used on I/O 

pins which have a calibrated termination assignment. 

String 





■ Arria V 

■ Cyclone V 





■ Stratix V 

Notes 





Syntax 

set_instance_assignment -name TERMINATION_CONTROL_BLOCK -to -entity 

 

Example 

set_instance_assignment -name TERMINATION_CONTROL_BLOCK 

"my_oct:inst|my_oct_alt_oct_toq:my_oct_alt_oct_toq_component|sd1a_0" -to 

pin_name 

See Also 





TREAT_BIDIR_AS_OUTPUT 


Type 

Directs the bidirectional pin to be essentially treated as an output pin meaning that 

the input path is used for feedback from the output path. This option is a modifier of 

IO_STANDARD option with Differential HSTL/SSTL I/O standard setting. The 

Quartus II software implements a legality check that requires differental HSTL/SSTL 

bi-directional pin connecting to a differential input buffer. This option disables this 

legality check if the output enable of the two single-ended output buffers of the pins 

are set to V CC. 

Boolean 





■ Arria V 





■ Cyclone V 





■ Stratix V 

Notes 



Syntax 

set_global_assignment -name TREAT_BIDIR_AS_OUTPUT 

set_global_assignment -name TREAT_BIDIR_AS_OUTPUT -entity 

 

set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT -to -entity 

 





Example 

set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT ON -to bidir_pin 

Default Value 

Off 

See Also 





TRI_STATE_SPI_PINS 

TRI_STATE_SPI_PINS 

Type 

This option controls Active Configuration Controller to tri-state the Active 

Configuration pins in user mode. This option is ignored if the selected configuration 

scheme is not an Active Configuration scheme. 

Boolean 





■ Arria V 









■ Stratix V 

Notes 


Syntax 

set_global_assignment -name TRI_STATE_SPI_PINS 

Default Value 

Off 




TXPMA_SLEW_RATE 

TXPMA_SLEW_RATE 

Type 

Overwrites TX PMA slew rate to 4 options: Off, Low, Medium, High. 

Enumeration 

■ High 

■ Low 

■ Medium 

■ Off 





Syntax 

set_global_assignment -name TXPMA_SLEW_RATE 

set_instance_assignment -name TXPMA_SLEW_RATE -to 

Default Value 

Low 




UNUSED_TSD_PINS_GND 

UNUSED_TSD_PINS_GND 

Type 

If this option is turned on, unused temperature sensing diode (TSD) pins, 

TEMPDIODEp/TEMPDIODEn, on the device are automatically set to GND in the 

Pin-Out File (.pin) file. By default, the TSD pins are available for connection to an 

external temperature sensing device; however, you must manually connect the pins to 

GND if they are not connected. Turning on this option only updates the information 

in the .pin file, it does not affect FPGA behavior. 

Boolean 




■ Stratix V 

Syntax 

set_global_assignment -name UNUSED_TSD_PINS_GND 

Default Value 

Off 




USER_START_UP_CLOCK 


Type 

Directs the device to use a user-supplied clock on the CLKUSR pin for initialization. You 

can select which clock source to use for initialization, either the internal oscillator or 

external clocks provided on the CLKUSR pin. This clock can synchronize the 

initialization of multiple devices. The default setting is to make CLKUSR pin available 


Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 




■ Stratix 






■ Stratix V 

Syntax 

set_global_assignment -name USER_START_UP_CLOCK 





Example 

set_global_assignment -name USER_START_UP_CLOCK ON 

set_global_assignment -name USER_START_UP_CLOCK OFF 

Default Value 

Off 

Old Names 


software: 

User Specified Start-up clock 

See Also 

■ “ACTIVE_SERIAL_CLOCK” on page 6–1 




VCCIO_CURRENT_1PT8V 


Type 

Overrides VCCIO current of 1.8-V I/O standard. The original current is 2 mA. 

Integer 



Syntax 

set_global_assignment -name VCCIO_CURRENT_1PT8V 






Type 

Overrides VCCIO current of 2.5-V I/O standard. The original current is 2 mA. 

Integer 



Syntax 

set_global_assignment -name VCCIO_CURRENT_2PT5V 




VCCIO_CURRENT_GTL 

VCCIO_CURRENT_GTL 

Type 

Overrides VCCIO current of GTL I/O standard. Not supported in MAX7000. 

Integer 



Syntax 

set_global_assignment -name VCCIO_CURRENT_GTL 




VCCIO_CURRENT_GTL_PLUS 

VCCIO_CURRENT_GTL_PLUS 

Type 

Overrides VCCIO current of GTL+ I/O standard. The original current is 0 mA. 

Integer 



Syntax 

set_global_assignment -name VCCIO_CURRENT_GTL_PLUS 

Fitter Assignments 




VCCIO_CURRENT_LVCMOS 

VCCIO_CURRENT_LVCMOS 

Type 

Overrides VCCIO current of LVCMOS I/O standard. The original current is 2 mA. 

Integer 



Syntax 

set_global_assignment -name VCCIO_CURRENT_LVCMOS 




VCCIO_CURRENT_LVTTL 

VCCIO_CURRENT_LVTTL 

Type 

Overrides VCCIO current of LVTTL I/O standard. The original current is 4 mA. 

Integer 



Syntax 

set_global_assignment -name VCCIO_CURRENT_LVTTL 




VCCIO_CURRENT_PCI 

VCCIO_CURRENT_PCI 

Type 

Overrides VCCIO current of PCI I/O standard. The original current is 4 mA. 

Integer 



Syntax 

set_global_assignment -name VCCIO_CURRENT_PCI 




VCCIO_CURRENT_SSTL2_CLASS1 


Type 

Overrides VCCIO current of SSTL2_CLASS1 I/O standard. The original current is 14 

mA. 

Integer 



Syntax 

set_global_assignment -name VCCIO_CURRENT_SSTL2_CLASS1 






Type 


mA. 

Integer 



Syntax 







Type 

Overrides VCCIO currentof SSTL3_CLASS1 I/O standard. The original current is 18 

mA. 

Integer 



Syntax 







Type 


mA. 

Integer 



Syntax 





VCCPD_VOLTAGE 

VCCPD_VOLTAGE 

Type 

Specifies the default I/O Bank VCCPD voltage to be used for pins on the target device. 

String 



■ Arria GX 




Syntax 

set_global_assignment -name VCCPD_VOLTAGE -section_id 

 

Default Value 

3.3 V, requires section identifier 




WEAK_PULL_UP_RESISTOR 


Type 

Enables the weak pull-up resistor when the device is operating in user mode. This 

option pulls a high-impedance bus signal to VCC. The Weak Pull-Up Resistor option 

should not be used at the same time as the Enable Bus-Hold Circuitry option. This 

option is ignored if it is applied to anything other than a pin. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Notes 



Syntax 

set_global_assignment -name WEAK_PULL_UP_RESISTOR 

set_global_assignment -name WEAK_PULL_UP_RESISTOR -entity 

 

set_instance_assignment -name WEAK_PULL_UP_RESISTOR -to -entity 

 

Example 

set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to pin 

Default Value 

Off 




XCVR_ANALOG_SETTINGS_PROTOCOL 


Type 

Specify protocol and its variant that are used to determine electrical analog settings 

for the transceiver. 

Enumeration 

■ BASIC 

■ CEI 

■ CPRI 

■ GIGE 

■ INTERLAKEN 

■ PCIE_GEN1 

■ PCIE_GEN2 

■ PCIE_GEN3 

■ QPI 

■ SATA1_I 

■ SATA1_M 

■ SATA1_X 

■ SATA2_I 

■ SATA2_M 

■ SATA2_X 

■ SFIS 

■ SONET 

■ SRIO 

■ TENG_BASER 

■ TENG_SDI 

■ XAUI 



■ Stratix V 

Notes 






Syntax 

set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL -to - 

entity 

Old Names 


software: 

HSSI_ANALOG_SETTINGS_PROTOCOL 




XCVR_GT_IO_PIN_TERMINATION 

XCVR_GT_IO_PIN_TERMINATION 

Type 

Allows the Compiler to configure the GT transceiver termination value. 

Integer 




■ Stratix V 

Note 


Syntax 

set_instance_assignment -name XCVR_GT_IO_PIN_TERMINATION -to -entity 

 




XCVR_GT_RX_COMMON_MODE_VOLTAGE 

XCVR_GT_RX_COMMON_MODE_VOLTAGE 

Type 

Specifies the GT receiver buffer common-mode voltage. 

Enumeration 

■ VTT_0P35V 

■ VTT_0P50V 

■ VTT_0P55V 

■ VTT_0P60V 

■ VTT_0P65V 

■ VTT_0P70V 

■ VTT_0P75V 

■ VTT_0P80V 


■ VTT_VCMOFF0 









■ Stratix V 

Note 


Syntax 

set_instance_assignment -name XCVR_GT_RX_COMMON_MODE_VOLTAGE -to - 

entity 




XCVR_GT_RX_CTLE 

XCVR_GT_RX_CTLE 

Type 

Specifies the static control for the continuous time equalizer in the receiver buffer. 

Integer 




■ Stratix V 

Note 


Syntax 

set_instance_assignment -name XCVR_GT_RX_CTLE -to -entity 




XCVR_GT_RX_DC_GAIN 

XCVR_GT_RX_DC_GAIN 

Type 

Controls the amount of the receiver buffer DC gain at a stage. 

Integer 




■ Stratix V 

Note 


Syntax 

set_instance_assignment -name XCVR_GT_RX_DC_GAIN -to -entity 




XCVR_GT_TX_COMMON_MODE_VOLTAGE 

XCVR_GT_TX_COMMON_MODE_VOLTAGE 

Type 

Specifies the GT transmitter common-mode driver voltage. 

Enumeration 

■ GROUNDED 

■ PULL_DN 

■ PULL_UP 


■ PULL_UP_TO_VCCELA 

■ TRISTATED1 




■ VOLT_0P35V 






■ VOLT_0P75V, 



■ Stratix V 

Note 


Syntax 

set_instance_assignment -name XCVR_GT_TX_COMMON_MODE_VOLTAGE -to - 

entity 




XCVR_GT_TX_PRE_EMP_1ST_POST_TAP 

XCVR_GT_TX_PRE_EMP_1ST_POST_TAP 

Type 

Specifies the GT transmitter preemphasis first post-tap setting value. 

Integer 




■ Stratix V 

Note 


Syntax 

set_instance_assignment -name XCVR_GT_TX_PRE_EMP_1ST_POST_TAP -to - 

entity 




XCVR_GT_TX_PRE_EMP_INV_PRE_TAP 

XCVR_GT_TX_PRE_EMP_INV_PRE_TAP 

Type 

Inverts the GT transmitter preemphasis pre-tap setting value. 

Boolean 



■ Stratix V 

Note 


Syntax 

set_instance_assignment -name XCVR_GT_TX_PRE_EMP_INV_PRE_TAP -to - 

entity 




XCVR_GT_TX_PRE_EMP_PRE_TAP 

XCVR_GT_TX_PRE_EMP_PRE_TAP 

Type 

Specifies the GT transmitter preemphasis pre-tap setting value. 

Integer 




■ Stratix V 

Note 


Syntax 

set_instance_assignment -name XCVR_GT_TX_PRE_EMP_PRE_TAP -to -entity 

 




XCVR_GT_TX_VOD_MAIN_TAP 

XCVR_GT_TX_VOD_MAIN_TAP 

Type 

Specifies the GT differential output voltage setting. 

Integer 




■ Stratix V 

Note 


Syntax 

set_instance_assignment -name XCVR_GT_TX_VOD_MAIN_TAP -to -entity 

 




XCVR_IO_PIN_TERMINATION 

XCVR_IO_PIN_TERMINATION 

Type 

Allows the Compiler to configure the Transceiver Termination value for a gigabit 

transceiver block I/O pin. It specifies the intended Transceiver Termination value for 

the specified gigabit transceiver block I/O pin. 

Enumeration 

■ 100_OHMS 

■ 120_OHMS 

■ 150_OHMS 

■ 85_OHMS 


■ EXTERNAL_RESISTOR 


■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_IO_PIN_TERMINATION -to -entity 

 

Old Names 


software: 

GXB_IO_PIN_TERMINATION 




XCVR_REFCLK_PIN_TERMINATION 

XCVR_REFCLK_PIN_TERMINATION 

Type 

Allows the Compiler to configure the Termination value for a dedicated refclk pin. It 

specifies the intended Termination value for the specified refclk pin. 

Enumeration 


■ AC_COUPLING 

■ DC_COUPLING_EXTERNAL_RESISTOR 

■ DC_COUPLING_INTERNAL_100_OHMS 


■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION -to -entity 

 

Old Names 


software: 

GXB_REFCLK_PIN_TERMINATION 




XCVR_RX_ACGAIN_A 

XCVR_RX_ACGAIN_A 

Type 

Sets reference voltage on EQA. 

Enumeration 


■ AREF_VOLT_0 

■ AREF_VOLT_0P5 




■ Arria V 

■ Cyclone V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_ACGAIN_A -to -entity 




XCVR_RX_ACGAIN_V 

XCVR_RX_ACGAIN_V 

Type 

Sets reference voltage on EQV. 

Enumeration 


■ VREF_VOLT_0 

■ VREF_VOLT_0P5 




■ Arria V 

■ Cyclone V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_ACGAIN_V -to -entity 




XCVR_RX_BYPASS_EQ_STAGES_234 

XCVR_RX_BYPASS_EQ_STAGES_234 

Type 

Bypasses continuous time equalizer stages 2, 3, and 4 to save power. This assignment 

eliminates significant AC gain on the equalizer and is appropriate for chip-to-chip 

short range communication on a PCB. 

Enumeration 


■ ALL_STAGES_ENABLED 

■ BYYPASS_STAGES_234 


■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_BYPASS_EQ_STAGES_234 -to - 

entity 




XCVR_RX_COMMON_MODE_VOLTAGE 

XCVR_RX_COMMON_MODE_VOLTAGE 

Type 

Receiver buffer common-mode voltage. 

Enumeration 

■ TRISTATE1 

■ TRISTATE2 

■ TRISTATE3 

■ TRISTATE4 

■ VTT_0P35V 

■ VTT_0P50V 

■ VTT_0P55V 

■ VTT_0P60V 

■ VTT_0P65V 

■ VTT_0P70V 

■ VTT_0P75V 

■ VTT_0P80V 


■ VTT_PDN_STRONG 

■ VTT_PDN_WEAK 

■ VTT_PUP_STRONG 

■ VTT_PUP_WEAK 


■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE -to -entity 

 




XCVR_RX_DC_GAIN 

XCVR_RX_DC_GAIN 

Type 

Controls the amount of a stage receive-buffer DC gain. 

Integer 




■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_DC_GAIN -to -entity 




XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE 

XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE 

Type 

If enabled, equalizer gain control is driven by the PCS block for PCI Express. If 

disabled, equalizer gain control is determined by the 

XCVR_RX_LINEAR_EQUALIZER_SETTING assignment. 

Boolean 



■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE -to 

-entity 




XCVR_RX_EQ_BW_SEL 

XCVR_RX_EQ_BW_SEL 

Type 

Sets the gain peaking frequency for the equalizer. For data rates lesser than 6.5 Gbps, 

set to HALF. For data rates greater than 6.5 Gbps, set to FULL. 

Enumeration 


■ BW_FULL_12P5 

■ BW_HALF_6P5 


■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_EQ_BW_SEL -to -entity 




XCVR_RX_INPUT_VCM_SEL 

XCVR_RX_INPUT_VCM_SEL 

Type 

When set to LOW_VCM, this assignment enables PMOS equalizer on stage 1 of the 

input buffer and disables the NMOS stage for QPI and other modes in which the DC 

coupled connection common voltage is at approximately 0.25 V. 

Enumeration 

■ HIGH_VCM 

■ LOW_VCM 



■ Arria V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_INPUT_VCM_SEL -to -entity 

 




XCVR_RX_LINEAR_EQUALIZER_CONTROL 

XCVR_RX_LINEAR_EQUALIZER_CONTROL 

Type 

Static control for the continuous time equalizer in the receiver buffer. The equalizer 

has 16 distinct settings from 0 to 15 corresponding to the increasing AC gain. 

Integer 




■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_LINEAR_EQUALIZER_CONTROL -to - 

entity 




XCVR_RX_SD_ENABLE 

XCVR_RX_SD_ENABLE 

Type 

Enables or disables the receiver signal detection unit. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_SD_ENABLE -to -entity 




XCVR_RX_SD_OFF 

XCVR_RX_SD_OFF 

Type 

Number of parallel cycles to wait before the signal detect block declares loss of signal. 

Integer 




■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_SD_OFF -to -entity 




XCVR_RX_SD_ON 

XCVR_RX_SD_ON 

Type 

Number of parallel cycles to wait before the signal detect block declares presence of 

signal. 

Integer 




■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_SD_ON -to -entity 

 




XCVR_RX_SD_THRESHOLD 

XCVR_RX_SD_THRESHOLD 

Type 

Specifies signal detection voltage threshold level. 

Integer 




■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_SD_THRESHOLD -to -entity 

 




XCVR_RX_SEL_HALF_BW 

XCVR_RX_SEL_HALF_BW 

Type 

Enable half bandwidth mode. For BW=3.25GHZ, select FULL_BW. For BW=1.5GHz, 

select HALF_BW. 

Enumeration 

■ FULL_BW 

■ HALF_BW 



■ Arria V 

■ Cyclone V 

Notes 


Syntax 

set_instance_assignment -name XCVR_RX_SEL_HALF_BW -to -entity 




XCVR_TX_COMMON_MODE_VOLTAGE 

XCVR_TX_COMMON_MODE_VOLTAGE 

Type 

Transmitter common-mode driver voltage. 

Enumeration 

■ GROUNDED 

■ PULL_DN 

■ PULL_UP 


■ PULL_UP_TO_VCCELA 














■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_COMMON_MODE_VOLTAGE -to -entity 

 




XCVR_TX_PLL_RECONFIG_GROUP 

XCVR_TX_PLL_RECONFIG_GROUP 

Type 

Specifies whether gigabit transceiver block transceiver channels with Dynamic TX 

PLL Reconfiguration can be placed in the same physical gigabit transceiver block 

quad. If the gigabit transceiver block transceivers have 2 dynamically reconfigured TX 

PLLs, the gigabit transceiver block transceivers are not placed into the same physical 

quad when the Dynamic TX PLL Reconfiguration setting is turned on unless they are 

in the same TX PLL reconfiguration group. If the gigabit transceiver block 

transceivers have one dynamically reconfigured TX PLL, gigabit transceiver block 

transceivers from two TX PLL reconfiguration groups can be placed into the same 

physical quad if the logical number of the TX PLLs are different. 

Gigabit transceiver block transceivers can be assigned to the same group if the 

following conditions are met: 

■ Gigabit transceiver block transmitters in the same group can only listen to 2 TX 

PLLs at one time 

■ You must maintain proper data rates on TX PLLs according to Altera user 

guidelines 

■ You must wait until the pll_locked signal is asserted for dynamic PLL 

reconfiguration completion, and the gigabit transceiver block receivers and 

transmitters are kept in reset until the dynamic reconfiguration of both is complete 

Integer 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name GXB_TX_PLL_RECONFIG_GROUP -to -entity 

 




XCVR_TX_PRE_EMP_1ST_POST_TAP 

XCVR_TX_PRE_EMP_1ST_POST_TAP 

Type 

Specifies the transmitter pre-emphasis first post-tap setting value. 

Integer 




■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_PRE_EMP_1ST_POST_TAP -to - 

entity 




XCVR_TX_PRE_EMP_2ND_POST_TAP 

XCVR_TX_PRE_EMP_2ND_POST_TAP 

Type 

Specifies the transmitter pre-emphasis second post-tap setting. 

Integer 


The value must be between 0 and15, inclusive. 


■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_PRE_EMP_2ND_POST_TAP -to - 

entity 




XCVR_TX_PRE_EMP_2ND_POST_TAP_USER 

XCVR_TX_PRE_EMP_2ND_POST_TAP_USER 

Type 

Specifies the transmitter preemphasis second post-tap setting value, including 

inversion. 

Integer 


The value must be between 0 and31, inclusive. 


■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_PRE_EMP_2ND_POST_TAP_USER -to - 

entity 




XCVR_TX_PRE_EMP_INV_2ND_TAP 

XCVR_TX_PRE_EMP_INV_2ND_TAP 

Type 

Inverts the transmitter pre-emphasis second post-tap setting value. 

Boolean 



■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_PRE_EMP_INV_2ND_TAP -to -entity 

 




XCVR_TX_PRE_EMP_INV_PRE_TAP 

XCVR_TX_PRE_EMP_INV_PRE_TAP 

Type 

Inverts the transmitter pre-emphasis, pre-tap setting value. 

Boolean 



■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_PRE_EMP_INV_PRE_TAP -to -entity 

 




XCVR_TX_PRE_EMP_PRE_TAP 

XCVR_TX_PRE_EMP_PRE_TAP 

Type 

Specifies the transmitter pre-emphasis, pre-tap setting value. 

Integer 




■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_PRE_EMP_PRE_TAP -to -entity 

 




XCVR_TX_PRE_EMP_PRE_TAP_USER 

XCVR_TX_PRE_EMP_PRE_TAP_USER 

Type 

Specifies the transmitter preemphasis pre-tap setting value, including inversion. 

Integer 




■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_PRE_EMP_PRE_TAP_USER -to - 

entity 




XCVR_TX_RX_DET_ENABLE 

XCVR_TX_RX_DET_ENABLE 

Type 

Enables or disables the receiver detector circuit at the transmitter. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_RX_DET_ENABLE -to -entity 

 




XCVR_TX_RX_DET_MODE 

XCVR_TX_RX_DET_MODE 

Type 

Sets the mode for the receiver detect block function. 

Integer 


The value must be between 0 and 15, inclusive. 


■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_RX_DET_MODE -to -entity 




XCVR_TX_RX_DET_OUTPUT_SEL 

XCVR_TX_RX_DET_OUTPUT_SEL 

Type 

Determines QPI or PCI Express mode for the Receiver Detect block. 

Enumeration 


■ RX_DET_PCIE_OUT 

■ RX_DET_QPI_OUT 


■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_RX_DET_OUTPUT_SEL -to -entity 

 




XCVR_TX_SLEW_RATE_CTRL 

XCVR_TX_SLEW_RATE_CTRL 

Type 

Specifies the slew rate of the output signal. The valid values span from the slowest 

rate to fastest rate. 

Integer 




■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_SLEW_RATE_CTRL -to -entity 

 




XCVR_TX_VCM_CTRL_SRC 

XCVR_TX_VCM_CTRL_SRC 

Type 

Controls the VCM driver (pulldown/pullup) dynamically from user signals when 

you set this assignment to DYNAMIC_CTL for QPI protocol. The default setting 

(RAM_CTL) causes the XCVR_TX_COMMON_MODE_VOLTAGE assignment to 

determine the state of the VCM driver. 

Enumeration 

■ DYNAMIC_CTL 

■ RAM_CTL 



■ Arria V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_VCM_CTRL_SRC -to -entity 

 




XCVR_TX_VOD 

XCVR_TX_VOD 

Type 

Differential output voltage setting. The values are monotonically increasing with the 

driver main tap current strength. 

Integer 




■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_VOD -to -entity 

 




XCVR_TX_VOD_PRE_EMP_CTRL_SRC 

XCVR_TX_VOD_PRE_EMP_CTRL_SRC 

Type 

When you set this assignment to DYNAMIC_CTL for PCI Express, the PCS block 

controls the VOD and preemphasis coefficients. When you set this assignment to 

RAM_CTL, the VOD and preemphasis are controlled by other assignments (for 

example, XCVR_TX_PRE_EMP_1ST_POST_TAP). 

Enumeration 

■ DYNAMIC_CTL 

■ RAM_CTL 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_TX_VOD_PRE_EMP_CTRL_SRC -to - 

entity 




XCVR_VCCA_VOLTAGE 

XCVR_VCCA_VOLTAGE 

Type 

Configures the VCCA_GXB voltage for a GXB I/O pin by specifying the intended 

VCCA_GXB voltage for a GXB I/O pin. If you do not set this option, the Compiler 

automatically sets the correct VCCA_GXB voltage. 

Enumeration 

■ 2_5V 

■ 3_0V 



■ Arria V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_VCCA_VOLTAGE -to -entity 

Old Names 


software: 

GXB_VCCA_VOLTAGE 




XCVR_VCCR_VCCT_VOLTAGE 

XCVR_VCCR_VCCT_VOLTAGE 

Type 

Configures the VCCR_GXB and VCCT_GXB voltage for a GXB I/O pin by specifying 

the intended supply voltages for a GXB I/O pin. If you do not set this option, the 

Compiler automatically sets the correct VCCR_GXB and VCCT_GXB voltage. 

Enumeration 

■ 0_85V 

■ 1_0V 

■ 1_1V 



■ Arria V 

■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to -entity 

 

Old Names 


software: 

GXB_VCCR_VCCT_VOLTAGE 




XSTL_INPUT_ALLOW_SE_BUFFER 


Type 

Allows the pin with a Differential-XSTL IO-standard to be used with a single-ended 

input buffer. 

This option is a modifier of IO_STANDARD option with Differential HSTL/SSTL 

I/O standards setting. This option is only available for families which implement 

differential HSTL/SSTL input with true differential input buffer. If this option is on, 

the Quartus II software implements differential HSTL/SSTL input with single-ended 

input buffer with voltage reference. This option affects placment because it allows a 

differential HSTL/SSTL input to be placed on a pin location which does not have 

differential input buffer, but it also requires its reference voltage to be consistent with 

other pins shared the same VREF pin. 

Boolean 













Notes 



Syntax 

set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER 

set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER -entity 

set_instance_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER -to -entity 

 





Example 

set_instance_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER ON -to pin 

Default Value 

Off 

See Also 








POWER_AUTO_COMPUTE_TJ 

Type 










June 2012 

7. Power Estimation Assignments 

Specifies whether the junction temperature is auto-computed during power 

estimation. If the junction temperature is not auto-computed, you must specify the 

junction temperature. 

Boolean 



■ Arria GX 



■ Arria V 






■ Cyclone V 





■ MAX V 





ISO 

9001:2008 

Registered 

Subscribe

7–2 Chapter 7: Power Estimation Assignments 

POWER_AUTO_COMPUTE_TJ 

■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_AUTO_COMPUTE_TJ 

Default Value 

On 



Chapter 7: Power Estimation Assignments 7–3 

POWER_BOARD_TEMPERATURE 

POWER_BOARD_TEMPERATURE 

Type 

Specifies the board temperature, in degrees Celsius, used during power estimation. 

Integer 



■ Arria GX 



■ Arria V 






■ Cyclone V 








■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_BOARD_TEMPERATURE 

Default Value 

25 




POWER_BOARD_THERMAL_MODEL 

POWER_BOARD_THERMAL_MODEL 

Type 

Specifies the board thermal model used during power estimation. 

String 



■ Arria GX 



■ Arria V 






■ Cyclone V 








■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_BOARD_THERMAL_MODEL 




POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 


Type 

Specifies the default toggle rate to be used on input I/O pins during power 

estimation. This value is only used if a toggle rate has not been specified for a node 

either through a Signal Activity File (.saf), Value Change Dump File (.vcd), or user 

assignment. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 

Default Value 

12.5% 




POWER_DEFAULT_TOGGLE_RATE 


Type 

Specifies the default toggle rate to be used on all nodes except input I/O pins during 

power estimation. This value is only used if a toggle rate has not been specified for a 

node either through a Signal Activity File (.saf), Value Change Dump File (.vcd), or 

user assignment. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 

Default Value 

12.5% 




POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 

POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 

Type 

Specifies the external supply voltage applied to the on-chip voltage regulator. This 

option applies only to devices which have an on-chip voltage regulator. 

String 




■ MAX V 

Notes 


Syntax 

set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 




POWER_HPS_ENABLE 


Type 

Specifies whether or not you must include the HPS processor subsystem for SoC 

power estimation. 

Boolean 



■ Arria GX 



■ Arria V 






■ Cyclone V 





■ MAX V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_HPS_ENABLE 





Default Value 

Off 




POWER_HPS_DYNAMIC_POWER_DUAL 


Tyoe 

Specifies the dynamic power of the dual processor core when HPS is active. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name POWER_HPS_DYNAMIC_POWER_DUAL 




POWER_HPS_DYNAMIC_POWER_SINGLE 


Type 

Specifies the dynamic power of the single processor core when HPS is active. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name POWER_HPS_DYNAMIC_POWER_SINGLE 




POWER_HPS_JUNCTION_TEMPERATURE 


Type 

Specifies the junction temperature when HPS is active. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name POWER_HPS_JUNCTION_TEMPERATURE 




POWER_HPS_PROC_FREQ 


Type 

Specifies the processor frequency of the HPS assumed by power estimation. The units 

for this value are in MHz and the value must be positive. The value provided must be 

within 0 to 1000. 

Double 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name POWER_HPS_PROC_FREQ 

Default Value 

0.0 




POWER_HPS_STATIC_POWER 


Type 

Specifies the static power when HPS is active. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name POWER_HPS_STATIC_POWER 




POWER_HPS_TOTAL_POWER 


Type 

Specifies the total power when HPS is active. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name POWER_HPS_TOTAL_POWER 




POWER_HSSI 

POWER_HSSI 

Type 

If the transceivers are unused, setting this option to Opportunistically power off 

directs the Quartus II software to consider the transceivers as powered down. Setting 

this option to Power on directs the Quartus II software to consider the transceivers 

powered regardless of their use. This setting affects the VCCA, VCCH_GXB, and VCCL_GXB 

power rails 

String 



Notes 



Syntax 

set_global_assignment -name POWER_HSSI 




POWER_HSSI_LEFT 

POWER_HSSI_LEFT 

Type 

If the transceivers on the left side of the device are unused, setting this option to 

Opportunistically power off directs the Quartus II software to consider the 

transceivers on the left side of the device powered down. Setting this option to Power 

on directs the Quartus II software to consider the transceivers on the left side powered 

regardless of their use. This setting affects the VCCA_L, VCCH_GXBL, VCCL_GXBL, VCCR_L, 

and VCCT_L power rails. 

String 



Notes 



Syntax 

set_global_assignment -name POWER_HSSI_LEFT 




POWER_HSSI_RIGHT 

POWER_HSSI_RIGHT 

Type 

If the transceivers on the right side of the device are unused, setting this option to 

Opportunistically power off directs the Quartus II software to consider the 

transceivers on the right side of the device powered down. Setting this option to 

Power on directs the Quartus II software to consider the transceivers on the right side 

powered regardless of their use. This setting affects the VCCA_R, VCCH_GXBR, VCCL_GXBR, 

VCCR_R, and VCCT_R power rails. 

String 



Notes 



Syntax 

set_global_assignment -name POWER_HSSI_RIGHT 




POWER_HSSI_VCCHIP_LEFT 

POWER_HSSI_VCCHIP_LEFT 

Type 

If the PCI Express hard IP blocks on the left side of the device are unused, setting this 

option to Opportunistically power off directs the Quartus II software to consider the 

PCI Express hard IP blocks on the left side of the device powered down. Setting this 

option to Power on directs the Quartus II software to consider the PCI Express hard IP 

blocks on the left side powered regardless of their use. 

String 



Notes 



Syntax 

set_global_assignment -name POWER_HSSI_VCCHIP_LEFT 




POWER_HSSI_VCCHIP_RIGHT 

POWER_HSSI_VCCHIP_RIGHT 

Type 

If the PCI Express hard IP blocks on the right side of the device are unused, setting 

this option to Opportunistically power off directs the Quartus II software to consider 

the PCI Express hard IP blocks on the right side of the device powered down. Setting 

this option to Power on directs the Quartus II software to consider the PCI Express 

hard IP blocks on the right side powered regardless of their use. 

String 



Notes 



Syntax 

set_global_assignment -name POWER_HSSI_VCCHIP_RIGHT 




POWER_INPUT_FILE_NAME 


Type 

Specifies the name of the Value Change Dump File (.vcd) or Signal Activity File (.saf) 

which should be used to initialize the toggle rates and static probabilities that are used 

during power estimation. 




■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name POWER_INPUT_FILE_NAME -entity - 

section_id 




POWER_INPUT_FILE_TYPE 


Type 

Specifies whether the input power file is a Value Change Dump File (.vcd) or Signal 

Activity File (.saf). 

Enumeration 

■ SAF 

■ VCD 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 










■ Stratix V 

Syntax 

set_global_assignment -name POWER_INPUT_FILE_TYPE -entity - 

section_id 




POWER_INPUT_SAF_NAME 

POWER_INPUT_SAF_NAME 

Type 

Specifies the name of the Signal Activity File (.saf) which should be used to initialize 

the toggle rates and static probabilities that are used during power estimation. 




■ Arria GX 

■ Cyclone 






■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 




Notes 


Syntax 

set_global_assignment -name POWER_INPUT_SAF_NAME 




POWER_INPUT_VCD_FILE_NAME 

POWER_INPUT_VCD_FILE_NAME 

Type 

Specifies the names of the Value Change Dump Files (.vcd) which should be used to 

initialize the toggle rates and static probabilities that are used during power 

estimation. 




■ Arria GX 

■ Cyclone 






■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 




Notes 


Syntax 

set_global_assignment -name POWER_INPUT_VCD_FILE_NAME 




POWER_OCS_VALUE 

POWER_OCS_VALUE 

Type 

Specifies the case-to-heat sink thermal resistance, in degrees Celsius per Watt, used 


String 



■ Arria GX 



■ Arria V 






■ Cyclone V 





■ MAX V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_OCS_VALUE 




POWER_OJB_VALUE 

POWER_OJB_VALUE 

Type 

Specifies the junction-to-board thermal resistance, in degrees Celsius per Watt, used 


String 



■ Arria GX 



■ Arria V 






■ Cyclone V 








■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_OJB_VALUE 




POWER_OJC_VALUE 

POWER_OJC_VALUE 

Type 

Specifies the junction-to-case sink thermal resistance, in degrees Celsius per Watt, 

used during power estimation. 

String 



■ Arria GX 



■ Arria V 






■ Cyclone V 





■ MAX V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_OJC_VALUE 




POWER_OSA_VALUE 

POWER_OSA_VALUE 

Type 

Specifies the heat sink-to-ambient thermal resistance, in degrees Celsius per Watt, 

used during power estimation. 

String 



■ Arria GX 



■ Arria V 






■ Cyclone V 





■ MAX V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_OSA_VALUE 




POWER_OUTPUT_SAF_NAME 


Type 

Specifies the name the Signal Activity File (.saf) should be written to containing the 

toggle rates and static probabilities used during power estimation. 




■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Notes 



Syntax 

set_global_assignment -name POWER_OUTPUT_SAF_NAME 




POWER_PRESET_COOLING_SOLUTION 

POWER_PRESET_COOLING_SOLUTION 

Type 

Specifies the preset cooling solution used during power estimation. 

String 



■ Arria GX 



■ Arria V 






■ Cyclone V 





■ MAX V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION 




POWER_READ_INPUT_FILE 


Type 

Assigns user-defined power input file characteristics to an entity. To specify a power 

input file, you must define a named group of power input file settings and assign 

them to an entity with this option. You can create these settings using the PowerPlay 

Power Analyzer Settings page. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name POWER_READ_INPUT_FILE -to -entity 

 




POWER_REPORT_POWER_DISSIPATION 


Type 

Specifies whether the PowerPlay Power Analyzer should report the thermal power 

dissipation calculated during power analysis in the Thermal Power Dissipation By 

Block report panel. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name POWER_REPORT_POWER_DISSIPATION 

set_instance_assignment -name POWER_REPORT_POWER_DISSIPATION -to - 

entity 

Default Value 

Off 




POWER_REPORT_SIGNAL_ACTIVITY 


Type 

Specifies whether the PowerPlay Power Analyzer should report the signal activities 

assumed for power analysis, and the sources for those activities. Signal activity 

consists of both the static probability and the toggle rate for the signals generated by 

the node or entity. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 










■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY 

set_instance_assignment -name POWER_REPORT_SIGNAL_ACTIVITY -to - 

entity 

Default Value 

Off 




POWER_SIGNAL_ACTIVITY_END_TIME 

POWER_SIGNAL_ACTIVITY_END_TIME 

Type 

Specifies the time at which toggle rates and static probabilities should stop being 

calculated for the output signals contained in the Value Change Dump Files (.vcd). 

Time 



■ Arria GX 

■ Cyclone 






■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 




Syntax 

set_global_assignment -name POWER_SIGNAL_ACTIVITY_END_TIME 




POWER_SIGNAL_ACTIVITY_START_TIME 

POWER_SIGNAL_ACTIVITY_START_TIME 

Type 

Specifies the time at which toggle rates and static probabilities should start to be 


Time 



■ Arria GX 

■ Cyclone 






■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 




Syntax 

set_global_assignment -name POWER_SIGNAL_ACTIVITY_START_TIME 




POWER_STATIC_PROBABILITY 


Type 

Specifies the fraction of time the signals generated by the node or entity are expected 

to be at VCC. Allowable values range from and include 0.0 through 1.0. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Syntax 

set_instance_assignment -name POWER_STATIC_PROBABILITY -to 




POWER_TJ_VALUE 


Type 

Specifies the junction temperature value, in degrees Celsius, used during power 

estimation. 

Integer 



■ Arria GX 



■ Arria V 






■ Cyclone V 





■ MAX V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_TJ_VALUE 





Default Value 

25 




POWER_TOGGLE_RATE 


Type 

Specifies the toggle rate assumed by power estimation for the signals generated by 

this node or entity. The units for this value are transitions per second and the value 

must be positive. The value provided should be the expected time-averaged toggle 

rate, rather than worst case (highest possible) toggle rate. A different assignment, 

Toggle Rate, applies to I/O pins only and is used by the Fitter and by I/O 

Assignment Analysis to verify signal integrity under worst case conditions (highest 

possible toggle rate). Use the Synchronizer Toggle Rate if you want to configure the 

data rates used for Metastability Reporting in the TimeQuest timing analyzer. 

Integer 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 










■ Stratix V 

Syntax 

set_instance_assignment -name POWER_TOGGLE_RATE -to 




POWER_TOGGLE_RATE_PERCENTAGE 


Type 

Specifies the toggle rate, as a percentage of clock domain frequency, assumed by 

power estimation for the signals generated by this node or entity. This percentage acts 

as a multiplier for the clock domain frequency of the given node. For example, a 

toggle rate percentage of 12.5 on a node with a clock domain frequency of 96 MHz 

would result in a toggle rate of 12 million transitions per second. The percentage 

value must be positive and can take on values greater than 100. The value provided 

should be representative of the expected time-averaged toggle rate, rather than worst 

case (highest possible) toggle rate. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 










■ Stratix V 

Syntax 

set_instance_assignment -name POWER_TOGGLE_RATE_PERCENTAGE -to 

 




POWER_USE_CUSTOM_COOLING_SOLUTION 


Type 

Specifies whether a custom cooling solution is used during power estimation. For a 

custom cooling solution, you must specify the case-to-heat sink, junction-to-case and 

heat sink-to-ambient thermal resistances. 

Boolean 



■ Arria GX 



■ Arria V 






■ Cyclone V 





■ MAX V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION 





Default Value 

Off 




POWER_USE_DEVICE_CHARACTERISTICS 


Type 

Specifies the device characteristics to be used during power estimation. 

Estimates are based on average power consumed by typical silicon at nominal 

operating conditions. For FPGA board power supply design, change to MAXIMUM 

to get worst-case values. 

Enumeration 

■ MAXIMUM 

■ TYPICAL 



■ Arria GX 



■ Arria V 






■ Cyclone V 





■ MAX V 





■ Stratix V 

Notes 






Syntax 

set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS 

Default Value 

TYPICAL 




POWER_USE_INPUT_FILE 

POWER_USE_INPUT_FILE 

Type 

Specifies whether or not Signal Activity Files (.saf) or Value Change Dump Files (.vcd) 

should be used to initialize the toggle rates and static probabilities that will be used 


Enumeration 

■ No File 

■ Signal Activity File 

■ VCD File 



■ Arria GX 

■ Cyclone 






■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 




Syntax 

set_global_assignment -name POWER_USE_INPUT_FILE 

Default Value 

No File 




POWER_USE_INPUT_FILES 


Type 

Specifies whether or not Signal Activity Files (.saf) or Value Change Dump Files (.vcd) 

should be used to initialize the toggle rates and static probabilities that will be used 


Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name POWER_USE_INPUT_FILES 

Default Value 

Off 




POWER_USE_PVA 

POWER_USE_PVA 

Type 

Specifies whether or not Power Vectorless Activity should be used to fill in undefined 

toggle rates and static probabilities. 

Boolean 



■ Arria GX 



■ Arria V 






■ Cyclone V 





■ MAX V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_USE_PVA 




POWER_USE_PVA 

Default Value 

On 




POWER_USE_TA_VALUE 


Type 

Specifies the ambient temperature value, in degrees Celsius, used during power 

estimation. 

Integer 



■ Arria GX 



■ Arria V 






■ Cyclone V 





■ MAX V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name POWER_USE_TA_VALUE 





Default Value 

25 




POWER_VCCAUX_USER_OPTION 

POWER_VCCAUX_USER_OPTION 

Type 

Allows you to specify settings for the VCCAUX power rail supply. For more information, 

refer to the respective device family data sheet. 

String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCAUX_USER_OPTION 




POWER_VCCA_GXB_USER_OPTION 

POWER_VCCA_GXB_USER_OPTION 

Type 

Allows you to specify settings for the VCCA_GXB power rail supply. For more 

information, refer to the device datasheet for the current device family. 

String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCA_GXB_USER_OPTION 




POWER_VCCA_L_USER_OPTION 

POWER_VCCA_L_USER_OPTION 

Type 

Allows you to specify settings for the VCCA_L power rail supply. For more information, 


String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCA_L_USER_OPTION 




POWER_VCCA_R_USER_OPTION 

POWER_VCCA_R_USER_OPTION 

Type 

Allows you to specify settings for the VCCA_R power rail supply. For more information, 


String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCA_R_USER_OPTION 




POWER_VCCCB_USER_OPTION 

POWER_VCCCB_USER_OPTION 

Type 

Allows you to specify settings for the VCCCB power rail supply. For more information, 


String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCCB_USER_OPTION 




POWER_VCCH_GXBL_USER_OPTION 

POWER_VCCH_GXBL_USER_OPTION 

Type 

Allows you to specify settings for the VCCH_GXBL power rail supply. For more 

information, refer to the respective device family data sheet. 

String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCH_GXBL_USER_OPTION 




POWER_VCCH_GXBR_USER_OPTION 

POWER_VCCH_GXBR_USER_OPTION 

Type 

Allows you to specify settings for the VCCH_GXBR power rail supply. For more 


String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCH_GXBR_USER_OPTION 




POWER_VCCH_GXB_USER_OPTION 

POWER_VCCH_GXB_USER_OPTION 

Type 

Allows you to specify settings for the VCCH_GXB power rail supply. For more 


String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCH_GXB_USER_OPTION 




POWER_VCCIO_USER_OPTION 

POWER_VCCIO_USER_OPTION 

Type 

Allows you to specify settings for the VCCIO power rail supply. For more information, 


String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCIO_USER_OPTION 




POWER_VCCL_GXB_USER_OPTION 

POWER_VCCL_GXB_USER_OPTION 

Type 

Allows you to specify settings for the VCCL_GXB power rail supply. For more 


String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCL_GXB_USER_OPTION 




POWER_VCCPD_USER_OPTION 

POWER_VCCPD_USER_OPTION 

Type 

Allows you to specify settings for the VCCPD power rail supply. For more information, 


String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCPD_USER_OPTION 




POWER_VCCR_GXBL_USER_OPTION 

POWER_VCCR_GXBL_USER_OPTION 

Type 

Allows you to specify settings for the VCCR_GXBL power rail supply. For more 


String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCR_GXBL_USER_OPTION 




POWER_VCCR_GXBR_USER_OPTION 

POWER_VCCR_GXBR_USER_OPTION 

Type 

Allows you to specify settings for the VCCR_GXBR power rail supply. For more 


String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCR_GXBR_USER_OPTION 




POWER_VCCR_GXB_USER_OPTION 

POWER_VCCR_GXB_USER_OPTION 

Type 

Allows you to specify settings for the VCCR_GXB power rail supply. For more 


String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCR_GXB_USER_OPTION 




POWER_VCCT_GXBL_USER_OPTION 

POWER_VCCT_GXBL_USER_OPTION 

Type 

Allows you to specify settings for the VCCT_GXBL power rail supply. For more 


String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCT_GXBL_USER_OPTION 




POWER_VCCT_GXBR_USER_OPTION 

POWER_VCCT_GXBR_USER_OPTION 

Type 

Allows you to specify settings for the VCCT_GXBR power rail supply. Refer to the 

device datasheet for the current device family for more details. 

String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCT_GXBR_USER_OPTION 




POWER_VCCT_GXB_USER_OPTION 

POWER_VCCT_GXB_USER_OPTION 

Type 

Allows you to specify settings for the VCCT_GXB power rail supply. For more 


String 



Notes 



Syntax 

set_global_assignment -name POWER_VCCT_GXB_USER_OPTION 




POWER_VCD_FILE_END_TIME 


Type 

Specifies the time at which toggle rates and static probabilities should stop being 


Time 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Syntax 

set_global_assignment -name POWER_VCD_FILE_END_TIME -entity 

-section_id 




POWER_VCD_FILE_START_TIME 


Type 

Specifies the time at which toggle rates and static probabilities should start to be 


Time 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 






■ Stratix V 





Syntax 

set_global_assignment -name POWER_VCD_FILE_START_TIME -entity -section_id 




POWER_VCD_FILTER_GLITCHES 


Type 

Specifies whether or not glitch filtering should be used when reading in Value Change 

Dump Files (.vcd). 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Notes 






Syntax 

set_global_assignment -name POWER_VCD_FILTER_GLITCHES 

Default Value 

On 




VCCAUX_USER_VOLTAGE 

VCCAUX_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCAUX power rail supply. For more information, refer to 

the respective device family data sheet. 

String 



Notes 



Syntax 

set_global_assignment -name VCCAUX_USER_VOLTAGE 




VCCA_GXBL_USER_VOLTAGE 

VCCA_GXBL_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCA_GXBL power rail supply. For more information, 

refer to the device datasheet for the current device family. 

String 



Notes 



Syntax 

set_global_assignment -name VCCA_GXBL_USER_VOLTAGE 




VCCA_GXBR_USER_VOLTAGE 

VCCA_GXBR_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCA_GXBR power rail supply. For more information, 


String 



Notes 



Syntax 

set_global_assignment -name VCCA_GXBR_USER_VOLTAGE 




VCCA_GXB_USER_VOLTAGE 

VCCA_GXB_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCA_GXB power rail supply. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCA_GXB_USER_VOLTAGE 




VCCA_L_USER_VOLTAGE 

VCCA_L_USER_VOLTAGE 

Type 

Specifies the default voltage of the VCCA_L power rail supply, which is applied if all 

transceivers on the left side of the device are powered and unused. To configure a 

transceiver for your intended protocol, use the ALTGX MegaWizard. For more 


String 



Notes 



Syntax 

set_global_assignment -name VCCA_L_USER_VOLTAGE 




VCCA_PLL_USER_VOLTAGE 

VCCA_PLL_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCA_PLL power rail supply. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCA_PLL_USER_VOLTAGE 




VCCA_R_USER_VOLTAGE 

VCCA_R_USER_VOLTAGE 

Type 

Specifies the default voltage of the VCCA_R power rail supply, which is applied if all 

transceivers on the right side of the device are powered and unused. To configure a 

transceiver for your intended protocol, use the ALTGX MegaWizard. For more 


String 



Notes 



Syntax 

set_global_assignment -name VCCA_R_USER_VOLTAGE 




VCCA_USER_VOLTAGE 

VCCA_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCA power rail supply. For devices in the Arria II family, 

this voltage is applied if the transceivers are powered. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCA_USER_VOLTAGE 




VCCCB_USER_VOLTAGE 

VCCCB_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCCB power rail supply. For more information, refer to the 


String 



Notes 



Syntax 

set_global_assignment -name VCCCB_USER_VOLTAGE 




VCCD_PLL_USER_VOLTAGE 

VCCD_PLL_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCD_PLL power rail supply. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCD_PLL_USER_VOLTAGE 




VCCD_USER_VOLTAGE 

VCCD_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCD power rail supply. For more information, refer to the 


String 



Notes 



Syntax 

set_global_assignment -name VCCD_USER_VOLTAGE 




VCCE_GXBL_USER_VOLTAGE 

VCCE_GXBL_USER_VOLTAGE 

Type 

Specifies the default voltage of the VCCE_GXBL power rail supplies, which is applied 

if all transceivers in the corresponding transceiver block are powered and unused. To 

configure a transceiver for your intended protocol, use the ALTGX MegaWizard Plug- 

In Manager. For more information, refer to the device datasheet for the current device 

family. 

String 



Notes 



Syntax 

set_global_assignment -name VCCE_GXBL_USER_VOLTAGE 




VCCE_GXBR_USER_VOLTAGE 

VCCE_GXBR_USER_VOLTAGE 

Type 

Specifies the default voltage of the VCCE_GXBR power rail supplies, which is applied 




family. 

String 



Notes 



Syntax 

set_global_assignment -name VCCE_GXBR_USER_VOLTAGE 




VCCE_GXB_USER_VOLTAGE 

VCCE_GXB_USER_VOLTAGE 

Type 

Specifies the default voltage of the VCCE_GXB power rail supplies, which is applied 




family. 

String 



Notes 



Syntax 

set_global_assignment -name VCCE_GXB_USER_VOLTAGE 




VCCE_USER_VOLTAGE 

VCCE_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCE power rail supply. For more information, refer to 

the device datasheet for the current device family. 

String 



Notes 



Syntax 

set_global_assignment -name VCCE_USER_VOLTAGE 




VCCEH_GXBL_USER_VOLTAGE 

VCCEH_GXBL_USER_VOLTAGE 

Type 

Specifies the default voltage of the VCCEH_GXBL power rail supplies, which is 

applied if all transceivers in the corresponding transceiver block are powered and 

unused. To configure a transceiver for your intended protocol, use the ALTGX 

MegaWizard Plug-In Manager. For more information, refer to the device datasheet for 

the current device family. 

String 



Notes 



Syntax 

set_global_assignment -name VCCEH_GXBL_USER_VOLTAGE 




VCCEH_GXBR_USER_VOLTAGE 

VCCEH_GXBR_USER_VOLTAGE 

Type 

Specifies the default voltage of the VCCEH_GXBR power rail supplies, which is 





String 



Notes 



Syntax 

set_global_assignment -name VCCEH_GXBR_USER_VOLTAGE 




VCCEH_GXB_USER_VOLTAGE 

VCCEH_GXB_USER_VOLTAGE 

Type 

Specifies the default voltage of the VCCEH_GXB power rail supplies, which is 





String 



Notes 



Syntax 

set_global_assignment -name VCCEH_GXB_USER_VOLTAGE 




VCCHIP_L_USER_VOLTAGE 

VCCHIP_L_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCHIP_L power rail supply. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCHIP_L_USER_VOLTAGE 




VCCHIP_R_USER_VOLTAGE 

VCCHIP_R_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCHIP_R power rail supply. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCHIP_R_USER_VOLTAGE 




VCCHIP_USER_VOLTAGE 

VCCHIP_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCHIP power rail supply. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCHIP_USER_VOLTAGE 




VCCHSSI_L_USER_VOLTAGE 

VCCHSSI_L_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCHSSI_L power rail supply. For more information, 


String 



Notes 



Syntax 

set_global_assignment -name VCCHSSI_L_USER_VOLTAGE 




VCCHSSI_R_USER_VOLTAGE 

VCCHSSI_R_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCHSSI_R power rail supply. For more information, 


String 



Notes 



Syntax 

set_global_assignment -name VCCHSSI_R_USER_VOLTAGE 




VCCH_GXBL_USER_VOLTAGE 

VCCH_GXBL_USER_VOLTAGE 

Type 

Specifies the default voltage of the VCCH_GXBL power rail supplies, which is applied if 

all transceivers in the corresponding transceiver block are powered and unused. To 

configure a transceiver for your intended protocol, use the ALTGX MegaWizard. For 

more information, refer to the respective device family data sheet. 

String 



Notes 



Syntax 

set_global_assignment -name VCCH_GXBL_USER_VOLTAGE 




VCCH_GXBR_USER_VOLTAGE 

VCCH_GXBR_USER_VOLTAGE 

Type 

Specifies the default voltage of the VCCH_GXBR power rail supplies, which is applied if 


configure a transceiver for your intended protocol, use the ALTGX MegaWizard. For 

more information, refer to the respective device family data sheet. 

String 



Notes 



Syntax 

set_global_assignment -name VCCH_GXBR_USER_VOLTAGE 




VCCH_GXB_USER_VOLTAGE 

VCCH_GXB_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCH_GXB power rail supply. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCH_GXB_USER_VOLTAGE 




VCCH_L_USER_VOLTAGE 

VCCH_L_USER_VOLTAGE 

Type 

Specifies the default voltage of the VCCH_L power rail supplies, which is applied if 




family. 

String 



Notes 



Syntax 

set_global_assignment -name VCCH_L_USER_VOLTAGE 




VCCH_R_USER_VOLTAGE 

VCCH_R_USER_VOLTAGE 

Type 

Specifies the default voltage of the VCCH_R power rail supplies, which is applied if 




family. 

String 



Notes 



Syntax 

set_global_assignment -name VCCH_R_USER_VOLTAGE 




VCCINT_USER_VOLTAGE 

VCCINT_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCINT power rail supply. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCINT_USER_VOLTAGE 




VCCIO_USER_VOLTAGE 

VCCIO_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCIO power rail supply. For more information, refer to the 


String 



Notes 



Syntax 

set_global_assignment -name VCCIO_USER_VOLTAGE 




VCCL_GXBL_USER_VOLTAGE 

VCCL_GXBL_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCL_GXBL power rail supply. For more information, refer 

to the respective device family data sheet. 

String 



Notes 



Syntax 

set_global_assignment -name VCCL_GXBL_USER_VOLTAGE 




VCCL_GXBR_USER_VOLTAGE 

VCCL_GXBR_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCL_GXBR power rail supply. For more information, refer 

to the respective device family data sheet. 

String 



Notes 



Syntax 

set_global_assignment -name VCCL_GXBR_USER_VOLTAGE 




VCCL_GXB_USER_VOLTAGE 

VCCL_GXB_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCL_GXB power rail supply. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCL_GXB_USER_VOLTAGE 




VCCL_USER_VOLTAGE 

VCCL_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCL power rail supply. For more information, refer to the 


String 



Notes 



Syntax 

set_global_assignment -name VCCL_USER_VOLTAGE 




VCCPD_USER_VOLTAGE 

VCCPD_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCPD power rail supply. For more information, refer to the 


String 



Notes 



Syntax 

set_global_assignment -name VCCPD_USER_VOLTAGE 




VCCPT_USER_VOLTAGE 

VCCPT_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCPT power rail supply. For more information, refer to the 


String 



Notes 



Syntax 

set_global_assignment -name VCCPT_USER_VOLTAGE 




VCCP_USER_VOLTAGE 

VCCP_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCP power rail supply. For more information, refer to 

the device datasheet for the current device family. 

String 

Device Families 


Notes 



Syntax 

set_global_assignment -name VCCP_USER_VOLTAGE 




VCCR_GXBL_USER_VOLTAGE 

VCCR_GXBL_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCR_GXBL power rail supply. For more information, 


String 



Notes 



Syntax 

set_global_assignment -name VCCR_GXBL_USER_VOLTAGE 




VCCR_GXBR_USER_VOLTAGE 

VCCR_GXBR_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCR_GXBR power rail supply. For more information, 


String 



Notes 



Syntax 

set_global_assignment -name VCCR_GXBR_USER_VOLTAGE 




VCCR_GXB_USER_VOLTAGE 

VCCR_GXB_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCR_GXB power rail supply. For more information, refer 

to the device datasheet for the current device family. 

String 



Notes 



Syntax 

set_global_assignment -name VCCR_GXB_USER_VOLTAGE 




VCCR_L_USER_VOLTAGE 

VCCR_L_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCR_L power rail supply. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCR_L_USER_VOLTAGE 




VCCR_R_USER_VOLTAGE 

VCCR_R_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCR_R power rail supply. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCR_R_USER_VOLTAGE 




VCCR_USER_VOLTAGE 

VCCR_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCR power rail supply. For more information, refer to the 


String 



Notes 



Syntax 

set_global_assignment -name VCCR_USER_VOLTAGE 




VCCT_GXBL_USER_VOLTAGE 

VCCT_GXBL_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCT_GXBL power rail supply. For more information, 


String 



Notes 



Syntax 

set_global_assignment -name VCCT_GXBL_USER_VOLTAGE 




VCCT_GXBR_USER_VOLTAGE 

VCCT_GXBR_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCT_GXBR power rail supply. For more information, 


String 



Notes 



Syntax 

set_global_assignment -name VCCT_GXBR_USER_VOLTAGE 




VCCT_GXB_USER_VOLTAGE 

VCCT_GXB_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCT_GXB power rail supply. For more information, refer 

to the device datasheet for the current device family. 

String 



Notes 



Syntax 

set_global_assignment -name VCCT_GXB_USER_VOLTAGE 




VCCT_L_USER_VOLTAGE 

VCCT_L_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCT_L power rail supply. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCT_L_USER_VOLTAGE 




VCCT_R_USER_VOLTAGE 

VCCT_R_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCT_R power rail supply. For more information, refer to 


String 



Notes 



Syntax 

set_global_assignment -name VCCT_R_USER_VOLTAGE 




VCCT_USER_VOLTAGE 

VCCT_USER_VOLTAGE 

Type 

Specifies the voltage of the VCCT power rail supply. For more information, refer to the 


String 



Notes 



Syntax 

set_global_assignment -name VCCT_USER_VOLTAGE 




VCC_USER_VOLTAGE 


Type 

Specifies the voltage of the VCC power rail supply. For more information, refer to the 


String 



C 

Notes 



Syntax 

set_global_assignment -name VCC_USER_VOLTAGE 







EDA_BOARD_BOUNDARY_SCAN_OPERATION 

Type 










June 2012 

8. EDA Netlist Writer Assignments 

Specifies the Boundary-Scan Description Language (BSDL) file operation either for 

pre-configuration or post-configuration 

Enumeration 


■ POST_CONFIG 

■ PRE_CONFIG 


Syntax 

set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION -section_id 

 

Default Value 

PRE_CONFIG, requires section identifier 

ISO 

9001:2008 

Registered 

Subscribe

8–2 Chapter 8: EDA Netlist Writer Assignments 

EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL 

EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL 

Type 

Specifies the boundary scan format used for board level boundary scan testing. 

String 



Notes 



Syntax 

set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL 

set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL -entity 

 

Default Value 

None 



Chapter 8: EDA Netlist Writer Assignments 8–3 

EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL 

EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL 

Type 

Specifies the EDA third-party tool used for board level signal integrity analysis. 

String 



Notes 



Syntax 

set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL 

set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL -entity 

 

Default Value 

None 




EDA_BOARD_DESIGN_SYMBOL_TOOL 

EDA_BOARD_DESIGN_SYMBOL_TOOL 

Type 

Specifies the EDA third-party tool used for board level schematic design. 

String 



Notes 



Syntax 

set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL 

set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL -entity 

Default Value 

None 




EDA_BOARD_DESIGN_TIMING_TOOL 

EDA_BOARD_DESIGN_TIMING_TOOL 

Type 

Specifies the EDA third-party tool used for board level timing analysis. 

String 



Notes 



Syntax 

set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL 

set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL -entity 

Default Value 

None 




EDA_BOARD_DESIGN_TOOL 

EDA_BOARD_DESIGN_TOOL 

Type 

Specifies the EDA third-party tool used for board level design and analysis. 

String 



Notes 



Syntax 

set_global_assignment -name EDA_BOARD_DESIGN_TOOL 

set_global_assignment -name EDA_BOARD_DESIGN_TOOL -entity 

 

Default Value 

None 




EDA_DESIGN_EXTRA_ALTERA_SIM_LIB 

EDA_DESIGN_EXTRA_ALTERA_SIM_LIB 

Type 

Specifies additional Altera simulation model libraries used by the design files. 

String 



Notes 


Syntax 

set_global_assignment -name EDA_DESIGN_EXTRA_ALTERA_SIM_LIB -section_id 

 




EDA_DESIGN_INSTANCE_NAME 

EDA_DESIGN_INSTANCE_NAME 

Type 

Specifies the instance name of the design in the test bench. 

String 



Notes 


Syntax 

set_global_assignment -name EDA_DESIGN_INSTANCE_NAME -section_id 




EDA_ENABLE_GLITCH_FILTERING 

EDA_ENABLE_GLITCH_FILTERING 

Type 

Writes logic to filter glitches in the simulation netlist. 

Boolean 



Notes 


Syntax 

set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING -section_id 

 

set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING -entity -section_id 

Default Value 





EDA_ENABLE_IPUTF_MODE 

EDA_ENABLE_IPUTF_MODE 

Type 

Allows you to simulate designs containing hw.tcl based IP cores. This may require 

adding .sip files to your Quartus II project. This variable may be removed in future 

releases 

Boolean 



Notes 


Syntax 

set_global_assignment -name EDA_ENABLE_IPUTF_MODE -section_id 

set_global_assignment -name EDA_ENABLE_IPUTF_MODE -entity - 

section_id 

Default Value 

On, requires section identifier 




EDA_EXTRA_ELAB_OPTION 

EDA_EXTRA_ELAB_OPTION 

Type 

Additional custom simulation elaboration options for one or more simulators. 

String 



Notes 



Syntax 

set_global_assignment -name EDA_EXTRA_ELAB_OPTION -section_id 

set_global_assignment -name EDA_EXTRA_ELAB_OPTION -entity - 

section_id 




EDA_FLATTEN_BUSES 

EDA_FLATTEN_BUSES 

Type 

Flattens all buses when creating the VHDL Output File (.vho). You should turn on this 

option if your third-party EDA environment does not support buses. 

Boolean 



Notes 


Syntax 

set_global_assignment -name EDA_FLATTEN_BUSES -section_id 

set_global_assignment -name EDA_FLATTEN_BUSES -entity - 

section_id 

Default Value 





EDA_FORMAL_VERIFICATION_ALLOW_RETIMING 

EDA_FORMAL_VERIFICATION_ALLOW_RETIMING 

Type 

Allows register retiming to be turned on for formal verification. 

Boolean 



Syntax 

set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING - 

section_id 

set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING -entity 

-section_id 

Default Value 





EDA_FORMAL_VERIFICATION_TOOL 

EDA_FORMAL_VERIFICATION_TOOL 

Type 

Specifies the EDA third-party tool used for formal verification. 

String 



Notes 



Syntax 

set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL 

set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL -entity 

Default Value 

None 




EDA_FV_HIERARCHY 

EDA_FV_HIERARCHY 

Type 

Determines how the hierarchy of design entities is to be processed during 

compilation. The BLACKBOX setting causes the entity to be handled as a black-box in 

the EDA flow. The NONE setting is the default and means that no special handling 

needs to be done. This option applies only to the design entity to which it is assigned; 

lower-level entities do not inherit the setting of their parent entity for this option. 

Enumeration 

■ BLACKBOX 

■ Off 



Syntax 

set_global_assignment -name EDA_FV_HIERARCHY -entity 

set_instance_assignment -name EDA_FV_HIERARCHY -to -entity 




EDA_GENERATE_FUNCTIONAL_NETLIST 

EDA_GENERATE_FUNCTIONAL_NETLIST 

Type 

Generates the Verilog or VHDL netlist for functional simulation with EDA simulation 

tools. The Standard Delay Format Output File (.sdo) is not generated for the project. 

This option is not available for the VCS MX simulation tool. 

Boolean 



Notes 


Syntax 

set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST -section_id 

 

set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST -entity 

-section_id 

Default Value 





EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT 

EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT 

Type 

Directs the EDA Netlist Writer to generate a command script to run gate-level 

simulation with a third-party EDA tool. 

Boolean 



Syntax 


EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT -section_id 


EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT -entity - 

section_id 

Default Value 





EDA_GENERATE_POWER_INPUT_FILE 

EDA_GENERATE_POWER_INPUT_FILE 

Type 

Generates a Power Input File (.pwf) to perform power analysis in the Quartus II 

software when using third-party simulation tools. 

Boolean 



Notes 


Syntax 

set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE -section_id 

 

set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE -entity -section_id 

Default Value 





EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT 

EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT 

Type 

Directs the EDA Netlist Writer to generate a command script to run RTL functional 

simulation with a third-party EDA tool. 

Boolean 



Syntax 

set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT - 

section_id 

set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT - 


Default Value 





EDA_GENERATE_TIMING_CLOSURE_DATA 

EDA_GENERATE_TIMING_CLOSURE_DATA 

Type 

Generates back-annotation data for performing in-place optimization with the 

LeonardoSpectrum software. 

Boolean 



Notes 


Syntax 

set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA -section_id 

 

set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA -entity 

-section_id 

Default Value 





EDA_IBIS_MODEL_SELECTOR 

EDA_IBIS_MODEL_SELECTOR 

Type 

Enable or disable model selector feature for IBIS Writer. 

Boolean 



Syntax 

set_global_assignment -name EDA_IBIS_MODEL_SELECTOR -section_id 

set_global_assignment -name EDA_IBIS_MODEL_SELECTOR -entity 

-section_id 

Default Value 





EDA_IBIS_MUTUAL_COUPLING 

EDA_IBIS_MUTUAL_COUPLING 

Type 

Allows you to print the per pin RLC package model with mutual coupling when 

generating IBIS Output Files (.ibs) with the EDA Netlist Writer. The lumped RLC 

package model information appears in the IBIS Output File (.ibs). 

Boolean 



Syntax 

set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING -section_id 

set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING -entity 

-section_id 

Default Value 





EDA_IBIS_SPECIFICATION_VERSION 

EDA_IBIS_SPECIFICATION_VERSION 

Type 

Specifies the IBIS Specification version. 

Enumeration 

■ 4p1 

■ 4p2 

■ 5p0 



■ Stratix V 

Syntax 

set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION -section_id 

 

Default Value 

4p1, requires section identifier 




EDA_IPFS_FILE 

EDA_IPFS_FILE 

Type 

Specifies the library to which IPFS file should be compiled. 




Notes 


Syntax 

set_global_assignment -name EDA_IPFS_FILE -section_id 

 




EDA_LAUNCH_CMD_LINE_TOOL 

EDA_LAUNCH_CMD_LINE_TOOL 

Type 

Allows you to launch third-party EDA tools in the command-line mode rather than 

opening the graphical user interface. 

Boolean 



Notes 


Syntax 

set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL -section_id 

set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL -entity 

-section_id 

Default Value 





EDA_MAINTAIN_DESIGN_HIERARCHY 

EDA_MAINTAIN_DESIGN_HIERARCHY 

Type 

Maintain the original user design hierarchy when generating Verilog or VHDL 

simulation netlist for the project. 

Enumeration 

■ OFF 

■ ON 


■ PARTITION_ONLY 


Notes 


Syntax 

set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY -section_id 

 

set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY -entity -section_id 

Default Value 

OFF, requires section identifier 




EDA_MAP_ILLEGAL_CHARACTERS 

EDA_MAP_ILLEGAL_CHARACTERS 

Type 

Maps the vertical bar (|), tilde (~), and colon (:) characters in Quartus II hierarchical 

node names to the legal Verilog HDL characters z, x, and underscore (_), respectively, 

in Verilog Output Files. Turning on this option also maps other illegal nonalphanumeric 

characters, including brackets [], parentheses, (), angle brackets , and 

braces {} to underscores (_). 

Boolean 



Notes 


Syntax 

set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS -section_id 

 

set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS -entity -section_id 

Default Value 





EDA_NATIVELINK_GENERATE_SCRIPT_ONLY 

EDA_NATIVELINK_GENERATE_SCRIPT_ONLY 

Type 

Allows you to generate the script for a third-party EDA tool without running the EDA 

tool. 

Boolean 



Syntax 

set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY - 

section_id 

Default Value 





EDA_NATIVELINK_PORTABLE_FILE_PATHS 

EDA_NATIVELINK_PORTABLE_FILE_PATHS 

Type 

Specifies that the file paths in the generated third-party EDA tool command scripts 

should be written out using relative paths for design and testbench files, and by using 

a variable to refer to Quartus II simulation library path. 

Boolean 



Notes 


Syntax 

set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS -section_id 

 

set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS -entity 

-section_id 

Default Value 





EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT 

EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT 

Type 

Specifies the script for EDA Tool. After compiling models, design files and test bench 

files, Native Link uses this script to set up the simulation. 




Notes 


Syntax 

set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT - 

section_id 




EDA_NATIVELINK_SIMULATION_TEST_BENCH 

EDA_NATIVELINK_SIMULATION_TEST_BENCH 

Type 

Specifies the active logical name of the test bench, that will be used to perform 

NativeLink Simulation. 

String 



Notes 


Syntax 

set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH - 

section_id 




EDA_NETLIST_WRITER_OUTPUT_DIR 

EDA_NETLIST_WRITER_OUTPUT_DIR 

Type 

Specifies the output directory for EDA Netlist Writer. 




Notes 



Syntax 

set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR -section_id 

 




EDA_RESYNTHESIS_TOOL 

EDA_RESYNTHESIS_TOOL 

Type 

Specifies the EDA tool used for resynthesis. 

String 



Notes 



Syntax 

set_global_assignment -name EDA_RESYNTHESIS_TOOL 

set_global_assignment -name EDA_RESYNTHESIS_TOOL -entity 

 

Default Value 

None 




EDA_RTL_SIMULATION_RUN_SCRIPT 

EDA_RTL_SIMULATION_RUN_SCRIPT 

Type 

Specifies the script file for performing RTL simulation using third-party simulation 

software. 




Notes 


Syntax 

set_global_assignment -name EDA_RTL_SIMULATION_RUN_SCRIPT -section_id 

 

set_global_assignment -name EDA_RTL_SIMULATION_RUN_SCRIPT -entity -section_id 




EDA_RTL_SIM_MODE 

EDA_RTL_SIM_MODE 

Type 

Enables the Advanced Options—VHDL or Verilog Simulation options for Test Bench 

mode, or Command or macro mode. 

Enumeration 

■ COMMAND_MACRO_MODE 

■ NOT_USED 


■ TEST_BENCH_MODE 


Syntax 

set_global_assignment -name EDA_RTL_SIM_MODE -section_id 

set_global_assignment -name EDA_RTL_SIM_MODE -entity - 

section_id 

Default Value 

NOT_USED, requires section identifier 




EDA_RTL_TEST_BENCH_FILE_NAME 

EDA_RTL_TEST_BENCH_FILE_NAME 

Type 

Specifies the RTL simulation test bench file name for Test Bench Mode. File type can 

be a VHDL Test Bench File (.vht), VHDL File (.vhd), Verilog HDL Test Bench File (.vt), 

or Verilog HDL file (.v). 




Notes 


Syntax 

set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -section_id 

 

set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -entity -section_id 




EDA_RTL_TEST_BENCH_NAME 

EDA_RTL_TEST_BENCH_NAME 

Type 

Specifies the name of top-level test bench in RTL simulation test bench file. 

String 



Notes 


Syntax 

set_global_assignment -name EDA_RTL_TEST_BENCH_NAME -section_id 

set_global_assignment -name EDA_RTL_TEST_BENCH_NAME -entity 

-section_id 




EDA_RTL_TEST_BENCH_RUN_FOR 

EDA_RTL_TEST_BENCH_RUN_FOR 

Type 

Specifies the time duration for RTL simulation using third-party simulation. 

Time 



Syntax 

set_global_assignment -name EDA_RTL_TEST_BENCH_RUN_FOR -section_id 

 

set_global_assignment -name EDA_RTL_TEST_BENCH_RUN_FOR -entity -section_id 




EDA_SDC_FILE_NAME 

EDA_SDC_FILE_NAME 

Type 

Name of Design Constraints file to be sourced in scripts generated for third party 

tools 




Notes 


Syntax 

set_global_assignment -name EDA_SDC_FILE_NAME -section_id 

set_global_assignment -name EDA_SDC_FILE_NAME -entity - 

section_id 




EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED 

EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLE 

D 

Type 

Disables setup and hold time violations detection in input registers of bi-directional 

pins. 

Boolean 



Notes 


Syntax 


EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED -section_id 

 

Default Value 





EDA_SIMULATION_RUN_SCRIPT 

EDA_SIMULATION_RUN_SCRIPT 

Type 

Specifies the script file for running a third-party simulation in Command/macro 

mode. 




Notes 


Syntax 

set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT -section_id 

set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT -entity -section_id 




EDA_SIMULATION_TOOL 

EDA_SIMULATION_TOOL 

Type 

Specifies the third-party EDA tool used for simulation. 

String 



Notes 



Syntax 

set_global_assignment -name EDA_SIMULATION_TOOL 

set_global_assignment -name EDA_SIMULATION_TOOL -entity 

 

Default Value 

None 




EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE 

EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE 

Type 

Specifies which type of output signals should be written out to the Tcl file which can 

be used in a third-party EDA simulation tool to generate a Value Change Dump File 

(.vcd). Writing out all output signals to the Tcl file may result in a very large Value 

Change Dump File (.vcd) being generated by the third-party simulation tool. 

Enumeration 

■ All 


■ All Except Combinational Logic Element Outputs 


■ Arria GX 

■ Cyclone 


■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 




Syntax 

set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE 

-section_id 

Default Value 

All Except Combinational Logic Element Outputs, requires section identifier 




EDA_SIMULATION_VCD_OUTPUT_TCL_FILE 

EDA_SIMULATION_VCD_OUTPUT_TCL_FILE 

Type 

Specifies whether or not a Tcl file should be written out which can be used in a thirdparty 

EDA simulation tool to generate a Value Change Dump File (.vcd). 

Boolean 



■ Arria GX 

■ Cyclone 


■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 




Syntax 

set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE -section_id 

 

Default Value 





EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME 

EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME 

Type 

Specifies the name the Tcl file should be written to which can be used in a third-party 

EDA simulation tool to generate a Value Change Dump File (.vcd). 




■ Arria GX 

■ Cyclone 


■ MAX V 

■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

■ Stratix 




Notes 


Syntax 

set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME - 

section_id 




EDA_TEST_BENCH_DESIGN_INSTANCE_NAME 

EDA_TEST_BENCH_DESIGN_INSTANCE_NAME 

Type 

Specifies the instance name of the design entity in the test bench file. 

String 



Notes 


Syntax 

set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME - 

section_id 

set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME -entity 

-section_id 




EDA_TEST_BENCH_ENABLE_STATUS 

EDA_TEST_BENCH_ENABLE_STATUS 

Type 

Enables the Advanced Options—VHDL or Verilog Simulation options for Test Bench 

mode or Command/macro mode. 

Enumeration 

■ COMMAND_MACRO_MODE 

■ NOT_USED 


■ TEST_BENCH_MODE 


Syntax 

set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS -section_id 

 

set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS -entity -section_id 

Default Value 

NOT_USED, requires section identifier 




EDA_TEST_BENCH_ENTITY_MODULE_NAME 

EDA_TEST_BENCH_ENTITY_MODULE_NAME 

Type 

Specifies the top-level design entity in the test bench file. 

String 



Notes 


Syntax 

set_global_assignment -name EDA_TEST_BENCH_ENTITY_MODULE_NAME -section_id 

 

set_global_assignment -name EDA_TEST_BENCH_ENTITY_MODULE_NAME -entity 

-section_id 




EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB 

EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB 

Type 

Directs NativeLink to add extra simulation libraries to the specified module. This is 

required by the memory controllers (both new and legacy). 

String 



Notes 


Syntax 

set_global_assignment -name EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB - 

section_id 




EDA_TEST_BENCH_FILE 

EDA_TEST_BENCH_FILE 

Type 

Associates a test bench file with the logical test bench name. 




Notes 


Syntax 

set_global_assignment -name EDA_TEST_BENCH_FILE -section_id 




EDA_TEST_BENCH_FILE_NAME 

EDA_TEST_BENCH_FILE_NAME 

Type 

Specifies the test bench file name for Test Bench Mode. File type can be a VHDL Test 

Bench File (.vht), Verilog HDL Test Bench File (.vt), or another design file type. 




Notes 


Syntax 

set_global_assignment -name EDA_TEST_BENCH_FILE_NAME -section_id 

set_global_assignment -name EDA_TEST_BENCH_FILE_NAME -entity 

-section_id 




EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY 

EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY 

Type 

Specifies the simulation library to which the gate level netlist is compiled. 

String 



Notes 


Syntax 

set_global_assignment -name EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY - 

section_id 




EDA_TEST_BENCH_MODULE_NAME 

EDA_TEST_BENCH_MODULE_NAME 

Type 

Associates a test bench file with the logical test bench name. 

String 



Notes 


Syntax 

set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME -section_id 

 




EDA_TEST_BENCH_NAME 

EDA_TEST_BENCH_NAME 

Type 

Defines a logical name for test bench. Each test bench logical name has associated 

section, containing test bench information, and section_id being the logical test bench 

name. 

String 



Notes 


Syntax 

set_global_assignment -name EDA_TEST_BENCH_NAME -section_id 




EDA_TEST_BENCH_RUN_FOR 

EDA_TEST_BENCH_RUN_FOR 

Type 

Specifies the simulation run time for a third-party simulation in test bench mode. 

Time 



Syntax 

set_global_assignment -name EDA_TEST_BENCH_RUN_FOR -section_id 

set_global_assignment -name EDA_TEST_BENCH_RUN_FOR -entity - 

section_id 




EDA_TEST_BENCH_RUN_SIM_FOR 

EDA_TEST_BENCH_RUN_SIM_FOR 

Type 

Specifies the time interval for running EDA Simulation. 

Time 



Syntax 

set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR -section_id 

 




EDA_TIME_SCALE 

EDA_TIME_SCALE 

Type 

Specifies the time unit used to represent timing delays in each Verilog Output File 

(.vo). The value for the Time Scale option may be between 0.001 ns and 10ns, and 

should be a multiple of 10. 

String 



Notes 



Syntax 

set_global_assignment -name EDA_TIME_SCALE -section_id 

set_global_assignment -name EDA_TIME_SCALE -entity - 

section_id 




EDA_TIMING_ANALYSIS_TOOL 

EDA_TIMING_ANALYSIS_TOOL 

Type 

Specifies the EDA third-party tool used for timing analysis. 

String 



Notes 



Syntax 

set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL 

set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL -entity 

 

Default Value 

None 




EDA_TRUNCATE_LONG_HIERARCHY_PATHS 

EDA_TRUNCATE_LONG_HIERARCHY_PATHS 

Type 

Truncates hierarchical node names to 80 characters. 

Boolean 



Notes 


Syntax 

set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS -section_id 

 

set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS -entity 

-section_id 

Default Value 





EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY 

EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY 

Type 

Specifies the directory in which you store the library generated with the EDA 

Simulation Library Compiler tool. You should not use this option to specify the 

directory for ModelSim-Altera precompiled libraries or Active-HDL precompiled 

libraries. 




Notes 


Syntax 

set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY 

-section_id 

Default Value 

None, requires section identifier 




EDA_VHDL_ARCH_NAME 

EDA_VHDL_ARCH_NAME 

Type 

Specifies the name of Architecture in the generated VHDL simulation netlist. 

String 



Notes 



Syntax 

set_global_assignment -name EDA_VHDL_ARCH_NAME -section_id 

Default Value 

Structure, requires section identifier 




EDA_WAIT_FOR_GUI_TOOL_COMPLETION 

EDA_WAIT_FOR_GUI_TOOL_COMPLETION 

Type 

Specifies that NativeLink should wait for the EDA tool GUI launched by it to finish. 

Boolean 



Syntax 

set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION -section_id 

 

Default Value 





EDA_WRITER_DONT_WRITE_TOP_ENTITY 

EDA_WRITER_DONT_WRITE_TOP_ENTITY 

Type 

Do not write top-level entity in VHDL Output File (.vho). 

Boolean 



Notes 


Syntax 

set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY -section_id 

 

Default Value 





EDA_WRITE_DEVICE_CONTROL_PORTS 

EDA_WRITE_DEVICE_CONTROL_PORTS 

Type 

Adds the devpor, devclrn, and devoe signals in the design as input ports in the toplevel 

design hierarchy in the Verilog or VHDL simulation netlist for the project. 

Boolean 



Notes 


Syntax 

set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS -section_id 

 

set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS -entity -section_id 

Default Value 





EDA_WRITE_NODES_FOR_POWER_ESTIMATION 


Type 

Writes the script for the simulation tool to generate a Value Change Dump File (.vcd) 

for outputs for power estimation. 

Enumeration 

■ ALL_NODES 

■ NO_COMBINATIONAL_OUTPUT 

■ Off 



Notes 


Syntax 

set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION - 

section_id 

set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION -entity 

-section_id 

Default Value 








ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE 

Type 










June 2012 

9. Assembler Assignments 

Allows signaldetect to propagate from PCS to the core, which will be blocked if you 

fix the CDR lockup issue. This is because a PMA direct route is unavailable in Arria II 

GX devices. 

Boolean 




Notes 


Syntax 

set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE 

set_instance_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE -to 

 

Default Value 

Off 

ISO 

9001:2008 

Registered 

Subscribe

9–2 Chapter 9: Assembler Assignments 

AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE 

AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE 

Type 

Automatically increments the JTAG user code in the second and subsequent 

configuration devices if the target device requires multiple configuration devices. 

Boolean 



■ Cyclone 

■ Stratix 


Notes 


Syntax 

set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE 

 

Default Value 

On 

Old Names 


software: 

AUTO_INCREMENT_USER_JTAG_CODE 



Chapter 9: Assembler Assignments 9–3 

AUTO_RESTART_CONFIGURATION 


Type 

Directs the device to restart the configuration process automatically if a data error is 

encountered. If this option is turned off, you must externally direct the device to 

restart the configuration process if an error occurs. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 




■ Stratix 






■ Stratix V 

Notes 


Syntax 

set_global_assignment -name AUTO_RESTART_CONFIGURATION 





Default Value 

On 

Old Names 


software: 

Auto restart on configuration error 




CLOCK_SOURCE 

CLOCK_SOURCE 

Type 

Specifies whether the configuration device generates an internal clock or applies an 

external clock. 

Enumeration 

■ External 

■ Internal 



Notes 


Syntax 

set_global_assignment -name CLOCK_SOURCE 

Default Value 

Internal 




COMPRESSION_MODE 

COMPRESSION_MODE 

Type 

Allows you to compress SRAM Object Files (.sof) stored in a Programmer Object File 

(.pof) for a configuration device. 

Boolean 



Notes 


Syntax 

set_global_assignment -name COMPRESSION_MODE 

Default Value 

Off 




CONFIGURATION_CLOCK_DIVISOR 

CONFIGURATION_CLOCK_DIVISOR 

Type 

Specifies the clock frequency divisor, which is used to determine the period of the 

system clock. 

String 



Notes 


Syntax 

set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 

Default Value 

1 




CONFIGURATION_CLOCK_FREQUENCY 

CONFIGURATION_CLOCK_FREQUENCY 

Type 

Specifies the clock frequency of the configuration device. 

String 



Notes 


Syntax 

set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY 

Default Value 

10 MHz 




CYCLONEIII_CONFIGURATION_DEVICE 

CYCLONEIII_CONFIGURATION_DEVICE 

Type 

Specifies the configuration device that you want to use as the means of configuring 

the target device. 

String 







Notes 


Syntax 

set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE 

Default Value 

Auto 




CYCLONEII_M4K_COMPATIBILITY 

CYCLONEII_M4K_COMPATIBILITY 

Type 

Directs the Quartus II software to produce programming files that are compatible 

with both rev A and rev B silicon. This option applies only to the Cyclone II device 

family. For more information, refer to the Cyclone II FPGA Family Errata Sheet. 

Boolean 




Notes 


Syntax 

set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY 

Default Value 

On 




CYCLONE_CONFIGURATION_DEVICE 

CYCLONE_CONFIGURATION_DEVICE 

Type 


the target Cyclone device. 

String 



■ Cyclone 

Notes 


Syntax 

set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE 

Default Value 

Auto 




DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE 

DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE 

Type 

Disables the nCS and OE internal pull-ups on the configuration device(s). 

Boolean 



■ Stratix 


Notes 


Syntax 

set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE 

 

Default Value 

Off 

Old Names 


software: 

DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE 




ENABLE_AUTONOMOUS_PCIE_HIP 

ENABLE_AUTONOMOUS_PCIE_HIP 

Type 

Directs the device to release the PCIe HIP after the periphery is configured and before 

core configuration is completed. This option only takes effect if CvP mode is disabled. 

Boolean 



■ Arria V 

■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP 

Default Value 

Off 

Old Names 


software: 

AUTO_RESTART_ON_CONFIGURATION_ERROR 




ENABLE_OCT_DONE 

ENABLE_OCT_DONE 

Type 

This option controls whether the INIT_DONE signal is gated by the OCT_DONE signal 

which indicates the Power-Up OCT calibration is completed. If this option is turned 

off, the INIT_DONE signal is not gated by the OCT_DONE signal. 

Boolean 




■ Arria V 





■ Cyclone V 

■ Stratix V 

Notes 


Syntax 

set_global_assignment -name ENABLE_OCT_DONE 

Default Value 

Off 




EPROM_USE_CHECKSUM_AS_USERCODE 

EPROM_USE_CHECKSUM_AS_USERCODE 

Type 

Uses the checksum value from the Programmer Object File (.pof) as the JTAG user 

code. 

Boolean 



Notes 


Syntax 

set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE 

Default Value 

Off 




GENERATE_HEX_FILE 

GENERATE_HEX_FILE 

Type 

Generates a Hexadecimal (Intel-format) Output File (.hexout) containing 

configuration data that can be programmed into a parallel data source, such as an 

EPROM or a mass storage device, which then in turn configures the target device. 

Boolean 



Notes 


Syntax 

set_global_assignment -name GENERATE_HEX_FILE 

Default Value 

Off 




GENERATE_RBF_FILE 

GENERATE_RBF_FILE 

Type 

Generates a Raw Binary File (.rbf) containing configuration data that an intelligent 

external controller can use to configure the target device. 

Boolean 



Notes 


Syntax 

set_global_assignment -name GENERATE_RBF_FILE 

Default Value 

Off 




GENERATE_TTF_FILE 

GENERATE_TTF_FILE 

Type 

Generates a Tabular Text File (.ttf) containing configuration data that an intelligent 

external controller can use to configure the target device. 

Boolean 



Notes 


Syntax 

set_global_assignment -name GENERATE_TTF_FILE 

Default Value 

Off 




HARDCOPYII_POWER_ON_EXTRA_DELAY 

HARDCOPYII_POWER_ON_EXTRA_DELAY 

Type 

Directs the HardCopy chip to wait before the INIT_DONE pin goes high and before the 

chip is in user mode. 

Enumeration 

■ Off 

■ Wait 1 ms 

■ Wait 2 ms 

■ Wait 4 ms 

■ Wait 50 ms 

■ Wait 8 ms 






Notes 


Syntax 

set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY 

Default Value 

Off 




HEXOUT_FILE_COUNT_DIRECTION 

HEXOUT_FILE_COUNT_DIRECTION 

Type 

Specifies the count direction for the data in a Hexadecimal (Intel-Format) Output File 

(.hexout) as up or down. 

Enumeration 

■ Down 

■ Up 



Notes 


Syntax 

set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION 

Default Value 

Up 

Old Names 


software: 

HEX_FILE_COUNT_UP_DOWN 




HEXOUT_FILE_START_ADDRESS 

HEXOUT_FILE_START_ADDRESS 

Type 

Specifies the starting memory address for a Hexadecimal (Intel-Format) Output File 

(.hexout). 

String 



Notes 


Syntax 

set_global_assignment -name HEXOUT_FILE_START_ADDRESS 

Default Value 

0 




MAX7000S_JTAG_USER_CODE 

MAX7000S_JTAG_USER_CODE 

Type 

Specifies user-defined information about the target device. The JTAG user code is an 

extension of the option register. This data can be read with the JTAG USERCODE 

instruction. 

String 



■ MAX7000A 

■ MAX7000S 

Syntax 

set_global_assignment -name MAX7000S_JTAG_USER_CODE 

Default Value 

FFFF 




MAX7000_JTAG_USER_CODE 

MAX7000_JTAG_USER_CODE 

Type 



instruction. 

String 



■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

Syntax 

set_global_assignment -name MAX7000_JTAG_USER_CODE 

Default Value 

FFFFFFFF 




MAX7000_USE_CHECKSUM_AS_USERCODE 

MAX7000_USE_CHECKSUM_AS_USERCODE 

Type 

Sets the JTAG user code to match the checksum value of the device programming file. 

The programming file is a Programmer Object File (.pof) for non-volatile devices, 

such as MAX II devices, or an SRAM Object File (.sof) for SRAM-based devices. If you 

turn this option on, the JTAG user code option is not available. 

Boolean 



■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE 

Default Value 

Off 




ON_CHIP_BITSTREAM_DECOMPRESSION 

ON_CHIP_BITSTREAM_DECOMPRESSION 

Type 

Allows the device to accept and decompress bitstreams during configuration. 

Produces compressed bitstreams and enables bitstream decompression. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION 

Default Value 

On 




RELEASE_CLEARS_BEFORE_TRI_STATES 


Type 

Directs the device to release the clear signal on registered logic cells and I/O cells 

before releasing the output enable override on tri-state buffers. If this option is turned 

off, the output enable signals are released before the clear overrides are released. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 




■ Stratix 






■ Stratix V 

Notes 


Syntax 

set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES 





Default Value 

Off 

Old Names 


software: 

Release clears before tri-states 




RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND 

RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND 

Type 

Reserves all unused pins on the target device in one of three states: as inputs that are 

tri-stated, or as outputs that drive an unspecified signal. 

Enumeration 





■ MAX3000A 

■ MAX7000A 

■ MAX7000S 

Syntax 

set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND 

Default Value 

As output driving an unspecified signal 

Old Names 


software: 

RESERVED_ALL_UNUSED_PINS_NO_OUTPUT_GND 




SECURITY_BIT 

SECURITY_BIT 

Type 

Enables the security bit support, which prevents a device from being examined and 

reprogrammed. 

Boolean 




■ MAX V 

■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

Notes 


Syntax 

set_global_assignment -name SECURITY_BIT 

Default Value 

Off 




STRATIXII_CONFIGURATION_DEVICE 

STRATIXII_CONFIGURATION_DEVICE 

Type 



String 



■ Arria GX 



■ Arria V 

■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE 

Default Value 

Auto 

Old Names 


software: 

STRATIX_II_CONFIGURATION_DEVICE 




STRATIXII_MRAM_COMPATIBILITY 

STRATIXII_MRAM_COMPATIBILITY 

Directs the Quartus II software to produce programming files that are compatible with both rev A and 

rev B silicon. This option applies only to EP2S30, EP2S90, EP2S130, EP2S180. For more information, refer to 

the Stratix II FPGA Family Errata Sheet. 

Boolean 

Type 




Notes 


Syntax 

set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY 

Default Value 

Off 

Old Names 


software: 

STRATIXII_SILICON_VERSION 




STRATIX_CONFIGURATION_DEVICE 

STRATIX_CONFIGURATION_DEVICE 

Type 



String 





■ MAX V 

■ Stratix 


Notes 


Syntax 

set_global_assignment -name STRATIX_CONFIGURATION_DEVICE 

Default Value 

Auto 

Old Names 


software: 

YEAGER_CONFIGURATION_DEVICE 




STRATIX_CONFIG_DEVICE_JTAG_USER_CODE 

STRATIX_CONFIG_DEVICE_JTAG_USER_CODE 

Type 

Specifies user-defined information about the configuration device. The JTAG user 

code is an extension of the option register. This data can be read with the JTAG 

USERCODE instruction. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 


■ MAX V 

■ Stratix 






■ Stratix V 

Syntax 

set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE 

Default Value 

FFFFFFFF 




STRATIX_JTAG_USER_CODE 


Type 



instruction. 

String 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 





■ MAX V 

■ Stratix 






■ Stratix V 

Syntax 

set_global_assignment -name STRATIX_JTAG_USER_CODE 





Default Value 

FFFFFFFF 




USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT 

USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT 

Type 

Loads a checkered pattern as initial RAM content into all RAM blocks without 

specified RAM content that supports content initialization. Turning on this option 

does not affect simulation, which may cause on-chip behavior to differ from 

simulation results. 

Enumeration 

■ 0000 

■ 0101 

■ 1010 

■ 1111 

■ OFF 

■ ON 

■ RANDOM 





■ Arria V 

■ Cyclone V 

■ Stratix 




■ Stratix V 

Notes 


Syntax 


USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT 

Default Value 

OFF 




USE_CHECKSUM_AS_USERCODE 


Type 

Sets the JTAG user code to match the checksum value of the device programming file. 

The programming file is a Programmer Object File (.pof) for non-volatile devices, 

such as MAX II devices, or an SRAM Object File (.sof) for SRAM-based devices. If you 

turn this option on, the JTAG user code option is not available. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 




■ MAX V 

■ Stratix 






■ Stratix V 

Notes 






Syntax 

set_global_assignment -name USE_CHECKSUM_AS_USERCODE 

Default Value 

Off 




USE_CONFIGURATION_DEVICE 


Type 

Specifies that you intend to use a configuration device(s) such as the EPC2 as the 

means of configuring the target device. This option directs the Compiler to create a 

Programmer Output File (.pof) for programming the configuration device. If multiple 

configuration devices are needed, one Programmer Output File (.pof) is created for 

each device, with names of the following format: name.pof, name_1.pof, name_2.pof, 

and so on. 

Boolean 



■ Arria GX 



■ Cyclone 






■ EPC1 

■ EPC2 


■ FLEX10KB 

■ FLEX8000 





■ MAX V 

■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 





■ MAX9000 

■ Stratix 






■ Stratix V 

Notes 


Syntax 

set_global_assignment -name USE_CONFIGURATION_DEVICE 



ACLK_CAT 

Type 










June 2012 

10. Design Assistant Assignments 

Directs the Design Assistant to detect asynchronous clock domains on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name ACLK_CAT 

ISO 

9001:2008 

Registered 

Subscribe

10–2 Chapter 10: Design Assistant Assignments 

ACLK_RULE_IMSZER_ADOMAIN 

ACLK_RULE_IMSZER_ADOMAIN 

Type 

Directs the Design Assistant to detect improper synchronizer which moves data 

across asynchronous domain boundaries on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN 



Chapter 10: Design Assistant Assignments 10–3 

ACLK_RULE_NO_SZER_ACLK_DOMAIN 

ACLK_RULE_NO_SZER_ACLK_DOMAIN 

Type 

Directs the Design Assistant to detect synchronizer between asynchronous clock 

domains on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN 




ACLK_RULE_SZER_BTW_ACLK_DOMAIN 

ACLK_RULE_SZER_BTW_ACLK_DOMAIN 

Type 

Directs the Design Assistant to detect synchronizer for every signal between 

asynchronous clock domains on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN 




CLK_CAT 

CLK_CAT 

Type 

Directs the Design Assistant to check all clock-related violations on the design. 

Expand the items to turn off the rule checking if irrelevant. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name CLK_CAT 




CLK_RULE_CLKNET_CLKSPINES 

CLK_RULE_CLKNET_CLKSPINES 

Type 

Directs the Design Assistant to check clock net not mapped to clock spines used on the 

design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES 




CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 

CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 

Type 

Specifies the Threshold value for clock net not mapped to clock spines rule. 

Integer 



Syntax 

set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 

Default Value 

25 




CLK_RULE_COMB_CLOCK 

CLK_RULE_COMB_CLOCK 

Type 

Directs the Design Assistant to check combinatorial logic output used as on-chip clock 

on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name CLK_RULE_COMB_CLOCK 




CLK_RULE_GATED_CLK_FANOUT 

CLK_RULE_GATED_CLK_FANOUT 

Type 

Directs the Design Assistant to check gated clock have feed to certain number of clock 

port to effectively save power. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name CLK_RULE_GATED_CLK_FANOUT 




CLK_RULE_INPINS_CLKNET 

CLK_RULE_INPINS_CLKNET 

Type 

Directs the Design Assistant to check illegal input pins connected to clock net used on 

the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name CLK_RULE_INPINS_CLKNET 




CLK_RULE_INV_CLOCK 

CLK_RULE_INV_CLOCK 

Type 

Directs the Design Assistant to check inverted clock used on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name CLK_RULE_INV_CLOCK 




CLK_RULE_MIX_EDGES 

CLK_RULE_MIX_EDGES 

Type 

Directs the Design Assistant to check mixed-clock edges used on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name CLK_RULE_MIX_EDGES 




DA_CUSTOM_RULE_FILE 

DA_CUSTOM_RULE_FILE 

Type 

Sets the path for the Design Assistant custom rule file. 




Notes 


Syntax 

set_global_assignment -name DA_CUSTOM_RULE_FILE 




DISABLE_DA_GX_RULE 

DISABLE_DA_GX_RULE 

Type 

Prevents Design Assistant from running when the Fitter is running. 

String 



Syntax 

set_global_assignment -name DISABLE_DA_GX_RULE 

set_instance_assignment -name DISABLE_DA_GX_RULE -to -entity 




DISABLE_DA_RULE 

DISABLE_DA_RULE 

Type 

Suppresses the Design Assistant rule locally, or turns off the Design Assistant rule 

globally for the general user 

String 



Syntax 

set_global_assignment -name DISABLE_DA_RULE 

set_instance_assignment -name DISABLE_DA_RULE -to -entity 




DRC_DEADLOCK_STATE_LIMIT 

DRC_DEADLOCK_STATE_LIMIT 

Type 

Specifies the maximum number of states that you want the Design Assistant to detect 

as a deadlock condition. A larger number results in longer processing time. 

Integer 



Syntax 

set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 

Default Value 

2 




DRC_DETAIL_MESSAGE_LIMIT 

DRC_DETAIL_MESSAGE_LIMIT 

Type 

Specifies the maximum number of detail messages that you want the Design Assistant 

to report. 

Integer 



Syntax 

set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 

Default Value 

10 




DRC_FANOUT_EXCEEDING 

DRC_FANOUT_EXCEEDING 

Type 

Specifies the minimum amount of fan-out that a node must have to be reported by the 

Design Assistant. 

Integer 



Syntax 

set_global_assignment -name DRC_FANOUT_EXCEEDING 

Default Value 

30 




DRC_GATED_CLOCK_FEED 

DRC_GATED_CLOCK_FEED 

Type 

Specifies the minimum amount of clock port a gated clock must feed so that it's an 

acceptable gated clock. 

Integer 



Syntax 

set_global_assignment -name DRC_GATED_CLOCK_FEED 

Default Value 

30 




DRC_REPORT_FANOUT_EXCEEDING 

DRC_REPORT_FANOUT_EXCEEDING 

Type 

Directs the Design Assistant to report all nodes with more than the specified amount 

of fan-out. 

Boolean 



Syntax 

set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING 




DRC_REPORT_TOP_FANOUT 

DRC_REPORT_TOP_FANOUT 

Type 

Directs the Design Assistant to report the specified number of nodes with the highest 

fan-out. 

Boolean 



Syntax 

set_global_assignment -name DRC_REPORT_TOP_FANOUT 




DRC_TOP_FANOUT 

DRC_TOP_FANOUT 

Type 

Specifies the number of nodes with the highest fan-out that you want the Design 

Assistant to report. 

Integer 



Syntax 

set_global_assignment -name DRC_TOP_FANOUT 

Default Value 

50 




DRC_VIOLATION_MESSAGE_LIMIT 

DRC_VIOLATION_MESSAGE_LIMIT 

Type 

Specifies the maximum number of violation messages that you want the Design 

Assistant to report. 

Integer 



Syntax 

set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 

Default Value 

30 




ENABLE_DA_RULE 

ENABLE_DA_RULE 

Type 

Desuppresses the Design Assistant rule locally, or turns on the Design Assistant rule 

globally for the general user. 

String 



Syntax 

set_global_assignment -name ENABLE_DA_RULE 

set_instance_assignment -name ENABLE_DA_RULE -to -entity 




ENABLE_DRC_SETTINGS 

ENABLE_DRC_SETTINGS 

Type 

Directs the Design Assistant to run during a compilation based on user settings. 

Boolean 



Syntax 

set_global_assignment -name ENABLE_DRC_SETTINGS 

Default Value 

Off 




FSM_CAT 

FSM_CAT 

Type 

Directs the Design Assistant to detect finite state machine rules in your design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name FSM_CAT 




FSM_RULE_DEADLOCK_STATE 

FSM_RULE_DEADLOCK_STATE 

Type 

Directs the Design Assistant to detect deadlock states in state machine in your design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name FSM_RULE_DEADLOCK_STATE 




FSM_RULE_NO_RESET_STATE 

FSM_RULE_NO_RESET_STATE 

Type 

Directs the Design Assistant to detect if the reset state is specified for the state 

machine in your design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name FSM_RULE_NO_RESET_STATE 




FSM_RULE_NO_SZER_ACLK_DOMAIN 

FSM_RULE_NO_SZER_ACLK_DOMAIN 

Type 

Directs the Design Assistant to detect the synchronizer between asynchronous clock 

domains feeding to the state machine in your design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name FSM_RULE_NO_SZER_ACLK_DOMAIN 




FSM_RULE_UNREACHABLE_STATE 

FSM_RULE_UNREACHABLE_STATE 

Type 

Directs the Design Assistant to detect an unreachable state in the state machine in 

your design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name FSM_RULE_UNREACHABLE_STATE 




FSM_RULE_UNUSED_TRANSITION 

FSM_RULE_UNUSED_TRANSITION 

Type 

Directs the Design Assistant to detect an unused transition in the state machine in 

your design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name FSM_RULE_UNUSED_TRANSITION 




HARDCOPY_FLOW_AUTOMATION 

HARDCOPY_FLOW_AUTOMATION 

Type 

Specifies which HardCopy flow is run in the HardCopy timing wizard 

Enumeration 


■ COMPILE_NEW_PROJECT 

■ FULL_COMPILATION 

■ MIGRATION_ONLY 


Syntax 

set_global_assignment -name HARDCOPY_FLOW_AUTOMATION 

Default Value 

MIGRATION_ONLY 




HARDCOPY_NEW_PROJECT_PATH 

HARDCOPY_NEW_PROJECT_PATH 

Type 

Specifies the directory path for the new or migrated HardCopy project. 

String 



Notes 


Syntax 

set_global_assignment -name HARDCOPY_NEW_PROJECT_PATH 




HCPY_CAT 

HCPY_CAT 

Type 

Directs the Design Assistant to detect HardCopy rules in your design. All HardCopy 

rules apply to HardCopy devices only. 

Boolean 



Syntax 

set_global_assignment -name HCPY_CAT 




NONSYNCHSTRUCT_CAT 

NONSYNCHSTRUCT_CAT 

Type 

Directs the Design Assistant to check for non-synchronous design structures on the 

design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name NONSYNCHSTRUCT_CAT 




NONSYNCHSTRUCT_RULE_COMBLOOP 

NONSYNCHSTRUCT_RULE_COMBLOOP 

Type 

Directs the Design Assistant to check for combinatorial loop with unidentified 

function on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP 




NONSYNCHSTRUCT_RULE_DELAY_CHAIN 

NONSYNCHSTRUCT_RULE_DELAY_CHAIN 

Type 

Directs the Design Assistant to check for delay chain with unidentified function on 

the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN 




NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN 

NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN 

Type 

Directs the Design Assistant to check illegal pulse generator on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN 




NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED 

NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED 

Type 

Directs the Design Assistant to detect latch of unidentified type on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED 




NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR 

NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR 

Type 

Directs the Design Assistant to check multi-vibrator on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR 




NONSYNCHSTRUCT_RULE_REG_LOOP 

NONSYNCHSTRUCT_RULE_REG_LOOP 

Type 

Directs the Design Assistant to check for combinatorial loop with output of register 

feeding its own control signal on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP 




NONSYNCHSTRUCT_RULE_RIPPLE_CLK 

NONSYNCHSTRUCT_RULE_RIPPLE_CLK 

Type 

Directs the Design Assistant to check ripple clock structure on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK 




NONSYNCHSTRUCT_RULE_SRLATCH 

NONSYNCHSTRUCT_RULE_SRLATCH 

Type 

Directs the Design Assistant to detect SR-latch on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH 




RESET_CAT 

RESET_CAT 

Type 

Directs the Design Assistant to check reset-related violations on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name RESET_CAT 




RESET_RULE_COMB_ASYNCH_RESET 

RESET_RULE_COMB_ASYNCH_RESET 

Type 

Directs the Design Assistant to check combinatorial logic output used as on-chip 

asynchronous reset on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET 




RESET_RULE_IMSYNCH_ASYNCH_DOMAIN 

RESET_RULE_IMSYNCH_ASYNCH_DOMAIN 

Type 

Directs the Design Assistant to check for reset which is improperly synchronized in 

receiving asynchronous domain on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN 




RESET_RULE_IMSYNCH_EXRESET 

RESET_RULE_IMSYNCH_EXRESET 

Type 

Directs the Design Assistant to check improper synchronization of external reset on 

the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET 




RESET_RULE_UNSYNCH_ASYNCH_DOMAIN 

RESET_RULE_UNSYNCH_ASYNCH_DOMAIN 

Type 

Directs the Design Assistant to check for reset which is not synchronized in receiving 

asynchronous domain on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN 




RESET_RULE_UNSYNCH_EXRESET 

RESET_RULE_UNSYNCH_EXRESET 

Type 

Suppresses unsynchronized external reset rule. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET 




SIGNALRACE_CAT 

SIGNALRACE_CAT 

Type 

Directs the Design Assistant to check signal race on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name SIGNALRACE_CAT 




SIGNALRACE_RULE_CLK_PORT_RACE 

SIGNALRACE_RULE_CLK_PORT_RACE 

Type 

Directs the Design Assistant to check race condition between clock port and any other 

port of the same register. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name SIGNALRACE_RULE_CLK_PORT_RACE 




SIGNALRACE_RULE_RESET_RACE 

SIGNALRACE_RULE_RESET_RACE 

Type 

Directs the Design Assistant to detect synchronous port and asynchronous port of 

same register driven by same signal source 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name SIGNALRACE_RULE_RESET_RACE 




SIGNALRACE_RULE_SECOND_SIGNAL_RACE 

SIGNALRACE_RULE_SECOND_SIGNAL_RACE 

Type 

Directs the Design Assistant to detect more than one secondary signal of same register 

driven by same signal source 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name SIGNALRACE_RULE_SECOND_SIGNAL_RACE 




SIGNALRACE_RULE_TRISTATE 

SIGNALRACE_RULE_TRISTATE 

Type 

Directs the Design Assistant to detect Tri-state signal race condition. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name SIGNALRACE_RULE_TRISTATE 




TIMING_CAT 

TIMING_CAT 

Type 

Directs the Design Assistant to check timing closure related violations on the design. 

Boolean 



■ Cyclone 


■ MAX V 

■ Stratix 


Syntax 

set_global_assignment -name TIMING_CAT 




TIMING_CAT 



EXCALIBUR_HEX_FILE 

Type 










June 2012 

11. Programmer Assignments 

Specifies the Hexadecimal (Intel-Format) File (.hex) to be used with the e 

Programmable Logic Partial SRAM Object File (.psof) to generate passive 

programming files. 




Notes 


Syntax 

set_global_assignment -name EXCALIBUR_HEX_FILE 

ISO 

9001:2008 

Registered 

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11–2 Chapter 11: Programmer Assignments 

GENERATE_CONFIG_HEXOUT_FILE 

GENERATE_CONFIG_HEXOUT_FILE 

Type 

Generates a Hexadecimal (Intel-format) Output File (.hexout) containing 

configuration data that can be programmed into a parallel data source, such as an 

EPROM or a mass storage device, which then in turn configures the target device. 

Boolean 




Notes 


Syntax 

set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE 

Default Value 

Off 



Chapter 11: Programmer Assignments 11–3 

GENERATE_CONFIG_ISC_FILE 

GENERATE_CONFIG_ISC_FILE 

Type 

Generates an In System Configuration File (.isc) containing configuration data that an 

intelligent external controller can use to configure the target device. 

Boolean 




Notes 


Syntax 

set_global_assignment -name GENERATE_CONFIG_ISC_FILE 

Default Value 

Off 




GENERATE_CONFIG_JAM_FILE 

GENERATE_CONFIG_JAM_FILE 

Type 

Generates a JEDEC STAPL Format File (.jam) containing configuration data that an 


Boolean 



■ EPC2 


Notes 


Syntax 

set_global_assignment -name GENERATE_CONFIG_JAM_FILE 

Default Value 

Off 




GENERATE_CONFIG_JBC_FILE 

GENERATE_CONFIG_JBC_FILE 

Type 

Directs the programmer to generate a compressed JAM Byte Code File (.jbc) 

containing configuration data that an intelligent external controller can use to 

configure the target device. 

Boolean 



■ EPC2 


Notes 


Syntax 

set_global_assignment -name GENERATE_CONFIG_JBC_FILE 

Default Value 

Off 




GENERATE_CONFIG_JBC_FILE_COMPRESSED 

GENERATE_CONFIG_JBC_FILE_COMPRESSED 

Type 

Directs the programmer to generate a compressed JAM Byte Codec File (.jbc) 



Boolean 



■ EPC2 


Notes 


Syntax 

set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED 

Default Value 

On 




GENERATE_CONFIG_SVF_FILE 

GENERATE_CONFIG_SVF_FILE 

Type 

Generates a Serial Vector Format File (.svf) containing configuration data that an 


Boolean 



■ EPC2 


Notes 


Syntax 

set_global_assignment -name GENERATE_CONFIG_SVF_FILE 

Default Value 

Off 




GENERATE_ISC_FILE 

GENERATE_ISC_FILE 

Type 

Directs the programmer to generate an In System Configuration File (.isc) containing 

configuration data that an intelligent external controller can use to configure the 

target device. 

Boolean 



■ MAX3000A 

■ MAX7000AE 

■ MAX7000B 

Notes 

This assignment is included in the Assembler report. 

Syntax 

set_global_assignment -name GENERATE_ISC_FILE 

Default Value 

Off 




GENERATE_JAM_FILE 


Type 

Directs the programmer to generate a JEDEC JESD71 STAPL Format File (.jam) 



Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 


■ MAX V 

■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name GENERATE_JAM_FILE 

Default Value 

Off 




GENERATE_JBC_FILE 


Type 

Directs the programmer to generate a compressed JAM Byte Code File (.jbc) 



Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 


■ MAX V 

■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name GENERATE_JBC_FILE 

Default Value 

Off 




GENERATE_JBC_FILE_COMPRESSED 


Type 

Generates a compressed JAM Byte Code File (.jbc) containing configuration data that 

an intelligent external controller can use to configure the target device. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 


■ MAX V 

■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED 

Default Value 

On 




GENERATE_SVF_FILE 


Type 

Directs the programmer to generate a Serial Vector Format File (.svf) containing 

configuration data that an intelligent external controller can use to configure the 

target device. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 


■ MAX V 

■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

■ Stratix 






■ Stratix V 





Notes 


Syntax 

set_global_assignment -name GENERATE_SVF_FILE 

Default Value 

Off 




ISP_CLAMP_STATE 

ISP_CLAMP_STATE 

Type 

Specifies the pin state during in-system programming. This option is ignored if it is 

assigned to anything other than pins. 

Enumeration 

■ High 

■ Low 

■ Sample and Sustain 

■ Tri-state 




■ MAX V 

■ MAX7000B 

Syntax 

set_instance_assignment -name ISP_CLAMP_STATE -to -entity 




ISP_CLAMP_STATE_DEFAULT 

ISP_CLAMP_STATE_DEFAULT 

Type 

For used pins that do not have an in-system programming clamp state assignment, 

this option allows you to specify the state that the pins take during in-system 

programming. Unused pins and dedicated inputs must always be tri-stated for insystem 

programming. 

Enumeration 

■ High 

■ Low 

■ Sample and Sustain 

■ Tri-state 




■ MAX V 

■ MAX7000B 

Notes 


Syntax 

set_global_assignment -name ISP_CLAMP_STATE_DEFAULT 

Default Value 

Tri-state 




MERGE_HEX_FILE 


Type 

Uses the Hexadecimal (Intel-Format) File (.hex) and the programmable logic Partial 

SRAM Object File (.psof) to create passive programming files. 

Boolean 



Syntax 

set_global_assignment -name MERGE_HEX_FILE 

Default Value 

Off 







ENABLE_LOGIC_ANALYZER_INTERFACE 

Type 










June 2012 

Enables the Logic Analyzer Interface for compilation. 

Boolean 


12. SignalTap II Assignments 


Notes 


Syntax 

set_global_assignment -name ENABLE_LOGIC_ANALYZER_INTERFACE 

ISO 

9001:2008 

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12–2 Chapter 12: SignalTap II Assignments 

ENABLE_SIGNALTAP 

ENABLE_SIGNALTAP 

Type 

Enables the SignalTap II Logic Analyzer for compilation. 

Boolean 



Notes 


Syntax 

set_global_assignment -name ENABLE_SIGNALTAP 



Chapter 12: SignalTap II Assignments 12–3 

STP_FILE 

STP_FILE 

Type 

Associates a SignalTap II Logic Analyzer File with this project. 




Notes 


Syntax 

set_global_assignment -name STP_FILE 




USE_LOGIC_ANALYZER_INTERFACE_FILE 

USE_LOGIC_ANALYZER_INTERFACE_FILE 

Type 

Specifies the Logic Analyzer Interface File (.lai) to be used for compilation. 




Notes 



Syntax 

set_global_assignment -name USE_LOGIC_ANALYZER_INTERFACE_FILE 



Chapter 12: SignalTap II Assignments 12–5 

USE_SIGNALTAP_FILE 


Type 

Specifies the SignalTap II Logic Analyzer File to be used for compilation. 




C 

Notes 



Syntax 

set_global_assignment -name USE_SIGNALTAP_FILE 

SignalTap II Assignments 







LL_AUTO_SIZE 

Type 










June 2012 

13. LogicLock Region Assignments 

Specifies whether the LogicLock region is auto-sized. The Compiler determines an 

appropriate size for auto-sized regions during compilation. If this keyword is set to 

On, LL_STATE must be set to Floating. 

Enumeration 

■ Off 

■ On 



Notes 


devices. 

Syntax 

set_global_assignment -name LL_AUTO_SIZE -entity -section_id 

 

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13–2 Chapter 13: LogicLock Region Assignments 

LL_ENABLED 

LL_ENABLED 

Type 

Specifies whether the region is enabled. 

Boolean 



Notes 


devices. 

Syntax 

set_global_assignment -name LL_ENABLED -entity -section_id 

 



Chapter 13: LogicLock Region Assignments 13–3 

LL_HEIGHT 

LL_HEIGHT 

Type 

Specifies the height of the LogicLock region in rows. 

Integer 



Notes 


devices. 

Syntax 

set_global_assignment -name LL_HEIGHT -entity -section_id 

 




LL_MEMBER_EXCEPTIONS 

LL_MEMBER_EXCEPTIONS 

Type 

If specified, the Fitter assigns all nodes under the target design entity or path to be 

members of the LogicLock region, except for nodes of the specified types. 

String 



■ Arria GX 

■ Cyclone 



■ MAX V 

■ Stratix 




Notes 



devices. 

Syntax 

set_global_assignment -name LL_MEMBER_EXCEPTIONS -entity - 

section_id 

set_instance_assignment -name LL_MEMBER_EXCEPTIONS -to -entity 

-section_id 

set_instance_assignment -name LL_MEMBER_EXCEPTIONS -from -to - 


Old Names 


software: 

LL_MEMBER_RESOURCE_EXCLUDE 




LL_MEMBER_OF 

LL_MEMBER_OF 

Type 

Assigns the current node(s) to a LogicLock region. 

String 



■ Arria GX 

■ Cyclone 



■ MAX V 

■ Stratix 




Notes 



devices. 


Syntax 

set_global_assignment -name LL_MEMBER_OF -entity -section_id 

 

set_instance_assignment -name LL_MEMBER_OF -to -entity - 

section_id 

set_instance_assignment -name LL_MEMBER_OF -from -to -entity 

-section_id 




LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE 

LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE 

Type 

Assigns the current signal to a security routing interface. 

String 



Notes 



devices. 


Syntax 

set_instance_assignment -name LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE -to 





LL_ORIGIN 

LL_ORIGIN 

Type 

Specifies the location of the origin of the LogicLock region. For APEX 20K and APEX 

II devices, the origin is the top left corner of the region. For newer devices, the origin 

is the bottom left corner of the region. The origin of a LogicLock region is specified as 

an absolute location on the device, regardless of whether the region is a top-level 

LogicLock region or a child LogicLock region. However, if the region is a child 

LogicLock region, the Quartus II software interprets the origin as a relative offset from 

the origin of the parent region. If LL_STATE is set to Locked, the Compiler places the 

LogicLock region at this location. If LL_STATE is set to Floating, the Compiler is free 

to determine an appropriate location for the region during compilation. 

Location 



Notes 


devices. 

Syntax 

set_global_assignment -name LL_ORIGIN -entity -section_id 

 




LL_PARENT 

LL_PARENT 

Type 

Specifies the name of the LogicLock region's parent LogicLock region. 

String 



Notes 



devices. 

Syntax 

set_global_assignment -name LL_PARENT -entity -section_id 

 




LL_PRIORITY 

LL_PRIORITY 

Type 

Indicates the priority of a wildcard or path-based LL_MEMBER_OF assignment 

relative to other wildcard or path-based LL_MEMBER_OF assignments. If a node 

matches more than one wildcard or path-based LL_MEMBER_OF assignment target, 

the assignment of which the target has the highest LL_PRIORITY value wins. 

Integer 



■ Arria GX 

■ Cyclone 



■ MAX V 

■ Stratix 




Notes 


devices. 

Syntax 

set_instance_assignment -name LL_PRIORITY -to -entity - 

section_id 

set_instance_assignment -name LL_PRIORITY -from -to -entity 

-section_id 




LL_RESERVED 

LL_RESERVED 

Type 

If set to On, the setting prevents the Fitter from placing non-member logic in the 

region. 

Boolean 



Notes 


devices. 

Syntax 

set_global_assignment -name LL_RESERVED -entity -section_id 

 

Old Names 


software: 

LL_RESERVE 




LL_ROOT_REGION 

LL_ROOT_REGION 

Type 

Indicates that the LogicLock region is a root region. 

Boolean 



Notes 


devices. 

Syntax 

set_global_assignment -name LL_ROOT_REGION -entity - 

section_id 




LL_STATE 

LL_STATE 

Type 

Specifies whether the location of the LogicLock region is locked or floating. The 

Compiler determines an appropriate location for floating regions during compilation. 

If this keyword is set to Locked, LL_AUTO_SIZE must be set to Off. 

Enumeration 

■ Floating 

■ Locked 

■ Soft 



Notes 


devices. 

Syntax 

set_global_assignment -name LL_STATE -entity -section_id 

 




LL_WIDTH 

LL_WIDTH 

Type 

Specifies the width of the LogicLock region in logic array blocks (LABs) or embedded 

system blocks (ESBs). 

Integer 



Notes 


devices. 

Syntax 

set_global_assignment -name LL_WIDTH -entity -section_id 

 




LL_WIDTH 



MIGRATION_AUTO_PACKED_REGISTERS 

Type 










June 2012 

14. Migration Assignments 

Register Packings that have been performed on a prototype device and that must be 

reproduced on the target migration device. 

String 



■ Arria GX 







Notes 


Syntax 

set_instance_assignment -name MIGRATION_AUTO_PACKED_REGISTERS -to - 

entity 

set_instance_assignment -name MIGRATION_AUTO_PACKED_REGISTERS -from 

-to -entity 

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14–2 Chapter 14: Migration Assignments 

MIGRATION_AUTO_PORT_SWAP 

MIGRATION_AUTO_PORT_SWAP 

Type 

Port Swappings that have been performed on a prototype device and that must be 

reproduced on the target migration device. 

String 



■ Arria GX 







Notes 


Syntax 

set_instance_assignment -name MIGRATION_AUTO_PORT_SWAP -to -entity 

 



Chapter 14: Migration Assignments 14–3 

MIGRATION_RAM_INFORMATION 


Type 

RAMs that have been created on a prototype device and that must be reproduced on 

the target migration device. 

String 



■ Arria GX 







Notes 


Syntax 

set_instance_assignment -name MIGRATION_RAM_INFORMATION -to -entity 

 



14–4 Chapter 14: Migration Assignments 




RTLV_GROUP_COMB_LOGIC_IN_CLOUD 

Type 










June 2012 

15. Netlist Viewer Assignments 

Allows the RTL Viewer to group combinational logic in a logic cloud. 

Boolean 



Syntax 

set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD 

Default Value 

Off 

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15–2 Chapter 15: Netlist Viewer Assignments 

RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV 

RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV 

Type 

Allows the Technology Map Viewer to group combinational logic in a logic cloud. 

Boolean 



Syntax 

set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV 

Default Value 

Off 



Chapter 15: Netlist Viewer Assignments 15–3 

RTLV_GROUP_RELATED_NODES 

RTLV_GROUP_RELATED_NODES 

Type 

Allows the RTL Viewer to group all related nodes into a single bus node. 

Boolean 



Syntax 

set_global_assignment -name RTLV_GROUP_RELATED_NODES 

Default Value 

On 




RTLV_GROUP_RELATED_NODES_TMV 

RTLV_GROUP_RELATED_NODES_TMV 

Type 

Allows the Technology Map Viewer to group all related nodes into a single bus node. 

Boolean 



Syntax 

set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV 

Default Value 

On 



Chapter 15: Netlist Viewer Assignments 15–5 

RTLV_REMOVE_FANOUT_FREE_REGISTERS 

RTLV_REMOVE_FANOUT_FREE_REGISTERS 

Type 

Allows the RTL Viewer to remove fanout free registers. 

Boolean 



Syntax 

set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS 

Default Value 

On 




RTLV_SIMPLIFIED_LOGIC 

RTLV_SIMPLIFIED_LOGIC 

Type 

Allows the RTL Viewer to remove wire nodes and merge chain of equivalent 

combinatorial gates. 

Boolean 



Syntax 

set_global_assignment -name RTLV_SIMPLIFIED_LOGIC 

Default Value 

On 



BOARD_MODEL_EBD_FAR_END 

Type 










June 2012 

16. Advanced I/O Timing Assignments 

Specifies the far-end node to be used in the Electronic Board Description (EBD) path 

description. 

String 



Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_EBD_FAR_END -to -entity 

 

ISO 

9001:2008 

Registered 

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16–2 Chapter 16: Advanced I/O Timing Assignments 

BOARD_MODEL_EBD_FILE_NAME 

BOARD_MODEL_EBD_FILE_NAME 

Type 

Specifies the Electronic Board Description (EBD) file that contains the path description 

for an I/O pin. 

String 



Notes 



Syntax 

set_instance_assignment -name BOARD_MODEL_EBD_FILE_NAME -to -entity 

 



Chapter 16: Advanced I/O Timing Assignments 16–3 

BOARD_MODEL_EBD_SIGNAL_NAME 

BOARD_MODEL_EBD_SIGNAL_NAME 

Type 

Specifies the Electronic Board Description (EBD) path description to be used with an 

I/O pin. You must specify the EBD file name. 

String 



Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_EBD_SIGNAL_NAME -to -entity 

 




BOARD_MODEL_FAR_C 

BOARD_MODEL_FAR_C 

Type 

Specifies, in farads, the board trace model far capacitance. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_FAR_C -to -entity 

set_global_assignment -name BOARD_MODEL_FAR_C -section_id 




BOARD_MODEL_FAR_DIFFERENTIAL_R 

BOARD_MODEL_FAR_DIFFERENTIAL_R 

Type 

Specifies, in ohms, the board trace model far differential resistance. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -to - 

entity 

set_global_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -section_id 

 




BOARD_MODEL_FAR_PULLDOWN_R 

BOARD_MODEL_FAR_PULLDOWN_R 

Type 

Specifies, in ohms, the board trace model far pull-down resistance. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -to -entity 

 

set_global_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -section_id 

 




BOARD_MODEL_FAR_PULLUP_R 

BOARD_MODEL_FAR_PULLUP_R 

Type 

Specifies, in ohms, the board trace model far pull-up resistance. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_FAR_PULLUP_R -to -entity 

 

set_global_assignment -name BOARD_MODEL_FAR_PULLUP_R -section_id 




BOARD_MODEL_FAR_SERIES_R 

BOARD_MODEL_FAR_SERIES_R 

Type 

Specifies, in ohms, the board trace model far series resistance. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R -to -entity 

 

set_global_assignment -name BOARD_MODEL_FAR_SERIES_R -section_id 




BOARD_MODEL_NEAR_C 

BOARD_MODEL_NEAR_C 

Type 

Specifies, in farads, the board trace model near capacitance. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_NEAR_C -to -entity 

set_global_assignment -name BOARD_MODEL_NEAR_C -section_id 




BOARD_MODEL_NEAR_DIFFERENTIAL_R 

BOARD_MODEL_NEAR_DIFFERENTIAL_R 

Type 

Specifies, in ohms, the board trace model near differential resistance. 

String 





■ Arria V 





■ Cyclone V 






■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -to - 

entity 

set_global_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -section_id 

 




BOARD_MODEL_NEAR_PULLDOWN_R 

BOARD_MODEL_NEAR_PULLDOWN_R 

Type 

Specifies, in ohms, the board trace model near pull-down resistance. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -to -entity 

 

set_global_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -section_id 

 




BOARD_MODEL_NEAR_PULLUP_R 

BOARD_MODEL_NEAR_PULLUP_R 

Type 

Specifies, in ohms, the board trace model near pull-up resistance. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R -to -entity 

 

set_global_assignment -name BOARD_MODEL_NEAR_PULLUP_R -section_id 




BOARD_MODEL_NEAR_SERIES_R 

BOARD_MODEL_NEAR_SERIES_R 

Type 

Specifies, in ohms, the board trace model near series resistance. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R -to -entity 

 

set_global_assignment -name BOARD_MODEL_NEAR_SERIES_R -section_id 




BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 

BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 

Type 

Specifies, in farads or inches, the board trace model near transmission line distributed 

capacitance. 

String 





■ Arria V 





■ Cyclone V 






■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH -to 

-entity 

set_global_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH - 

section_id 




BOARD_MODEL_NEAR_TLINE_LENGTH 

BOARD_MODEL_NEAR_TLINE_LENGTH 

Type 

Specifies, in inches, the board trace model near transmission line length. 

String 





■ Arria V 





■ Cyclone V 






■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -to - 

entity 

set_global_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -section_id 

 




BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 

BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 

Type 

Specifies, in henrys or inches, the board trace model near transmission line distributed 

inductance. 

String 





■ Arria V 





■ Cyclone V 






■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH -to 

-entity 

set_global_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH - 

section_id 




BOARD_MODEL_TERMINATION_V 

BOARD_MODEL_TERMINATION_V 

Type 

Specifies, in volts, the board trace model termination voltage. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_TERMINATION_V -to -entity 

 

set_global_assignment -name BOARD_MODEL_TERMINATION_V -section_id 




BOARD_MODEL_TLINE_C_PER_LENGTH 

BOARD_MODEL_TLINE_C_PER_LENGTH 

Type 

Specifies, in farads or inches, the board trace model far transmission line distributed 

capacitance. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -to - 

entity 

set_global_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -section_id 

 




BOARD_MODEL_TLINE_LENGTH 

BOARD_MODEL_TLINE_LENGTH 

Type 

Specifies, in inches, the board trace model far transmission line length. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH -to -entity 

 

set_global_assignment -name BOARD_MODEL_TLINE_LENGTH -section_id 




BOARD_MODEL_TLINE_L_PER_LENGTH 

BOARD_MODEL_TLINE_L_PER_LENGTH 

Type 

Specifies, in henrys or inches, the board trace model far transmission line distributed 

inductance. 

String 



■ Arria GX 



■ Arria V 





■ Cyclone V 







■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -to - 

entity 

set_global_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -section_id 

 




ENABLE_ADVANCED_IO_TIMING 

ENABLE_ADVANCED_IO_TIMING 

Type 

Allows the TimeQuest timing analyzer to use Advanced I/O Timing to generate I/O 

timing results. Timing results are based on the board trace model specified for each 

pin, and may differ from the results currently reported. 

Boolean 



■ Arria GX 



Syntax 

set_global_assignment -name ENABLE_ADVANCED_IO_TIMING 




OUTPUT_IO_TIMING_ENDPOINT 

OUTPUT_IO_TIMING_ENDPOINT 

Type 

Specifies the node at which output I/O Timing ends. 

Enumeration 

■ Far End 

■ Near End 





■ Arria V 





■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name OUTPUT_IO_TIMING_ENDPOINT -to -entity 

 

set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT -entity 

set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT 

Default Value 

Near End 




OUTPUT_IO_TIMING_FAR_END_VMEAS 

OUTPUT_IO_TIMING_FAR_END_VMEAS 

Type 

Specifies, in volts, the measurement voltage at the far-end. 

String 





■ Arria V 





■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS -to - 

entity 

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS -section_id 

 

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS 




OUTPUT_IO_TIMING_NEAR_END_VMEAS 

OUTPUT_IO_TIMING_NEAR_END_VMEAS 

Type 

Specifies, in volts, the measurement voltage at the near-end. 

String 





■ Arria V 





■ Cyclone V 





■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS -to - 

entity 

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS -section_id 

 

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS 




PCB_LAYER 

PCB_LAYER 

Type 

Specifies which PCB layer the signal breaks out on. 

Integer 



Notes 


Syntax 

set_instance_assignment -name PCB_LAYER -to -entity 

 

set_global_assignment -name PCB_LAYER -section_id 

 




PCB_LAYERS 

PCB_LAYERS 

Type 

Specifies the properties of all PCB layers. 

Integer 



Notes 


Syntax 

set_instance_assignment -name PCB_LAYERS -to 




PCB_LAYER_THICKNESS 

PCB_LAYER_THICKNESS 

Type 

Specifies the thickness of the specific PCB layer. 

String 



Notes 


Syntax 

set_instance_assignment -name PCB_LAYER_THICKNESS -to -entity 

set_global_assignment -name PCB_LAYER_THICKNESS -section_id 




SYNCHRONOUS_GROUP 

SYNCHRONOUS_GROUP 

Type 

A logic option that assigns a synchronous group number for the specified node. This 

option directs the SSN Analyzer to view the specified nodes as a synchronous group 

during SSN voltage noise analysis. This option can be set in the Assignment Editor. 

Integer 





■ Arria V 




■ Cyclone V 



■ Stratix V 

Notes 


Syntax 

set_instance_assignment -name SYNCHRONOUS_GROUP -to -entity 



ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS 

Type 










June 2012 

17. TimeQuest Timing Assignments 

Directs the Quartus II TimeQuest timing analyzer to analyze latches as synchronous 

elements, rather than as combinational elements. Although latches continue to be 

implemented as a LUT feeding back onto itself, turning on this option directs the 

TimeQuest analyzer to analyze all latches as synchronous elements. Specifically, the 

clock enable is analyzed as an inverted clock. The TimeQuest analyzer reports the 

results of setup and hold analysis on these latches. 

Boolean 



Syntax 

set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS 

 

Default Value 

On 

ISO 

9001:2008 

Registered 

Subscribe

17–2 Chapter 17: TimeQuest Timing Assignments 

DO_COMBINED_ANALYSIS 


Type 

Analyzes both the fast corner (min delays) and the slow corner (max delays) and 

reports the results from each analysis. 

Directs the TimeQuest analyzer to run and report timing results using both the Fast 

timing model (best-case) and slow timing model (worst-case). The results of each 

analysis are reported in the Fast Timing and Slow Timing folders of the TimeQuest 

analyzer report. When you run a combined fast or slow analysis, the netlist is 

annotated only with worst-case timing model results. 

Boolean 



■ Arria GX 



■ Cyclone 










■ MAX V 

■ Stratix 






Syntax 

set_global_assignment -name DO_COMBINED_ANALYSIS 



Chapter 17: TimeQuest Timing Assignments 17–3 


Default Value 

Off 




INPUT_TRANSITION_TIME 

INPUT_TRANSITION_TIME 

Type 

Specifies the input transition time to be used for HardCopy designs. This assignment 

is used in the Quartus II software to adjust the timing of the I/O buffers. It is also used 

when generating the PrimeTime script that it is used by the HardCopy back end. This 

assignment gets converted as a set_input_transition SDC command. If the 

assignment does not exist, the Quartus II software generates a set_input_transition 

using 80% of VCCN * 1V/ns where VCCN depends on the I/O standard used. 

Time 





■ Arria V 





■ Cyclone V 




■ Stratix 




■ Stratix V 

Notes 



Syntax 

set_instance_assignment -name INPUT_TRANSITION_TIME -to -entity 

 




MAX_CORE_JUNCTION_TEMP 

MAX_CORE_JUNCTION_TEMP 

Type 

This is the maximum core junction temperature that will be encountered during 

operation. Specified in degrees Celsius. 

String 


■ Arria GX 



■ Arria V 










■ MAX V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 




MIN_CORE_JUNCTION_TEMP 

MIN_CORE_JUNCTION_TEMP 

Type 

This is the minimum core junction temperature that will be encountered during 

operation. Specified in degrees Celsius. 

String 


■ Arria GX 



■ Arria V 










■ MAX V 





■ Stratix V 

Notes 


Syntax 

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 




NOMINAL_CORE_SUPPLY_VOLTAGE 

NOMINAL_CORE_SUPPLY_VOLTAGE 

Type 

Specifies the voltage for the core power supply. For Stratix III devices, the core supply 

voltage applies only to the VCCL power rail. For more information, refer to the 


String 













■ Stratix V 

Notes 



Syntax 

set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 




PACKAGE_SKEW_COMPENSATION 

PACKAGE_SKEW_COMPENSATION 

Type 

Indicates that the package skew for the signal is compensated by the board trace 

delays. 

Boolean 



Notes 


Syntax 

set_instance_assignment -name PACKAGE_SKEW_COMPENSATION -to -entity 

 




PLL_EXTERNAL_FEEDBACK_BOARD_DELAY 

PLL_EXTERNAL_FEEDBACK_BOARD_DELAY 

Type 

Specifies an external board delay between a feedback output pin and a feedback input 

pin (fbin) for a PLL in external feedback mode. This option is ignored if it is assigned 

to anything other than the fbin pin of a PLL. 

Time 



■ Arria GX 



■ Arria V 

■ Cyclone V 




■ Stratix 






■ Stratix V 

Syntax 

set_instance_assignment -name PLL_EXTERNAL_FEEDBACK_BOARD_DELAY -to - 

entity 

set_global_assignment -name PLL_EXTERNAL_FEEDBACK_BOARD_DELAY 




TIMEQUEST_DO_CCPP_REMOVAL 


Type 

Directs the TimeQuest analyzer to remove common clock path pessimism (CCPP) 

during slack computation. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 

■ EPC1 

■ EPC2 


■ FLEX10KB 

■ FLEX8000 





■ MAX V 

■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

■ MAX9000 





■ Stratix 






■ Stratix V 

Syntax 

set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL 




TIMEQUEST_DO_REPORT_TIMING 

TIMEQUEST_DO_REPORT_TIMING 

Type 

Directs the TimeQuest analyzer to report the worst-case path per clock domain and 

analysis. 

Boolean 



Syntax 

set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING 

Default Value 

Off 




TIMEQUEST_MULTICORNER_ANALYSIS 


Type 

Directs the TimeQuest analyzer to perform multicorner timing analysis, which 

analyzes the design against best-case and worst-case operating conditions. Turning on 

this option does not enable multicorner analysis in the Fitter. To optimize fast-corner 

timing, see the Fitter Settings page of the Settings dialog box. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 

■ EPC1 

■ EPC2 


■ FLEX10KB 

■ FLEX8000 





■ MAX V 

■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 





■ MAX7000S 

■ MAX9000 

■ Stratix 






■ Stratix V 

Syntax 

set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS 




TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 

TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 

Type 

Specifies the maximum number of worst-case timing paths for the TimeQuest 

analyzer to report per clock domain and analysis. 

Integer 




Syntax 

set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 

 

Default Value 

100 




TIMEQUEST_REPORT_SCRIPT 

TIMEQUEST_REPORT_SCRIPT 

Type 

Specifies the name of the Tcl script that is used to overwrite the default TimeQuest 

report panels created during a normal compile. 




Notes 


Syntax 

set_global_assignment -name TIMEQUEST_REPORT_SCRIPT 




TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS 

TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS 

Type 

Directs the TimeQuest Timing Analyzer to perform default timing analysis prior to 

running the user-specified report script specified by TIMEQUEST_REPORT_SCRIPT. 

Boolean 



Syntax 


TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS 

Default Value 

On 




TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS 


Type 

Directs the TimeQuest analyzer to report worst-case timing paths per clock domain 

and analysis. 

Boolean 



■ Arria GX 



■ Arria V 

■ Cyclone 






■ Cyclone V 

■ EPC1 

■ EPC2 


■ FLEX10KB 

■ FLEX8000 





■ MAX V 

■ MAX3000A 

■ MAX7000A 

■ MAX7000AE 

■ MAX7000B 

■ MAX7000S 

■ MAX9000 





■ Stratix 






■ Stratix V 

Syntax 

set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS 

 







Revision History 










June 2012 

Additional Information 

The Quartus ® II design software settings are made in the Quartus II Settings File 

(.qsf). 

The following table shows the revision history for this manual. 

Date and 

Document Version Changes Made Summary of Changes 

June 2012, v12.0 ■ Updated for Quartus II version 12.0 — 

December 2011, v10.0 ■ Updated for Quartus II version 11.1 — 

May 2011, v9.0 ■ Updated for Quartus II version 11.0 — 


September 2010, v7.0 ■ Updated for Quartus II version 10.0 — 


November 2008, v5.0 ■ Updated for Quartus II version 8.1 

— 

■ Undated new document template 

■ Updated “Revision History” section 

September 2008, v4.2 ■ Minor editorial updates — 

September 2008, v4.1 ■ Minor editorial updates — 

July 2008, v4.0 ■ Updated for Quartus II version 8.0 — 


ISO 

9001:2008 

Registered

About–2 Appendix : 

How to Contact Altera 

How to Contact Altera 

Typographic Conventions 

For the most up-to-date information about Altera ® products, see the following table. 

Contact (1) 

Contact 

Method Address 

Technical support Website www.altera.com/support 

Technical training Website www.altera.com/training 

Email custrain@altera.com 

Product Literature Website www.altera.com/literature 

Altera literature services Email literature@altera.com 

Non-technical support (General) Email nacomp@altera.com 

(Software Licensing) Email authorization@altera.com 

Note: 

(1) You can also contact your local Altera sales office or sales representative. 

The following table shows the typographic conventions that this document uses. 

Visual Cue Meaning 

Bold Type with Initial Capital 

Letters 

Command names, dialog box titles, checkbox options, and dialog box options are 

shown in bold, initial capital letters. Example: Save As dialog box. 

bold type External timing parameters, directory names, project names, disk drive names, file 

names, file name extensions, and software utility names are shown in bold type. 

Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file. 

Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters. Example: AN 75: 

High-Speed Board Design. 

Italic type Internal timing parameters and variables are shown in italic type. 

Examples: tPIA, n + 1. 

Variable names are enclosed in angle brackets (< >) and shown in italic type. 

Example: , .pof file. 

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: 

Delete key, the Options menu. 

“Subheading Title” References to sections within a document and titles of on-line help topics are shown 

in quotation marks. Example: “Typographic Conventions.” 

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, 

input. Active-low signals are denoted by suffix n, e.g., resetn. 

Anything that must be typed exactly as it appears is shown in Courier type. For example: 

c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a 

Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well 

as logic function names (e.g., TRI) are shown in Courier. 

1., 2., 3., and 

a., b., c., etc. 

Numbered steps are used in a list of items when the sequence of the items is important, 

such as the steps listed in a procedure. 

■ ■ Bullets are used in a list of items when the sequence of the items is not important. 

v The checkmark indicates a procedure that consists of one step only. 

1 The hand points to information that requires special attention. 



Appendix : About–3 

Assignment Value Syntax 

c 

Visual Cue Meaning 


There are rules for using certain characters in assignment values to ensure the value is 

legal. An unquoted value with only alphabetic, numeric, underscore (_), period (.) or 

forward slash (/) characters is legal. A value containing any of the following 

characters must be enclosed in double quotation marks (" ") to be legal. 

{ } ( ) ; : , < >= - # " 

In addition, values containing any of the following characters must escape the 

character with a backslash: 

{ } $ " \ 

For example, the following values are legal: 

■ “EPF10K10LC84-3” 

■ MODE1 

■ “ModelSim (VHDL output from Quartus II)” 

Although it is not required, you can also enclose assignments containing only legal 

characters in double quotation marks. 

Assignment Types 

Each Quartus II assignment has a required type that identifies legal values for the 

assignment. This section describes the types and lists some examples of legal values. 

bool 

An assignment with type bool requires a boolean value of ON or OFF. Boolean 

arguments are not case sensitive.. For example, ON, On, oN, and on are all legal. 

int 

A caution calls attention to a condition or possible situation that can damage or 

destroy the product or the user’s work. 

A warning calls attention to a condition or possible situation that can cause injury to 

w 

the user. 

r The angled arrow indicates you should press the Enter key. 

f The feet direct you to more information on a particular topic. 

The envelope links to the Email Subscription Management Center page of the Altera 

website, where you can sign up to receive update notifications for Altera documents. 

The feedback icon allows you to submit feedback to Altera about the document. 

Methods for collecting feedback vary as appropriate for each document. 

The social media icons allow you to inform others about Altera documents. Methods 

for submitting information vary as appropriate for each medium. 

An assignment with type int requires an integer value. The value must be an integer, 

such as 1. Some assignment definitions may list a range of legal integers. 





string 

An assignment with type string requires an argument that is a string. If the string 

contains any illegal characters, you must enclose the entire string argument in double 

quotation marks. 

filename 

An assignment with type filename requires a value that is the name of a file. You can 

specify directory separators with the forward slash character (/) or back slash 

characters (\). For example, the following values are legal: 

■ simulation/output.vho 

■ “c:\design\top.edf” 

All filename assignment values are case sensitive.. 

time 

An assignment with type time requires a value that is a time. A time value consists of 

a numeric value and text representing units of duration. The numeric value can 

include a decimal point, and the numeric value and units of duration can be separated 

by a single space. For example, the following values are legal: 

■ “1 ps” 

■ “-2ns” 

■ 10.0µs 

Table About–1 shows abbreviations for units of time. 

Table About–1. Abbreviations for Units of Time 

Time Unit Description 

s second(s) 

ms millisecond(s) 

µs microsecond(s) 

ns nanosecond(s) 

ps picosecond(s) 

fs femtosecond(s) 

Hz hertz 

kHz kilohertz 

MHz megahertz 

GHz gigahertz 

enum 

An assignment with type enum requires an value from the enumerated list included 

with the assignment definition. Only values in the list are legal. 

location 

An assignment with type location requires a value that defines a physical resource 

location in a device. For example, the following values are legal in certain devices: 



Appendix : About–5 

Overview 

Overview 

■ LC_X1_Y20_N0 

■ LAB_X1_Y1 

■ M4K_X17_Y12 

frequency 

An assignment with type frequency requires a value that is a frequency. A frequency 

value consists of a numeric value and text representing units of frequency. The 

numeric value can include a decimal point, and the numeric value and units of 

frequency can be separated by a single space. For example, the following values are 

legal: 

■ “50.5 MHz” 

■ 10kHz 

Benefits of Command-Line Operation & Tcl Scripting Support 

Each stage of the Quartus II software design flow corresponds to a command-line 

executable file. Many of these executable files also support industry-standard Tcl 

scripting for custom functionality or processing beyond the GUI design flow. The 

Quartus II software offers the following scripting support benefits, also known as 

CAR: 

■ Custom Analysis 

■ Automation 

■ Reproducibility 

Custom analysis allows you to build test procedures into the script and change design 

processing based on the test results. Scripts can automate design flows to perform on 

multiple computers simultaneously and easily archive and restore projects. 

Reproducibility ensures that scripts use the same project setup and assignments for 

every compilation, even when you transfer a project from one engineer to another. In 

other words, you can use scripts as another level of design quality assurance. 




Overview

Quartus II Settings File Reference Manual - Altera

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