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ASIC SA-27E Databook, Part 1: Base Library and I/Os - CSAIL People

ASIC SA-27E Databook, Part 1: Base Library and I/Os - CSAIL People

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<strong>SA</strong>-<strong>27E</strong><br />

IP25D2T, IP25D2T_PM<br />

2.5V CMOS (3.3V Tolerant) Test DI2 Receiver<br />

Cell: IP25D2T, IP25D2T_PM<br />

Function: 2.5V CMOS (3.3V Tolerant) Test DI2 Receiver<br />

Description:<br />

St<strong>and</strong>-alone noninverting receiver that interfaces<br />

2.5V off-chip unidirectional data buses with ZDI<br />

1.8V internal logic <strong>and</strong> is tolerant of 3.3V LVTTL<br />

levels. Serves as first block of DI2 daisy chain.<br />

Receiver input has hysteresis.<br />

PAD External DI2/driver inhibit input (1st<br />

block)<br />

ZDI Driver inhibit output (DI out)<br />

Receiver Truth Table<br />

Input Output<br />

PAD ZDI<br />

St<strong>and</strong>ard Cell<br />

1024<br />

0 0<br />

1 1<br />

Receiver Propagation Delays<br />

Path<br />

(Input to<br />

Output)<br />

Performance<br />

Level<br />

PAD-ZDI A<br />

Parameter<br />

Capacitance (in units of N std ) <strong>and</strong> Cell Sizes<br />

Delay (ns) = intercept + slope (N std)<br />

V dd = 1.65V<br />

V dd250 = 2.3V<br />

T j = 125˚C<br />

Process = Slow<br />

V dd = 1.8V<br />

V dd250 = 2.5V<br />

T j = 25˚ C<br />

Process = Nom.<br />

V dd = 1.95V<br />

V dd250 = 2.7V<br />

T j = 0˚C<br />

Process = Fast<br />

t PLH 0.611 + 0.002N std 0.420 + 0.001N std 0.331 + 0.001N std<br />

t PHL 0.539 + 0.002N std 0.439 + 0.001N std 0.360 + 0.001N std<br />

Input Pins<br />

Performance Level<br />

A<br />

PAD (Receiver Input) 130.708<br />

Internal 61.741<br />

Cell Units 2 cells<br />

PAD<br />

<strong>SA</strong>14-2208-03<br />

June 4, 2001

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