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ASIC SA-27E Databook, Part 1: Base Library and I/Os - CSAIL People

ASIC SA-27E Databook, Part 1: Base Library and I/Os - CSAIL People

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Cell: IP25LTT, IP25LTT_PM<br />

Function: 2.5V CMOS (3.3V Tolerant) Leakage Test Receiver<br />

Description:<br />

St<strong>and</strong>-alone inverting receiver that interfaces<br />

2.5V off-chip unidirectional data buses with 1.8V ZLT<br />

internal logic <strong>and</strong> is tolerant of 3.3V LVTTL levels.<br />

Receiver input has hysteresis.<br />

PAD External LT inhibit input<br />

ZLT Driver inhibit output (LT out)<br />

Receiver Truth Table<br />

Input Output<br />

PAD ZLT<br />

<strong>SA</strong>14-2208-03<br />

June 4, 2001<br />

0 1<br />

1 0<br />

Receiver Propagation Delays<br />

Path<br />

(Input to<br />

Output)<br />

Performance<br />

Level<br />

PAD-ZLT A<br />

Parameter<br />

Capacitance (in units of N std ) <strong>and</strong> Cell Sizes<br />

<strong>SA</strong>-<strong>27E</strong><br />

IP25LTT, IP25LTT_PM<br />

2.5V CMOS (3.3V Tolerant) Leakage Test Receiver<br />

Delay (ns) = intercept + slope (N std )<br />

V dd = 1.65V<br />

V dd250 = 2.3V<br />

T j = 125˚C<br />

Process = Slow<br />

V dd = 1.8V<br />

V dd250 = 2.5V<br />

T j = 25˚ C<br />

Process = Nom.<br />

V dd = 1.95V<br />

V dd250 = 2.7V<br />

T j = 0˚C<br />

Process = Fast<br />

t PLH 0.751 + 0.002N std 0.586 + 0.001N std 0.473 + 0.001N std<br />

t PHL 0.615 + 0.002N std 0.417 + 0.001N std 0.325 + 0.001N std<br />

Input Pins<br />

Performance Level<br />

A<br />

PAD (Receiver Input) 130.821<br />

Internal 64.510<br />

Cell Units 1 cell<br />

PAD<br />

St<strong>and</strong>ard Cell<br />

1025

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