preliminary - Bad Request - Cern

Abstract
The construction of the LHC is proceeding well. The
problems encountered with civil engineering work last year
which are now resolved, and the letting of contracts for
machine components is on schedule. Although the initial
deliveries of equipment are up to a few months behind those
planned, suppliers are confident they will be able to make
good on this once the full-scale production is running. The
machine layout is stable as is the expected performance, and
we can look forward with confidence to the first physics run
in 2006.
I. INTRODUCTION
The LHC (Large Hadron Collider)[1], under construction at
CERN, is designed to provide proton-proton collisions at a
center-of-mass energy of 14 TeV and luminosity of
10 34 cm 2 .s -1 . This machine is a major advanced engineering
venture. It consists of two synchrotron rings, interleaved
horizontally, the main elements of which are the two-in-one
superconducting dipole and quadrupole magnets operating in
superfluid helium at 1.9 K. The collider will be installed in the
existing tunnel of 26.7 km in circumference which until
recently housed the LEP collider. This has constrained the
layout to resemble closely that of LEP, with eight identical
2.8 km long arcs, separated by eight 540 m long straight
sections, the centres of which are referred to as “Points”. At
four of these points the beams are brought into collision.
Points 1 and 5 will house the high luminosity multipurpose
experiments ATLAS and CMS, for which considerable civil
engineering is required. The more specialized experiments
ALICE and LHCb will be installed in the existing caverns,
which previously housed LEP experiments, at Points 2 and 8.
Major systems of the collider itself will be installed in the
remaining four straight sections. Points 3 and 7 are dedicated
to beam cleaning, Point 4 to beam acceleration, and Point 6 to
beam extraction. The general layout of the LHC is shown in
Figure 1, and a simulated view of the installed machine is
shown in Figure 2.
Following a decade of R&D and technical validation of
the major systems of the collider at CERN, at collaborating
institutes and with industry, construction of the LHC is now
underway. Contracts have been awarded to industry for the
supply of superconducting magnets, cryogenic refrigeration
plants and other machine equipment, and manufacture has
begun. The components of some systems, such as those of the
injection lines and the superconducting RF are nearing
completion. The upgrading of the injector complex of existing
CERN accelerators is practically finished. Civil engineering is
now advancing well after some setbacks associated with the
The Status of the LHC Machine.
T.M.Taylor
CERN, 1211 Geneva 23, Switzerland
Tom.Taylor@cern.ch
terrain, but not before leading to a review of the schedule. It is
now planned to start installation in autumn 2003, to
commission the first sector (Point 8 to Point 7) in summer
2004, and to complete installation by the end of 2005. After
an initial set-up test with beam in spring 2006, it is foreseen to
start a seven-month physics programme in autumn 2006.
RF
& Future Expt.
Cleaning
ALICE
Low ß (Ions)
Octant 3
Injection
Octant 4
Octant 2
Low ß (pp)
High Luminosity
CMS
Octant 5
Octant 1
ATLAS
Low ß (pp)
High Luminosity
Figure 1: General layout of the LHC
Octant 6
Octant 8
Figure 2: Simulated view of the LHC in its tunnel
Octant 7
Injection
Dump
Low ß
(B physics)
Cleaning
LHC-B

II. THE LATTICE
The main parameters of the LHC as a proton collider are
listed in Table 1.
The design of the lattice has matured over the past years
both in terms of robustness and flexibility, and critical
technologies and engineering solutions have been validated,
while nevertheless maintaining the initially declared
performance of the machine. The FODO lattice is composed
of 46 half-cells per arc; each half-cell is 53.45 m long and
consists of three twin-aperture dipoles having a magnetic
length of 14.3 m, and one twin aperture quadrupole, 3.1 m in
length.
Table 1: Main parameters of the LHC
Energy at collision 7 TeV
Energy at injection 450 GeV
Dipole field at 7 TeV 8.33 T
Coil inner diameter 56 mm
Distance between aperture axes (1.9 K) 194 mm
Luminosity 10 34
cm -2 s -1
Beam current 0.56 A
Bunch spacing 7.48 m
Bunch separation 24.95 ns
Number of particles per bunch 1.1 x 10 11
Normalized transverse emittance (r.m.s.) 3.75 μm
Total crossing angle 300 μrad
Luminosity lifetime 10 h
Energy loss per turn 6.7 keV
Critical photon energy 44.1 eV
Total radiated power per beam 3.8 kW
Stored energy per beam 350 MJ
III. THE SUPERCONDUCTING MAGNETS
A major technological challenge of the LHC is the
industrial production of 1232 superconducting main dipoles
[2] operating at 8.3 T, 400 superconducting main quadrupoles
[3] producing gradients of 223 T m -1 , and several thousand
other superconducting magnets [4], for correcting multipole
errors, steering and colliding the beams, and increasing
luminosity in collision. All these magnets (Table 2), which
must produce a controlled field with a precision of 10 -4 , are
presently being manufactured by industry in Europe, India,
Japan and the USA.
A specific feature of the main dipoles, a cross-section of
which appears in Figure 3, is their twin-aperture design. To
produce the fields required for bending the counter-rotating
beams, two sets of windings are combined in a common
mechanical and magnetic structure to constitute twin-aperture
magnets. This design is more compact and efficient than two
separate strings of magnets, as the return flux of one aperture
contributes to increasing the field in the other. The high
quality field in the magnet apertures is produced by winding
flat multi-strand cables, in a two-layer cos θ geometry. The
large electromagnetic forces acting on the conductors are
reacted by non-magnetic collars resting against the iron yoke,
contained in a welded cylinder which also act as a helium
enclosure.
Table 2: Superconducting magnets in the LHC
Type Quantity Purpose
MB 1232 Main dipole
MQ 400 Main quadrupole
MSCB 376 Combined chromaticity and closedorbit
corrector
MCS 2464 Sextupole for correcting dipole
MCDO 1232
persistent currents
Octupole/decapole for correcting
MO 336
dipole persistent currents
Landau octupole for instability control
MQT 256 Trim quadrupole for lattice correction
MCB 266 Orbit correction dipole
MQM 100 Dispersion suppressor quadrupole
MQX 32 Low-β insertion quadrupole
MQY 20 Enlarged-aperture quadrupole
Figure 3: Transverse cross-section of the dipole in its cryostat
CERN supplies the superconducting cable to the
companies assembling the magnets. In view of the quantity of
cable required (~1250 tonnes), all European wire
manufacturers (together with one in the USA and one in
Japan) are involved in this production.
The LHC magnets must preserve their field quality over a
large dynamic range, in particular at low levels when
persistent currents in the superconductor give rise to remanent
field effects. This requires a small diameter of the Nb-Ti
filaments in the cable strands. The chosen diameter of ~7μm
represents a compromise that also takes into account the
requirement to maximize overall current density in the strand.
It is also necessary to apply a uniform resistive coating to the
strands to control inter-strand currents. Together with the tight
dimensional tolerances, these constraints have presented quite
a challenge to the manufacturers, but after a difficult start
most companies are now producing satisfactory material.
However, with present delays of about 12 months we shall
require a large increase in throughput to satisfy the needs of
magnet production as it accelerates in the next months.

Following a decade of development and model work, final
prototypes magnets built in industry have permitted the
validation of technical design choices and manufacturing
techniques, thus leading the way for the adjudication of preseries
and series contracts for the dipoles, quadrupoles and
correctors, the production of which has now started and will
continue over the next four years (Figure 4). The first three
magnets of the dipole series have been tested and are
acceptable for installation in the machine. Preparations for the
production of the quadrupoles are advancing well, and
deliveries of corrector magnets have already started.
b)
Figure 4: First pre-series superconducting magnets under test. a)
Main dipole at CERN; b) Low-β quadrupole at Fermilab
IV. CRYOGENICS
The LHC uses superfluid helium for cooling the magnets
[5]. The main reason for this is the lower operating
temperature, with corresponding increased working field of
the superconductor. The low viscosity of superfluid helium
enables it to permeate the magnet windings, thereby
smoothing thermal disturbances, thanks to its very large
specific heat (~2000 times that of the cable per unit volume),
and conducting heat away, thanks to its exceptional thermal
conductivity (1000 times that of OFHC copper, peaking at
1.9 K).
a)
The LHC magnets operate in static baths of pressurized
superfluid helium, cooled by continuous heat exchange with
flowing saturated superfluid helium. This cooling scheme,
which requires two-phase flow of superfluid helium in nearly
horizontal tubes, has been intensively studied on test loops
and validated on a full-scale prototype magnet string [6].
Individual cryogenic loops extend over 107 m, the length of a
lattice cell, and these loops are fed in parallel from each
cryogenic plant over the 3.3 km sector length through a
compound cryogenic distribution line [7] running along the
cryo-magnets in the tunnel.
The high thermodynamic cost of refrigeration at low
temperature requires careful management of the system heat
loads. This has been achieved by the combined use of
intermediate shielding, multi-layer insulation and conduction
intercepts in the design of the cryostats (see Figure 3), and by
the installation of beam screens cooled at between 5 and 20 K
by supercritical helium, for absorbing a large fraction of the
beam-induced heat loads [8]. To cope with its heat load, the
LHC will employ eight large helium cryogenic plants, each
producing a mix of liquefaction and refrigeration at different
temperatures, with an equivalent capacity of 18 kW @ 4.5 K
and a coefficient of performance of 230 W/W [9]. The cold
box of the first LHC cryogenic plant, presently undergoing
reception tests at CERN, is shown in Figure 5.
Figure 5: Coldbox of first 18 kW @ 4.5 K helium refrigerator
In view of the low saturation pressure of helium at 1.8 K,
the compression of high flow-rates of helium vapour over a
pressure ratio of 80 requires multi-stage cold hydrodynamic
compressors (Figure 6). This technology, together with that of
low-pressure heat exchangers, was developed specifically for
this purpose. Following detailed thermodynamic studies and
prototyping conducted in partnership with industry, eight
2400 W @ 1.8 K refrigeration units have been ordered from

two companies, and the first one has been delivered to CERN
for reception tests. The overall coefficient of performance of
these units, when connected to the conventional 4.5 K helium
refrigerators, is about 900 W/W.
Figure 6: Impellers of cold compressors for the first 2.4 kW @ 1.8 K
refrigeration unit
V. HIGH TEMPERATURE SUPERCONDUCTOR
CURRENT LEADS
Powering the magnet circuits in the LHC will require
feeding up to 3.4 MA into the cryogenic environment. Using
resistive vapour-cooled current leads for this purpose would
result in a heavy liquefaction load. The favourable cooling
conditions provided by 20 K gaseous helium available in the
LHC cryogenic system make the use of HTS-based current
leads in this system particularly attractive. With a comfortable
temperature difference to extract the heat from the resistive
section in a compact heat exchanger, this allows operation of
the upper end of the HTS section below 50 K, at which the
presently available materials, e.g., BSCCO 2223 in a
silver/gold matrix, exhibit much higher critical current density
than at the usual 77 K provided by liquid nitrogen cooling.
The thermodynamic appeal of such HTS-based current leads
is presented in Table 3.
Table 3: Performance of HTS-based current leads for the LHC,
compared to resistive vapour-cooled leads
Lead type
Resistive,
vapourcooled
(4 to 300 K)
HTS (4 to 50 K)
Resistive, gas
cooled (50 to
300 K)
Heat into LHe [W/kA] 1.1 0.1
Total exergy [W/kA] 430 150
Electrical
f
[W/kA] 1430 500
After conducting tests on material samples, CERN
procured from industry and tested extensively prototypes of
HTS-based current leads for 13 kA and 0.6 kA. This has
enabled us to demonstrate feasibility and performance of this
solution, to identify potential construction problems, to
address transient behaviour and control issues, and to prepare
the way for procurement of series units [10].
VI. INSTALLATION AND TEST STRING 2
The tight constraints of the LHC tunnel, the large quantity
of equipment to be transported and installed, and the limited
time for installation require detailed preparation, including
both CAD simulation and full-scale modeling. Using the
information from verifications of the tunnel geometry that
were performed in 1999, 3D mock-ups have been developed
for critical tunnel sections. As a result of these studies areas of
interference have been identified, and transport and
installation scenarios have been confirmed. The recent
experience gained in the assembly of the first half of Test
String 2 [11], featuring a full 107 m long cell comprising
dipoles and quadrupoles, has been of great value in validating
the techniques and tooling developed for the installation and
interconnection of the lattice magnets. The Test String is
shown in Figure 7.
Figure 7: Test String 2.

VII. PERFORMANCE AND UPGRADE POTENTIAL
It is confidently expected that in the first year of running a
luminosity of 10 33 cm -2 s -1 will be achieved at the nominal
centre-of-mass energy of 7+7 TeV, and that the machine will
provide an integrated luminosity of 10 fb -1 during the first 6month
period of physics data-taking. It will probably then
take another two to three years to ramp up to the nominal
peak luminosity of 10 34 cm -2 s -1 in the high luminosity
experiments. As concerns upgrade potential, the accelerator is
being engineered so as to allow the possibility of achieving up
to about 7.5 TeV per beam, but this may require changing
some of the weaker dipoles. It can also be envisaged to further
increase the luminosity by up to a factor of two by reducing
the β−function at the interaction point from 0.5 m to 0.25 m,
but this will call for the replacement of the inner triplet
quadrupoles with larger aperture magnets. This new
generation of high field superconducting magnets, based on
the use of Nb3Sn or Nb3Al material, is presently the subject of
R&D in several laboratories; we expect that in 5-7 years it
should be possible to embark on the production of a small
series suitable for the low-β insertions. Studies are also
underway regarding more radical upgrading of the machine,
such as increasing the luminosity by another factor of five, or
replacing the main lattice magnets with more powerful
magnets to take the beam energy up to 10-12 TeV. But this
will be for a far more distant future.
VIII. CONCLUSION
After a decade of comprehensive R&D, the LHC
construction is now in full swing [12]. Industrial contracts
have been awarded for the procurement of most of the 7000
superconducting magnets and for the largest helium cryogenic
system ever built, and the production of this equipment is
underway. Although located at CERN and basically funded by
its twenty member states, the project, which will serve the
world’s high-energy physics community, is supported by a
global collaboration, with special contributions from Canada,
India, Japan, Russia and the USA. A full-scale test of the first
sector is planned for 2004, and colliding beams for physics
are expected to be available from 2006 onwards.
IX. REFERENCES
1. The LHC Study Group, The Large Hadron Collider,
Conceptual Design, CERN/AC/95-05, 1995.
2. Wyss, C., "The LHC Magnet Programme: from
Accelerator Physics Requirements to Production in
Industry", in Proc. EPAC2000, edited by J.L. Laclare et
al., Austrian Academy of Science Press, Vienna, Austria,
2000, pp. 207-211.
3. Billan, J. et al., "Performance of the Prototypes and Startup
of Series Fabrication of the LHC Arc Quadrupoles",
paper presented at PAC2001, Chicago, USA, 2001.
4. Siegel, N., "Overview of LHC Magnets other than the
Main Dipoles", in Proc. EPAC2000, edited by
5.
J.L. Laclare et al., Austrian Academy of Science Press,
Vienna, Austria, 2000, pp. 23-27.
Lebrun, Ph., "Cryogenics for the Large Hadron Collider",
IEEE Trans. Appl. Superconductivity 10, pp. 1500-1506
(2000).
6. Claudet, G. & Aymar, R., "Tore Supra and He-II Cooling
of Large High-field Magnets", in Adv. Cryo. Eng. 35A,
edited by R.W. Fast, Plenum, New York, 1990, pp. 55-
67.
7. Erdt, W. et al., "The LHC Cryogenic Distribution Line:
Functional Specification and Conceptual Design", in Adv.
Cryo. Eng. 45B, edited by Q.-S. Shu, Kluwer
8.
Academic/Plenum, New York, 2000, pp. 1387-1394.
Gröbner, O., "The LHC Vacuum System", in Proc.
PAC97, edited by M. Comyn, M.K. Craddock &
9.
M. Reiser, IEEE Piscataway, New Jersey, USA, 1998,
pp. 3542-3546.
Claudet, S. et al., "Economics of Large Helium
Cryogenic Systems: Experience from Recent Projects at
CERN", in Adv. Cryo. Eng. 45B, edited by Q.-S. Shu,
Kluwer Academic/Plenum, New York, 2000, pp. 1301-
1308.
10. Ballarino, A., "High-temperature Superconducting
Current Leads for the Large Hadron Collider", IEEE
Trans. Appl. Superconductivity 9, pp. 523-526 (1999).
11. Bordry, F. et al., "The Commissioning of the LHC Test
String 2", paper presented at PAC2001 Chicago, USA,
2001
12. Ostojic, R., "Status and Challenges of LHC
Construction", invited paper at PAC2001, Chicago, USA,
2001.

Trends and Challenges in High Speed Microprocessor Design
Kerry Bernstein
IBM Microelectronics
Essex Junction, VT USA
Phone: (802) 769-6897 Fax: (802) 769-6744 Internet: kbernste@us.ibm.com
Abstract
Entropy is a worthy adversary! High performance logic design
in next-generation CMOS lithography must address an
increasing array of challenges in order to deliver superior performance,
power consumption, reliability and cost. Technology
scaling is reaching fundamental quantum-mechanical
boundaries! This paper reviews example mechanisms which
threaten deep submicron VLSI circuit design, such as tunneling,
radiation-induced logic corruption, and on-chip delay
variability. Architectures, circuit topologies, and device technologies
under development are explored which extend “evolutionary”
concepts and introduce “revolutionary” paradigms.
It will be these revolutionary technologies which will bring
our industry to the threshold of human compute capability.
Introduction
The overwhelming success of VLSI arises from the convergence
of advances in multiple disciples: MOSFET device
design, process development, innovative new circuit topologies,
and power new state machine architectures. Each has
consistently contributed opportunities for improving transaction
throughput. So successful has been this progression, that
limits in the design space must now be confronted. This pro-
gression, known as scaling 1 , has provided benchmarks for
each discipline, generation over generation. We first examine
the scaling experience, look at example mechanisms limiting
continued scaling, and then explore how designs have
responded to these new capabilities and limitations. Finally,
we will muse over the compute power continued scaling may
enable.
Scaling Experience
Scaling refers to the practice of simultaneously reducing a collection
of key electrical and physical design parameters by a
constant value. Figure 1 shows the application of scale factor a
to the physical dimensions of a MOSFET. Frank, etal
describes how the retention of these relationships preserves
device optimization 2 . This relationship has in fact been preserved,
more or less, through multiple generations of CMOS
Lithography, yield the performance trend shown in Figure 2.
Also evident is the requirement more recently for the constant
infusion of innovative structures and materials to sustain this
improvement. The underlying engine driving this capability is
photolithography. Smaller and smaller minimum critical
dimensions have given rise to channel length reductions seen.
speed, provided the other following boundary conditions are
met.
Scaling Limitations
Nonetheless, even with innovation, “Moore’s Law” has been
observed to be eroding. A roll-off in device performance arises
from the inability to scale threshold voltage as quickly as supply.
This results in (V GS-V T) overdrive voltage reduction.
Process tolerance presents a second challenge to scaling. As
critical parameter tolerance becomes harder to maintain at
smaller lithography, the amount of timing margin consumed
by the resulting delay variation impacts yield. Figure 3 shows
the offset between the functionality window (defined by the
dispersion of delay in paths of varying composition) and the
full process tolerance window. It is evident that to maintain
yield, performance must be sacrificed in the form of margin.
Aside from process, voltage and temperature variation across
die also contribute to delay variability. Typically a design may
present up to 3% performance change per 10degC in temperature
change, or 5% performance change per 100 mV in supply
voltage variation. A fourth challenge to scaling lies in its
intrinsic response to radiation events. Alpha particles arising
from semiconductor materials or high energy protons or neutron
daughters of cosmic ray events both have the opportunity
to deliver charge necessary to corrupt the content of a bistable,
or to glitch a logic level. Figure 4 shows the steady decrease in
QCRIT, the minimum charge necessary to induce an event,
against scaling. As feature dimensions are reduced, the capacitance
reservoir of charge balancing an event is also reduced.
A fifth challenge is associated with the integrity of gate dielectrics
in the MOSFET. As dimensions sizes reduce, it is essential
to reduce gate oxide thickness for the gate to retain control
over the inversion layer formation. Thinner dielectrics have
higher tunneling currents and more frequent breakdowns.
Design Response
To understand how designs have exploited this capability and
address its emerging limitations, it is useful to examine the
Patterson-Hennessy Formula 3 for performance contributions.
Time = Instr/pgm x Cycles/Instr x Seconds/Cycle
(1) (2) (3)
The first term is the responsibility of the compiler; improvement
in the second term comes from architectural enhancements,
which have been responsible for perhaps half of recent
performance gains. Out of order execution, speculative
branching, multi-threading, and superscalar functional units
are examples. These features, while improving through-put,
also add extra circuits and devices, increasing power consumption.
Figure 5 shows this trend and its implausible trend.
The third term falls squarely in the lap of the process and circuit
designers. The lies, however, an even more insidious subtle
trend (A”red-hat topic”!). Because more and more circuitry
has been added to boost architecture performance, wire
lengths have not reduced with scaling as die sizes have not
shrunk. Worse, these additions create deeper pipelines with
less intrinsic delay per pipeline. In short a signal has to go farther
than before, and has even less time to get there than

efore, both after scaling. The result is that less and less of the
chip may be accessed in a given cycle, as shown in Figure 6.
The design response as is “logical islands” are not defined during
placement, considering which functions must be less than
1 cycle latency away.
Capabilities of the Extended Paradigm
To combat this trend the, high speed microprocessors require
constant innovation. A denser device with lower parasitic
capacitance and which puts out more current is one such inno-
vation. The Strained Silicon MOSFET 4 is an evolutionary
MOSFET improvement (Figure 7); it derives it’s performance
advantage from strain induced in the layer in which the inversion
channel is formed. In the cited reference, a thin SiGe
layer is deposited on a Si substrate. With different lattice constants,
the resulting strain induces improved mobility in 2 of
Silicon’s 6 degenerate states. An architectural direction likely
to improve throughput is increased parallelism. Figure 8
shows the results of an analysis of various means of achieving
equivalent performance. It supports the conclusion that an
array of smaller simpler processors run at lower voltages can
meet the equivalent performance of fewer processors at high
voltage, saving, power and design resource. Finally, new circuit
topologies promise to help reduce cycle time. Figure 9
shows Clock-Delayed Domino, an emerging circuit family
used in semi-synchronous and “locally-asynchronous-globally-synchronous”
microprocessors. At its heart, the circuit is
a simple dynamic domino, which has traveling along with it its
own clock. The clock can serve one circuit or one time-sliced
column of circuits. It’s delay is tuned via the passgate beta
ratio.
Conclusions
Technology scaling is a paradigm that has indeed served our
industry well. It is directly as well as indirectly responsible for
the historic performance, density, and power trend known as
“Moore’s Law.” Most recently, quantum-mechanical limitations
to scaling have become evident and have required compensation
by the designer at the architecture as well as circuit
topology level. Innovation in novel MOSFET design, new circuit
families, and logic architectures will provide a path for
evolution of existing approaches, and buy time to develop revolutionary
concepts. Just as scaling up to now has enabled
more function to be brought onboard chip with less latency,
continued scaling will before long allow our industry to
deliver transaction throughput rivaling human compute capability.
It is incumbent, then, to wisely invest our physical as
well as intellectual resources, to most fruitfully enjoy this
future capability.
References
[1]B. Davari, etal., “CMOS Scaling for High Performance and Low
Power - The Next 10 Years,” Proceedings of the IEEE, Vol. 83, No.4,
April, 1995, pp. 595-606.
[2] D. Frank, etal., “Generalized Scale Length for Two-Dimensional
Effects in MOSFETs”, IEEE Electron Device Letters, Vol. 19, No.
10, October 1998, pp 385-387.
[3]D. Patterson, etal., “Computer Architecture: A Quantitative
Approach”, Morgan Kaufmann Publishers, 1995, ISBN 1558603298
[4] K. Rim, etal., “Strained Si NMOSFETs for High Performance
CMOS Technology”, Proceedings of 2001 VLSI Technology Symposium,
pp. 59-60.
[5] F. Pollack, “New Microarchitecture Challenges in the Coming
Generations of CMOS Process Technologies”, Micro32.
Figure 1: MOSFET Device ideal scaling relationships
h
Relative Device Performance
0.2
1986
1992
Figure 2: Innovation and Scaling
1998
2004
Year of Technology Capability
2010
Figure 3: Timing Margin Consumption by Process Variation
Qcrit (fC)
30
25
20
15
10
5
0
20
10
5.0
2.0
1.0
0.5
0.5✙
Bulk
0.25✙
Bulk
0.22✙
Bulk
33.1 18.8 9.88 8.64 7.5 7 4.81 4.23 3.67 2.48 1.97 2.16
Cell Area (um2)
0.18✙
Bulk
0.13✙
SOI
Figure 4: Channel hot electron degradation dependence on V T.

Figure 5: Trends in Power Consumption 5
Control Area Scaling
Accessible Die Area
120%
110%
100%
90%
80%
70%
60%
50%
40%
30%
20%
0.5 0.45 0.45 0.35
Figure 6: Area of Control [3]
Figure 7: Strained Silicon MOSFET
uP Count (Green)
Scaled Area Fixed Die Area
Scale Factor
Sys Pwr ,Watts (Blue)
80
75
2500
70
2000
65
60
1500
55
50
1000
45
500
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
uP count, nom proc
Pwr, nom proc
uP count, Proc A
Pwr, Proc A
uP Count, Proc B
Pwr, Proc B
Voltage
IBM study shows uP count and voltage combos providing 50% sys perf w/various device options
Figure 8: Distributed Processing’s Power x Delay advantages.
Figure 9: Clock-Delayed Dynamic Domino Logic

Abstract
Most modern HEP experiments use pixel detectors for
vertex finding because these detectors provide clean and
unambiguous position information even in a high multiplicity
environment. At LHC three of the four main experiments will
use pixel vertex detectors. There is also a strong development
effort in the US centred around the proposed BTeV
experiment. The chips being developed for these detectors
will be discussed giving particular attention to the
architectural choices of the various groups. Radiation tolerant
deep sub-micron CMOS is used in most cases. In light of
predicted developments in the semiconductor industry and
bearing in mind some fundamental limits it is possible to
foresee the trends in pixel detector design for future
experiments.
I. INTRODUCTION
Pixel detectors are now important components in modern
High Energy Physics (HEP) experiments. The initial
development work for SSC and LHC was first applied in a
heavy ion experiment [1] and in LEP [2]. This provided a
basis for confidence for use in the future p-p experiments at
LHC [3, 4, 5], the Alice heavy ion experiment [6] as well as
to the proposed BTeV experiment at the Tevatron [7]. An
extensive overview of the history of the development of pixel
detectors for HEP is given in [8]. The present paper takes a
closer look at the design of the electronics for the different
present-day systems. Some basic concepts relevant to pixel
electronics are reviewed. Then the work in progress for the
new experiments is discussed with particular reference to the
chosen readout architectures. Finally, an attempt is made to
explore the way ahead for such detectors in future.
II. DEFINITIONS AND BASIC CONCEPTS
A pixel detector is a 2-dimensional matrix of microscopic
(

compromise between the required timing resolution and noise.
The equations for series, ENC d, and parallel noise, ENC o, [11]
can be simplified to:
2
C
2
2 t
ENCd
∝ ENCo ∝ I oτ
s
gmτ
s
where Ct is the total capacitance on the input node of one
channel, gm is the transconductance of the input transistor, τs is
the shaping time and Io is the leakage current of the sensor
element. Other parallel noise sources have to be added to Io. In
modern pixel detector systems the parallel noise is much
lower than the series noise due to a fast shaping time and the
small leakage current (fA-pA) from the tiny sensor volume.
The rise time, tr, of the front end amplifier is given by:
m
where C L is the load on the output of the front-end amplifier
and C f is the amplitude of the feedback capacitance which is
inversely proportional to the voltage gain of the system. From
these expressions one can observe that C t and C L should be
minimised and g m maximised to obtain high speed. C t may
indeed be minimised by careful detector design, C L by
reducing the load on the preamplifier output, but maximising
g m implies increased power consumption.
III. PIXEL DETECTOR SYSTEMS FOR HEP
There are 4 major developments for HEP experiments
underway at present. The Atlas and CMS vertex detectors are
aimed towards the high event rate p-p experiments at LHC.
The common Alice/LHCb development has two quite
different aims: the rather low event rate but very high
multiplicity Alice vertex detector and the LHCb RICH
detector readout. At the proposed BTeV experiment in
Fermilab the chip should provide information for the first
level trigger. The intention in what follows is to highlight the
similarities and differences between them.
A. Atlas and CMS
t
r
C ( C t L + C f )
∝
g C
Atlas and CMS have very similar environments. Both
vertex detectors must withstand neutron fluences of up to
10 15
neq/cm 2
and each has to provide unambiguous 2dimensional
hit information every 25 ns. Both have the usual
requirements of minimal power consumption and material. As
the total neutron fluence is well above the value where the ntype
bulk material behaves as p-type, n +
on n detectors are
used. Atlas uses a p-spray as isolation between pixels [12] and
CMS uses two concentric broken p +
guard rings [13]. Both
experiments expect to operate the detectors not fully depleted
near the end of the lifetime because of reverse annealing.
Therefore the most probable peak energy deposited by
particles will be strongly attenuated. There may also be
charge collection time issues. As mentioned above a threshold
must be set in each pixel to keep the data volume from the
detector manageable and this should be around one third of
the most probable peak. This implies that the required
minimum operating threshold be around 2 - 2.5 ke -
. The Atlas
group has decided for rectangular pixels (50 µm x 400 µm)
f
giving optimum spatial resolution in r-φ while CMS planned
to have square pixels (at present 150 µm x 150 µm) making
use of the Lorentz angle of the charge drift in the sensor
produced by the 4 T magnetic field at CMS. Both experiments
elected to make first full scale prototype chips in the DMILL
technology [14] and this has had a strong influence on the
choice of layout and readout architecture.
The Atlas chip is organised as a matrix of 18 x 160 pixels.
The layout of the cell is such that the columns are grouped as
pairs enabling two columns to use the same readout bus. This
means that the layout is flipped from one column to its
neighbour, a practice which is not normally recommended
where transistor parameter matching is important. Each pixel
comprises a preamplifier-shaper (t peak = 25 ns) with a transistor
in feedback which is biased by a diode connected transistor
connected to the preamplifier output followed by a
discriminator, see Fig. 2 taken from [15]. There is a 3-bit
register which permits threshold adjustment pixel-by-pixel
and two further bits which control masking and testing
operations. The power consumption per channel is expected to
be 40 µW. As the feedback is a constant current in the linear
range of the amplifier the discriminator provides Time-over-
Threshold (ToT) information.
Fig. 2. Schematic of the Atlas pixel taken from [15].
When a pixel is hit, it sends a Fast-OR signal to the End of
Column (EoC) logic. A token is sent up the column pair and
the first hit pixel encountered puts its address on the bus along
with a timestamp. It does the same for the trailing edge of the
hit. The token then drops to the next hit pixel. There is an 16cell
deep hit buffer at the bottom of the column which stores
the addresses, timestamps and ToT values for the hit pixels.
There is also logic at the End of Column (EoC) which
compares the timestamps of the hits with the external trigger
input. Extra peripheral logic is used to package the hit
information into a serial stream for readout. Although results
on test chips were encouraging [16] the first results from the
bump-bonded full-scale prototypes were disappointing. Some
of the problems were traced to yield issues associated with the
very high component density of the design. A new full-scale
prototype is under development using deep sub-micron
technology.
The CMS chip is organised as a matrix of 53 x 52 pixels.
Also in this case alternating columns are mirrored and
grouped as pairs, two columns sharing the same readout bus.
The front-end is a classic preamplifier-shaper circuit
(t peak = 27 ns). The schematic of the front-end is shown in
Fig. 3 taken from [17]. The buffered output of the shaper is
sent to a discriminator which has a 3-bit trim DAC. At the

output of the discriminator a pulse stretching circuit is used to
produce a signal which sample-and-holds the analog value of
the buffered shaper output. The pulse width is tuned to sample
the analog signal on or near to the peak. The power
consumption of one pixel is around 40µW.
Fig. 3. Schematic of the CMS pixel cell taken from [17]
When a pixel is hit a Fast-OR signal is sent to the EoC
logic and this saves a timestamp and sends a token through
the column pair. Up to 8 timestamps can be saved in the EoC.
When the token arrives at a hit pixel both the address and the
analog value of the hit are sent to the EoC as analog signals.
There is a 24-deep buffer which stores this information. The
timestamp, addresses and analog values of the hit pixels are
sent as analog information to the control room following a
positive comparison of the hit timestamps with the Level 1
trigger. Good results have been reported from smaller test
chips [18] and a full-scale prototype is almost ready for
submission. There are also plans to convert the design to deep
sub-micron technology in the coming year.
B BTeV
There is one large-scale development underway inside the
HEP community but outside the LHC programme. This is the
FNAL pixel development which aims towards the proposed
BTeV experiment but which might also be useful for the
upgrades of the other experiments at the Tevatron. The
radiation environment at the BTeV experiment is similar to
the LHC but the bunch crossing interval is 132 ns instead of
25 ns. n +
on n detectors will be used but the decision about pspray
or p-stop isolation is pending. The group chose to
design the chip in deep sub-micron CMOS following the
radiation tolerant design techniques used by the RD49
Collaboration [19]. Interestingly, the FNAL team developed a
common rules file which allows them produce a design which
is compatible with two different 0.25 µm processes.
The largest prototype to date has 18 x 160 pixels and the
pixel cell size is 50µm x 400µm. Each cell has a preamplifier
followed by a shaper (t peak = 150 ns). The feedback of the
preamplifier has two branches: a very low bandwidth
feedback amplifier which drives a current source at the input
which compensates for detector leakage current, and a simple
NMOS transistor which provides the fast return to zero, see
Fig. 4 taken from [20]. This dual feedback system was needed
as the W/L ratio of the enclosed gate NMOS cannot be made
lower than 2.3 [21]. Another unique feature of the pixel cell is
the 3-bit ADC which has been implemented at the output of
the shaper.
Vdda
Sensor
-
+
Test
Vff
Inject
Vref
-
+
Threshold
Thresholds
Flash Latch
Thermometer
to Binary
Encoder
Command Interpreter
00 - idle
01 - reset
10 - output
11 - listen
4 pairs of
Command Lines
RFastOR Throttle
HFastOR
Fig. 4. Schematic of the BTeV pixel cell taken from [20]
Kill
Token Out
When a pixel is hit it pulls down a Fast-OR signal which
indicates a hit to the EoC logic. The EoC logic notes the
timestamp and sends a token up the column. When a hit pixel
receives the token it sends its address and the contents of the
ADC to the EoC. There is some core logic which packages
the timestamp, address and amplitude information for
immediate readout. In the case of BTeV this information is
used in the generation of the first level trigger.
C Alice/LHCb
The chip which has been developed for the Alice tracker
and the LHCb RICH readout is probably the most
complicated of the readout chips to date containing over 13
million transistors. Neither experiment expects a radiation
dose even close to those of Atlas and CMS. Straightforward p +
on n detectors were chosen as these are cheaper and easier to
obtain. The chip has a matrix of 256 x 32 cells and each cell
measures 50 µm x 425 µm. The preamplifier is differential
which should improve the power supply rejection ratio and
limit the substrate induced noise at the expense of increased
power consumption. As a fast return to zero was required for
the LHCb application a new front-end architecture was used
which uses the preamplifier along with two shaping stages,
see Fig. 5 taken from [22]. The circuit is ready to accept
another hit after 150 ns. The output of the second shaper is
connected to a discriminator with 3-bits of threshold adjust.
There are two readout modes of operation: Alice and LHCb.
Resets
Bus
Controller
ADC
Row
Address
Read Clock
Read Reset
Token In
Token Reset

IN
C in
L.F.
Feedback
Preamp Shaper Shaper
#1 #2 Discrim.
Bias
test FF
Analog test input
Thres.
Th. Adj.
FFs
Fig. 5. Schematic of the Alice/LHCb pixel cell.
3
FO-FM
delay
8
BCO
mask
FF
Coinc.
logic
strobe
In Alice mode, if the discriminator fires one of the two
registers stores the timestamp in the block marked delay. The
contents of the 8-bit timestamp bus are ramped up and down
with a modulo determined by the Level 1 trigger latency.
When there is a coincidence with a Level 1 trigger and a hit
resulting from the positive comparison of one of the register
contents with the timestamp, a 1 is put in a 4-bit FIFO. A
Level 2 trigger accept triggers the transfer of the FIFO
information to a 256-bit shift register for readout.
In LHCb mode, the outputs of the discriminators of 8
pixels are ORed together and the 16 registers are used
sequentially to store timestamps. On Level 0 trigger the event
is stored in a 16-bit FIFO. A Level 1 trigger initiates the
readout of the matrix. 32 clock cycles are needed for full
readout. A full description of the readout system is given in
[23]. Results from this full scale prototype chip are presented
in [24].
D General remarks
All of the above developments are either aiming at, or have
achieved, noise levels of less than 200 e - rms and a threshold
uniformity at or below that level. The requirements in timing
and power consumption are similar also. It is interesting to
note that the developments using DMILL have chosen
architectures which require < 100 transistors per pixel while
the other developments use many hundreds of transistors with
the attendant increase in functionality and pixel complexity.
A common issue however, is that the tracking precision of
all of these detectors is not limited by pixel dimension but by
material thickness. Thinner detectors and electronics are
desirable but these are fragile. A main contributor to material
is the cooling systems which are required to evacuate the heat
dissipated by the electronics. At around 100 µW/pixel the
total power consumption is around 0.5 W/cm 2 . This gives
some hints about where future technical efforts should focus.
IV. FUTURE TRENDS
4-bit
FIFO
R W
data
FF
Vertex detector development is now and forever
intimately linked to developments in the electronics industry.
Even the CERN pixel developments follow Moore's law of
exponentially increasing component density with time [25].
Experience with the LHC pixel detectors has taught us that we
ou
t
Previous pixel
DFF
Next pixel
DFF
must use as much as possible industry standard technology to
be able to achieve our aims within a tolerable price range.
New particle accelerators beyond LHC and the Tevatron
are being discussed. It may be that technical limits in the
detectors should now be given serious consideration in the
earliest stages of design of new machines. One of the major
issues here is the problem of cooling and its influence on
material and hence tracking precision. As the push towards
smaller pixels continues the power consumption density (for
the same time precision) increases. This is because the input
capacitance is dominated by pixel-to-pixel capacitance and
the total pixel-to-pixel capacitance per unit area increases
with granularity. Increasing the bunch crossing frequency
would lead to a further increase in power density.
Radiation tolerance of future CMOS technologies seems
to be obtainable using the design techniques already
mentioned. However, it will be necessary to monitor carefully
each generation of technologies for unexpected phenomena.
In all cases Single Event Upset will probably present the main
challenge to designers.
There seem to be two kinds of machine emerging each
having a distinctive physics reach and environment: the large
linear electron-positron colliders, and the next generation of
hadron colliders. The e-p machines will provide events which
are essentially clean with low multiplicity and with event rates
in the range of kHz. For these applications it may still be
possible to use projective detectors or pixel-type detectors
where every pixel is read out. CCD and APS sensors seem the
most likely candidates here. Both detectors provide the very
highest spatial resolution but the readout tends to be relatively
slow. APS sensors based on standard CMOS technologies are
being studied [26].
For the hadron machines the pattern recognition capability
of pixel detectors is likely to still be the dominant
requirement. The very tiny charge collection from standard
APS detectors makes achieving good pattern recognition
extremely difficult. An interesting modification to the APS
idea is presented in [27]. In this development cooling is used
to obtain a larger charge collection in the substrate of the
standard CMOS components. Also an interesting detector
biasing scheme is proposed. Cryogenic CMOS is discussed
later. However, developing cryogenic mixed-mode electronics
on top of the sensor volume remains a formidable challenge.
There are some developments which could be applied in
many future pixel systems. MCM-D is a technology which is
of great interest although it has only been studied so far by the
Atlas pixel community [28] who had both the courage and the
resources to investigate it. Here the detector is used as the
substrate and the MCM layers, which are alternately BCB and
metal, are grown on top. In this way each pixel is connected
through the layers to its bump bond and all of the readout
lines and power supply lines can be brought in on the same
substrate. As high dielectric constant insulating layers may be
used power supply decoupling can be provided as well. This
technology offers great promise as it leads to a reduction in
the overall mass of the detector while offering good

mechanical rigidity and at the same time the possibility to
map sensor elements to readout channels of different
dimensions.
Some detector development work based at
Stanford/Hawaii [29] uses reactive ion etching to make high
aspect ratio holes in Si. These are subsequently filled with
doped Si to make a detector which is made up of pillars of
alternating p +
and n +
doping. This has the advantage that the
voltage needed to deplete the detector is much reduced and
may be of particular interest in detectors where radiation
damage causes inverse annealing to take place. Of particular
interest to the pixel community in general would be the
possibility this technology might offer in reducing strongly
the dead area which surrounds present pixel detectors for
guard rings. One could imagine that the same technique is
used to etch a very clean cut near the edge of the sensitive
pixel matrix. This edge may have doped Si applied and this
would limit the electric field laterally. Also the clean edge
from the etch might reduce surface leakage currents.
Cryogenic operation of the readout electronics has the
advantage that a better transconductance to drain current ratio
is obtained even if the transistor thresholds are increased [30].
This may lead to the possibility of reducing the problem of
power consumption density. In any case cryogenically cooled
Si detectors, with or without defect engineering [30, 31], will
probably be used in future experiments. There is a whole new
field of mixed-mode, cryogenic deep sub-micron design
opening up.
V. SUMMARY AND CONCLUSIONS
Pixel detectors are key components in most new large
scale HEP experiments. The developments for the LHC
experiments are well under way with most groups now
focussing on deep sub micron CMOS. All of the present
systems are limited in physics performance by materials
budget which is strongly correlated to power consumption
density and the subsequent cooling systems. Expected
increases in granularity and speed in future systems will
require very careful system optimisation. Novel circuit
architectures should be developed and some technology
advances may also help.
VI. ACKNOWLEDGEMENTS
Many people assisted me in preparing this manuscript and
the associated talk. I am particularly indebted to Kevin
Einsweiller of Atlas, Roland Horisberger of CMS and Abder
Mekkaoui and Ray Yarema of BTeV for providing me with
material. I receive constant help and encouragement from my
friends and colleagues in the CERN Microelectronics Group,
the Alice and LHCb RICH pixel teams and the Medipix
Collaboration. Dave Barney and Mike Lamont advised me on
machine matters. Erik Heijne and Cinzia Da Via' contributed
greatly with discussions about present and future detectors.
VII. REFERENCES
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Abstract
Some principal design features of front-end electronics
for calorimeters in experiments at the LHC will be
highlighted. Some concerns arising in the transition from
the research and development and design phase to the
construction will be discussed. Future challenges will be
indicated.
I. INTRODUCTION
Calorimetry in large detectors at the LHC poses some
requirements on readout electronics that are quite different
than for any other detector subsystem. The main distinction
is, a) in the large dynamic range of energies to be measured;
and b) uniformity of response and accuracy of calibration
over the whole detector. As in all other functions of the
detector, low noise of front-end amplifiers is essential.
Unique, too, is the requirement for very low coherent noise,
as the energy measurement involves summation of signals
from a number of calorimeter sections (towers, strips,
preshower detectors). Power dissipation and cooling is a
major concern as in any other detector subsystem, in some
respects only more so, since all the elements of the signal
processing chain require more power due to the large
dynamic range, speed of response, high precision, and low
noise at higher values of electrode capacitance.
The key requirements on the calorimetry readout
electronics are summarized in Table 1. The requirements
are clearly most demanding in electromagnetic (EM)
calorimetry. The dynamic range is somewhat smaller for
hadron calorimeters. However, the noise has to be low, if
muons have to be observed, and since in hadron shower
energy measurement the signals from a larger volume of
the calorimeter have to be added up.
While there are quite significant differences in the
principles and the technology among various scintillatorbased
calorimeters and those based on ionization in liquids,
the signal is finally reduced to charge (current) from a
capacitive source in all cases, and the signal processing
chain – in a simplified picture – could be identical.
* Work supported by the U.S. Department of Energy: Contract No. DE-
AC02-98CH10886.
Electronics for Calorimeters at LHC
Veljko Radeka
Brookhaven National Laboratory, Upton, NY 11973-5000
radeka@bnl.gov
Major design differences in the readout design arise in
different experiments from trying to balance the answers
to two questions: a) how much electronics and what
electronic functions need to be on the calorimeter; and b)
how to minimize the number of interconnections and
transmission lines (copper or fiber) for transfer of
information from the calorimeter.
Each experiment uses a unique approach, in which
preference of the designers has played a decisive role. One
of the design considerations was how near to the signal
input to digitize and, consequently, whether to have an
analog or digital pipeline. The readout systems were
described in some detail in the Proceedings of the 6th Workshop on Electronics for LHC Experiments, 2000. The
two large hadron collider experiments, CMS and ATLAS,
each have several different types of EM and hadron
calorimeters for the barrel, end-cap, and forward regions.
I will comment here only on some common or unique
readout aspects, and not attempt to review readouts for all
calorimeter components. ALICE has one EM calorimeter
over a small solid angle, based on lead tungstate crystals
and avalanche photodiodes as in CMS, but taking advantage
of a lower operating temperature (-25C) and a longer
shaping time (~ 3 microseconds) to obtain a larger signal.
Table 1: Key Requirements on Calorimeter Readout
1. Energy Resolution
EM:

ECAL
HCAL
SPD
PreShower
clip
PM
clip
PM
3m Optical fibre PM
SPD
VFE
3m Optical fibre PM PRS
VFE
Analogue 10 m
same
electronics
Digital 5 -15 m
Analogue 5-15 m
II. UNIQUE ASPECTS OF LHC CALORIMETER FRONT-
END ELECTRONICS
A. LHCb
Although a limited solid angle experiment, LHCb has a
large sampling calorimeter based on scintillatorwavelength
shifter technology and on photomultiplier light
readout. The readout concept for the four calorimeter
components, and the location of various functions, is shown
in Fig. 1. ECAL and HCAL have a significantly larger light
output with smaller fluctuations and they use a
deadtimeless integrator (integrator filter without any
switches). The concept is illustrated in Fig. 2. The dominant
component of the photomultiplier signal decays
exponentially with a time constant of ~ 10 ns, allowing
formation of a short pulse by delay line clipping. The flat
top provides a degree of independence from small
fluctuations in the time of arrival and the shape of the
ADC
Pipeline
ADC
Pipeline
L0
L0
Trigger
Readout
Readout
Trigger
Figure 1. Front-End Electronics for LHC calorimeters. (Design of the
Integrator Filter for ECAL and HCAL is by LAL Orsay, and VFE for
the Scintillator Pad Detector and for the Preshower is by LPC Clermont-
Ferrand.)
PM
AMS BiCMOS 0.8u ASIC
4 channels per chip
50 Ω
5ns - 50 Ω 25ns - 100 Ω
100 Ω
100 Ω
Analog chip
Rf = 12 MΩ
Cf = 2pF
-
ADC
+
100nF
22nF
Buffer Integrator
Figure 2. Principle of the Integrator Filter for the LHCb ECAL and
HCAL. The exponentially decaying signal is first clipped at the
photomultiplier output to 5 ns. The integrator receives the clipped
signal, and then after 25 ns the same but with opposite polarity, to
provide an output with a flat top, which returns to zero, as shown in
Fig. 3.
Current [a.u.]
Voltage [a.u.]
0
Buffer output current before integration
T=0 T=25ns
Output integrated signal
0
0 10 20 30
Time [ns]
40 50 60
Strobe on the flat top ( ≈ 10ns).
Shaping : h(t) = ∫ [i(t)-i(t+25ns)]dt
Figure 3. Signals in the Integrator Filter in Fig. 2.
signal. At the integrator output, the pileup for consecutive
pulses spaced more than 25 ns is negligible. The dynamic
range of this circuit is about 4×103 .
The scintillator pad detector and the preshower have a
lower light output with larger fluctuations, so that switched
integrators were found to be more appropriate.
The design for essentially all circuits for LHCb
calorimeters has been completed, and prototype circuits
completed and tested (also in the test beam). (One more
ASIC iteration for the Integrator Filter is planned only for
a small change.) The review of calorimeter electronics
performed in April, 2001 was, overall, very positive. The
only significant finding was that the power distribution
system has not been designed yet.
B. CMS Electromagnetic Calorimeter
This is a total energy absorption calorimeter based on
lead tungstate (PbWO ) crystals and avalanche photodiode
4
(APD) readout for the barrel, and vacuum phototriode in
the endcaps. An outline of the electronics chain is shown
in Fig. 4, illustrating the “light-to-light” readout, with an
ADC at the detector and an optical fiber for data
transmission for each crystal. This is the most ambitious
subsystem in terms of the number of optical fibers. The
dynamic range for the ADC is reduced by using four
different gains in a configuration called Floating Point
PreAmplifier (FPPA)[1], Fig. 6. The signal before and after
shaping is shown in Fig. 5. The noise requirements in this
case are rather stringent: a) the light signal from lead
tungstate is small, resulting in ~5 photoelectrons/MeV in a
pair of APDs; b) APD gain is expected to be ~50; and c) the

Energy
→
Light
Light
→
Current
Current
→
Voltage
PbWO 4 APD FPPA
Voltage
→
Bits
ADC
Bits
→
Light
Σ
Pipeline
To DAQ
Upper-Level VME Readout Card
(in Counting Room)
Digital
Trigger Σ
Figure 4. Readout chain for the CMS electromagnetic calorimeter. Preamplifier with range selection (Floating Point Preamplifier – FPPA) and
analog-to-digital converter are located at the detector (PbWO 4 crystals with avalanche photodiode readout). There is 1 fiber per crystal for data
transmission from the detector. Digital pipelines are in the counting room.
Preamp Output [V]
1.0
0.8
0.6
0.4
0.2
Pk-2
Pk
Pk-1
Pk+1
0
0
0 50 100 150 200 250
Time [ns]
1.0
0.8
0.6
0.4
0.2
Photocurrent [mA]
Figure 5. PbWO 4 /APD signal before and after shaping. Sampling points
every 25 ns are indicated.
External feedback
Cd
APD
Q2
R1
Q1’
Q1
Rf
Cf
Cc
-A
Baseline
control
Input transconductance
dominated by R
Current feedback amplifiers
(Closed loop BW: 250 MHz)
Vref
(from ADC)
+
X1
-
+
X5
-
+
X9
-
+
X33
-
R
R
R
R
Matched R and C
C
C
C
C
To FPU
Figure 6. Circuit topology of the CMS ECAL floating point preamplifier.
Four samples at different gains are stored every 25 ns. The sample
with the highest gain below saturation is selected and fed to the ADC
via a multiplexer, resulting in a waveform as in Fig. 7.
capacitance of interconnections and APDs optimized with
respect to the crystal and the sensitivity to shower particles
is ~200 pF. The noise in an ideal case is determined by
transistors Q and Q and by R . The signal at the output of
1 2 1
the analog multiplexer, composed of analog samples with
different gains, is shown in Fig. 7.
The FPPA has been fabricated in bipolar technology and
functional tests have been satisfactory, but one more run
is in process to satisfy the noise requirements.
Power dissipation per channel is expected to be ~1.4
watts, resulting in about 100 kwatt at the detector.
Preamp. output
33 9 5 9
33
Gain
FPPA output
40MHz clock
Figure 7. Waveform at the output of the analog multiplexer of CMS
ECAL floating point preamplifier (FPPA). It consists of consecutive
samples every 25 ns, each sample taken from one of the four amplifiers
which provides the best precision for a given signal amplitude (a short
transient is superposed as boundaries between different gains are
crossed; sample magnitudes are measured at points in between the
transients).

Test Pulse
Test Pulse
SPLITTER
INTEGRATOR
ENCODER
CMS QIE
CMS QIE
FADC
Exponent(1:0)
CapID(1:0)
Mantissa(4:0)
Clock
Reset
Pedestal(3:0)
Clock
Reset
Pedestal(3:0)
Exponent(1:0)
CapID(1:0)
Mantissa(4:0)
Channel
Control
ASIC
Global Reset
Bunch Crossing Zero
40 MHz Clock
Clock
Data(15:0)
Control
Serial Control Bus
800 Mbit/s
Serializer
Figure 8. Block diagram of the CMS hadron tile calorimeter readout. The front end, including analog-to-digital conversion, is based on the
pipelined multi-ranging integrator and encoder (ref. ), known as “QIE”. The encoder is based on a multi-ranging current splitter and a nonlinear
flash ADC. Encoded samples are serialized and transferred from the detector by (one) optical link for every two channels.
C. CMS Hadron Calorimeter
The photodetector for the tile calorimeter is a hybrid
photomultiplier (HPD), which can operate in the strong
magnetic field. This unique approach [2,3], illustrated by
the block diagram in Fig. 8, has been developed in an
attempt to digitize the signal very near to its source. It
combines a multi-ranging integrator and a nonlinear flash
ADC, with a response as in Fig. 9. The nonlinear 5-bit ADC
provides constant resolution of ~0.9% rms in each range.
All of these functions have been incorporated in a single
ASIC, realized in a BiCMOS technology. Functional tests
of the prototype have been satisfactory. One more run
before production may be needed.
D. ATLAS Liquid Argon Calorimeter
Each readout channel has three gain ranges with 12-13
bit dynamic range each and linear response. It is also the
only one of the LHC experiments using switched capacitor
arrays as analog memories. After digitization, the data are
transferred via optical links. The only communication via
(differential) copper transmission lines is for analog sums
Nominal QIE8 ADC Counts
35
30
25
20
15
10
5
0
VCSEL
for level 1 trigger. The power dissipation in the front-end
board is ~0.7 watts/channel for all functions. The design
of all the circuits located on the detectors in the front-end
crates, which serve as a “Faraday Cage” (Figs. 10 and 11),
has been completed. Analog parts (preamps, shapers, SCAs)
are in mass production in radiation-resistant technologies.
Range 0
Range 1
Range 2
Range 3
0 5 10 15 20 25 30
Input Charge (pC)
Figure 9. Response of the CMS charge integrator encoder (QIE) over
the four gain ranges.

Accordion
Electrodes
SB
MB
Mother Boards
& Calibration
Back
Front
Cold Vessel Warm Vessel
Cryogenic Services
Faraday Cage
Front End Board
Pedestal and Warm Cable
Vacuum Cable
Cold Cable & Pigtail
Feedthrough
Figure 10. An illustration of the readout of the ATLAS liquid argon
(barrel) EM calorimeter. The crates (“Faraday Cage”) containing all
the functions outlined in the lower half of Fig. 11 are mounted directly
on signal feedthroughs.
The digital part has been prototyped in radiation hard
technology. The emphasis in testing has been on fine
effects important for calibration and coherent noise. These
are illustrated in Figs. 12-14. Due to the uniformity and
stability of an ionization calorimetry response, an accurate
intercalibration by electronic means is practical. A small
effect on calibration (a few tenths of one percent) of the
small inductance of electrode connections is illustrated in
Fig. 12. This effect is inversely proportional to the shaping
time. Fig. 14 shows the dependence of the coherent noise
on shielding and grounding of the front-end boards in the
front-end crate. An attenuation of the EMI (from digital
operations) of ~10 6 is required to achieve a usable dynamic
range approaching 10 5 .
III. DYNAMIC RANGE IN THE FRONT-END
All the readout schemes for a large dynamic range
(approaching 105 ) require multiple gain ranges (or multiranging)
prior to analog-to-digital conversion at the speed
of interest at the LHC. To achieve this dynamic range, an
input stage with sufficiently low noise – where the noise
of a single input transistor dominates – is required. An
example is the configuration in Fig. 15. More generally,
the problem is illustrated in Fig. 16. The noise value
assumed is for the best bipolar junction transistors and
advanced CMOS devices. It corresponds to an equivalent
series noise resistance of ~15 ohms. Even if the intrinsic
device noise could be reduced below this value (by
increasing the device width and/or reducing the electron
transit time), lower values are difficult to realize in practice
due to additional resistances, e.g., in the base or in the
metalization in monolithic circuits. The maximum signal
at the preamplifier output is likely to be even less than 3
volts, particularly as the trend to lower operating voltages
continues. This limits the dynamic range of a linear frontend
stage to about 10 5 (an analysis with respect to the
current gives the same result). This happens to be just
sufficient for EM calorimetry at the LHC.
IV. MAIN CONCERNS FOR LHC CALORIMETRY
ELECTRONICS
A. Transition from R&D Mode to Production
Mode
A number of ASICs for almost all calorimeters need “one
more iteration”. Finalizing an ASIC is a balance between
when and where to stop making incremental improvements
and the designer’s reluctance to sign off on the final design.
This has affected the construction schedules to the extent
that electronics has become a critical path item in several
calorimeter subsystems.
B. Radiation Hardness
The progress in designing circuits in radiation hard
technologies and in testing and qualifying commercial-offthe-shelf
components has been good, but this very tedious
process will also have an adverse effect on the construction
schedules. The advent of 0.25 micron CMOS technology,
and the contribution by the CERN group to the design of
standard cells, have been most valuable.
C. Low Voltage Regulators
Some readout boards require 10-20 radiation-resistant,
low voltage regulators. These are under development by
the CERN project RD49 with S. T. Microelectronics. Some
development problems appear to have been overcome and
a critical evaluation of a large number of samples is
expected to be performed soon. These regulators are the
most prominent item on the critical path list for the design
and construction of readout boards.

C d
Cryostat
Motherboard
Electrode
T=90K
~15k
~180k
Calibration
Preamps
Tower Builder
Control
On Detector (Faraday Cage)
Front End Crate
Front End
Board
R c
L c
Clock
Shapers
DAC
SCA (144 Cells)
Control
I
Layer Sum
Buffering
&
ADC
40MHz CLK
LV1 Acc.
Reset
Controller
Optical
Link
32 Bits
40 MHz
CPU
Level 1
Interface
System Control
Mapping Board
E= Σ a S
i i
T= Σ b S
i i
TTC Interface
Trigger Cavern
Calorimeter
Monitoring
TTC
ROD
Level 1
Processor
Figure 11. Readout chain of the ATLAS liquid argon calorimeter. After the preamplifiers, the readout chain is identical for all the liquid argon
calorimeters. The end-cap hadron calorimeter has preamplifiers based on GaAs technology at the electrodes inside the cryostat. Each preamplifier
output is split into three shaping amplifiers with different gains and analog (switched capacitor) memories, and then digitized with 12 bit
resolution. Data are transferred from the detector via one optical link for every 128 signal channels.
128 outputs
5Ω
0.1%
5Ω
0.1%
PMOS
10000/0.8
PMOS
10000/0.8
+5V
NE 856
-
Low
Offset
+
enable
+
Low
Offset
128
DAC
16 bits
16
Driver
White
follower
8
Calib
Logic
SPAC
Slave
TTCRx
Figure 12. Calibration signal generator. A dc current controlled to 0.1% is switched off to generate on an LR network an exponentially decaying
current pulse which approximates closely (within the shaping time) the calorimeter signal.
Delay
CTP
2
2
1
Ext.
Trig.
Network
DAQ

ADC Counts [RMS]
25
20
15
10
Calibration Board
Amplitude [V]
-0.35
0
No shields
MotherBoard &
Summing Board
R inj
PA-out
Detector
Max Signal 3 TeV ~7.5mA 2.5V
Random noise/channel 40MeV 100nA 33µV
Sum of 64 channels 320MeV 0.8µA 260µV
Coherent noise in the sum
~ 200nA < 64 µV
Coherent noise in one channel 3nA

1 ⁄ gm1 RC1 ZIN = ---------------- + --------------------------
G 1 + R2 ⁄ R1 RC2 G = -----------------------------------------
1 ⁄ gm2 + R1//R 2
ΖIN
T1
Vcc1
RC1
Vcc2
RC2
Figure 15. LAr calorimeter preamplifier configuration with well defined
input impedance. The conversion gain (output voltage/input current)
is determined only by R C1 , and the noise is determined only by T 2 .
E. Availability of Semiconductor Technology
and Lack of Resources for Spares
We have to assume that some (or most) of the technologies
of ASICs will not be available throughout the lifetime of the
experiments. This requires careful planning for acquisition
of ASICs, and/or additional wafers for any replacement
maintenance.
V. FUTURE CHALLENGES – “ENERGY AND LUMINOSITY
FRONTIERS”
From recent discussions and studies about future hadron
accelerator developments, two major advances are being
considered. One is a continuing quest for increasing
luminosity – an increase by an order of magnitude at the
LHC is already being contemplated. Considering the
difficulties that had to be overcome, and the time and effort
still being expended in the development of the radiation
hard electronics for the present design luminosity, this will
be a challenge which will require a renewed major R&D
effort.
On a longer time scale, there is also a continuing quest
for higher energies (Snowmass 2001). The dynamic range
required in EM calorimetry at the LHC is just about at the
limit that a front-end amplifier device can accommodate
in linear regime, as discussed in Section III. A very large
hadron collider (“VLHC”) will require a different approach
to the dynamic range problem than the present designs for
the LHC.
R1
T2
1
R2
Vo
I(t)
Preamplifier Gain ~10
e n
C D
Z f
-
e n ≅ 0.5 nV/Hz 1/2
BW ≅10MHz
n e n
n ≥ 2
2 nd stage
} ⇒3µV
Noise at preamplifier output ≅ 30 µV (Gain ~ 10 to overcome second
stage noise)
Max signal at preamplifier output ≅3V (technology dependent)
Max dynamic range (with respect to rms noise) ~ 10 5 (or 16-17 bits)
Figure 16. Dynamic range limit for the linear preamplifier is limited by
the ratio of the maximum voltage amplitude at the output divided by
the noise over the bandwidth of interest.
VI. ACKNOWLEDGEMENTS
The information and some of the material for this report
has been generously provided by J. Christiansen for LHCb,
P. Denes and J. Elias for the CMS, B. Skaali for ALICE, and
W. Cleland and C. de La Taille for ATLAS. Discussions
with them are gratefully acknowledged. In the brief
comments here, it was not possible to acknowledge the
large efforts and individual contributions that went into
the development of the elaborate readout electronics for
LHC calorimeters.
The author is grateful to his colleague, B. Yu, for his
help in preparing this report.
VII. REFERENCES
1. P. Denes, private communication.
2. R. Yarema, et al., “A Pipelined Multiranging Integrator
and Encoder ASIC for Fast Digitization of Photomultiplier
Tube Signals”, Fermilab-Conf-92/148.
3. T. Zimmerman and M. Sarraj, “A Second Generation
Integrator and Encoder ASIC”, IEEE Trans. on Nucl. Sci.
Vol. 43, No. 3, June (1996), p1683.
4. H. Takai, et al., “Development of Radiation Hardened
DC-DC Converter for the ATLAS Liquid Argon
Calorimeter”, these Proceedings.

I. EVOLUTION AND REVOLUTION
FPGA progress is evolutionary and revolutionary.
Evolution results in bigger, faster, and cheaper FPGAs, in
better software with fewer bugs and faster compile times, and
in better technical support.
Users expect large capacity at reasonable cost (100,000 to
millions of gates, on-chip RAM, DSP support through fast
adders and dedicated multipliers). System clock rates now
exceed 150 MHz, which requires sophisticated clock
management. I/Os have to be compatible with many new
standards, and must be able to drive transmission lines.
Designers are in a hurry, and expect push-button tools with
fast compile times, and a wide range of proven, reliable
cores, including microprocessors. And power consumption is
a serious concern.
Progress is driven by semiconductor technology, giving us
smaller geometries, and more and faster transistors. Improved
wafer defect density makes it possible to build larger and
denser chips on larger wafers at lower cost.
Innovative architectural and circuit features are equally
important, as are advancements in design methodology,
modular team-based design, and even internet-based
configuration methods.
Figure 1: A Decade of Progress
1000x 1000
100x 100
10x
10
1x
1
Capacity
Speed
Price
XC4000
1/91 1/92 1/93 1/94 1/95 1/96 1/97 1/98 1/99 1/00 1/01
Year
Evolution, Revolution, and Convolution
Recent Progress in Field-Programmable Logic
P. Alfke
Xilinx, 2100 Logic Drive, San Jose, California 95124
peter.alfke@xilinx.com
Virtex-II
(excl. Block RAM)
Virtex & Virtex-E
(excl. Block RAM)
Spartan
II. HISTORY
Over the past 10 years, the max FPGA capacity has
increase more than 200-fold (from 7,000 to 1.5 million
gates), speed has increased more than 20-fold, and the cost
for a 10,000-gate functionality has decreased by a factor of
over a hundred. There is every indication that this evolution,
the result of “Moore’s Law”, will continue for many more
years.
Supply voltage is dictated by device geometries, notably
oxide thickness, and is on a steady downward path. This
results in faster and cheaper chips, and it reduces power
consumption dramatically, but it also causes problems in
power distribution and decoupling on the PC-board. That is
the price of progress!
XC4000 and Spartan families use a 5-V supply, The –XL
families use 3.3 V, Virtex and Spartan-II use 2.5 V, (but also
3.3 V for I/O). Virtex-E uses 1.8 V, and Virtex-II and the
upcoming Virtex-IIPro use 1.5 V, but maintain 3.3-V
tolerance on their outputs.
Over the past 16 years, Xilinx has introduced a series of
FPGA families with increasing capabilities in size and in
features.
Figure 2: Logic Capacity and Features
LUTs & FFs Additional Features
• XC4000/Spartan: 152…12,312 Carry, LUT-RAM
• Virtex/Spartan-II: 432…27,648 4K-BlockRAM, DLL, SRL16
• Virtex-E: 1,728…43,200 differential I/O
• Virtex-II: 512…67,548 18K-BlockRAM,
Multipliers, DCM,
Controlled Impedance I/O
• Virtex-II Pro: 2,816…45,184 PowerPC,
3.125 Gbit/sec I/O

Many of the earlier families are still in production (except
XC2000 and XC6200) but the old 5-V families should not be
considered for new designs. 5V was the dominant standard
for over 30 years, but it is now obsolete. Designers must learn
to migrate fast to the newer families that provide a much
more attractive cost/performance ratio. As a general rule, IC
technology matures 15 times faster than a human being. A
technology introduced barely 4 years ago is now well beyond
its prime, and should not be a candidate for new designs,
except in certain niche applications.
For new designs, use Spartan-II, Virtex, and Virtex-E for
their maturity, availability and price, use Virtex-II for higher
performance and advanced features. But for designs starting
in 2002, consider Virtex-IIPro with on-chip PowerPC
microprocessors and gigabit serial I/O.
III. EVOLUTIONARY FEATURES
Virtex devices offer better global clock distribution with
short delays and extremely small skew (

This flexibility is essential when the FPGA must interface
to a wide variety of other ICs. The drive capability is
important for driving transmission lines, since many
interconnect lines must now be treated as transmission lines.
Signal delay on a PC-board is 50…70 ps per cm, which
means that - at a 1-ns transition time - interconnects as short
as 7 cm must be treated as transmission lines to avoid
excessive ringing and other signal integrity issues. The line
must be terminated either at the driving end (series
termination) or at the far end (parallel termination).
Placing these termination resistors around and very close
to 400 – 1100-pin fine-pitch BGA packages is not only
difficult and expensive, but also wasteful in PC-board area.
That’s why Virtex-II now has an option that converts any
output into a controlled-impedance driver, matched to the line
it has to drive. Or any input can be made a termination
resistor. All this is implemented in the I/O buffer on the chip,
right where it is needed. There is no cost and no wasted
space. Digitally controlled impedance is the only practical
way to deal with fast signal edges between high pin-count
packages. And it is available today.
Figure 5: Digitally Controlled Impedance
~12 9
50 9
Impedance
Controller
33 9
50 9
Conventional I/Os
50 9
SelectIO -Ultra
External resistors eliminated
Impedance maintained by FPGA
Figure 6: PC Board Routing Impact
IC1
Resistor
IC2
Conventional
Multiply this by 1000 pins per chip, and by the N chips per board
IC1
IC2
No resistor
DCI
Fewer Layers, fewer resistors, smaller board
In the past, system clock rates have doubled every 5
years, and IC geometries have shrunk 50% every 5 years.
Trace width on the PC-board has always been about 100
times wider than inside the IC. Whenever the clock rate
doubles, the distance a signal can travel in, say 25% of a
clock period, is being cut in half. At 3 MHz in 1970 it was 20
m, at 200 MHz in 2000 it was barely 30 cm, and it will shrink
to 15 cm in 2005, and 7 cm in 2010, as system clock rates
keep doubling. Not a pretty outlook!
This indicates the demise of traditional synchronous board
design. The next wave will be source-synchronous design,
where the clock is intermingled with the data busses, and
clock delay thus equals data delay. High-speed designs will
use double-data-rate clocking, which means the clock
bandwidth need not be higher than the max data bandwidth.
The disadvantage of source-synchronous clocking is the
unidirectional nature of the clock distribution, and thus the
need for significantly more clock pins and clock lines, and
the need to handle multiple clock domains on-chip.
Figure 7: Evolution
Max Clock Rate (MHz)
Min IC Geometry (µ)
Number of IC Metal Layers
PC Board Trace Width (µ)
Number of Board Layers
1965
1
-
1
2000
1-2
Figure 8: Moore vs. Einstein
1980
10
5
2
500
2-4
1995
100
0.5
3
100
4-8
2010
1000
0.05
10
25
8-16
Every 5 years: System speed doubles, IC geometry shrinks 50%
Every 7-8 years: PC-board min trace width shrinks 50%
2048
1024
512
256
128
64
32
16
8
Moore Meets Einstein
Clock Frequency
in MHz
Trace Length
in cm per 1 /4 clock period
4
2
1
’65 ’70 ’75 ’80 ’85 ’90 ’95 ’00 ’05 ’10
Year
M Speed Doubles Every 5 Years…
…but the speed of light never changes

The future solution is bit-serial self-clocking data transfer at
gigabit rates, first 3.125 Gbps for 2.5 Gbps data rate in 2002,
and up to 10 Gbps later. This approach saves pins and makes
physical distances almost irrelevant, especially when using
optical interconnects. The on-chip serializer/ deserializer
(SERDES) performs the function of an ultra-fast UART with
a PLL for clock recovery, 8B/10B encoding/decoding and
local FIFOs, to reduce the parallel data rate by a factor of 16
or even 32.
C. Microprocessors
Incorporating a microprocessor inside the FPGA gives the
user additional freedom to divide the task at hand: use the
FPGA fabric for its very fast, massively parallel operation,
and the microprocessor for the more sophisticated sequential,
and thus slower operations. Soft implementations are
available today. MicroBlaze from Xilinx is a 32-bit RISC
processor running at 125 MHz and using less than 900 Logic
Cells, i.e.

B. Designing for Signal Integrity
Signal Integrity refers to signal quality on the PC-board,
where it is important to avoiding reflections which show up
as ringing, resulting in erroneous clocking or even data dropout.
The user should develop a good understanding of
transmission-line effects, and the various methods to
terminate the lines.
The controlled-impedance output drivers, available on all
Virtex-II outputs, are a big help.
Power supply decoupling is becoming more and more
important. In CMOS circuits, power-supply current is
predominantly dynamic. In a single-clock synchronous
system, there is a supply-current spike during each active
clock edge, but no current in-between. This dynamic current
can be many times the measured dc value, and these current
spikes cannot possibly be supplied from the far-away power
supply. They must come from the local decoupling
capacitors. The rule is: attach one 0.01 to 0.1 uF very closely
to each Vcc pin, and tie them directly to the ground plane.
The capacitance is not critical, low resistance and inductance
are far more important. Two capacitors in parallel are much
better than one large capacitor.
Model the PC-board behavior with HyperLynx. Multilayer
PC-boards with uninterrupted ground- and Vcc planes
are a must, as is the controlled-impedance routing of clock
lines.
1) Tricks of the Trade
To improve signal integrity, reduce output strength. Both
LVTTL and LVCMOS have options for 2, 4, 6, 8, 12, 16, and
24mA sink and source current. Controlled-impedance outputs
(series-termination) is even better, but watch out for loads
that are distributed along the line. They will see a staircase
voltage, which will cause severe problems.
Explore different supply voltages and I/O standards.
Optimize drive capability and input threshold for the task at
hand. Use differential signaling, e.g. LVDS when necessary.
Avoid unnecessary fan-out, load capacitance and trace length.
To combat Simultaneously Switching Output (SSO)
problems causing ground-bounce, add virtual ground pins:
High sink-current output pins that are internally and
externally connected to ground.
2). Test for Performance and Reliability
You can manipulate the IC speed while it sits on the
board:
High temperature and low Vcc = slow operation,
Low temperature and high Vcc = fast operation.
If operation fails at hot, the circuit is not fast enough.
Check the design for speed bottlenecks, add pipeline stages,
or buy a faster speed-grade device.
If operation fails at cold, the circuit is too fast. Check the
design for signal integrity and hold-time issues, check for
clock reflections. Look for internal clock delays causing
hold-time issues, look for “dirty asynchronous tricks” inside
the chip, like decoders driving clocks. In short, if it fails cold,
there is something wrong with the design, not with the
device.
C. BlockROM State Machines.
The Virtex-II BlockROMs can be used as surprisingly
efficient state machines.
With a common algorithm stored in the RAM (used as
ROM) one BlockRAM can implement a 20-bit binary or
Grey counter, or a 6-digit BCD counter (with the help of one
additional CLB). More generally, the two ports of one
BlockRAM can be assigned each half of the RAM space, and
one port be configured 1k x 9. It can be used as a 256-state 4way
branch Finite State Machine. The other port can be
configured 256 x 36, sharing its eight address inputs with the
first port. This one BlockRAM, without any additional logic,
is a 256-state Finite State Machine where each state can jump
to any four other states under the control of two inputs, and
each state has 37 arbitrarily assigned outputs. There are no
constraints, and the design runs at >150 MHz.
Figure 10: Block RAM State Machine
Branch
8 bits
BlockROM
1K x 9
8 + 1 bits
Control bits
Unused
Output
M 256 states, 4-way branch, 150 MHz operation
Branch
Control 2 bits
Block ROM
1K x 9
8 bits 8 + 1 bits
8 bits 256 x 36
36 bits
M 36 additional parallel outputs
Output

D. Designing for Radiation Tolerance
Radiation can hurt CMOS circuits in three different ways:
In the extreme case, it can trigger any CMOS buffer to be
a very low on-impedance SCR. This is called latch-up, and
often destroys the device. In the best case, it requires Vcc
recycling.
“Total dose” effects cause premature aging (threshold
shifts, increased leakage current, and decreased transistor
gain) over time, usually over weeks and months.
There is always the probability of “single-event upsets”
that cause data corruption by changing the state of a flip-flop,
causing a non-destructive soft error.
Xilinx offers variations of certain XC4000XL and Virtex
circuits, manufactured with an epitaxial layer underneath the
transistors, but otherwise identical with their namesake nonepitaxial
commercial parts. These devices have been tested to
be immune to latch-up for radiation up to 120 MeVcm2/mg
@ 125ûC.
These devices tolerate between 60 and 300 krads of total
ionizing dose.
Like with all CMOS circuits, there is the probability of
single-event upsets. But they can easily be detected by
readback of the configuration and flip-flop data, and they can
be mitigated by continuous scrubbing and partial
reconfiguration.
Xilinx and Xilinx users have also tested designs using
triple redundancy to avoid any functional interrupt. For
details, see:
www.xilinx.com/products/hirel_qml.htm
VI. CIRCUIT TRICKS FROM THE XILINX ARCHIVES.
A. Asynchronous clock multiplexing
This circuit handles three totally asynchronous inputs,
Clock A, Clock B, and Select. The output is guaranteed not to
have any glitches or shortened pulses.
Figure 11: Asynchronous Clock MUXing
Clock A
Select
Clock B
D
QA
D QB
Output
Clock
The circuit waits for the presently selected clock signal to
go Low, then keeps its output Low until the other clock input
goes Low and then High.
B. Schmitt Trigger
This simple circuit provides user-defined hysteresis on
one input, but it requires the use of two device pins, plus two
external resistors. It is practical only when significant
hysteresis is absolutely required.
Figure 12: Schmitt Trigger
To
FPGA
Logic
C. RC Oscillator
FPGA
• Hysteresis = 10% of Vcc
This circuit has a wide frequency range, using resistors
from 100 Ohm to 100 kilohm, and capacitors from 100 pF to
1 microfarad. The circuit is guaranteed to start up, is
insensitive to Vcc and temperature changes, and can easily be
turned on or off from inside the chip.
Figure 13: RC Oscillator
Oscillator
Output
FPGA
10R
C
R
R
R
Input
Signal

D. Coping with Clock Reflections
In some cases, the user may have to accept bad clock
reflections. When the PC-board is already laid out it may cost
too much time and money to change the clock lines to have
good signal integrity. The following two circuits suppress the
effect of incoming clock ringing.
The first circuit suppresses ringing on the active clock
edge, shown here as the rising clock edge. A delay in front of
its D input can make any flip-flop insensitive to fast double
triggering. Since the extra clock pulse usually occurs within
2 ns after the active clock edge, the added delay need only be
a few ns, and will thus not interfere with normal operation,
e.g. of a counter.
Figure 14: Reflection on the Active Edge
Delay
• Problem: Double pulse
on the active edge
• Solution: Delay D,
to prevent the flip-flop
from toggling soon again
The second circuit protects against ringing on the other
clock edge, when the flip-flop mysteriously seems to change
state on the wrong clock polarity. No flip-flop can possibly
change state on the wrong polarity clock edge! This
perplexing problem can easily be resolved by using the
inverted clock as a delayed enable input. Right after the
falling clock edge, the flip-flop is still disabled and will,
therefore, ignore the double pulse on the clock line.
Figure 15: Reflection on the Inactive Edge
Delay CE
D Q
D Q
External
Clock
Internal
Clock
Data
Delayed
Data
External
Clock
Internal
Clock
Clock
Enable
These circuits are just BandAids for a poorly executed
design, but they have proven useful in desperate cases.
D. Floating-Point Adder/Multiplier
The combinatorial multiplier in Virtex-II can also be used
as a shifter. Four multipliers can multiply 32 x 32 bits, and
other multipliers can perform the normalizing shift
operations.
This makes it possible to design either IEEE-standard or
even other performance-optimized floating-point units. Fast
floating point is now possible in FPGAs.
VII. THE FUTURE
In 2005, FPGAs will implement 50 million system gates,
have 2 billion transistors on-chip, using 70-nm technology,
with 10 layers of copper metal. An abundance of hard and
soft cores will be available, among them microprocessors
running at a 1-GHz clock rate, and there will be a direct
interface to 10 Gbps serial data.
FPGAs have not only become bigger, faster, and cheaper.
They now incorporate a wide variety of system functions.
FPGAs have truly evolved from glue logic to cost-effective
system platforms.
VIII. LIST OF GOOD URLS
M www.xilinx.com
M www.xilinx.com/support/sitemap.htm
— www.xilinx.com/products/virtex/handbook/index.htm
— www.xilinx.com/support/techxclusives/techX-home.htm
— www.xilinx.com/support/troubleshoot/psolvers.htm
General FPGA-oriented Websites:
—www.fpga-faq.com
—www.optimagic.com
Newsgroup: comp.arch.fpga
All datasheets: www.datasheetlocator.com
Search Engine (personal preference): www.google.com

Single Event Upset Tests of Commercial FPGA for Space Applications 1
Abstract
Space based systems are looking more and more to the
benefits from high performance, reconfigurable computing
systems and Commercial Of The Shelf components (COTS).
One critical reliability concern is the behaviour of the
complex integrated circuits in a radiation environment. Field
programmable gate arrays (FPGAs) are well suited for the
small volumes in space applications. This type of products
are driven by the commercial sector, so devices intended for
the space environment must be adapted from commercial
product. Heavy ion characterisation has been performed on
several FPGA types and technologies to evaluate the onorbit
radiation performance. As the geometry keeps
shrinking, the relative importance of various radiation
effects may change. Investigation of radiation effects on
each technology generation is found to be necessary. This
paper presents methodologies and results of radiation tests
performed on commercial FPGA s for space applications.
Mitigation of Single Event Upsets will be discussed.
I. INTRODUCTION
Programmable logic has advantages over ASIC designs
for the space community in the faster and cheaper
prototyping, and reduced lead-time before flight. FPGAs
based on antifuse technology are frequently used in space
applications. Reprogrammable logic would offer additional
benefit of allowing on-orbit design changes. From Single
Event Upsets point of view the antifuse technology has
offered better control and reliability. However, mitigation
methods for reprogrammable logic technologies are under
constant development. This paper discusses the Heavy Ion
SEU testing of several Actel antifuse-based FPGAs and
Xilinx Virtex FPGA.
A. Test Board
II. RADIATION TEST SYSTEM
The test system developed by Saab Ericsson Space
consist of two boards, one Controller board managing the
test sequence and the serial interface to the PC and one
DUT-board housing two Devices Under Test (DUT). A
Stanley Mattsson
Saab Ericsson Space AB, S-40515 Goteborg, Sweden
stanley.mattsson@space.se
1 This work performed by Saab Ericsson Space, is supported by the European space Agency
schematic drawing is given in Fig.3.
The Controller board tests one DUT at a time using a
"virtual golden chip" test method. The principal of the
measuring technique is to compare each output from the
DUT with the correct data stored in SRAM’s. The general
procedure for the tests are to load data into the devices
under test, pause for a pre-set time, read data out, and
analyse the errors for various error type signatures. New
data are loaded into the DUT at the same time as old are
read out. When an error is detected (when outputs do not
match), the state of all outputs and position in cycle of the
failing shift register will be temporarily stored in FIFOs. Data
in the FIFOs is continually send to a PC through a RS232
serial interface. After each test run the data are analysed
and stored in a database by the controlling PC. For each
DUT, errors can be traced down to the logic module, logic
value and position.
B. Test Facility
Heavy ion tests were performed at the CYClotron of
LOuvain la NEuve (CYCLONE), Belgium. This accelerator
can cover an energy range of 0.6 to 27.5 MeV/AMU for
heavy ions produced in a double stage ECR source. The
use of an ECR source allow the acceleration of an ion
"cocktail" composed of ions with very close mass over
charge ratio. The preferred ion is selected by fine-tuning of
the magnetic field or a slight change of the RF frequency.
Within the same cocktail it takes only a few minutes to
change ion species.
The facility provides beam diagnostic and control with
continuous monitoring of beam fluence and flux via plastic
scintillators. The irradiations are performed in a large
vacuum chamber with the test board mounted on a movable
frame. Normally each device is tested with a variety of
atomic species up to a fluence of 1e+6- 1e+7 ions/cm2,
depending on the cross section for the device under test.

III. ANTIFUSE FPGA TECHNOLOGY
FPGA’s from Actel Corporation are widely used in
Aerospace applications. The company has been providing
products to the stringent space requirements for several
years. During the last years several new products have
been introduced with the aim of having improved radiation
resistance and logic circuit density.
The company uses several different manufacturers for
the wafer production. Only wafers manufactured by
Matshushita (MEC) are used in the products for space. The
same products sold under the same electrical specification
are likely manufactured in several fabs. Some of these
products have been tested for total dose and found only
good for a few krad(Si) total dose. Over the years there have
been many SEU tests using heavy ions performed on Actel
products, both to determine the SEU probability for the user
logic’s as well as determining effects of heavy ions on the
antifuses. [1] Results obtained by Saab Ericsson Space are
presented below.
IV. RESULTS ON ANTIFUSE FPGA
All results presented below have been tested with the
same test method and test board described above.
1.0E-04
1.0E-05
1.0E-06
1.0E-07
1.0E-08
1.0E-09
A14100A Vcc=3.3V & 5V
0 20 40 60 80 100 120
LET (MeV/mg/cm2)
Figure 1 Heavy ion data on Actel A14100A S-module for
5V and 3.3V biasing conditions. Flip from logic “0” to
logic “1” is noted S0. The opposite is noted S1. The
dashed curves are showing the 3.3V data for the two SEU
modes.
S0
S1
S0
S1
Page 2
A. Actel A14100A
This FPGA is manufactured by Matshushita (MEC) in
antifuse ONO gate 0.8μm two-level metal CMOS technology
with 1153 logic modules. The SEU behaviour of this device
is very typical for Actel devices. Biasing at 3.3V give a
higher SEU probability. Actel has a large asymmetry in the
flip-flop sensitivity between flip from logic “zero” to logic
“one” compared to the reverse. This device type has been
on the market for several years and according to Actel there
are at the moment no plans to take it out of the market. This
device type has been designed in on many spacecraft’s, but
only a few have been launched so far.
B. Actel RT54SX16
This FPGA is manufactured by Matshushita (MEC) in
antifuse metal-to-metal gate 0.6μm 3-metal CMOS
technology. This device type exists in a 32 kgate version as
well. However, the device types became obsolete before it
came out on the market because MEC decided to close
down the 0.6μm line.
The SEU behaviour of this device is very similar to
A14100A. The large asymmetry in the flip-flop sensitivity
between flip from logic “zero” to logic “one” compared to
the reverse could be observed here as well. The total dose
tolerance for this type is around 50 krad(Si) compared to
that of A14100A which only around 10-15 krad(Si). There
are large differences in total dose tolerance between
different production lots of these types.
Critical functions in space applications must be triple
module redundant to mitigate for SEU. This consumes large
portion of the devices and the cost per bit becomes quite
expensive.
1.E-04
1.E-05
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0
LET [ MeV/mg/cm2 ]
S/N#3 ; 1-0
S/N#3 0-1
S/N#4 ; 1-0
S/N#4 0-1
NASA
A14100 S 0-1
A14100 S 1-0
Figure 2. Heavy ion data on Actel RT54SX16 R-module.
The data for A14100A are shown as dashed curves.

V. SRAM FPGA TECHNOLOGY
The Xilinx Virtex FPGA is an SRAM based device that
supports a wide range of configurable gates from 50k to 1M.
It is fabricated on thin-epitaxial silicon wafers using the
commercial mask set and the Xilinx 0.25µ CMOS process
with 5 metal layers. SEU risks dominate in the use of this
technology for most applications. In particular, the
reprogrammable nature of the device presents a new
sensitivity due to the configuration bitstream. The function
of the device is determined when the bitstream is
downloaded to the device. Changing the bitstream changes
the design’s function. While this provides the benefits of
adaptability, it is also an upset risk. A device configuration
upset may result in a functional upset. User logic can also
upset in the same fashion seen in fixed logic devices. These
two upset domains are referred to as configuration upsets
and user-logic upsets. Two features of the Virtex
architecture can help overcome upset problems. The first is
that the configuration bitstream can be read back from the
part while in operation, allowing continuous monitoring for
an upset in the configuration and the part supports partial
reconfiguration, which allows for real-time SEU correction.
Secondly, Triple Module Redundancy (TMR) can be
implemented in order to filter out SEU effects.
VI. TEST METHODS FOR SRAM FPGA
A. SRAM Bitstream Readback
On the test board described above, a configuration
controller chip on the DUT-board is controlling a PROM
and configuration ports of the DUT. A program command
can be sent to the DUT, which clears its configuration
memory and starts an automatic re-configuration of the
Figure 3 Schematic drawing of DUT board with
configuration interface for the Virtex device
Page 3
DUT from the PROM During the test of the DUT the
configuration controller is continuously scrubbing the DUT
configuration memory with new configuration data from the
PROM’s. A schematic drawing of the test board is shown in
Fig 3
All data from the PROM’s to the DUT is transferred
through the parallel SelectMAP interface, which supports
the partial configuration feature making it possible to
continuously scrub the device with new configuration data
during operation.
B. Error Separation
Errors could originate from SEU in registers of the
device, SEU in the configuration data causing functional
errors in parts of the device and from errors in control
registers of the device causing global functional errors. The
analysed data errors are separated into three different
domains, SEU in registers, SEU in configuration data, and
SEU in device control registers.
SEU in the register is corrected with the new data loaded
into the DUT. The error will not last in next test cycle.
SEU in the configuration data would be permanent until
the device is scrubbed with new configuration data. The
SEU gives an error in only part of the device and could, for
example, corrupt the function of one of the shift registers in
the DUT. This means that the shift register will be out of
function until the configuration data is corrected with new
data.
The control register “POR” controls the initialisation
sequence of the device when it powers up. An SEU in this
register could change state of the whole device by initiating
a complete clearing of the configuration memory. This type
of error is detected when all shift registers go out of
function at the same time.
C. DUT Designs
Two design methods were tested for comparison, TMR
and non-TMR designs. Both designs have the same basic
functionality. The TMR version uses the Triple Module
Redundancy design techniques that Xilinx recommends for
use with the Virtex FPGA [3]. The non-TMR design is a
standard design used for Actel antifuse as well.
The non-TMR design, schematically shown in figure 4,
implements into the device 14, 144 stage, pipeline shift
register and a small self test circuit.
The TMR design, schematically shown in figure 5,
implements a functionally equivalent circuit as the non-
TMR design but with full internal triple redundancy. The
outputs of the TMR design use triple tri-state drivers to
filter data errors from the output.

Figure 4 Schematic drawing of non-TMR DUT design
D. Other Test Considerations
An SEU in configuration data causing a functional error
is corrected when new configuration data is written to the
DUT. To be able to detect all of these errors the DUT must
be continuously tested. Since the DUT is paused in our
tests, we will not see all of these errors. Therefor we have to
estimate the fraction of errors that we detect (Detection
factor).
Two different pause times (time where DUT is not
clocked between read/write of data) are used during the
tests, 223ms and 4ms. Testing the non-TMR design mostly
used the long pause time since the flow of error data was
too high.
The test system allows selecting the scrub time between
10,38ms / 22,93ms and 166ms. The longer scrubbing rates
were only used in the first test runs for calibration
purposes.
VII. SRAM TEST RESULTS
Each test was performed with a variety of atomic species
up to a fluence of 1e+6 ions/cm2, or until either one of the
shift registers was permanently disabled by the “Persistent”
error or all 14 shift registers were eliminated by the “SEFI”
error. With this error in a shift register no data came out and
the registers couldn’t be tested. The fluence is calculated
from the total fluence of the test and the mean value until
each Persistent or SEFI type error. In this way the fluence of
when the device is actually tested is achieved.
Page 4
Figure 5 Schematic drawing of TMR DUT design
A. Configuration induced Error types
Errors that are caused by SEU in the configuration are
quantified by observing the following signatures in the test
data: The results are shown in figure 6
1) Routing
An SEU in the configuration logic (routing bits and
lookup tables) may cause errors in the configured function
of the operational device. This gives errors from the shift
registers that are permanent until next time the device is
scrubbed with new configuration data.
2) Persistent
A persistent error is a permanent error that is not
corrected with new configuration data. The device needs to
be reset to correct this error. This is the result of SEU in
“week keeper” circuits used in the Virtex architecture when
logical constants are implied in the configured design such
as unused clock enable signals for registers.
3) SelfTest
SelfTest errors are of same type as the routing type, but
instead of interrupting a shift register it interrupts the
function of the SelfTest module.
4) SEFI type
Function of the whole device is interrupted in one hit
and all shift register data is lost. The device requires a reset
and complete reconfiguration for correction.
These errors are tested in a dynamic way, but due to
limitations of the test system the device is rested between
clocking of data. Since the device is continuously scrubbed
with new configuration data, there will be a significant
amount of errors of the routing and SelfTest data not seen

at read out (corrected before read out). The detection factor
correlates the results for this.
5) Non-TMR design
At a LET of 2.97 MeV/mg/cm 2 each configuration type
error was observed. Cross-sections are presented in Fig. 6.
The presented data for all configuration type errors are
correlated with an estimated “detection factor”. With a
scrub time of 10 ms and a pause time of 4 ms the detection
factor is estimated to be 0.6 and with the longer pause time
of 223 ms, it is estimated to be 0.05.
The cross section is specific for this design. To predict
cross section for a 100% utilised device you must multiply
these cross sections with the utilisation factor for this
design (about 32% for the routing errors and maybe 5% for
the SelfTest module).
Cross Section [ cm2/device ]
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0E-06
1.0E-07
0 10 20 30 40
LET [MeV/mg/cm2 ]
Routing
Persistent
SelfTest Mod.
SEFI type
Figure 6 Configuration errors for non-TMR Design. The cross
sections are per device and are specific for this design. For the
non-TMR design one SEFI type error was recorded, at a LET of
14.1 MeV/mg/cm 2 . This is likely due to the very low fluence
required for the test to finish. Arrows indicate test without any
errors.
6) TMR design
The SEFI type error was the only observable error type.
The Persistent error is not observed. The SEFI was
observed at a LET of 5.85 MeV/mg/cm2. This demonstrated
that the TMR design method effectively eliminated all non-
SEFI configuration induced errors.
The “SEFI type” error is believed to be an SEU in the
POR control register, clearing the whole device from
configuration data. All I/Os are 3-stated in this state and
this was detected at the read out data, which slowly went
from read high state to read low state after some test cycles.
Page 5
Cross Section [ cm2/device ]
1.0E-04
1.0E-05
1.0E-06
1.0E-07
1.0E-08
0 10 20 30 40
LET [MeV/mg/cm2 ]
SEFI type
Routing
Persistent
SelfTest Mod.
Figure 7 Configuration errors for TMR Design. Except for SEFI
errors only one “routing” error was recorded at a LET of 14.1
MeV/mg/cm 2 . Arrows indicate test without any upsets.
In one test run a “Routing” error was observed. The flux
was ~1333 ions/cm2/s and the device were scrubbed with
new configuration data every 10,38ms. This gives a
flux/scrub-cycle ratio of 13ions/cm2/scrub.
Xilinx has reported that the number of accumulated
configuration bit upsets to cause a functional failure in a
TMR design ranges between 2 and 30 bits. It is therefore
possible that enough errors in the configuration logic were
allowed to accumulate before the next scrub cycle to cause
the error. Therefore, the observed errors are most likely an
artefact of the flux/scrub-cycle ratio.
B. Register Error Types
These errors are tested in a static fashion. Data is
clocked into the shift registers, held for a pre-set time, and
then clocked out for comparison. The procedure is repeated
constantly during the test run. The data are analysed for
single bit errors and categorised into the following error
types:
FF(0-1) Read ‘1’ from flip-flop registers when ‘0’ is
expected.
FF(1-0) Read ‘0’ from flip-flop registers when ‘1’ is
expected.
FF A summation of all FF errors (above) read from the shift
registers.
DataSwap This was an error type that had two errors in
registers next to each other in the register chain. First a ‘0’
was read when ‘1’ was expected and in the next register a ‘1’
is read when a ‘0’ was expected. This error was isolated for
two registers in the whole chain of 144 registers and didn’t
occur again in the next test cycle.
One possible explanation for this error type is that a
routing bit error was being corrected just as test data was
being read out for comparison.

1) Non-TMR design
FF errors were observed at a LET greater than 2.97
MeV/mg/cm2 with a saturation cross-section of ~1e-6cm2.
Cross Section [ cm2/bit ]
1.0E-05
1.0E-06
1.0E-07
1.0E-08
1.0E-09
1.0E-10
0 5 10 15 20 25 30 35 40
LET [MeV/mg/cm2 ]
FF(0-1)
FF(1-0)
FF
DataSwap
Figure 8 Register errors for non-TMR Design. Arrows
indicate test without any upsets.
2) TMR design
Only one FF error was observed at a LET 14.1
MeV/mg/cm2 with an estimated cross-section of ~5e-10cm2.
No other FF errors were recorded in absence of a SEFI type
error. It is considered that this error is the result of the
flux/scrub-cycle ratio as previously mentioned.
Cross Section [ cm2/device ]
1.0E-04
1.0E-05
1.0E-06
1.0E-07
1.0E-08
0 10 20 30 40
LET [ MeV/mg/cm2 ]
TMR
non-TMR
Figure 10 SEFI errors for non-TMR and TMR design.
The non-TMR tests were performed to less fluence than the
TMR, therefor less SEFI errors have been observed for non-
TMR design. In principal the SEFI error cross section
should be the same for the two designs. With the
assumption the control registers have the same heavy ion
sensitivity as the user registers. The number of fatal failure
control bits of the device seems to be around ten. The LET
threshold of the SEFI errors would with this assumption be
around 5 MeV/mg/cm 2 .
Page 6
VIII PROTON INDUCED SEU
The main mechanism in energy loss leading to single
event phenomena is due to inelastic collisions between
incident protons and atoms in the substrate. The recoiling
nucleus will thus be the particle that causes the SEU. The
final mechanism for proton induced SEU is therefore very
similar to that envisaged for heavy ions.
In Fig 11 below are proton data from Actel A14100A and
Xilinx Virtex shown. The cross sections for proton SEU are a
factor 10 -8 lower than those observed for heavy ions. The
low threshold observed for Xilinx manifest itself in the
sensitivity for low energetic protons. For A14100A, is likely
only the flip of logic “0” to logic “1” that is observed in the
proton SEU. Circuits having a threshold higher than LET=
15 MeV/mg/cm2 are not sensitive to proton upset.
1.E-10
1.E-11
1.E-12
1.E-13
1.E-14
1.E-15
1.E-16
1.E-17
1.E-18
0 100 200 300 400
Proton Energy (MeV)
Virtex
XQVR300
A14100A
Fig 11 Proton upsets as a function of proton Energy for
Actel A14100A and Xilinx Virtex QRV300. For Actel
A14100A, no proton upsets have been observed at
energies below 150 MeV. The results for Xilinx is taken
from Ref [3]

IX SINGLE EVENT TRANSIENTS
In addition to “conventional” SEUs, charge particles can
also induce transients in combinatorial logic, in global clock
lines and in global control lines. These single event
transients (SET) have only minor effects on technologies
around 0.8-0.5 μm since the speed of these circuits are
insufficient to propagate the 100 to 200 ps wide SET pulse
any appreciable distance. However, as smaller feature size
technologies are being used in spaceborne systems, these
transients become indistinguishable from normal circuit
signals.
If a charge particle strike occurs within the combinatorial
logic block of a sequential circuit, and the logic is fast
enough to propagate the induced transient, then the SET
will eventually appear at the input of data latch where it may
be interpreted as a valid signal. Similar invalid transient data
might appear at the outputs of lookup tables and on routing
lines due to SETs generated in the programming elements.
While conventional SEU error rates are independent of
the chip clock frequency, SET increase in direct proportion
of the operating frequency. Smaller feature size results in
smaller gate delays that permit circuits to be operated at
higher clock frequencies. For typical FPGA designs, SET
induced error rates may actually exceed the SEU rate of
unhardened latches as clock speeds approach 100 MHz for
CMOS designs.
Fig.12 Critical Transient Width vs Feature Size for
unattenuated propagation. The picture is taken from Ref
[4]
In figure 12 is illustrated the critical transient pulse width
as function of technology feature size needed to propagate
without attenuation through any number of gates [x]. At
pulse widths smaller than the critical width, the inherent
inertial delay of the gate will cause the transient to be
attenuated and the pulse will after passing a few gates die
Page 7
out. At pulse widths equal or larger than the critical width,
the transient will propagate through the gate just as though
it was a normal circuit signal.
A. RT54SX-S Details
The architecture of Actel RT54SX-S devices is an
enhanced version of Actel SX-A device architecture. The
RT54SX-S devices are manufactured using a 0.25µm
technology at the Matsushita (MEC) facility. The RT54SX-S
family incorporates up to four layers of metal interconnects.
To achieve good SEU requirements each register cell (R-
Cell) in the RT54SX-S are build up with Triple Module
Redundancy (TMR) The R-cells in the SX-S device consists
of three master and three slave latches gated by opposite
edges of the clock. The feedback path of each of the three
latches is voted with the outputs of the other two latches. If
one of the three latches is struck by an ion and starts to
change state, the voting with the other two latches prevents
the change from feeding back and permanently latching.
With this solution the latches is continuously corrected
and theoretically the only possibility for a SEU in a R-
register is to have two latches hit by two ions within the
recovery time of the transient created by the ions.
B. SEU Results of RT54SX32-S
No SEU in the R-register cells have been observed
under static conditions up to LET= 64.5 MeV/cm2/mg.
Irradiation with heavy ions under 5 MHz dynamic
condition resulted in errors, which had the same signature
as if they were proper SEU. When lowering the FPGA
operating frequency by a factor of 4 to 1.25 MHz no errors
could be observed. From the static condition test it was
concluded that the R-cells do not upset. Thus, the errors
observed in 5 MHz dynamic mode are very likely due to
transient effects SET which are clocked through to the
output.
The duration and magnitude of the transients are,
however, technology and circuitry design dependent. In the
present experimental set-up it is not possible to isolate the
error data to certain areas or functions of the device.

CrossSection [/bit/cm2]
1.00E-08
1.00E-09
1.00E-10
1.00E-11
RT54SX32s
1.00E-12
0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0
LET [ MeV/mg/cm2 ]
Fig 13 Single Event Transient cross section as a
function of LET value for RT54SX32S. Errors have only
been detected in 5 MHz dynamic test mode. The data
points with arrows indicate fluence for test run without
errors. The error bars are the standard deviation
indicating counting statistics for each test run. No
conventional SEU can be detected for this device type.
X. CONCLUSION
Test results presented in this paper are all on COTS type
of FPGAs. The use of COTS in radiation environment
require, however, that testing to the needed reliability
requirements are performed. A vast majority of complex
IC’s will not pass the minimum requirement of being latchup
free in a charge particle environment. Once the single
event upset problems have been characterised there are
techniques to mitigate the SEU problems. Such knowledge
helps selecting between hardened technologies and speed
and area trade-offs in a softer technology. With decreasing
feature size, the single event transients will become more
important. For frequencies above 100 MHz, the probabilities
are in the same order as for conventional upsets. So far no
experimental data have been published which show the
transient probabilities at proton energies for complex CMOS
technologies.
S/N#01 Static
S/N#01 5 MHz
S/N#02 Static Low
S/N#01 1 Mhz
Page 8
XI REFERENCES
[1] http://klabs.org/fpgas.htm, https://escies.org/
[2 Earl Fuller, Michael Caffrey, Anthony Salazar, Carl
Carmichael, Joe Fabula, Radiation Characterization,
and SEU Mitigation, of the Virtex FPGA for Space
based Reconfigurable Computing, NSREC 2000,
October 2000.
[3] C. Carmichael, E. Fuller, J. Fabula, Fernanda De Lima,
proton Testing of SEU Mitigation Methods for the
Virtex FPGA. Xilinx Report
[4] D.G.Mavis and P.H.Eaton, Temporally Redundant
Latch for Preventing Single Event Disruptions in
Sequential IC, Technical Report P8111.29, Mission
Reseach Corporation, 1998.

Electronics Commissioning Experience at HERA-B
Bernhard Schwingenheuer
Max-Planck-Institut fur Kernphysik, 69117 Heidelberg, Germany
Bernhard.Schwingenheuer@mpi-hd.mpg.de
Abstract
The readout of Hera-B has been uni ed to a large extend.
Only the HELIX and ASD8 chips with corresponding
readout electronics were used and the data acquisition
is constructed entirely with Sharc DSPs. This approach
minimized the work load and was successful. The feedback
of the ASD8 digital outputs to the analog inputs caused
oscillations and the e orts to solve this problem still continued
in the commissioning phase. The electronics of the
sophisticated hardwaretriggerwas commissioned successfully
while some problems remain with the self-made 900
Mbit optical data transmission.
I Introduction and Overview
Hera-B is a xed-target experiment at the HERA storage
ring at DESY, Hamburg [1]. Protons interact with thin
target wires of di erent materials. The wires and hence the
rate of interactions are steerable. A silicon vertex detector
(VDS) is located downstream of the target. A dipole magnet
with tracking chambers inside and after the magnetic
eld follow. Because of the anticipated particle ux and
radiation damage the tracking chamber are divided into
an inner part with high track density (ITR, micro strip gas
chambers with gas electron multiplier foils) and an outer
part (OTR, honeycomb driftchambers). Kaon identi cation
is performed with a ring imaging Cherenkov detector
(RICH). An electromagnetic calorimeter (ECAL) and
a muon detector (MUON) allow for lepton identi cation.
A special set of three layers of tracking chambers (HighPt)
are foreseen inside the magnetic eld. Their signals allow
fast triggering on tracks with large transverse momentum.
Table 1 gives an overview over the applied detector technologies,
readout chips, front-end technologies and whether
the subdetector is used by the hardware trigger (FLT).
With the exception of the ECAL only two readout chips
were applied (HELIX and ASD8) and consequently only
two versions of front-end electronics had to be developed.
1 The TDCs for the ASD8 digitization are on the detector
while the data of the HELIX chips are digitized in the
trailer. The latter is always accessible in a low radiation
1 The TDC chip could be operated in a binary readout mode for
MUON, RICH and HighPt.
area and houses in addition all components of the data acquisition
(sect. VII) and of the hardware trigger (sect. VI).
Hera-B was largely assembled by theendof1999and
commissioning took place in 2000. The goal of measuring
CP violation in the neutral B meson system was not
reached. The shortcuts due to problems with the electronics
and some of the experiences gained during the construction
are described in this article. For a detailed description
of the electronics components itself the reader is referred
to the references.
From September 2000 to July 2001 the accelerator was
shut down for a luminosity upgrade for the collider experiments
H1 and ZEUS. Hera-B has used this time to solve
most of the identi ed problems.
II Vertex Detector and Inner Tracker
The Vertex Detector (VDS) and the Inner Tracker (ITR)
both use the HELIX readout chip [2]. Hence most of the
electronics like the digital control signal generation (including
their optical transmission to the detector), the analog
optical data transmission to the trailer and the digitization
of the data is common for both systems. The low voltage
power supplies and the technique of programming the HE-
LIX chips di ered.
The VDS was fully commissioned by 2000 [3]. For the
electronics an important feature of the HELIX was used
intensively for monitoring: the analog data is stored internally
in a pipeline and upon a trigger the data together
with the pipeline location is available at the output. By
comparing this location from all chips the synchronization
of the VDS can be guaranteed.
In 1998 a rst version of the optical transmission for the
digital control signals was installed using commercial components.
The receivers were located in a low radiation area
under the magnet. Particles hitting the receiver's pin diode
generated spurious digital signals because of low switching
threshold. Consequently within minutes of operation parts
of the VDS became asynchronous. The self-made receiver
for the analog optical signals in conjunction with a comparator
did not show this problem and is used instead.
During the 2000 operation several HELIX chips ceased
functioning correctly. The fraction increased with time
from about 1% at the beginning to 4% at the end. Most of

Table 1: Characterization of the readout electronics for all subdetectors.
subdetector technology readout chip chn digitization data transm. to trailer used by FLT
VDS silicon microstrip HELIX 150k FADC analog optical no
ITR MSGC with GEM HELIX 130k FADC analog optical yes
OTR honeycomb drift ASD8 120k TDC LVDS digital yes
RICH Cherenkov +PMT ASD8 28k binary(TDC) LVDS digital no
MUON tube,pad,pixel ASD8 30k binary(TDC) LVDS digital yes
HighPt pad,pixel ASD8 25k binary(TDC) LVDS digital yes
ECAL shashlik PMT 8k ADC analog coaxial yes
these chips were however not broken. Several procedures
were tried to revive them(changing the phase between signals,
turning them o /on) with varying success. Because
of the redundancy of layers in the VDS these losses did
not seriously a ect the tracking e ciency. A clear understanding
of the problem is not yet reached but recently
some problems in the download software were found which
explain some observations.
The Inner Tracker [4] was delayed by two years because
of radiation hardness problems of the MSGC technology.
The 2000 run was thus its rst commissioning period. The
initial grounding scheme asked for one central point per
chamber as a "reference ground" to avoid ground loops.
The backside of the MSGC, the PCBs with the HELIX
chips and other boards had a ground connection to this
point. Further optimization studies showed that a massive
direct ground connection between the MSGC and the HE-
LIX PCB and using a large surface ground bar with short
connections is much more favorable. Especially when the
prompt digital trigger outputs of the HELIX (open collector)
are activated the new grounding reduces crosstalk
of the digital outputs to the analog inputs substantially.
Modi cations on the HELIX and a reduction of the collector
pull-up voltage reduces the crosstalk further.
The low voltage power supplies have a "power factor correction"
(PFC) circuit to ensure that the phase between
current and voltage is not distorted by the device under
load. While these power supplies have been operated in
the lab routinely for long time the PFC broke repeatedly
during the 2000 operation in the experiment. It is known
from other HERA experiments that the 240 Volt power
lines have spikes in the experimental halls close to the accelerator.
It was therefore advised to add lters and ferrite
rings to reduce spikes in the power lines. Whether this
cures the PFC failures is not yet known but seems likely.
III The ASD8 Commissioning
The ASD8 [5] is used by the gaseous detectors (Outer
Tracker, Muon detector and HighPt detector) and by the
RICH detector (for PMT signal readout). It consists
for each of 8 channels of a di erential input ampli er,
a two-stage shaper, a discriminator with externally pro-
grammable threshold and an open collector di erential output
stage. The shaping time is below 10 nsec.
Figure 1 shows the OTR on-detector electronic components
as an example [6]. The anode wire is at high voltage
and connected via a coupling capacitor to one ASD8 input.
The second ASD8 di erential input is connected to
the cathode, i.e. to the ground of the chamber. The connection
between the analog ground of the ASD8 board and
the chamber ground was found to be very important for
noise reduction, especially the Copper-Beryllium springs
which hold the board at the chamber make good contact.
Another problematic item is the crosstalk (feedback) between
the digital output of the ASD8 and its analog input.
The size of this e ect depends on the exact con guration
and the number of the cables and hence can not be easily
estimated in the lab. Operation of the ASD8 at a threshold
with large hit e ciency is however impossible without
special e orts.
The subdetectors have followed di erent strategies to reduce
the crosstalk. All groups use shielding over the rst
meters of the twisted-pair cables from the ASD8 to the
TDC. In most con gurations a good connection of the cable
shield to the digital ground of the ASD8 is su cient
while for some HighPt chambers this method is not adequate.
Instead the connection is made with a 50 resistor.
A possible explanation of this behavior is that the phase
of the feedback to the analog ASD8 input is changed by
the resistor and thus a constructive interference and oscillations
are avoided. In case of the Muon detector [7] large
e orts went into the routing of the cables and spacers were
added to avoid crosstalk from one cable to the next.
All chambers could be operated in 2000 with hit e ciencies
well above 90%but for the Muon pad chambers the
above mentioned e orts were not su cient. Each Muon
pad is connected to a preampli er mounted directly on the
chamber. The signal is then driven by a di erential ECL
line driver via a 3 m twisted-pair cable to the inputs of
the ASD8. In the original design the backside of the pad is
oating. Connecting this plane to ground reduces the noise
substantially but the signal size is deteriorated as well such
that the hit e ciencies are limited to around 90%. Since
the pad chambers were too noisy (oscillating) without this
modi cation almost all modules were modi ed in the con-

CHAMBER
HV BOARD
GAS BOX
HV
00 11
00 11
00 11
01
01
01
01
01
01
ASD BOARD
ASD
LV SUPPLY
TEST PULSE
DISTRIBUTION BOARD
TDC
Figure 1: Schematic of the on-detector electronics of the OTR.
struction phase. The unmodi ed ones as well as some others
with poor grounding (about 20% of the channels) were
noisy in 2000.
Recently test beam measurements were performed to
nd a reliable solution. The most promising one is to exchange
the preamp and some modules have beenmodi ed
in Hera-B .
In the 2000 commissioning an additional source of feedback
to the analog input of the ASD8 was observed. The
TDC board has digital outputs for the connection to the
hardware trigger (FLT in gure 1) and when those cables
were plugged ASD8 oscillations were observed. In
this case the crosstalk could occur via spikes on the TDC
ground. 2 Ferrite rings were added on the cables and the
driver strength of the TDC signals was reduced. Test measurements
indicate su cient suppression of the feedback
after these modi cations.
IV OTR High Voltage Channels Loss
During the 2000 run about 0.5% of the OTR anode wires
developed a "short" and had to be disconnected. This
corresponds to arateofone per 7 hours. Because of the
grouping of HV channels about 8
The HERA luminosity shutdown was used to disassemble
all chambers and the cause for the shorts were identied:
remnants from the soldering of lter capacitors on the
backside of the HV board became conductive with time.
This problem was not observed in the pre-series production
since the soldering technique applied at that time was
di erent. In addition the time constant of this problem is
50000 hours and it would have been di cult to discover
the failure with the pre-series boards in any case. By now
all 14000 a ected capacitors have been replaced and the
losses are an order of magnitude smaller.
2 The pull-up resistors for the open collector outputs of the ASD8
are located on the TDC board with a pull-up voltage of 1.25 Volt.
The 2 mA current per channel ows through one of the wires of the
twisted-pair cable to the ASD8 and back via the ground connection
of the power supplies to the TDC. Obviously any disturbance on the
ground level and/or pull-up voltage will couple to the ASD8. A LVDS
driver on the ASD8 board would have been a more robust solution
but impossible to implement at the time the problem was discovered.
DSP
FLT
V ECAL Noise
The signals from the electromagnetic calorimeter are
transmitted with (8000) coaxial cables to the ADC boards
in the trailer. The calorimeter is oating with respect to its
frame in the experimental area and the ground is de ned
via the connections of the cable shielding. Each signal is
terminated at both ends with 50 to avoid re ections.
During last year's running an excess of noise was observed
corresponding to a voltage of a few mV at the input
of the ADCs. This noise limited the resolution of the ECAL
but had litte impact on the pretrigger performance. The
origin of the noise was traced back to di erent ground levels
of the readout crates in the trailer and hence di erent
ground levels along a coaxial cable. Via the 50 termination
on the PMT side any ground bounce will couple
to the signal line and hence create noise. All terminators
were exchanged on the PMT side by 10 k resistors and
rst measurements indicate a su cient suppression of the
noise.
VI The Hardware Trigger
The main thrust of Hera-B was to nd CP violation
in the decay channel B o ! J= K S. Since the anticipated
rate of 5 proton interactions every 96 nsec is large, a sophisticated
hardware trigger (First Level Trigger) [8, 9]was
designed to reduce the event rate to 50 kHz, a level which
can be handled by the data acquisition and a PC farm for
further processing.
The basic idea is to detect both electrons or both muons
from the J= decay, calculate their momenta and the invariant
mass. The search starts with a pre-trigger for electrons
(looking for ECAL towers above threshold) and for
muons (calculating coincidences in the pad chambers of the
last two superlayers).
The "work horse" of the trigger is the track nding unit
(TFU). There are 72 TFUs in the entire system, typically
10 per superlayer of the tracking chambers. The TFUs of
one layer receive the hit information of the corresponding
chambers for every bunch crossing. In addition they receive
messages from the TFUs of the previous layer and
transmit messages to the TFU of the next layer. A message
contains the current parameters of track candidates
and their uncertainties. From the incoming message the
TFU calculates a region-of-interest where the track should
have passed through the superlayer and use the information
from the chamber to search for con rmation hits in
three stereo views. 3 If found the track parameters will be
updated and a new message will be sent to the next TFU
layers. If no con rmation hit is found (in one or more
stereo views) no output message will be generated.
3 There are two layers of tracking chambers per stereo view and
the OR is used in the trigger.

The search direction is opposite to the particle direction
and starts with the pre-triggers at the downstream end of
the detector. It ends at the chamber closest to the magnet.
At thispoint the track parameters are well determined and
the momentum can be calculated (with a track parameter
unit) assuming that the track comes from the target. For
two tracks the invariant mass can be determined (with the
trigger decision unit). The trigger hence consists only of
3 di erent types of boards and the total processing time
including the pre-triggers is less than 10 sec. Its data input
is 1 Tbit/sec from the tracking chambers and at design
rate about 500 million track candidates per second are followed
through the hardware. The rate reduction should be
at least 200. Hence the 10 MHz bunch crossing frequency
is reduced to a trigger rate of 50 kHz.
The TFU is the most complicated board of Hera-B
(23000 solder pads). The hardware and rmware is designed
such thatsoftware tests allow rigorous debugging of
the entire board and the detailed identi cation of problems
like bad solder points. These boards were tested for one
week before they arrived at DESY and showed no problems.
The large amount of data transmitted from the tracking
chambers to the trigger (1 Tbit/sec) is realized with about
1500 self-made 900 Mbit optical links [10]. At the time
of the design there was no commercially available solution
at this speed available. Our design uses the Autobahn
spanceiver from Motorola to serialize a 20 MHz 32-bit wide
input. The serial (di erential PECL) Autobahn output is
transmitted with a VCSEL from the experiment to the
trailer. The optical receiver converts the light back into
a serial (di erential PECL) signal and a second Autobahn
recovers the parallel data.
The requirement of the hardware trigger is that close
to 100% of these data links have towork perfectly since a
single missing hit causes ine ciencies of the trigger. Unfortunately
about 5% of the links were periodically unstable,
i.e. had a large bit error rate. Ine ciencies were nevertheless
avoided since the TFU hardware could arti cially set
all hits to \1" for the identi ed links. The most relevant
data link problems were due to instabilities of the VC-
SEL (changes of the light output and poor eye pattern),
mechanical problems with the ST-connectors and the fact
that the duty cycle of the serial bit stream varies 4 which
reduces the stability of the transmission line.
Recently remotely programmable DACs have been added
to adjust the amplitude and o set of the VCSELs. Thus
some of the problems should be solved. However the data
transmission remains a worry for the next data taking.
The muon pre-trigger [11] nds track seeds by calculating
coincidences of the pad (and pixel) chambers signals of the
last two superlayers. Since several pad modules were un-
4 The duty cycle is almost identical to the occupancy since the
Autobahn simply serializes the input data stream.
stable and individual channels became noisy for some time
during the operation, those channels contributed largely to
the coincidence rate and had to be masked. The identi -
cation was relatively easy because of a build-in feature of
the hardware: a small fraction of the coincidence messages
were not only sent to the hardware trigger but also written
to a VME accessible register. The online software was
hence able to locate those channels quickly and mask them
online without stopping the data acquisition.
The online masking is an involved task since the updated
mask has to be stored in a database and the information
of the new version has to be distributed to all PCs of the
Second Level Trigger farm. In total the online software
consists of about 20 di erent processes running on 10 different
computers. About 10 man years have been invested
in the software (including o ine monitoring) which almost
equals the e ort for building the hardware (15 man years).
For the ECAL pre-trigger [12] online masking was also
needed. Here the origin was a di erent one: the quality
of the commercially produced boards was very poor which
caused long delays and for the installed boards bit errors
in the cluster energy. Hence local hot towers were observed
and had to be masked.
VII The Data Acquisition
While the hardware trigger is processing hits of a given
bunch crossing the detector front-end keeps the full data in
a pipeline. When a trigger is issued the digitized event is
stored in the Second Level Bu ers (SLB) with a depth of
270 events. The maximum event input rate is 50 kHz. The
Second Level Trigger (a farm of 240 PCs) then accesses the
event data via the Switch fromtheSLBs and performs a
partial event reconstruction based on the tracks found by
the hardware trigger [13]. Another process (called Event
Controller) keeps track of the free bu ers on the SLB and
the idle PCs.
The Event Controller, the SLBs and the Switch are realized
with Sharc DSPs from Analog Devices. Each Sharc
has six 40 MB/sec input ports, a 32-bit bus for Sharc-to-
Sharc connections, a 40 MHz CPU and 4 Mbit dualported
memory. For Hera-B a custom made VME board with
6 DSPs was developed of which about 200 are in use. The
board worked reliably.
The challenge is to guarantee that no message from the
Second Level Trigger to the SLBs and back is lost, i.e. to
back pressure messages and not to loose any interrupt on
a Sharc. For speed consideration Assembler was used for
the Switch programming while the language C was used
elsewhere [14].
The advantage of the uni ed hardware approach for the
data acquisition is the easy connectivity in the entire experiment
and the minimal amount of man power needed
for development (6manyears) and maintenance.

The maximum bandwidth of the Switch is1GB/secand
the limit on message rate is 2.6 MHz. This is according the
speci cations and the same is true for the SLBs and the
Event Controller.
VIII Summary
Hera-B was largely completed at the end of 1999. The
electronic commissioning in 2000 revealed some surprises
(like the feedback from the TDC-FLT connection to the
ASD8). Prior to the installation and during the commissioning
oscillation problems of the ASD8 readout chip
caused problems and delays. Perfect grounding could reduce
the noise in most cases to an acceptable level. For
the Muon pad system this could only be accomplished by
grounding the backside of the pads which let a smaller hit
e ciency. During the HERA shutdown most of these problems
could be xed or reduced and for the next data taking
period a large improvement is expected.
The electronic of the hardware trigger was working reliably,
especially the TFUs. The only exception is the optical
data transmission from the tracking chambers to the
trigger which remains problematic for future running.
The data acquisition and the front-end electronics
(FADC boards for the HELIX digitization and the TDC
boards for ASD8 digitization) were largely uni ed in the
experiment andworked successfully.
The example of the trigger shows that the hardware design
has to support debugging and online monitoring. High
quality software tools are needed for commissioning and
the amount ofmanyears equals the time used to build the
hardware.
Let me conclude with two personal recommendations.
The experience shows that many small design mistakes
can have a large impact on the quality of the experiment.
To nd them regular reviews by experts from other experiments
would help. Although this is a big e ort the
knowledge about problems and solutions would spread fast
within the HEP community. One example is the usage of
open collector outputs. They should be avoided and be
replaced by LVDS signals.
References
[1] E.Hartouni et al., Hera-B Design Report, DESY-
PRC 95/01, (1995).
[2] W. Fallot-Burghardt et al., HELIX128S-2 Users
Manual, HD-ASIC-33-0697, http://wwwasic.kip.uniheidelberg.de/
~ feuersta/projects/Helix/index.html.
[3] C.Bauer et al., Status of the Hera-B Vertex Detector,
Nucl. Instr. Meth. A447 (2000) 61.
[4] W.Gradl, Nucl. Instr. Meth. A461 (2001) 80-81�
T.Hott, Nucl. Instr. Meth. A408 (1998) 258-265.
[5] M.Newcommer et al., IEEE Trans. Nucl. Sci. NS-40
(1990) 690.
[6] K.Berkhan et al., Large System Experience with the
ASD8 Chip in the Hera-B Experiment, Proceedings
of the 5th Workshop on Electronics for LHC, Snwomass
1999.
[7] V.Eiges et al., The Muon Detector at the Hera-B
Experiment, Nucl. Instr. Meth. A461 (2001) 104-106.
[8] T.Fuljahn et al., Concept of the First Level Trigger
for Hera-B , IEEE Trans. Nucl. Sci. NS-45 (1998)
1782-1786.
[9] M.Bruinsma, D.Ressing at al., these proceedings.
[10] J.Gla et al., Terabit per Second Data Transfer for the
Hera-B First Level Trigger, Proceedings of IEEEE
Conference on Realtime Systems, pp 38/42, Valencia,
Spain, June 2001.
[11] M.Bocker et al., The Muon Pretrigger System of the
Hera-B Experiment, IEEE Trans. Nucl. Sci. NS-48
(2001) TNS-00118-2000.
[12] C.Baldanza et al., The Hera-B Electron Pre-Trigger
System, Nucl. Instr. Meth. A409 (1998) 643.
[13] J.M.Hernandez et al., Hera-B Data Acquisition
System, Proceedings of IEEEE NSS-MIC conference,
Lyon, France, November 2000.
[14] Hera-B Collaboration, Digital Signal Processor
Software for the Hera-B Second Level Trigger,
Proceedings of the Conference on Computing
in High Energy Physics, Chicago, August 1998,
http://www.hep.net/chep98/PDF/109.pdf.

Design of ladder EndCap electronics for the ALICE ITS SSD
R. Kluit, P. Timmer, J. D. Schipper, V. Gromov
NIKHEF, Kruislaan 409, 1098SJ Amsterdam, The Netherlands
r.kluit@nikhef.nl
A.P. de Haas
NIKHEF, Princetonplein 5 (BBL), 3584 CC, Utrecht, The Netherlands
A.P.dehaas@phys.uu.nl
Abstract
The design of the control electronics of the front-end of the
ALICE SSD is described. This front-end will be built with the
HAL25 (LEPSI) chip. The controls are placed in the ladder
EndCap. The main EndCap functions are; power regulation
and latch-up protection for the front-end, controlling the local
JTAG bus, distribution of incoming control signals for the
front-end and buffering of the outgoing analogue detector
data. The system uses AC coupled signal transfer for doublesided
detector readout electronics.
Due to radiation-, power-, and space requirements, two
ASIC’s are under development, one for analogue buffering
and one with all other functions combined.
I. INTRODUCTION
For the control- and readout functions for the ALICE Silicon
Strip Detector (SSD) of the Inner Tracker System
(ITS)[5], additional electronics is needed between the Data
acquisition and the front-end modules. The SSD consists of 2
layers of ladders, the inner with 34 and the outer with 38 ladders.
The inner ladders contain 23 modules and the outer 26.
The detector modules will be connected to the DAQ- & Control
system via EndCap units mounted at the end of each side
of the ladder via Kapton cables (Figure 1). So one EndCap
controls ½ a ladder and we need 144 EndCap’s in total. The
available space is ~ 70x70x45 mm for one unit.
The limited available space requires a dense design, which
immediately adds the requirement for low power. In addition,
the volume of the cabling should be kept as low as possible.
Therefore serializing and multiplexing of data and the use of
low-mass cables is necessary. The latter requires regeneration
of signals in order to guarantee a proper quality at the frontend.
The SSD is based on Double Sided Detectors with 768
strips on each side. The detectors will be read out by the
HAL25 (Hardened ALice128 in .25µCMOS) front-end chip
developed by LEPSI/Ires Strasbourg. This chip contains 128
analogue channels with preamp and shaper. An analogue multiplexer
provides a serial readout. All bias voltages and cur-
(For the ALICE collaboration)
rents are programmable via internal DAC’s and the chip has
binary controls for readout, test and status check functions.
These functions can be addressed via a serial bus that uses the
JTAG protocol.
Figure 1 Two modules with cable on a ladder.
Because double-sided detectors are used, the readout electronics
on both sides operate at a different potential (detector
bias max. 100V). To avoid ADC- and control modules to operate
at these bias potentials, all signals will be AC coupled to
the corresponding voltage level. In addition, the analogue
readout data will be AC coupled to a multiplexer/buffer,
which is able to drive the differential signal to ADC modules
(over 25m @ 10MHz). The front-end chips of the detector
modules are readout successively; the P- and N side of one
detector module occupy one ADC channel.
The required low voltage power for the front-end chips
(2.5V) of the P- and N-side is regulated inside the EndCap.
This circuit not only provides the latch-up protection for the
front-end but also for the control electronics and buffers in the
EndCap itself.
Since the front-end electronics is controlled via the JTAG
bus, the bus is also used to control and monitor the EndCap
functions. Errors like latch-up can be detected and appropriate
action can now be taken. Defect front-end chips can be disabled
and can be put in “by-pass” mode. This information is
available for the DAQ system. During the assembly and test
phase of the EndCap, the JTAG bus will be used to test interconnections
inside the module during the production.

The EndCap will communicate with the Front-End Read
Out Module (FEROM) placed at a 25m distance from the
detector. LVDS levels are used to reduce interference between
the signals and the environment. Inside the EndCap, only the
JTAG signals will be carried out with single ended CMOS
levels (2.5V).
A. Radiation Environment
In the initial phase of the design, no clear numbers were
available for the expected radiation levels inside the SSD area
of the ITS. The Front-end would be designed in 1.2µm CMOS
and the EndCap would consist of commercial components.
Radiation studies showed that Single Event Latch-up
(SEL) would occur once every 5 minutes in these SSD frontend
chips [1]. For this reason it was decided that a latch-up
protection circuit must be included in the power supply. The
supply circuit itself must also be insensitive for SEL. Due to
the uncertainty of the expected dose levels and the expected
SEL frequency at that time, the step was made to switch to
0.25µ CMOS with the use of radiation tolerant design techniques
to improve the susceptibility for latch-up and total dose
irradiation damage. Now all SSD electronics inside the detector
volume is designed using a 0.25µ CMOS process.
Radiation calculations [2] predict max 100Gy (10krad) total
dose and 4*10 11 neutrons/cm 2 1Mev equivalent over 10
years. With the use of a 0.25µm CMOS process, the design
can be made with an acceptable susceptibility for radiation.
II. FUNCTIONALITY
The overall functionality is that the EndCap is the interface
for and distributor of the control and data signals between
the detector modules and the Data acquisition 25 m
further on. We can classify four main functions:
• Power control and protection
• Signal buffering and coupling
• Readout Control
• JTAG detector control and monitoring
A. Power Control
By nature, the front-end chips need burnout protection for
SEL. This means that if the supply current reaches a specified
level, the power of the corresponding hybrid must be switched
off. Of course, the other electronics in the EndCap needs the
same protection. For that reason, the ASIC’s inside the End-
Cap will receive their power from an identical circuit as the
hybrids. The supply itself must be insensitive for SEL. The
output voltage is programmable and the supply can be
switched on/off via the JTAG bus. A local voltage reference
defines the proper value for the output voltage. The status as
well as the output voltage can be monitored via the control
bus. If a latch-up or other error occurs, an OR-ed error signal
of all supplies in the EndCap will notify the DCS immediately.
The DCS can readout the status and can find out which
supply (hybrid of EndCap control) is switched off. The power
supplies provide a power on reset for the front-end chips as
well as for the local controllers and coupler circuits.
The EndCap has separated power for P-side, N-side, and
Interface electronics at ground potential.
B. Buffering and coupling
All signals will cross the detector bias potentials once
(Figure 4). This means that after the signals are at the right
bias potential, the local bus in the EndCap and the drivers
work at this potential. All connections to the outside of the
detector volume are at ground potential. Since all signals
cover a distance of ~25m, they have to be regenerated before
being send to the front-end chips. After these receivers, the
signals are coupled (AC) to the corresponding bias potential.
In case of a SEL on a hybrid that must be reset, the outputs
of the signal drivers to the hybrids must go in high impedance
state so they are not able to conduct any current to the frontend.
The output signals of the EndCap are 1 error signal and 14
analogue outputs. The analogue output multiplexer (Figure 3)
makes it possible to readout a P- and N-side hybrid succes-
sively. This results in one
analogue signal per module.
In order to create a
signal with one polarity,
one of the two signals is
inverted (Figure 2).
C. Readout control
Figure 2 Simplified Analogue Output
The serial readout of the front-end chips is based on token
passing. Once the token has entered the chip, the 128 channels
will put its sampled voltage on the output at each 10MHz
clock cycle. The front-end chip needs some additional clock
cycles before and after the readout for token handling.
clock
token
P- Hybrid with 6 FE chips N- Hybrid with 6 FE chips
token P delayed token N
controller
error
amplitude
return token P
return token N
analogue data
768 P-channels
from 6 P-side
FE chips
Det. Module
EndCap
Figure 3 Token Readout principle
768 N-channels
from 6 N-side
FE chips
mux driver
need to be
inverted
to ADC
The readout is organised in a way that clock and token are
being send to the Detector, and all modules are read out in
parallel. One detector module consists of one P- and one Nside
detector hybrid with 6 front-end chips (HAL25). One
module connects to one ADC input, so the two signals are
multiplexed to one line at ground potential (Figure 3). This
means that halfway the readout a multiplexer has to switch,
and that the two hybrids receive their tokens successively.
The switching and token handling will be done in the End-
Cap, via a programmable token delay. It is programmable
because a broken front-end chip requires a decrease of the
number of clock cycles for the readout. A “bypass” capability
time

will maintain the token passing for the readout. Once the last
chip in the chain is read out, the token is passed to the controller
again. It checks if it arrived at the correct time. If not, an
error signal will be generated, indicating a problem in the
readout sequence.
In case of a ‘Fast Clear” during readout, all delays will be
reset and the event can be cleared from all buffers. Within a
few clock cycles, the system is ready for a new readout cycle.
D. JTAG control and monitoring
The control of the front-end chip goes via the JTAG bus.
Therefore, it is obvious that it should also be used to control
and monitor the EndCap. An important function in the End-
Cap is that the power will switch off in case of a SEL in a
hybrid. The controller looks after an uninterrupted JTAG
chain. The controller restores the original chain after the hybrid
power is switched on again.
The EndCap JTAG logic has registers for the power supply
voltage DAC’s, readout control, the ADC to monitor temperature
and detector bias current, and for Boundary Scan
interconnection tests.
III. ENDCAP IMPLEMENTATION
Since the Detector Control and Data Acquisition electronics
are at ground potential, the interface connections work on
the same level. Therefore, the signals should cross the bias
levels inside the EndCap before they are connected to the
corresponding detector side.
FEROM
control
analogue
data
Error &
JTAG
Interface Card (1x) Supply Card (7x)
Interface
buffers
& control
(GND)
��������Ã
14x
Ccouple
P-side
buffer
&
control
��������Ã
N-side
buffer
&
control
��������Ã
Figure 4 EndCap architecture
To minimise space and power, AC coupling has been chosen
to cross the bias potentials for differential and single
ended digital signals. The analogue output that is clocked out
at 10MHz is also carried out with differential AC coupling.
This concept has been proven in the HERMES Lambdawheels
(HERA, DESY).
As shown in Figure 4, the EndCap is built out of 8 PCB’s,
1 InterfaceCard, and 7 SupplyCard’s. These PCB’s will be
placed on a back plane using miniature connectors. Kapton
cables (max 70cm) connect each SupplyCard to 4 hybrids on
the ladders. The FEROM is connected to a patch panel using
“standard” cables and from here to the InterfaceCard with a
Kapton cable.
bus
bus
������Ã
P-side
supply
&
buffers
(14x)
��������Ã
N-side
supply
&
buffers
(14x)
��������Ã
to 28
hybrids
All functions of the EndCap electronics are being integrated
into two ASIC’s; the control chip “ALice Control And
POwer NExus” named ALCAPONE, and the analogue buffer
“ALice Analogue BUFfer” named ALABUF. The
ALCAPONE chip integrates the control- and power functions
plus the LVDS and CMOS buffers that are used for the AC
coupling of the digital signals (Figure 6). The multiplexer and
analogue buffers that send the serial data to the ADC are
placed in the second chip. The InterfaceCard houses 3
ALCAPONE chips (Figure 4), one at ground potential for the
interface and two at the detector bias levels after the AC coupling.
By using the same IC process for the ASIC’s as the
front-end chip, the signal levels are fully compatible.
A. The control chip, ALCAPONE
This ASIC (Figure 5) has the following main features:
• LVDS & CMOS (AC) buffering
• JTAG control of readout, monitor and power
functions
• Power supply and reference.
Temp
Det. Current
Error
out
A
D
C
CMOS receivers & drivers
LVDS receivers & drivers
Reference &
Shunt-
Regulator
JTAG logic + control
registers
Control logic
D
A
C
Vref Supply power
Power
supply
Figure 5 Block diagram of the ALCAPONE ASIC
Token check
Sel P/N readout
Error in
For the receivers “standard” cells are used. The drivers
have an additional tri-state output capability. The positive
feedback (Figure 6) of the receiver output creates a latch function
after the AC coupling. An additional reset circuit for the
latch ensures that the correct signal polarity after power on
can be determined.
Single Ended
Ccouple
in
15pF
pos. feedback
50k
buffer
out
Capacitors not integrated in the ASIC’s
Differential
in
Ccouple
15pF
pos. feedback
50k
Figure 6 Digital AC coupling with receivers
The design of the JTAG interface is according to the IEEE
standard. Additional is a parity check for all bits in the registers
to detect a Single Event Upset. Control- and status registers
exist to check for power- and readout errors. Errors can
be masked in case of real defects.
The chip is designed in such a way that it can be used as
EndCap interface, AC coupler, and hybrid driver. Hence, the
ALCAPONE chips exist with 3 different functions in the
EndCap on 2 different types of PCB’s.
50k
out

B. Power supply
The power supply has two main parts, a regulator with
voltage reference, and the supply
circuit. Since the incoming power
voltage is about 3V, it needs to be
regulated down to 2.5V. The Bandgap-
and the supply circuit voltage
may not exceed this value. This is
realised with a shunt regulator in
parallel with the Bandgap reference.
Vin 2.7-5V
Reference
Vref
1.25V
Regulator shunt
500
Vdd
2.5V
supply
circuit
Figure 7 Shunt regulator diagram
Now that the primary power voltage is generated, the supply
circuit (Figure 8) can be turned on. It uses a start-up circuit
that includes a timer that switches off the current limit
during the first 250µs (charge up of load capacitance). It also
generates a power-on reset signal to clear the error latch.
Vref
On/Off
OK
Control
start-up
circuit with
timer
Vdd
GND
error
amplifier
overcurrent
circuit with
timer
External Power
2.7-5V
external
transistor &
R-network
PO reset
Figure 8 Block diagram of the power supply
Power Out
2.5V
An external sense resistor (75mΩ for 320mA) defines the
current limit. In case of over current, the over current timer
will delay the signal for 25µs before the output is switched
off. Other external components (7 x Res., 2 x Trans.) are used
for current- and voltage feedback and power regulation. The
transistors are necessary because the externally delivered
voltage (>2.7 V) is higher than the maximum allowed voltage
for the used IC process (2.5V). The minimum dropout voltage
is 200mV and the maximum output current with the used
components is 2A. The current used by the circuit itself is
600µA.
Figure 9 Layout of the supply circuit (280 x 70 µm)
C. The analogue buffer chip, ALABUF
The analogue buffer must be able to drive the signal over a
25m distance with 10-bit accuracy in the required range. The
range of the front-end chip is 0-13 MIP, but the highest accuracy
is required below 5 MIP detector signal. The required
linearity below 5 MIP must be better then 1%. Settling time at
the output should be max. 20ns. Additional RMS noise <
1mV.
Because a SupplyCard contains the electronics for two detector
modules, the ALABUF chip (Figure 10) is equipped
with two buffers with analogue multiplexers.
The analogue multiplexer
(Figure 11) connects the hybrid outputs
of one module to the analogue
buffer. Between two readout cycles,
the outputs are connected to a reference
voltage to avoid any voltage
drift during this quiet state.
data from
P-hybrid
data from
N-hybrid
200
200
200
200
Ccouple
ext. int.
100nF
Vref
Vref
P
notP
N
notN
in P
inN
in P
inN
SelP
SelN
SelP
SelN
Figure 11 Analogue multiplexer diagram
disable
Hybrid A
Hybrid B
Figure 10 ALABUF ASIC
Vdd
buffer
GND
The OPAMP used in the buffer (Figure 12) is a fully
complementary Self-biased CMOS differential amplifier [4].
Additional RC networks have been added for stability of the
complete circuit to ensure that some expected capacitive load
would not influence the behaviour.
-in
+in
Input Amplifier
10k
10k
30k
-
+
30k
-
+
Vref
10k
10k
output stage
Common mode
feedback
-out
+out
Figure 12 Simplified Analogue buffer schematic
Cable
The buffer must amplify the signal from the front-end chip
to maximum output range in order to minimise any “pick-up”
while being transferred over the cable. The differential input
amplifier has an extra feedback OPAMP. This feedback circuit
reduces the common-mode error and ensures that the output
voltage “zero level” has the value of Vref (½ the supply
voltage).
In order to drive a 100Ω cable, the output must be able to
drive 20mA for an output voltage of 2V. Therefore, the driver
circuit as in Figure 13 is used. This circuit has a gain of 1, so
the input amplifier defines the gain
Vdd
of the complete buffer (gain = 2.6).
+
The buffers are provided with a
-
in
out
disable function to reduce the
+
power consumption between read-
-
outs. Two of these circuits create
disable GND
the differential output.
Figure 13 Buffer output stage
100

Analogue switches
Figure 14 Analogue buffer Layout (600 x 400µm)
D. InterfaceCard
On the InterfaceCard, the AC coupling and the control
power supplies are located (Figure 4). The EndCap receiver’s
–in one ALCAPONE- are connected (AC) to two buffer
ALCAPONE chips. These two chips drive bus lines to the
SupplyCard’s. The shunt regulators are used only at this Card,
to generate the local power for the control electronics.
E. SupplyCard
Input amplifier
Two output stages
The Hybrid power supplies are placed on the SupplyCard.
Each card contains 2 P-side- and 2 N-side supplies (4x
ALCAPONE), plus one ALABUF chip at ground potential to
drive the two analogue module outputs to the ADC. These
ALCAPONE chips are powered from the InterfaceCard.
IV. MECHANICS
Because of the space limitation, the temperature control of
the EndCap needs extra attention. Therefore, the PCB’s will
be made of an Aluminium carrier with Kapton multi layer
PCB’s on both sides. At the short sides, the cards have the
hybrid cable connectors and at one long side the back plane
connector. The other long side is used for a heat bridge to the
cooling tubes that are used for cooling the detector modules.
The power budget for one EndCap is 10W, and simulations
and measurements indicate that it is feasible.
V. SIMULATION AND MEASUREMENTS
Irradiation of the transistors of the power supply with 10 13
neutrons/cm 2 1Mev equivalent shows degradation in β of
60%. The supply can work within specifications after this 25
times higher flux than expected in 10
years of operation.
First measurements of the buffer
shows a difference in gain, exp. 2.6,
measured 2.3. The circuit is not stable
due to larger capacitances of the
NWELL resistors then expected.
Figure 15 Simulation of the buffer
The simulation (Figure 16) of the power supply shows the
start-up sequence of the circuit with an over current detection.
After the start-up timer is finished,
the over-current is detected.
After the over-current
timer is finished the output power
is switched off. Measurements on
the prototype show that the functionality
is correct. The specifications
need to be verified.
Figure 16 Simulation of the power supply
VI. STATUS AND PLANS
At this time, (Sept. 2001) the EndCap is in the design and
prototype phase. Two test IC’s have been submitted and just
became available for tests. The produced circuits are the analogue
buffer + AC coupling, power supply, and the power
supply shunt regulator that delivers the power for the supply
circuit.
Later this year a prototype of the ALCAPONE is planned,
together with the final prototype of the ALABUF chip. The
circuits will be irradiated to test their tolerance. The first
complete EndCap is planned for Q2 2003.
Mechanical prototyping has started to investigate the cooling,
cabling, and PCB handling.
VII. CONCLUSIONS
Full SEL protection of all EndCap electronics is possible.
Simulations of the individual circuits showed the feasibility of
using the 0.25µ CMOS process for the electronic components
of the EndCap.
VIII. ACKNOWLEDGEMENTS
Acknowledgements go out to the ALICE Pixel chip design
collaboration for the use of the design of the voltage DAC
(designed by D. San Segundo Bello, NIKHEF, Amsterdam),
the CERN microelectronics design group for the use of the
Bandgap voltage reference cell (Paulo Moreira) and the support
for prototype production. Most “components” of the
ASIC’s come out of the Library delivered by RAL [3].
IX. REFERENCES
1. Measurement of Single Event Latch-up Sensitivity of the
Alice128C chip; Wojeiech Dulinski LEPSI, 20/10/1998
2. Status of radiation calculations for mis-injected beam into
LHC; Blahoslav Pastircak, ALICE pres. 31/8/2000
3. Design Kit for 0.25u CMOS technology with radiation
tolerant layout; Support by RAL.
4. Two Novel Fully differential self-biased CMOS differential
amplifiers; Mel Bazes, IEEE J. of Solid State Circuits,
Vol.26, no. 2, p 165-168.
5. ALICE TDR 4, CERN/LHCC 99-12, 18 June 1999.

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Development of a High Density Pixel Multichip Module at Fermilab
S. Zimmermann, G. Cardoso, J. Andresen, J.A. Appel, G. Chiodini,
D.C. Christian, B.K. Hall, J. Hoff, S.W. Kwan, A. Mekkaoui, R. Yarema
Fermi National Accelerator Laboratory, P.O. Box 500, Batavia, IL 60510 USA
zimmer@fnal.gov
Abstract
At Fermilab, a pixel detector multichip module is being
developed for the BTeV experiment. The module is composed
of three layers. The lowest layer is formed by the readout
integrated circuits (ICs). The back of the ICs is in thermal
contact with the supporting structure, while the top is flip-chip
bump-bonded to the pixel sensor. A low mass flex-circuit
interconnect is glued on the top of this assembly, and the
readout IC pads are wire-bounded to the circuit. This paper
presents recent results on the development of a multichip
module prototype and summarizes its performance
characteristics.
I. INTRODUCTION
At Fermilab, the BTeV experiment has been approved for
the C-Zero interaction region of the Tevatron [1]. One of the
tracker detectors for this experiment will be a pixel detector
composed of 62 pixel planes of approximately 100x100 mm 2
each, assembled perpendicular to the colliding beam and
installed a few millimeters from the beam.
Carbon Fiber Shelves
Beam
Horizontal Shingles
Vertical Shingles
Figure 1: Pixel Station
Cooling Pipes
Work supported by the U.S. Department of Energy under
contract No. DE-AC02-76CH03000. Fermilab Conf-01/247-E
The planes in the pixel detector are formed by sets of
different lengths of pixel-hybrid modules, each composed of a
single active-area sensor tile and of one row of readout ICs.
The modules on opposite faces of the same pixel station are
assembled perpendicularly in relation to each other (see
Figure 1).
The BTeV pixel detector module is based on a design
relying on a hybrid approach. With this approach, the readout
chip and the sensor array are developed separately and the
detector is constructed by flip-chip mating the two together.
This approach offers maximum flexibility in the development
process, the choice of fabrication technologies, and the choice
of sensor material.
The multichip modules must conform to special
requirements dictated by BTeV: the pixel detector will be
inside a strong magnetic field (1.6 Tesla in the central field),
the flex circuit and the adhesives cannot be ferromagnetic, the
pixel detector will also be placed inside a high vacuum
environment, so the multichip module components cannot
outgas, the radiation rates (around 3 Mrad per year) and
temperature (-5 o C) also impose severe constraints on the pixel
multichip module packaging design.
The pixel detector will be employed for on-line track
finding for the lowest level trigger system and, therefore, the
pixel readout ICs will have to read out all detected hits. This
requirement imposes a severe constraint on the design of the
readout IC, the hybridized module, and the data transmission
to the data acquisition system.
Several factors impact the amount of data that each IC
needs to transfer: readout array size, distance from the beam,
number of bits of pulse-height analog to digital converter
(ADC) data format, etc. Presently, the most likely dimension
of the pixel chip array will be 128 rows by 22 columns and 3
bits of ADC information.
II. PIXEL MODULE READOUT
The pixel module readout must allow the pixel detector to
be used in the lowest level experiment trigger. Our present
assumptions are based on simulations that describe the data
pattern inside the pixel detector [3]. The parameters used for

the simulations are: luminosity of 2×10 32 cm −2 s −1 (corresponds
to an average of 2 interactions per bunch crossing), pixel size
of 400×50 µm 2 , threshold of 2000 e − and a magnetic field of
1.6 Tesla.
Module 1 → 11 13 17 17 20 18 16 13 8
Module 2 → 11 18 26 31 39 33 25 18 12
Module 3 → 16 20 37 61 76 59 39 26 18
Module 4 → 17 35 63 141 234 130 65 36 16
Module 5 → 23 35 74 234 •
Beam
Figure 2: Average Bit Data Rate at Middle Station, in Mbit/s
Figure 2 shows a sketch of the 40 chips that may compose
a pixel half plane and the data rate for the station in the middle
of 31 stations. The beam passes at the place represented by the
black dot. These numbers assume the 23-bit data format
shown in Figure 3. Table 1 presents the required bandwidth
per module. From this table we see that each half-pixel plane
requires a bandwidth of approximately 1.8 Gbit/s.
22 0
ADC Beam Crossing Number Column Row
Figure 3: Pixel Module Data Format (23 bits)
Table 1: Half Plane Required Bandwidth, in Mbit/s
Req. Bandwidth
Module 1 133
Module 2 213
Module 3 352
Module 4 737
Module 5 366
Total 1801
We’ve used simulations of the readout architecture with a
clock of 35MHz. This frequency can support a readout
efficiency of approximately 98% when considering three times
the nominal hit rate for the readout ICs closest to the beam.
Efficiency is lost either due to a pixel being hit more than once
before the first hit can be read out, or due to bottlenecks in the
core circuitry.
A. Proposed Readout Architecture
The readout architecture is a direct consequence of the
BTeV detector layout. The BTeV detector covers the forward
direction, 10-300 mrad, with respect to both colliding beams.
Hence, the volume outside this angular range is outside the
active area and can be used to house heavy readout and
control cables without interfering with the experiment. The
architecture takes advantage of this consideration.
The Data Combiner Board (DCB) located approximately
10 meters away from the detector remotely controls the pixel
modules. All the controls, clocks and data are transmitted
between the pixel module and the DCB by differential signals
employing the Low-Voltage Differential Signaling (LVDS)
standard. Common clocks and control signals are sent to each
module and then bussed to each readout IC. All data signals
are point to point connected to the DCB. Figure 4 shows a
sketch of the proposed readout architecture. For more details
refer to [6].
This readout technique requires the design of just one radhard
chip: the pixel readout IC. The point-to-point data links
minimize the risk of an entire module failure due to a single
chip failure and eliminate the need for a chip ID to be
embedded in the data stream. Simulations have shown that
this readout scheme results in readout efficiencies that are
sufficient for the BTeV experiment.
Flex Circuit
Conductors
Readout Chip
~10m
Figure 4: Pixel Module Point-to-Point Connection
III. PIXEL MODULE PROTOTYPE
Data
Combiner
Board
Figure 5 shows a sketch of the pixel module protoype.
This design uses the FPIX1 version of the Fermilab Pixel
readout IC [3].
Connectors
Decoupling
Capacitors
Figure 5: Sketch of the Pixel Multichip Module
Wire Bonds
Flex Circuit
Sensor
FPIX1 Chip
The pixel module is composed of three layers, as depicted
in Figure 6. The pixel readout chips form the bottom layer.
The back of the chips is in thermal contact with the station
supporting structure, while the other side is flip-chip bumpbonded
to the silicon pixel sensor. The clock, control, and

power pad interfaces of FPIX1 extend beyond the edge of the
sensor [2].
Silicon-Flex
Circuit adhesive
Bump bonds
Silicon-Carbon
Fiber adhesive
Flex Circuit
Sensor
FPIX1
Wire bonds
Support Structure
Figure 6: Sketch of the Pixel Multichip Module “Stack”
The interconnect circuitry (flex circuit) is placed on the
top of this assembly and the FPIX1 pad interface is wirebonded
to the flex circuit. The circuit then extends to one end
of the module where low profile connectors interface the
module to the data acquisition system. The large number of
signals in this design imposes space constraints and requires
aggressive design rules, such as 35 µm trace width and traceto-trace
clearance of 35 µm.
This packaging requires a flex circuit with four layers of
copper traces (as sketched in Figure 7). The data, control and
clock signals use the two top layers, power uses the third layer
and ground and sensor high voltage bias use the bottom layer.
The flex circuit has two power traces, one analog and one
digital. These traces are wide enough to guarantee that the
voltage drop from chip to chip is within the FPIX1 ±5%
tolerance. The decoupling capacitors in the flex circuit are
close to the pixel chips. The trace lengths and vias that
connect the capacitors to the chips are minimized to reduce
the interconnection inductance. A picture of the flex circuit
made by CERN is shown in Figure 8.
Flex Circuit
Digital lines
Digital
Ground
Analog lines
Analog
Layer 2
Layer 3
Flex Circuit-Silicon Adhesive
Sensor
Kapton ®
Layer 1
Dielectric Layer
Figure 7: Sketch of Flex Circuit Cross Section
Metal Layer 1
Metal Layer 2
Metal Layer 3
High Voltage
Metal Layer 4
Bias Pad (1mm 2 )
Gold Epoxy
Bias Window
Top
Bottom
Connectors
Terminations
H.V.
Figure 8: Flex Circuit Picture
Wire bonding pads
Decoupling Caps.
To minimize coupling between digital and analog
elements, signals are grouped together into two different sets.
The digital and analog traces are laid out on top of the digital
and analog power supply traces, respectively. Furthermore, a
ground trace runs between the analog set and the digital set of
traces.
A. High Voltage Bias
The pixel sensor is biased with up to 1000 VDC through
the flex circuit. The coupling between the digital traces and
the bias trace has to be minimized to improve the sensor noise
performance. To achieve this, the high voltage trace runs in
the fourth metal layer (ground plane, see Figure 7) and bellow
the analog power supply trace. The high voltage electrically
connects to the sensor bias window through Gold epoxy. An
insulator layer in the bottom of the flex circuit isolates the
ground in the fourth metal layer of the flex circuit from the
high voltage of the pixel sensor.
B. Assembly
The interface adhesive between the flex circuit and the
pixel sensor has to compensate for mechanical stress due to
the coefficient of thermal expansion mismatches between the
flex circuit and the silicon pixel sensor. Two alternatives are
being pursued. One is the 3M thermally conductive tape [7].
The other is the silicone-based adhesive used in [8].
The present pixel module prototypes were assembled using
the 3M tape with a thickness of 0.05mm. Before mounting the
flex circuit onto the sensor, a set of dummies with bump-bond
structures where used to evaluate the assembly process. This
assembly process led to no noticeable change in the resistance
of the bumps. Figure 9 shows a picture of the dummy.
Flex Circuit
Bump Bonded Dummy
Figure 9: Dummy Bump Bond Structure

IV. PIXEL MODULE EXPERIMENTAL RESULTS
Two pixel module prototypes were characterized. One of
these modules is a single readout IC (FPIX1) bump bonded to
a SINTEF sensor (Figure 10) using Indium bumps. In the
second pixel module the readout IC is not bump bonded to a
sensor (Figure 11). In this prototype the flex interconnect is
located on the top of the sensor (as in the baseline design).
The pixel modules have been characterized for noise and
threshold dispersion. These characteristics were measured by
injecting charge in the analog front end of the readout chip
with a pulse generator and reading out the hit data through a
PCI based test stand. The results for different thresholds are
summarized in Table 2.
Wire Bonds
Flex Circuit Readout IC Sensor
Figure 10: Pixel Module with SINTEF Sensor
Figure 11: Pixel Module without Sensor
Wire Bonds
Table 2: Performance of the Pixel Prototype Modules (in e − )
Without Sensor With Sensor
µ Th σ Th µ Noise σ Noise µ Th σ Th µ Noise σ Noise
7365 356 75 7 7820 408 94 7.5
6394 332 78 12 6529 386 111 11
5455 388 79 11 5500 377 113 13
4448 378 78 11 4410 380 107 15
3513 384 79 12 3338 390 116 20
2556 375 77 13 2289 391 117 21
The comparison of these results with previous results
(single readout IC without the flex circuit on top) shows no
noticeable degradation in the electrical performance of the
pixel module [4]. Figure 12 shows the hit map of the pixel
module with sensor using a radioactive source (Sr 90),
confirming that the bump bonds remain functional.
Figure 12: Pixel Module Hit Map
V. RESULTS OF THE HYBRIDIZATION TO
PIXEL SENSORS
The hybridization approach pursued offers maximum
flexibility. However, it requires the availability of highly
reliable, reasonably low cost fine-pitch flip-chip mating
technology. We have tested three bump bonding technologies:
indium, fluxed solder, and fluxless solder. Real sensors and
readout chips were indium bumped at both the single chip and
at the wafer level by BOEING, NA. Inc (Anaheim, CA) and
Advance Interconnect Technology Ltd. (Hong Kong) with
satisfactory yield and performance. For more details refer to
[5].
VI. CONCLUSIONS
We have described the baseline pixel multichip module
designed to handle the data rate required for the BTeV
experiment at Fermilab. The assembly process of a single chip
pixel module prototype was successful. A 5-chip pixel module
prototype (Figure 13) will be assembled using the same
process. The characterization of the two single-chip modules
showed that there is no degradation in the electrical
performance of the pixel module when compared with
previous prototypes.

[mm]
Readout chip Pixel Sensor
Figure 13: 5-chip Pixel Module with Indium Bumps
VII. ACKNOWLEDGEMENTS
The authors would like to thank CERN, and in particular
Rui de Oliveira, for producing the flex circuit for this
prototype.
VIII. REFERENCES
1. Kulyavtsev, A., et al., BTeV Proposal, Fermilab, May
2000.
2. Cardoso, G., et al., “Development of a high density pixel
multichip module at Fermilab”, 51 st ECTC, Orlando,
Florida, May 28-31, 2001.
3. Christian, D.C., et al., “Development of a pixel readout
chip for BTeV,” Nucl. Instr. and Meth. A 435, pp.144-152,
1999.
4. Mekkaoui, A., et al., “FPIX2: an advanced pixel readout
chip,” 5 th Workshop on Elect. LHC Exp., Snowmass, pp.
98-102, Sept. 1999.
5. Cihangir, S., et al., “Study of thermal cycling and radiation
effects on Indium and fluxless solder bump-bonding
devices”, to be presented in the 7 th Workshop on Elect.
LHC Exp., Stockholm, September 2001
6. Hall, B., et al., “Development of a Readout Technique for
the High Data Rate BTeV Pixel Detector at Fermilab”, to
be presented in the 2001 Nuclear Science Symposium and
Medical Imaging Conference, San Diego, November 2001.
7. Thermally Conductive Adhesive Transfer Tapes, Technical
datasheet, 3M. April 1999.
8. Abt, I., et al., “Gluing Silicon with Silicone”, Nucl. Instr.
and Meth. A 411, pp. 191-196, 1998.

Radiation tolerance studies of BTeV pixel readout chip prototypes.
G. Chiodini, J.A. Appel, G. Cardoso, D.C. Christian, M.R.Coluccia, J. Hoff, S.W. Kwan,
A. Mekkaoui, R. Yarema, and S. Zimmermann
Fermi National Accelerator Laboratory, P.O. Box 500 Batavia, IL 60510, USA 1
email address of the corresponding author: chiodini@fnal.gov
Abstract
We report on several irradiation studies performed on
BTeV preFPIX2 pixel readout chip prototypes exposed to a
200 MeV proton beam at the Indiana University Cyclotron
Facility. The preFPIX2 pixel readout chip has been
implemented in standard 0.25 micron CMOS technology
following radiation tolerant design rules. The tests confirmed
the radiation tolerance of the chip design to proton total dose
of 26 MRad. In addition, non destructive radiation-induced
single event upsets have been observed in on-chip static
registers and the single bit upset cross section has been
measured.
I. INTRODUCTION
The BTeV experiment plans to run at the Tevatron collider
in 2006 [1]. It is designed to cover the “forward” region of the
proton-antiproton interaction point at a luminosity of
2·10 32 cm -2 s -1 . The experiment will employ a silicon pixel
vertex detector to provide high precision space points for an
on-line lowest level trigger based on track impact parameters.
The “hottest” chips, located at 6 mm from the beam, will
experience a fluence of about 10 14 cm -2 y -1 . This is similar to
the high radiation environments at ATLAS and CMS at LHC.
A pixel detector readout chip (FPIX) has been developed
at Fermilab to meet the requirements of future Tevatron
collider experiments. The preFPIX2 represents the most
advanced iteration of very successful chip prototypes [2] and
has been realized in standard deep-submicron CMOS
technology. As demonstrated by the RD49 collaboration at
CERN, the above process can be made very radiation tolerant
following specific design rules [3]. The final FPIX will be
fabricated using radiation tolerant 0.25 micron CMOS process
with enclosed geometry NMOS transistors and guard rings.
We show results of radiation tests performed with
preFPIX2 chip prototypes including both total dose and single
event effects. The tests have been performed exposing the
chip to 200 MeV protons at the IUCF. The comparison of the
chip performance before and after exposure shows the high
radiation tolerance of the design to protons up to about 26
Mrad total dose. Last year exposures of preFPIXT chips to
radiation from a Colbalt-60 source at Argonne National
Laboratory verified the high tolerance to gamma radiation up
to about 33 Mrad total dose [4].
Total dose effects are not the only concern for reliable
operation of the detector. Ionising radiation can induce single
event upset (SEU) effects, as unwanted logic state transitions
in digital devices, corrupting stored data.
The single event upsets just described do not permanently
alter the chip behaviour, but they could result in data loss,
shifts of the nominal operating conditions, and loss of chip
control. If the single event upset rate is particularly high, it
could be mitigated by circuit hardening techniques. If it is not
high, the upset rate could be tolerated simply by a slow
periodic downloading of data and full system resetting in the
worse case. During the irradiation, we set up tests in order to
observe the occurrence of single event upsets in the preFPIX2
registers and we measured the corresponding single bit upset
cross section.
II. THE RADIATION TOLERANT FPIX CHIP
In order to satisfy the needs of BTeV, the FPIX pixel
readout chip must provide “very clean” track crossing points
near the interaction region for every 132 ns beam crossing.
This requires a low noise front-end, an unusually high output
bandwidth, and radiation-tolerant technology.
A. The preFPIX2I and preFPIXTb chip
prototypes
The road to the desired performances has been paved by
fabricating preFPIX2 chip prototypes in deep-submicron
technology from two vendors. The preFPIX2I chip,
containing 16 columns with 32 rows of pixel cells and
complete core readout architecture, has been manufactured
through CERN. The preFPIX2Tb chip, contains, in addition to
the preFPIX2I chip features, a new programming interface
and digital-to-analog converters. It has been manufactured by
Tiawan Semiconductor Manufacturing Company. Based on
test results, some of them reported here, we intend to submit a
full-size BTeV pixel readout chip before the end of the year
2001. That chip will include the final 50 micron by 400
micron pixel cells and high speed output data serializer.
The analog-front end [4] and the core architecture [5] of
the pixel readout chips fabricated in deep-submicron CMOS
technology have been described elsewhere. In this paper we
briefly describe the additional features of the preFPIX2Tb
chip because of their relevance in the single event upset tests
reported.
1 Work supported by the U.S. Department of Energy under contract No. DE-AC02-76CH03000. Fermilab Conf-01/214-E.

B. Registers in preFPIX2Tb readout chip
The programming interface permits download of mask and
charge-injection registers and digital-to-analog (DAC)
registers. These registers control features of the chip and
minimize the number of connections between the chip and the
outside world.
The mask and charge-injection registers consist of small
size-daisy chained Flip-Flop’s (FF’s) and are implemented in
each pixel cell. A high logic level stored in one of the mask
FF’s disables the corresponding cell. This is meant to turn off
noisy cells. Analogously, a high logic level stored in one of
the charge-injection FF’s enables the cell to receive at the
input an analogue pulse for calibration purposes. Thus, there
are two independent long registers, which are serpentine
through the chip. In the preFPIX2Tb periphery, there are 14
DAC registers implemented, each one 8 bits long. The stored
digital value is translated to in an analogue voltage or
analogue current to set bias voltages, bias currents and
threshold discriminators.
The FF’s for DAC registers are of larger size than the FF’s
for the shift-registers. In fact, the DAC FF’s are more
complex and uses larger size NFET devices. The reason for
this choice is the high reliability required for the DAC
registers, which regulate the operational point of the cells.
III. EXPERIMENTAL SETUP
C. Irradiation facility at IUCF
The proton irradiation tests took place at the Indiana
University Cyclotron Facility where a proton beam line of 200
MeV kinetic energy is delivered to users. The beam profile
has been measured by exposing a sensitive film. The beam
spot, defined by the circular area where the flux is not less
than 90% of the central value, had a diameter of about 1.5 cm,
comfortably larger than the chip size (the larger chip is
preFPIX2Tb which is 4.3 mm wide and 7.2 mm long). Before
the exposure the absolute fluence was measured by a Faraday
cup; during the exposure by a Secondary Electron Emission
Monitor. The cyclotron has a duty cycle factor of 0.7% with a
repetition rate of about 17MHz and most of the tests were
done with a flux of about 2·10 10 protons cm -2 s -1 .
The irradiation was done in air at room temperature, and
no low energy particle or neutron filters were used. The
exposures with multiple boards were done placing the boards
about 2 cm behind each other and with the chips facing the
beam. Mechanically, the boards were kept in position by an
open aluminium frame. The beam was centred on the chips.
The physical position of the frame was monitored constantly
by a video camera to ensure that no movements occurred
during exposure.
We irradiated 4 boards with preFPIXI chips to 26 Mrad
(December 2000), one board with preFPIX2Tb to 14 Mrad
(April 2001), and recently 4 boards with preFPIX2Tb to 29
Mrad (August 2001). One of the boards with preFPIX2Tb
chips on it was irradiated twice collecting 43 Mrad total dose.
Due to the alignment precision and measurement technique
employed, the systematic error on the integrated fluence is
believed to be less than 10%.
D. Hardware and software
Each chip under test was wire-bonded to a printed circuit
board in such a way that it could be properly biased,
controlled and read out by a DAQ system. The DAQ system
was based on a PCI card designed at Fermilab (PCI Test
Adapter card) plugged in a PCIbus extender and controlled by
a laptop PC. The PTA card generated digital signals to control
and read back the readout chips. The software to control the
PCI card IO busses was custom and written in C-code. The
PCI card IO busses were buffered by LVDS differential
driver-receiver cards near by the PCIbus extender located in
the counting room. The differential card drove a 100 foot
twisted pair cable followed by another LVDS differential
driver-receiver card which finally was connected with a 10
foot flat cable to the devices under test. All the DAQ
electronics were well behind thick concrete walls, protecting
the apparatus from being influenced by the radiation
background from the cyclotron and from activated material.
IV. ANALYSIS AND RESULTS
E. Performed tests
1) Bias currents monitor
During the irradiation tests, the analogue and digital
currents where continuously monitored by a GPIB card. The
analogue current decreased slightly and the digital currents
increased slightly during the proton exposure.
2) Noise and threshold dispersion
The noise and the discriminator threshold of each
individual cell were measured before and after the irradiation
in exactly the same bias conditions for the four preFPIX2I
chips 2 . Every cell works after irradiation with a noise about
10% less and a decrease of about 20% in the threshold
dispersion among cells. Figure 1 and 2 show the noise and
threshold distributions of a preFPIXI chip irradiated with a
proton dose of 26 Mrad.
3) Single Event Upsets (SEU)
In our tests, a great deal of attention was focused on
measuring radiation induced digital soft errors. We
concentrated our effort on the preFPIX2Tb registers storing
the initialisation parameters, because they have a large
number of bits and the testing procedure is easy to prepare.
The results obtained allow prediction of the performance of
other parts of the chip potentially affected by the same
phenomena.
2 The results for the four preFPIXTb chips are going to be
available in early October ‘01.

Figure 1: Measured amplifier noise in the 576 cells of preFPIX2I
before and after 26 Mrad of 200 MeV proton irradiation.
Figure 2: Measured discriminator threshold in the 576 cells of
preFPIX2I before and after 26 Mrad of 200 MeV proton irradiation.
The single event upset tests performed are very similar to
the ones reported in reference [6]. The SEU measurements
consisted of detecting single bit errors in the values stored in
the registers. The testing procedure consisted of repeatedly
downloading all the registers and reading back the stored
values after one minute. The download and read-back phases
took about 3 seconds. The download of the parameters was
done with a pattern with half of the stored bits having a
logical value 0 and the other half having a logical value 1
(except in one case, see Footnote 3). For the shift-registers,
the patterns were randomly generated at every iteration loop.
For the DAC registers, the patterns were kept constant. A
mismatch between the read-back value and the download
value is interpreted as a single event upset due to the proton
irradiation. No errors were observed in the system with the
beam off and running for 10 hours.
In a specific test, the mask register of one board was
operated in clocked mode with a clock frequency of 380 kHz.
The low clock frequency value was due to our DAQ
limitation. In this test, the mask register was downloaded with
a logical level 1 in each flip-flop, in order to increase the
statistics in view of the fact that a stored logical level 1 is
easier to upset with respect to a logical level 0 (see results).
After the initialisation, a continuous read cycle was performed
and stopped every time a logical level 0 was detected.
We collected 14 errors for an effective integrated fluence of
5.8·10 13 protons cm -2 .
A summary of the total single bit errors detected in the
preFPIX2Tb readout chips, together with other relevant
quantities, is shown in Table 1. The value in square brackets
represents the initial stored logical level of the upset bit. One
of the boards (indicated as board 4 in Table 1) was placed not
orthogonal to the beam, as the other ones, but at 45 degrees to
explore possible dependence of the error rate on the beam
incident angle. The number of single bit upsets, for an equal
amount of total dose, is statistically consistent among the
various chips. In addition, the data do not show any
statistically significant difference in the error rate between the
tilted board and the other ones.
Table 1: Total single bit errors in preFPIX2Tb registers.
Board Integrated
Fluence (cm -2 )
Errors in shiftregs
(1152 bit)
Errors in DAC
regs (112 bit)
1 2.33·10 14 53=18[0] +35[1] 10=8[0]+2[1] 3
1 3.65·10 14 80=23[0] +57[1] 20=8[0] +12[1]
2 3.65·10 14 74=22[0] +52[1] 19=9[0] +10[1]
3 3.65·10 14 86=27[0] +59[1] 19=8[0] +11[1]
4 3.65·10 14 77=14[0] +63[1] 31=19[0] +12[1]
Table 2: Single bit upset cross section in preFPIX2Tb registers.
Flip-flop Mode Cross section
(10 -16 cm 2 )
Shift-regs 0 to 1 Un-clocked 1.0±0.1
Shift-regs 1 to 0 Un-clocked 2.7±0.2
Shift-regs 1 to 0 Clocked (380kHz) 4.2±1.2
DAC regs 1 to 0 Un-clocked 5.5±0.6
It is common practise to express the error rate of a register as
a single bit upset cross section, defined as the number of
errors per bit per unit of integrated fluence. The single bit
upset cross section has been computed for the shift-registers
and for the DAC registers. The results are shown in Table 2.
Only the statistical error on the cross section has been
considered. For the shift-registers, the cross section has been
computed separately for the radiation induced transition from
0 to 1 and from 1 to 0 because the data have enough precision
to show the existence of an asymmetry.
3 The observed asymmetry in this case is due to the unequal
numbers of zero’s (82) and one’s (30) downloaded into the
DAC registers.

The high beam fluence used during the irradiation was of
some concern regarding any saturation effect in the error rate.
To study this, we collected some data at a fluence of about
4·10 9 protons cm -2 s -1 , about 5 times less than the nominal
fluence. In this short test, only one board was irradiated (Apr.
‘01 test) and the single bit cross section was measured to be
(1.4±1)·10 -16 cm 2 and (3.5±1.6 )·10 -16 cm 2 for the shift-
registers and (7±5)·10 -16 cm 2 for the DAC registers in unclocked
mode, statistically compatible with the results at
higher fluence.
F. Discussion of the results
No power supply trip-offs or large increases in the bias
currents were observed during the irradiation. There is no
evidence of single event latch-up or of significant radiation
induced leakage currents. Moreover, the absence of noisy
cells and no large difference in individual thresholds due to
irradiation, strongly suggest that single event gate rapture is
not a concern.
The prediction of the single bit upset cross section is very
difficult because a lot of parameters came into play [7].
Nevertheless, some gross features of the data can be
understood simply by some general considerations.
The disparity in the cross section between the shift
registers and the DAC registers is likely caused by the
different size of the active area of the NFET transistor, which
is larger for the DAC register FF’s. Besides that, the DAC
register FF’s have a more complicated design and an increase
in complexity, as a rule of thumb, translates to a larger
number of sensitive nodes that can be upset.
The SEU asymmetry for the transition from 0 to 1 with
respect to 1 to 0 can be explained in terms of the FF design.
The FF’s of the shift-registers are D-FF’s implemented as
cross-coupled nor-not gates. Such a configuration has
different sensitive nodes for 0 to 1 and 1 to 0 upsets. No such
an asymmetry is expected at all for the DAC registers because
the FF’s are D-FF’s implemented as cross-coupled nor-nor
gates. This symmetric configuration has the distribution of
sensitive nodes for low logical level the same as when a high
logical level is stored.
A decrease of the energy threshold for single bit upset has
been reported (in reference [6]) for a static register in clocked
mode with respect to unclocked mode. Our data, taken with a
clock frequency of 380 kHz, do not show a statistically
significant difference from the data taken in the unclocked
mode.
In reference [8] a beam angular dependence is expected
for devices with very thin sensitive volumes that have Linear
Energy Transfer (LET) threshold over 1 MeV cm 2 /mg and
tested with 200 MeV protons. We didn’t observe any
dependence of the upset rate on the beam incident angle. In
fact, due to the smaller device size of the deep submicron
elements, the sensitive volumes are more like cubic than slab
shaped.
V. CONCLUSIONS
The results of the total dose test validate the deep
submicron CMOS process as radiation tolerant, particularly
suitable for pixel readout chips and other electronics exposed
to large integrated total dose. The single event upset cross
sections of static registers are relatively small, but measurable
(10 -16 to 5·10 -16 cm 2 ). The experience gained from the
gamma and proton irradiation of pre-prototype chips has been
of importance in allowing us to proceed with the submission
of a full-size BTeV pixel readout chip and developing an
approach to handle SEU.
VI. ACKNOWLEDGEMENTS
We thank Chuck Foster and Ken Murray for the generous
technical and scientific assistance they provided us during the
irradiation tests at IUCF.
VII. REFERENCES
[1] A. Kulyavtsev et al., “Proposal for an Experiment to
measure Mixing, CP Violation, and Rare Decays in Charm
and Beauty Particle Decays at Fermilab Collider,” (2000),
http://www-btev.fanl.gov/public_documents/btev_proposal/.
[2] D.C. Christian, et al., “Development of a pixel readout
chip for BTeV,” Nucl. Instrum. Meth. A 435, 144-152, 1999.
[3] L. Adams, et al., “2 nd RD49 Status Report: Study of
the Radiation Tolerance of Ics for LHC,” CERN/LHCC 99-8,
LEB Status Report/RD49, 8 March 1999, available at
http://rd49.web.cern.ch/RD49/Welcome.html#rd49docs.
[4] A. Mekkoui, J. Hoff, “30Mrad(SiO2) radiation tolerant
pixel front end for the BTeV experiment”, Nucl. Instr. And
Meth. A 465, 166 (2001).
[5] J. Hoff, et al., “PreFPIX2: Core Architecture and
Results”, IEEE Trans. Nucl. Sci. 48, 485 (2001).
[6] P. Jarron, et al., “Deep submicron CMOS technologies
for the LHC experiments”. Nucl. Phys. B (Proc. Suppl.) 78,
625 (1999).
[7] M. Huhtinen, F. Faccio, et al., “Computational method
to estimate Single Event Upset rates in accelerator
environment”, Nucl. Instr. And Meth. A 450, 155 (2000).
[8] P.M. O’Neill, et al., “Internuclear Cascade –
Evaporation Model for LET Spectra of 200 MeV Protons
Used for Parts Testing”, IEEE Trans. Nucl. Sci. 45, 2467
(1998)

The ALICE Pixel Detector Readout Chip Test System.
F. Antinori (1,2) , M. Burns (1) , M. Campbell (1) , M. Caselle (3) , P. Chochula (1, 4) ,
R. Dinapoli (1) , F. Formenti (1) , J.J.Van Hunen (1) , A. Kluge (1) , F. Meddi (1, 5) , M. Morel (1) , P
Riedler (1) , W. Snoeys (1) , G. Stefanini (1) , K. Wyllie (1) .
(For the ALICE Collaboration)
(1) CERN, 1211 Geneva 23, Switzerland
(2) Università degli Studi di Padova, I-35131 Padova, Italy
(3) Universita degli Studi di Bari, I-70126 Bari, Italy
(4) Comenius University, 84215 Bratislava, Slovakia
(5) Universita di Roma “La Sapienza”, I-00185 Roma, Italy
Abstract
The ALICE experiment will require some 1200
Readout Chips for the construction of the Silicon Pixel
Detector [1] and it has been estimated that approximately
3000 units will require testing.
This paper describes the system that was developed
for this task.
I. INTRODUCTION
The Pixel Readout chip [2] is a mixed signal device
containing both analogue and digital circuits. It is made
up as a matrix of 32 columns by 256 rows of Pixel cells.
Each cell comprises of a pre-amplifier, pulse shaper,
discriminator, two digital delay units and a 4 event derandomising
buffer. These cells are connected as 32
parallel shift registers each of 256 bits read out
sequentially at 10MHz. Each cell contains five
configuration bits, three for the threshold fine control and
two to enable testing and masking of the cell.
The test system used for testing the prototype version
of the readout chip was made up of several modules each
performing a specific function, but were invariably of
different formats and often requiring adaptation between
them. The computer used to control the system was not
flexible enough to be able to be programmed to give a
rapid online indication of the quality of the device under
test or to present the results of the completed
measurement in a graphic manner. With so many devices
to be characterised and tested the opportunity was taken
to develop a simple yet flexible test system incorporating
the required functionality which could be used at all
stages of the testing and qualifying of the Readout chips
and sub assemblies.
The test system should be capable of supplying the
necessary signals to ensure the correct functionality of the
internal circuitry of the device as well as finding use in
other areas of the qualification process.
II. THE TEST PROCEDURE
Initially, several devices were tested on an Integrated
Circuit (IC) tester capable of performing simple low level
tests. These tests ensured that the various sections within
the devices functioned correctly and could be accessed for
more complete tests 1 . Once the design had been proved to
function correctly on the IC tester they were transferred to
the Test System for higher level tests.
Using the test system each device was fully
characterised for its dc operating conditions, power
consumption and the functioning of the various internal
sections, including dynamic testing of the sensitivity and
spread of thresholds, noise, calibration of the internal
configuration digital to analogue converters.
At each step the system is capable of displaying the
progress of the measurement and once finished the results
are displayed in a graphical form. Data is stored into a
database for reference at a future date.
The same hardware was used for beam tests and tests
of radiation tolerance.
III. THE SYSTEM DESIGN
The test system was designed taking the following
requirements into account:
• Hardware Requirements
• To supply the necessary supply voltage and
biases as required by the device,
1 We shall not discuss these tests in detail as they are
beyond the scope of this paper.

• provide an interface between the DAQ
environment and the Pixel Chip environment,
• be flexible enough to perform a variety of DAQ
functions such as Wafer Probe testing, testing
subassemblies of the Pixel Detector, radiation
and beam tests,
• be simple, compact and easy to reproduce,
• use off-the-shelf and industry-standard
components whenever possible,
• Software Requirements
• Have powerful graphic capabilities,
• be flexible and adaptable when choosing
hardware,
• a comprehensive Graphical User Interface (GUI)
should be developed,
• full monitoring facilities should be available,
• generation and maintenance of a database,
• be adaptable to different test scenarios.
The test system has been designed around a PC
connected to a VME crate, as shown in Figure 1. The
connection is made by a National Instruments MXI
connection.
Figure 1: The layout of the basic test system
A Readout Controller (PILOT Module) [3] has been
developed in the VME standard to control the readout of
the Pixel Readout Chip. As the Pixel Readout Chip is
configured and controlled by JTAG [4] so JTAG is also
used control a DAQ Adapter board that is situated close
to the Pixel readout chip under test. There are various
choices of JTAG controller: models which use a PC
parallel port, models which may be installed in the PC, or
as in our case a module installed in the VME crate.
Differential connections between the modules installed in
the VME crate and the DAQ Adapter board allow the use
of long interconnecting cables making the system suitable
for use where the readout/test system must be sited away
from the actual Pixel Readout chip.
• The PC
As the functioning of the system relies heavily
on software and that large amounts of data need to be
manipulated, a fast PC with a large amount of memory
and storage is preferable.
• MXI Controller
The MXI Controller [5] provides the connection
between the PCI bus of the PC and the DAQ VME crate.
• Readout Controller
The readout controller (Figure 2) is a VME
module that, on receipt of commands from either the
VME bus or an external source of trigger signals,
generates all signals necessary for the readout of the Pixel
Chip. Zero skipping and hit encoding are performed to
reduce the amount of data to be stored. A test path has
been included to allow testing the system with known
data.
• JTAG Controller
VME INTERFACE
Test Data
Hit Data
CRATE END FIFO
(Hit Data)
VME Control & Trigger
External Trigger
The JTAG controller requires two channels, one
for controlling and configuring the Pixel Readout Chip,
the other to control the DAQ Adapter Board. Using two
channels reduces the risk of a faulty Pixel Readout Chip
impeding the correct functioning of the DAQ Adapter
Board.
• DAQ Adapter Board
ZERO SKIP
&
DATA ENCODING
CONTROL LOGIC
The DAQ Adapter Board is situated between the
Pilot Module and Pixel Chip under test and serves as an
interface between the two environments. It houses the line
drivers and receivers necessary for the DAQ connection
and Gunning transceiver Logic (GTL) drivers necessary
for the Pixel Chip bus connection.
It also houses the circuitry to derive the
necessary power and bias supplies. Monitoring of both
applied voltage and consumed current are possible.
CLOCK
TEST DATA
INPUT FIFO
(Raw data)
Data[31:0]
/CS[9:0]
RO Control
Test Pulse
RO Clock
PILOT MODULE
Figure 2: The block diagram of the Readout Controller.

Control JTAG
Multiplicity
Pixel JTAG
Pilot Module
Trst
Tms
Tck
Tdi
Tdo
Mult[9:0]
Ready
Trst
Tms
Tck
Tdi
Tdo
Data[31:0]
CS[9:0]
RO[n:0]
Test Pulse
RO Clk
Feed Back
16 Bit Data Register
Function
Decoder
8 Bit Instruction
Register
Register
Multiplicity
Additional circuitry has been included to allow a
multiplicity measurement to make a rapid evaluation of
the total number of hit Pixels within the chip.
The control of the Adapter Board is by means of a
simple JTAG protocol consisting of an 8 bit IR Scan to
address a device and a 16 bit DR Scan to write or read a
data value.
Delay
Data bus [15:0]
Control bus [n:0]
BS cells
DACs
ADCs
ADC
Fast
OR
I to V
TTL/GTL Level Adaptors
TTL/GTL Level Adaptors
Trst
Tms
Tck
Tdi
Tdo
Data[31:0]
CONTROL
Fast OR
CS[9:0]
RO
Control
Test
Pulse
RO Clock
MISC.
PIXEL JTAG
PILOT INTERFACE
DAQ ADAPTER BOARD
Figure 3: The block diagram of the DAQ Adapter Board.
Connections to IC Tester and DAQ Adapter Board
Multliplicity Out
Fast OR Out
Trst
Tms
Tck
Tdi
Tdo
Power and Biases
Internal Feedback
Misc.
Signals
JTAG
Control
Pixel Data[31:0]
/CS
Control Signals
Test Pulse
Clk
PIXEL CHIP
UNDER TEST
Data
Readout
Internal Nodes
Test PIXEL CHIP CARRIER BOARD
Jumper Selection
Figure 4: The block diagram of the Pixel Carrier Board.
Pixel JTAG
Pixel Databus
Scope Monitoring
• Pixel Readout Chip Carrier Board
The individual Pixel Readout chips are wire
bonded to the carrier board (Figure 4), which may be
connected to either the IC tester, or the DAQ Adapter
board. Test points have been included on all bus signals.
Facilities have been provided to allow observation of
various internal nodes of the device.
Variations of the carrier board have lent
themselves for both wafer probing tests and evaluation of
the prototype bus structure currently under design for use
in the Pixel Detector.
IV. TEST SYSTEM SOFTWARE
The final testing and production of the Alice
Pixel detector will take place in several laboratories. For
practical reasons the number of operating systems and
software environments must be kept to a minimum.
The test software architecture reflects the
flexibility of the hardware. Its modularity guaranties that
the system can be used with different hardware
Applications
Services and Shared Memory
Drivers
VISA ADO
Hardware Database
Figure 5: The PTS software architecture
Root
Interface
Root
Logfiles
configurations without the need of rewriting the software
core.
Windows 9x/NT/2K and National Instrument’s
LabView were chosen as the main software
environments. In addition, CERN’s package ROOT [6] is
used for offline analysis. The system has taken advantage
of several industrial standards, such as VISA [7] or ADO
[8] to simplify hardware and database access.
To enhance the flexibility, software modules are
logically grouped into three basic layers: the drivers,
services and applications to form the full Pixel Test
System (PTS). The relationship between architectural
layers is shown in Figure 5.
The driver layer handles the communication
between the software system and hardware components.
Its main role is configuration of connected devices and
basic I/O operations (e.g. JTAG data scan). Drivers
communicate with the service layer by means of a fixed
protocol, which simplifies system adaptation to hardware
modifications. A hardware modification requires only a
minimum set of software modules to be changed.

Figure 6: A snapshot of DAQ Monitor display with an example of plugins
On the lowest level, the drivers rely on Virtual
Software Architecture (VISA). This industrial standard
provides a unified interface to different busses (e.g. VME,
VXI, GPIB, RS-232 or Ethernet). For non-VISA
compliant devices Windows compatible DLL libraries are
used.
The service layer acts mainly on the data level.
Its role is data formatting and integrity checking. For
example, pixel data are checked for consistency at this
level. Corrupted frames, buffer overflows or missing
triggers can be immediately signalled to the applications,
which can then take the proper action. Another important
role of the service layer is data flow control. For example,
two applications are not allowed to access the same
hardware at the same time. Device execution timeouts are
also handled at this level so that an accidental hardware
failure will not lock the software system. Inter-module
communication is simplified by using shared memory
also provided by this layer.
Programs belonging to the highest layer are
divided into two basic categories: the Control Panels and
the Applications. Each hardware component of the system
has its own associated Control Panel, which enables low
level register access, device reconfiguration and macro
command execution. Programs belonging to this category
are mainly used for debugging or low-level device
commissioning. On the other hand, the Applications
perform the most complicated tasks including JTAG
integrity checks, DAC calibrations and threshold scans.
V. THE TESTBEAM SOFTWARE SYSTEMS
The Test beam DAQ and monitoring program is
also a part of the highest PTS layer. It is the most
powerful part of PTS so far. A single application (called
DAQ Monitor) enables the acquisition of data in a variety
of conditions ranging from free running modes with either
software or external triggering up to the synchronous
operation with an external triggering system. The DAQ
Monitor can service a variable number of connected
detectors.
In order to keep the testbeam control system at
the level of a single application, a concept of plugins has
been introduced. These plugins are software modules
used to perform specialized tasks, such as checking of
trigger efficiencies, monitoring of system performance
and calculation of cluster size distributions. The online
system loads the plugins on demand. For example they
are completely omitted if the highest system speed is
required. The offline analysis can re-use the same plugins
for data reconstruction. An example of the DAQ displays
is shown in Figure 6.
The DAQ software is capable of operating at a
sustained trigger rate of 65 kHz, which is adequate for
testbeam purposes requiring a trigger rate of ~10 kHz.
The detector control system monitors voltages
and temperatures in the different parts of the system. A
LabView controlled multiplexer connects input channels
to an external GBIB based multimeter. The position of the

irradiated chips can be changed by using a remotely
controlled x-y table.
VI. OFFLINE ANALYSIS AND DATABASE
ACCESS
Despite its flexibility, the physics community
does not commonly use LabView for data analysis.
Instead, the Root system is usually employed to perform
the offline processing. The PTS includes an interface that
allows for this task. By using Root, the PTS can take
advantage of the variety of its classes for efficient
analysis. The choice of Root was motivated also by
economical factors, since it is a free system and does not
require the purchase of expensive compilers. A nonnegligible
fact is also the portability of code to different
operating system platforms. However our mainstream
system remains Windows.
To perform the characterization of the full
production of about 3000 chips, several Terabytes of data
must be processed. The production data and measured
optimal settings for each chip must be preserved in an
accessible way for the actual PTS as well as for future
final DAQ and Control systems. Our choice has been the
MySQL [9] database running under the Linux operating
system. To interface the database to LabView we use
Microsoft’s Active Data Objects (ADO). This technology,
based on ActiveX [10], provides a unique way of
accessing different data sources either locally or over a
network. One of the main advantages of ADO is that
being an industrial-standard our system will be
compatible with any common database which we might
choose in the future. In a manner similar to the hardware
drivers, it is only necessary to change a software driver
(data provider) to make the PTS compatible with any
other data sources.
VII. CONCLUSIONS
The test system described has proved to be flexible
enough to satisfy all the requirements ranging from wafer
probing, readout chip testing, radiation and beam testing.
The software has greatly reduced the time necessary
to characterize the devices. The PTS has proved
invaluable not only to rapidly asses the device under test
is functioning but also to assist with the debugging of the
overall system
VIII. REFERENCES
[1] ALICE – Technical Design Report of the Inner
Tracking System (ITS), CERN/LHCC 99-12, June
1999.
[2] W. Snoeys at al.: Pixel Readout Electronics
development for the Alice Pixel Vertex and LHCb
Rich detector, Nucl.Instrum.Meth.A465:176-
189,2000
[3] P.Chochula, F.Formenti and F.Meddi: User’s Guide
to the Alice VME Pilot System, Alice-int-2000-32,
CERN 2000
[4] IEEE Std 1149.1. Test Access Port and Boundary
Scan Architecture.
[5] See http://www.ni.com
[6] Rene Brun and Fons Rademakers, ROOT - An Object
Oriented Data Analysis Framework, Proceedings
AIHENP'96 Workshop, Lausanne, Sep. 1996, Nucl.
Inst. & Meth. in Phys. Res. A 389 (1997) 81-86. See
also http://root.cern.ch/.
[7] National Instruments VISA pages, see for example
http://www.ni.com/Visa
[8] J.T.Roff: ADO : ActiveX Data Objects, O'Reilly &
Associates; ISBN: 1565924150
[9] M.Koffler: MySQL, APress; ISBN: 1893115577
[10] D. Chapell: Understanding Activex and Ole,
Microsoft Press; ISBN: 1572312165
P6: M.Kofler: MYSQL, APress; ISBN: 1893115577

The HAL25 Front-End Chip
for the ALICE Silicon Strip Detectors
D. Bonnet, A. Brogna, J.P. Coffin, G. Deptuch, C. Gojak, C. Hu-Guo * , J.R. Lutz, A. Tarchini
IReS (IN2P3-ULP), Strasbourg, France
*Corresponding author Christine.hu@ires.in2p3.fr
Abstract
The HAL25 is a mixed low noise, low power consumption
and radiation hardened ASIC intended to read out the
Silicon Strip Detectors (SSD) in the ALICE tracker. It is
designed in a 0.25 micron CMOS process and is
conceptually similar to a previous chip, ALICE128C. It
contains 128 analogue channels, each consisting of a
preamplifier, a shaper and a storage capacitor. The
analogue data is sampled by an external logic signal and
then is serially read out through an analogue multiplexer.
This voltage signal is converted into a differential current
signal by a differential linearised transconductance
output buffer. A slow control complying with the JTAG
protocol was implemented to set up the circuit.
Introduction
The HAL25 is a mixed, analogue digital, ASIC designed
for read-out of Silicon Strip Detectors (SSD) in the
ALICE tracker. It is based on the ALICE first generation
chip, ALICE128C [1]. The ALICE128C chip
performances were successfully maintained up to 50 krad
of the ionising dose. It is now used in the SSD front-ends
electronic of the STAR tracker.
In order to maintain some safety margin in radiation
environment a new circuit has been designed. It has been
demonstrated that commercial deep sub-micron CMOS
processes exhibit intrinsic radiation tolerance [2]. HAL25
has been designed in a 0.25 micron CMOS process. In
addition special design techniques have been used to meet
the demands of low noise, low power consumption and
radiation hardness required by the ALICE experiment.
For the SSD layer, the ALICE experiment needs a readout
device having a very large dynamic range (+/- 13 MIPs)
with a good linearity and an adjustable shaping time from
1.4 µs to 2.2 µs. This is a challenge for such a circuit
designed in a deep sub-micron process operated at only
2.5 V which is the edge of the use of standard analogue
design techniques.
This paper explains the design of the chip. Since HAL25
is still under evaluation, only preliminary results will be
given.
J.D. Berst, G. Claus, C. Colledani
LEPSI (IN2P3-ULP), Strasbourg, France
HAL25 Block Diagram
Figure 1 shows the circuit block diagram. HAL25
contains 128 channels, each consisting of a preamplifier,
a shaper and a capacitor to store the voltage signal
proportional to the collected charge on a strip of a silicon
detector. The data is sampled by an external logic signal
and is read out at 10 MHz through an analogue
multiplexer. This voltage signal is converted to a
differential current signal by a differential linearised
transconductance output buffer. The chip is
programmable via the JTAG protocol which allows:
• to set up a programmable bias generator which tunes
the parameter of the analogue chains;
• to check analogue behaviour of the chip by injecting
adjustable charges to the inputs of selected channels
with a programmable pulse generator ;
• to perform the boundary scan.
AIN
AIN
CMOS Sig.
LVDS Sig.
Analogue Sig.
127
P
U
L
S
E
R
E
G
0
P
U
L
S
E
G
E
N
BIAS
PULSE
PULSE
DAC
127
|
|
|
ANALOGUE CHANNELS
|
|
|
0
A
N
A
M
U
X
127
P
O
W
E
R
O
N
R
E
G
BIAS GENERATORS
BIAS DAC
JTAG CONTROLER
0
127
R
E
A
D
O
U
T
R
E
G
0
TEMPO
Current
Output
Buffer
OUTBUF
CTRL
BYPASS BSR ID STATUS POWER_ENA TOKEN_ENA
PULSE
ID
GNDREF
PWRSTB
TRSTB
TCK
TDI
TMS
TDO
HOLD
Fig. 1 HAL25 block diagram
Table 1 shows the main specifications
Specification
Input range ± 13 MIPs
ENC ≤ 400 e -
Readout rate 10 MHz
Power ≤ 1mW / Channel
Tuneable Shaping Time 1.4 µs to 2.2 µs
Single power supply 0 – 2.5 V
TK_IN
FSTRB
+
-
RCLK
TK_OUT
A
N
_
O
U
T

I. Preamplifier
The preamplifier is a charge amplifier made from a
single-ended cascode amplifier with an NMOS input
transistor dimensioned to meet the noise specification.
The additional bias branch is used to increase the current
in the input transistor [3]. Figure 2 shows the preamplifier
schematic.
IN
Cf
Fig. 2. Preamplifier schematic
The advantages of the circuit compared to a conventional
folded cascode structure are as follows:
• A 2.5 V single power supply voltage which
simplifies power supply circuit. This is a strong
requirement from the ALICE experiment.
• The drain current of the input transistor which is the
sum of the current flowing in both bias branches.
This improves power efficiency.
Simulation shows that preamplifier has a gain of 10
mV/MIP (24000 e - ) and a power consumption of 225 µW.
II. Shaper
The ALICE experiment needs a front-end circuit having a
very large dynamic range (±13 MIPs) with a good
linearity and a shaping time adjustable from 1.4 to 2.2 µs.
A conventional shaper using a transistor as a feedback
resistor (Fig. 3a) cannot satisfy the required dynamic and
the linearity range. A linearised source degenerated
differential pair (Fig. 3b) is used as an active feedback
resistor. The details of the shaper are shown in figure 4.
Cf
Cc
Hold
IN OUT
Gm V bias3
Cload
Fig. 3a. Shaper A Fig. 3b. Shaper B
The active feedback circuit is a linearized
transconductance amplifier with a very low
transconductance value built with the differential pair M1,
Vdd
gnd
VPRE
IN Cc
V offset
V bias1
V bias2
OUT
V bias4
G m
Cf
Hold
OUT
Cload
M2 transistors. Transistors M3, M4 are used for source
degeneration of the differential pair linearising its
transconductance. Transistors M5, M6 are current
sources. The M7 and M8 constitute the non-symmetrical
active load of the differential pair. The transconductance
value of the feedback circuit depends on the
transconductance of M1, M2 and the value of
conductance gDS of the transistors M3, M4 connected in
parallel [4]. Because the transconductance value of the
transistors M1 and M2 depends on the bias current, it is
easy to change the total transconductance of the circuit.
This means that the equivalent resistance, on the feedback
path, can be varied by changing the bias current. The
output DC level of the shaper is fixed by Vdc.
IN
V bias
V dc
Cc
M5 M6
M1
Vdd
M4
M3
M2
M7 M8
gnd
ISHA
Cf
Fig.4 Shaper schematic
OUT
Cload
The noise contribution from the active feedback depends
mainly on the bias current and the value of gm of M7. In
order to reduce the noise of the circuit, the following
points are taken into account:
• minimum bias current ;
• minimum gm of M7.
A PMOS inverter is chosen as an amplifier stage in the
shaper because it is the simplest way to meet the
specification of the very long peaking time. This
approach is a trade off between the values of the
capacitors and the gm of the amplifier. The coupling and
feedback capacitors are 3 pF and 0.6 pF, respectively.
The storage capacitor is 10 pF.
Another advantage of this shaper is that its DC output
level is adjustable via M1. It is possible to tune different
voltage values for positive and negative inputs in order to
increase dynamic range.
The shaper has a power consumption of 65 and 130 µW
corresponding to the shaping time of 2.2 µs and 1.4 µs
respectively. The total front-end gain is 35 mV/MIP in ±
13 MIPs range. A non linearity less than 3% is obtained
by simulation within ± 10 MIPs range. The simulated
ENC of the front-end circuit is :
ENC = 207 e - + 10 e - /pF for τs = 1.4 µs
ENC = 158 e - + 10 e - /pF for τs = 2.2 µs
Where τs is the peaking time.

The signal is sampled on the storage capacitor by an
external LVDS HOLD signal activated at τs with respect
to the peaking time.
III. Analogue Multiplexer
The analogue multiplexer is made of 128 intermediate
buffers, two 128 bits shift registers (POWERON,
READOUT) and two extra bits flip-flop cells (TEMPO)
(Fig. 1). The readout is performed by injecting a token
which is shifted through READOUT. TEMPO is used to
delay by two clock pulses the injected token (TK_IN) in
order to switch “ON” the first two intermediate buffers
before beginning the readout. POWERON controls the
power on and off of the intermediate buffers while
READOUT controls the serial data transfer.
Only 3 of 128 buffers are powered on at the same time
during the readout cycle. They are the buffer N
corresponding to the channel being read and two adjacent
buffers i.e. channels N-1 and N+1. At the same time the
buffer N-2 is switched off and the buffer N+2 is switched
on. This means only 4 buffers dissipate power during the
readout.
The out going token (TK_OUT signal) is picked up two
channels before the end of the readout of a chip in order
to allow a daisy chaining of several HAL25 circuits
without extra clock cycles. An asynchronous FAST
CLEAR signal can reset the token and abort the cycle at
any moment of the readout.
The multiplexer can be set by JTAG in order to test a
single channel. This test is called “transparent mode”.
With HOLD signal inactive, the analogue response of an
injected signal can be observed at the output of the chip.
IV. Differential Current Buffer
Figure 5 shows the three main parts of the analogue
output buffer:
• Single ended to differential voltage converter;
• Linearised transconductor;
• Output voltage reference controller.
From MUX
Vdc
V+
V-
Linearised
Transconductor
Readout
Vref
Vref
V level
control
Vref
On chip
Fig. 5. Output buffer block diagram
I+
I-
25 pF
200 Ω
25 pF
The current gain and the output DC level are adjustable
by the programmable bias generator. Analogue output of
several chips can be connected in parallel. Only the chip
selected to be read out drives the output lines. The
outputs of the remaining chips are in a high impedance
state. Non selected chips have their output buffers
powered off in order to reduce the total power
consumption. The voltage reference controller sets the
quiescent output level. This allows to use a simple
floating input differential buffer outside the chip to pick
up the signal.
a. Single ended to differential voltage converter
The single ended to differential voltage converter has a
unity gain. It is built with three operational amplifiers
and a resistive ladder. The common mode output signal of
this stage is clamped to the internal reference DC level,
Vdc, common to the shaper and the multiplexer.
b. Linearised transconductor
The linear transconductor is based on the differential pair
linearised by the cross-coupled quad cell [5].
OUT1
MP4
2.5
MN5
5
MN2
1
MP1
BIASP
(n+1)I DC
aIDC MC2 MC1
IN+
M6 M1 M2
M5
M3 M4 M7
IN-
1:n n:1
1:n n:1
aI DC
(n+1)I DC
MC3
BIASN
MN1
MN3 MN4
2:1 MC4
1:2
Fig. 6 Linearised transconductance
1
MP3
2.5
MP2
MN6
5
OUT2
The schematic of the transconductance element is shown
in Fig. 6. Transistors M1-M4 form the cross-coupled
quad cell, while M6 and M7 constitute the differential
pair. The bias current of the differential pair is delivered
by the cross-coupled quad cell through the M5 transistor
and the current source MC1. The bias current of the
differential pair has a quadratic dependence on the
differential input voltage. The output current presents a
linear dependence of the input signal by a careful choice
of the weighting factor n. The additional current gain is
achieved on the cascade of current mirrors MN1-MN2
with MP1-MP2 and MN3-MN4 and MP3-MP4. The
output has a gain of 175 µA/MIP at nominal bias.
c. Output voltage reference controller
The classical control of the quiescent output levels by a
common mode feedback circuitry with low pass signal
filtering was not possible because it has to be off when
the chip is not selected. Another solution, using a dummy
transconductance stage and a feed forward circuitry for
referencing the output of the buffer, was preferred (Fig.
7). Both inputs of the dummy transconductor are fed with
the common mode signal and resulting not balanced
output signal is assumed to be the same for the main
circuitry. The output of the dummy element is balanced
by comparing its voltage level to the reference signal in

the error amplifier. As a result, a balanced voltage equal
to the reference value Vref is established at the output of
the dummy transconductor. The both outputs of main
transconductor are forced to the same value through
current mirrors. This design is potentially sensitive to
mismatches, thus special care was taken at the layout
level. An eventual mismatch in the output voltage
quiescent level can be adjusted by changing Vref.
Dummy
Transconductor
Vdc
B2
B1
1 1 1 1
Iref
Vref
Iref/2
I+
V+
I-
Linearised
Transconductor
V-
1 1 1 1
Fig. 7. Quiescent output level controller
V. Bias Generators and Current Reference
The bias generators provide DC currents and voltages to
bias accurately all the analogue parts. They consist of
nine 8 bit DACs. Each DAC is made of a JTAG register,
current sources and when necessary a current to voltage
converters. The JTAG register consists of a shift register
and a shadow register designed with a majority voting
logic approach in order to prevent Single Event Upset
(SEU).
In the HAL25 chip, an internal current source provides
current reference to the bias generators. It is designed to
be insensitive to a +/- 8% power supply variation. To
prevent poly-silicon resistor value variation (+/- 20%) due
to the process, the reference is adjustable by JTAG in 5
steps from -15% to +15% around nominal value.
VI. Test Pulse Generator
This feature can test analogue channels by injecting
adjustable charge pulses. The dynamic range for test
pulse is more than +/-15 MIPs, enough to test the full
dynamic range of analogue channels. A programmable
number of channels can be tested together.
VII. JTAG Controller
The control interface of HAL25 complies with the JTAG
IEEE 1149.1 standard. It allows the access to the registers
in the chip, especially for setting the bias and switching
between the running and the test modes. These modes are
the pulse test, the transparent test and the boundary scan
of the pads involved in the readout.
After reset of the controller, the circuit is in the bypass
state. For JTAG this means that serial data can skip the
circuit with one extra JTAG clock cycle per bypassed
circuit. For the readout part the token passes directly from
the previous to the next HAL25. An ID number can be
read from the chip by setting 4 input pads.
HAL25 Power Consumption
Three types of power consumption can be calculated:
• Power consumption per channel during acquisition:
P (no read out) = 355 µW (τs =1.4 µs)
P (no read out) = 290 µW (τs = 2.2 µs)
• Power consumption per channel during readout:
P (read out) = 750 µW (τs =1.4 µs)
P (read out) = 680 µW (τs = 2.2 µs)
• Mean power consumption per channel for a read out
cycle of 1 ms:
= 360 µW (τs =1.4 µs)
= 265 µW (τs = 2.2 µs)
HAL25 Layout
Fig. 8. HAL25
Circuit Evaluation
The HAL25 has an area of 3.65 x
11.90 mm 2 (Fig. 8). The process
has 1 poly and 3 metal layers. The
enclosed gate geometry with guard
ring technique was used in the
layout to prevent post-irradiation
leakage currents in NMOS channel
transistors.
The I/O pad sizes and placement
pitches were designed to be
directly compatible with the
existing Tape Automated Bonding
(TAB) technique. All the pads
except the power supply pads are
protected with diodes. Pads used
by the JTAG protocol are CMOS
while the readout control pads
comply with the LVDS standard.
Evaluation of HAL25 is underway. Several chips have
been tested on a probe station. Correct functionality of the
chip has been verified.
Figure 9 shows output stream from channel 1 to channel
128. A 1 MIP signal injected on one channel shows up
clearly after the average channel pedestals have been
subtracted.

Fig. 9 Output stream
Figure 10 shows analogue pulse shapes at output buffer as
a function of the injected charges.
output diff HAL25 (V)
0.8
0.6
0.4
0.2
0
0 5 10 15 20
-0.2
-0.4
-0.6
-0.8
From +/- 2 to +/- 14 MIPs
time (µs)
Fig. 10 Output shapes
A good linearity (

Abstract
The front−end system of the Silicon Drift Detectors
(SDDs) of the ALICE experiment is made of two ASICs. The
first chip performs the preamplification, temporary analogue
storage and analogue−to−digital conversion of the detector
signals. The second chip is a digital buffer that allows for a
significant reduction of the connections from the front−end
module to the outside world.
In this paper the results achieved on the first complete
prototype of the front−end system for the SDDs of ALICE
are presented.
I. Introduction
Silicon drift detectors provide xy coordinates of the
crossing particles with a spatial precision of the order of 30
µm, as well as a charge resolution such that the dE/dx is
dominated by Landau fluctuation. The detector is hexagon−
shaped with a total area of 72.5x87.6 mm 2 and an active area
of 70.2x75.3 mm 2 . It is divided into two 35 mm drift regions.
At the end of each drift region 256 anodes collect the charge.
The pitch of the anodes is 294 µm.[1][2]
Each anode has to be readout with a sampling frequency
of 40 MS/s. The number of samples to be taken per event
must cover the whole drift time, which is around 6 µs,
therefore a number of 256 samples has been chosen. The
total amount of data for each half−detector (corresponding to
one drift region) is 64 kSamples.
The basic idea behind our readout scheme is to convert
the samples into a digital format as soon as possible. Due to
the tight requirements in term of material and also the small
space available on the support structures ( ladders ) it would
be extremely difficult to transmit analogue data outside the
detectors at the required speed.
Owing to the low power budget ( 5 mW/channel ) it is
not possible to have a 40 MS/s A/D converter for each
channel, therefore a different approach has been adopted.
The signal from the detector is continuously amplified and
Test results of the front−end system
for the silicon drift detectors of ALICE
G.Mazza 1 , A.Rivetti 2 , G.Anelli 3 , M.I.Martinez 1,4 , F.Rotondo 1 ,
F.Tosello 1 , R.Wheadon 1
for the ALICE Collaboration
1 INFN Sezione di Torino, via P.Giuria 1 10125 Torino, Italy
2 Dip. di Fisica Sperimentale dell’Universita‘ di Torino, via P.Giuria 1 10125 Torino, Italy
3 CERN, 1211 Geneva 23, Switzerland
4 CINVESTAV, Mexico City, Mexico
mazza@to.infn.it
rivetti@to.infn.it
sampled on an 256−cells analogue memory at 40 MS/s.
When the trigger signal is received the analogue memory
stops the write phase and moves to the read phase where its
samples are converted by a slower A/D converter. This of
course introduces some dead time since during the
conversion the system is not sampling the detector signal.
The maximum allowed dead time is 1 ms/event. A
reasonable value for the settling time of the analogue
memory is 500 ns and a 2 MS/s ADC every two channels is
also acceptable in term of area and power consumption. With
those values the dead time is 512 µs, a factor of two below
the requirement.
DCS
Voltage regulators
& LVDS tx/rx
AMBRA
PASCAL
Figure 1 : SDD readout scheme
Silicon Drift Detectors
A schematic view of the readout architecture is shown in
Figure 1.
In order to further decrease the number of cables from the
front end system a digital multi−event buffer is placed close
to the front−end chip. The data from the A/D converter are
first quickly stored into a digital event buffer over a wide bus
and then sent outside the detector area over a single 8−bit
bus for each front−end board.
The introduction of the event buffers introduces an
additional dead time; however, it has been calculated that
with 4 buffers the dead time due to event buffer overflow is
only 0.04%.
...
CARLOS
GOL
laser
Low voltage boards
Front−end boards End ladder board

II. The front−end ASICs
The front−end system is based on two ASICs, named
PASCAL and AMBRA.
PASCAL can be divided in three parts : 64
preamplification and fast analogue storage channels, 32
successive approximation A/D converters (each ADC is
shared between two analogue memory channels) and a logic
control unit that provides the basic control signals for the
analogue memory and the converter.
The present prototype is half sized : 32 input channels
with preamplifier and 256 cells analogue memory are
connected to 16 A/D converters. A scheme of the prototype
is shown in Figure 2.
Preamplifier + buffer
Figure 2 : PASCAL scheme
Control Unit
Analogue memory
The preamplifier is based on the standard charge
amplifier plus shaper configuration and provides a gain of
around 35 mV/fC with a peaking time of 40 ns. The
preamplifier is DC coupled with the detector; baseline
variations and detector leakage currents are compensated via
a low frequency feedback around the second stage. The
amplifier is buffered with a class−AB output stage in order to
be able to drive the analogue memory with a low power
consumption.[3]
The analogue memory is an array of 256x32 switched
capacitor cells controlled via a shift register. The cells can be
written at 40 MHz and read out at 2 MHz. The architecture is
such that the voltage across the capacitor (and not the
charge) is written and read; therefore the sensitivity to the
absolute value of the capacitors and to the timing is greatly
reduced.[5]
The 10−bit A/D converter is based on the successive
approximation principle; a scaled array of switched
capacitors provides both the DAC and the subtraction
functions, and a three−stage offset compensated comparator
is used to check if the switched capacitor array output is
positive or negative and to drive the successive
approximation register that, in turn, controls the DAC. The
successive approximation architecture is a good compromise
between speed and low power consumption; it requires no
operational amplifiers and only one zero crossing
comparator. The conversion speed is one clock cycle per
bit.[6]
SAR
SAR
SAR
FF
FF
FF
A/D converter
MUX
Two calibration lines, connected to the even and odd
channel inputs via a 180 fF capacitor, provide the capability
of testing the circuit without the detector.
The prototype has been designed in a commercial 0.25
µm CMOS technology with radiation tolerant layout
techniques. The chip size is 7x6 mm 2 .
AMBRA provides 4 level of event buffering. Each buffer
has a size of 16 kbytes and is based on static RAM in order to
increase the SEU resistance and to avoid the refresh
circuitry. The control unit provides buffer management,
controls the operations of PASCAL and provides the front−
end interface to the rest of the system. The present prototype
has only 2 event buffers and can work up to 50 MHz. [4]
The prototype has been designed in Alcatel 0.35 µm
technology with standard layout. The chip size is 4.4x3.8
mm 2 . 89% of the core area is occupied by the two memory
buffers.
The PASCAL−AMBRA system operates as follows :
when AMBRA receveis the trigger signal it sends an SoP
(Start of oPeration) command to PASCAL. PASCAL stops
the sampling of the detector outputs and starts the readout of
the analogue memory and the A/D conversion. When the first
sample of the 32 channels has been converted, a write_req
(write request) signal is sent to AMBRA which in turn, if a
buffer is available, replies with a write_ack (write
acknowledge ) and starts the data acquisition. The sequence
continues for the other samples of the analogue memory until
AMBRA sends an EoP (End of oPeration ) command, then
PASCAL returns to the acquisition phase. The EoP
command can be issued for two reasons : all the 256 cells
have been readout, or an abort signal has been received. The
latter indicates that the trigger signal, which is generated
from the level−0 ALICE trigger, has not been confirmed by
the higher level triggers. Since the reject probability can be
very high (it can reach 99.8% in Pb−Pb interactions) it is
very important to stop as soon as possible the conversion and
restart the acquisition.
write_req
write_ack
data_in
Event Buffer
data_out
Write Counter A
Read Counter
Write Unit Control Unit Read Unit
Figure 3 : AMBRA scheme
Event Buffer
B
data_write
data_stop
trig_busy
trig_abort
As soon as an event buffer is full, AMBRA starts the
transmission of the data. The data_write command is used to
indicate that there are valid data on the output bus. This
signal remains high as long as the data are transmitted. A
data_end signal remains high for one clock cycle in
correspondance of the last byte. It is possible to suspend the
data transmission via the data_stop command.

III. Test results of the front−end circuit
The two prototypes have been evaluated together on a
test board.
The inputs have been provided via the calibration lines
while the outputs have been readout via a logic state
analyzer. A data pattern generator has been used to provide
the clock and the other digital control signals to the two
chips.
The two prototypes have also been tested connected to a
detector in a test beam at CERN PS. Data analysis is in a
preliminary stage; therefore in this paper we discuss only the
lab measurement performed on the system.
Figure 4 shows a typical output from a 4 fC charge signal
from the calibration lines. Even with a δ−like pulse at least 4
samples are significantly above the noise in the time
direction. For a particle crossing the detector far from the
anodes a slower signal is obtained and more samples can be
above the noise floor; on the other hand, since the total
charge does not change, the signal to noise ratio on the
individual sample is worse.
ADC counts
Figure 5 shows the output code against the input charge
for the 32 channels of a chip. It can be seen that the dynamic
range is well above the required 32 fC.
900
800
700
600
500
400
300
200
100
0
150
100
50
0
0 10 20 30 40 50 60
Cell number
Figure 4 : Typical output from a 4 fC input signal
Output code vs. input charge ch 0
0 3 5 8 10 13 15 18 20 23 25 28 30 33
Figure 5 : Dynamic range
Figure 6 shows the deviation of the curve of Figure 5
from linear fit. The non−linearity is less than 0.8% over the
whole dynamic range and it is mainly related to the
saturation of the preamplifier at the highest part of the range.
ch 1
ch 2
ch 3
ch 4
ch 5
ch 6
ch 7
ch 8
ch 9
ch 10
ch 11
ch 12
ch 13
ch 14
ch 15
ch 16
ch 17
ch 18
ch 19
ch 20
ch 21
ch 22
ch 23
ch 24
ch 25
ch 26
ch 27
ch 28
ch 29
ch 30
ch 31
Another source of non−linearity is the voltage dependance of
the memory capacitors, again in the highest part of the range.
20
10
0
−10
Deviation from linear fit
−20
0 5 10 15 20 25 30
Figure 6 : Linearity
Figure 7 shows the gain variation across channels of 5
different chips. The number of tested chip is too small to
have a significant statistic; however, from these results the
variation between channels of the same chip is of the order
of few percent while the chip to chip variation is of the order
of 10−15%.
A small slope of the gain distribution across the channels
of the same chip can be identified. This slope is due to a
voltage drop on the power and reference lines across the
chip. With a proper sizing of these critical lines it will be
probably possible to recover some of the gain variation in the
final version of the chip.
30.0
29.0
28.0
27.0
26.0
25.0
24.0
23.0
22.0
21.0
20.0
0 3 5 8 10 13 15 18 20 23 25 28 30
Figure 7 : Gain
Gain ( counts/fC )
chip 0
chip 1
chip 3
chip 4
chip 5
Noise measurements give an rms noise below 2 counts,
which corresponds to around 400 e − . This number is slightly
above the requirements and comes essentially from the
coupling between the analogue part and the digital one at the
substrate level and/or at the board level ( the measured noise
of the preamplifier alone is less that 180 e − ). A better
grounding scheme is under study for the final version of the
chip and for the final board design.
The measurements give less than 5 and around 10 mW per
channel for average and peak power consumption,

espectively. These numbers fulfill the ALICE SDD
requirements.
Another important aspect is the amplifier recovery time
from saturation. In the ALICE environment very high signals
(up to 400 fC) are possible. Despite these signals are not of
concern for the data analysis, it is important that the
preamplifier does not remain "hanged" for milliseconds.
Tests show a recovery time of 350 ns for a 100 fC signal.
This time rises with higher signals and saturates at 500 ns for
signals above 200 fC. These very high signals are very rare,
therefore this recovery time is acceptable.
IV. Radiation tolerance and technology issues
The drift detectors and the front−end electronics in the
ALICE environment will have to survive to a quite low, but
not negligible, level of radiation. The foreseen dose for 10
years of operation is around 20 krds. This value is at the limit
of what a modern standard technology can accept, therefore
the choice between a standard and a radiation hard
technology was not straightforward.
200
175
150
125
100
75
50
25
0
Supply current vs dose
0 25 50 75 100 125 150 175 200 225 250 275 300 325
Figure 8 : AMBRA irradiation test results : supply current
(mA) vs dose (krds)
While radiation hard technologies remain two or three
generation behind the standard technologies, a new approach
based on specific layout techniques and deep submicron
standard technologies has been carried out by the RD49
research program at CERN. The effectivness of this approach
has been demostrated up to 30 Mrds. Its main disadvantage is
some area penalty, expecially in the digital design, if
compared with a standard deep submicron technology.
However, the digital radiation tolerant cells are still smaller
when compared with the standard cells of a radiation hard
processes.
Owing to the low radiation level in ALICE the first
PASCAL prototype has been designed in a commercial 0.25
µm with radiation tolerant techniques while the first AMBRA
has been designed in Alcatel 0.35 µm technology with the
commercial standard cell library.
The reason of this choice was that, on one side, analogue
circuits are more sensitive to leakage currents and threshold
variation (expecially the analogue memory, where leakage
currents would destroy the cells content ) while, on the other
hand, digital circuits are more robust but the area penalty due
to the radiation tolerant techniques is much more significant.
Radiation tests for total dose effects have shown very
small variations in the parameters of the PASCAL chip up to
30 Mrds. The irradiated AMBRA chips show full
functionality up to 1 Mrd; unfortunately the leakage current
shows a dramatic increase at 50−60 krds ( Figure 8 ) and,
despite this effect does not affect the chip functionality, it
will lead to an unacceptable power consumption.
For this and other reasons (cost, phasing out of the 0.35
µm process by Alcatel ) the final version of the AMBRA chip
will use the 0.25 µm technology radiation tolerant standard
cells library.
V. Conclusions
A 32 channels prototype and a 2 event−buffer prototype
of the two ASICs for the readout of the ALICE SDDs have
been designed and tested. The 2−chip system shows an
excellent linearity and a good gain uniformity. The system
fulfills the ALICE requirements and shows the effectivness
of the chosen architecture.
A minor problem related to voltage drop in the internal
power supply and reference lines has been identified and will
be corrected in the final version. Owing to the fact that the
threshold for the leakage current in the 0.35 µm process used
for AMBRA is too close to the foreseen radiation level, the
final version of both chips will be designed using the
radiation tolerant approach.
VI. References
[1] ALICE Technical Design Report, CERN/LHCC 99−
12
[2] ALICE Technical Proposal, CERN/LHCC 95−71
[3] A.Rivetti et al, "A mixed−signal ASIC for the silicon
drift detectors of the ALICE experiment in a 0.25 µm
CMOS" CERN−2000−010, CERN−LHCC−2000−041, pp.
142−146
[4] G.Mazza et al, "Test Results of the ALICE SDD
Electronic Readout Prototypes", CERN−2000−010, CERN−
LHCC−2000−041, pp. 147−151,
[5] G.Anelli et al., "A Large Dynamic Range Radiation−
Tolerant Analog Memory in a Quarter−Micron CMOS
Technology", IEEE Trans. on Nucl. Sci., vol.48, pp. 435−
439, Jun 2001
[6] A.Rivetti et al., "A Low−Power 10 bit ADC in a 0.25
µm CMOS: Design Consideration and Test Results",
presented at Nucl. Sc. Symposium and Med. Imaging
Conference, Lyon, Oct 2000

Irradiation and SPS Beam Tests of the Alice1LHCb Pixel Chip
J.J. van Hunen, G. Anelli, M. Burns, K. Banicz, M. Campbell, P. Chochula, R. Dinapoli, S. Easo, F.
Formenti, M. Girone, T. Gys, A. Kluge, M. Morel, P. Riedler, W. Snoeys, G. Stefanini, K. Wyllie
European Organization for Nuclear Research (CERN), 1211 Geneva 23, Switzerland
jeroen.van.hunen@cern.ch
A. Jusko, M. Krivda, M. Luptak
Slovak Academy of Sciences, Watsonova 47, SK-043 53, Kosice
M. Caselle, R. Caliandro, D. Elia,V. Manzari, V. Lenti
Università degli Studi di Bari, Via Amendola, 173, I-70126, Bari
F. Riggi
Università di Catania, Corso Italia, 57, I-95129, Catania
F. Antinori
Università degli Studi di Padova , Via F. Marzolo, 8, I-35131, Padova
F. Meddi
Università di Roma I, La Sapienza, Piazzale Aldo Moro, 2, I-00185, Roma
Abstract
The Alice1LHCb front-end chip [1,2] has been designed
for the ALICE pixel and the LHCb RICH detectors. It is
fabricated in a commercial 0.25 µm CMOS technology, with
special design techniques to obtain radiation tolerance. The
chip has been irradiated with low energy protons and heavy
ions, to determine the cross-section for Single Event Upsets
(SEU), and with X-rays to evaluate the sensitivity to total
ionising dose. We report the results of those measurements.
We also report preliminary results of measurements done with
150 GeV pions at the CERN SPS.
(For the ALICE collaboration)
I. INTRODUCTION
The aim of ALICE (A Large Ion Collider Experiment) is
to study strongly interacting matter that is created by heavy
ion collisions at LHC. The experiment is designed to handle
particle multiplicities as high as 8000 per unit of rapidity at
central rapidity. Therefore the innermost cylindrical layers
need to be two-dimensional tracking detectors with a high
granularity. The two innermost layers are made of ladders of
hybrid silicon pixel assemblies (readout chips bump-bonded
to silicon sensors) at radii 3.9 and 7.6 cm, respectively. A
large part of the momentum region of interest for ALICE
consists of hadrons with an energy of several hundred MeV,
and the momentum and vertex resolution are dominated by
multiple scattering. Therefore the amount of material in the
acceptance must be minimised. A development is under way

to thin the pixel chip wafers, after bump deposition, to less
300µm. Sensor wafers of thickness 150 to 200 µm can be
obtained in production. For the RICH detector of LHCb, the
assembly will be encapsulated in a vacuum tube for the
detection of the photoelectrons, and the thickness of the
assembly is not relevant.
Since the pixel layers are very close to the interaction
region, they need to be resistant to Total Ionising Dose (TID)
effects and to Single Event Effects (SEE). The expected TID
after 10 years of operation at LHC is 500 Krad. The effects of
the TID are well known; threshold shifts, leakage currents,
and charge mobility reduction as a result of trapped charge
and interface states [3]. The SEEs originate from a large
amount of charge being deposited by a single event, usually
through an interaction of the incident hadron with the silicon
atoms. This may lead to [3]:
• Single Event Upset (SEU): a change of a logic level
(0→1 or 1→0)
• Single Event Latch-up (SEL): a high power supply
current
• Single Event Gate Rupture (SEGR): a breakdown of a
transistor gate.
In this paper we focus on the application in ALICE, and
describe tests of the Alice1LHCb pixel chip and of pixel
single assembly prototypes, consisting of 300 µm p +
n sensors
bump-bonded to pixel chips from wafers of 750 µm thickness.
The pixel front-end chip (Alice1LHCb) contains 8192
readout cells of each 425×50 µm 2 and measures 13.5×15.8
mm 2
. It is designed in a 0.25 µm CMOS technology, where
the radiation tolerance has been enhanced by the
implementation of guard-rings and by using NMOS
transistors in an enclosed geometry [4]. The measures that
have been taken to reduce the effects of the TID also reduce
the probability for Single Event Latch-up. Implementing
redundancy for the memory cells in the chip reduces the
effects of Single Event Upsets.
In this document, we outline first the performance of the
chip, particularly in what concerns minimum threshold and
noise, as derived from laboratory measurements. We then
report the results of irradiation with x-rays (TID) as well as
with heavy ions and 60MeV protons (SEE). Preliminary
results of the measurements with singles assemblies in a 150
GeV pion beam at the CERN SPS are presented.
II. MINIMUM THRESHOLD AND NOISE
Each pixel contains a capacitor for testing purposes. A
voltage step over this capacitor injects a certain amount of
charge into each pixel. For different settings of the global
threshold the efficiency is measured as a function of the size
of the applied voltage step. This gives a calibration of the
global threshold in mV as is shown in figure 1. Using the
known value of the test capacitor, and additionally by using
the X-rays of a Fe 55
source (which give rise to around 1600
electrons in 300 µm silicon) it is found that a threshold of 20
mV equals a threshold of about 1000 electrons.
Threshold (mV)
80
70
60
50
40
30
20
10
0
Figure 1: The measured average threshold of the pixel chip as a
function of the setting of the DAC that is used to set the global
threshold. A threshold of 20 mV is equivalent to about 1000
electrons.
The minimum threshold at which the chip can be operated
is around 800 electrons. From the measurement of the
efficiency as a function of the size of the voltage step, the
noise (σ noise ) in each pixel was determined to be less than 110
Equivalent Noise Charge (4σ noise ≈ difference in threshold
when the efficiency is 2% and 98%, respectively). A pixel
assembly has only a slightly higher noise (< 120 ENC), while
the minimum threshold is around 1000 electrons.
III. SINGLE EVENT EFFECTS
A hadron with an energy of several GeV does not deposit
enough charge through direct ionisation to create a Single
Event Effect. However, it may interact elastically and inelastically
with the silicon atoms in the pixel chip. The recoils
and fragments will deposit a large amount of charge in the
chip, and may therefore lead to single event effects. Both
SEGR and SEL are generally not observed for circuits
designed in 0.25 µm with special layout techniques. For
SEGR the electric fields are not high enough, while the
implementation of guard rings prevent SEL to occur. During
measurements on the Alice1LHCb chip neither SEGR nor
SEL were observed. The SEU do however occur, and we have
to measure the cross-section for a SEU in the memory cells of
the pixel chip. The cross-section is determined in two
different ways. Firstly heavy ions with an LET (Linear
Energy Transfer) between 6 and 120 MeVmg -1
Minimum
threshold
170 180 190 200 210 220 230
Global threshold (DAC units)
cm 2
were used,
since these deposit a large amount of charge and the
probability for SEU is large. From these results the SEU
cross-section for other hadrons can be calculated. Secondly
the measurements were repeated with 60 MeV protons.

A. Measurements with Ions
In order to vary the value of the LET, different ions can be
chosen (Xe 26+ , Ar 8+ , Ne 4+ , Kr 17+ ). Additionally the chip can be
tilted with respect to the propagation direction of the ions to
increase the path length of the ion through the sensitive part of
the memory cells and therefore increase the amount of
deposited charge in this region. To determine the number of
SEUs the chip is loaded with a test pattern. After irradiation
for a certain amount of time (several seconds or minutes) the
memory cells are read-out and compared with the loaded test
pattern. All differences are attributed to SEUs. It was verified
that there are no SEUs without irradiation. The results of the
measurements are shown in figure 2. For two pixel chips the
SEU cross-section was measured. The results of these two
chips are in good agreement. When the LET is larger than 6.3
MeVmg -1 cm 2 , enough charge is deposited to create a SEU.
Increasing the LET increases the SEU cross-section. At high
values of the LET (> 20 MeVmg -1 cm 2 ) the cross-section
increases slowly with increasing LET due to the fact that
enough charge is available for a SEU, while only the
probability to deposit the charge in the sensitive region of a
memory cell remains. The curve in the figure represents the
Weibull equation [5] that is used to estimate the cross-section
for SEU in the case when the chip is irradiated with hadrons
instead of ions. The data presented in figure 2 were used to
determine the SEU cross-section for protons with an energy of
60 MeV, leading to 9×10 -16
cm 2
[5].
SEU Cross Section (cm 2 )
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
1.E-11
chip 43
chip 72
Weibull
0 20 40 60 80 100 120
LET (MeV mg -1 cm 2 )
Figure 2: The SEU cross-section as a function of the LET (Linear
Energy Transfer) for 2 different pixel chips. The curve represents the
Weibull equation and is used for the interpretation of the data
A. Measurements with 60 MeV Protons
The SEU cross-section measurements were repeated with
60 MeV protons in order to confirm the heavy ion results.
During 7 hours the chip was irradiated, leading to a fluency of
6.4 10 12 cm -2 . The results of the measurements are summarised
in table 1. In total 84 SEUs were found, while 41296 memory
cells were irradiated. The SEU cross-section for 60 MeV
protons equals thus 3×10 -16 cm 2 . This result is in good
agreement with the result for 60 MeV protons as calculated
from the heavy ion data (9×10 -16 cm 2 ).
Table 1: Number of SEUs and the SEU cross-section per memory
cell when irradiating with 60MeV protons.
Fluency
(cm -2 )
# SEUs
-
# irradiated cells
-
Cross-section
(cm 2
)
6.4 10 12 84 41296 3.2 10 -16
In order to obtain an estimate for the number of SEUs in the
entire pixel detector of ALICE, the calculations which were
performed for the CMS experiment [5] are scaled with the
particle flux as expected for ALICE and with the SEU crosssection
as measured with 60 MeV protons. The neutron flux
in central Pb-Pb collisions at ALICE equals 6.4×10 4
cm -2
s -1
for the first pixel detector layer. The hadron flux originating
from the Pb-Pb interactions was simulated using GEANT [7]
and equals 2×10 5 cm -2 s -1 . For the entire ALICE pixel detector
these particle fluxes would result in an upset rate of less than
1 bit of one digital to analogue converter every 10 hours. It
can therefore be concluded that SEU do not form a threat for
continuous operation of the ALICE pixel detector. As
mentioned earlier, SEGR and SEL have not been observed
during the measurements.
IV. TOTAL IONIZING DOSE EFFECTS
The effect of the TID was studied by irradiating the pixel
chip with 10 KeV X-rays from a SEIFERT X-ray generator,
which is available at CERN. Due to the large size of the chip
the irradiation had to be performed on two different positions
on the chip in order to cover all the digital to analogue
converters (DAC) located at the bottom of the chip, as well as
a significant part of the pixel arrays. The bottom left and right
(see figure 3) were irradiated to 12 Mrad at a rate of 0.6
Mrad/hour. Due to some overlap of the 2 irradiated regions
some parts receive as much as 24 Mrad. The top part of the
chip, i.e. rows 0-50, was not irradiated. Figure 3 shows the
threshold map of the chip after irradiation. The determination
of the threshold of each pixel is explained in section I.
Row
0
-50
-100
-150
-200
-250
0 5 10 15 20 25 30
Column
30
25
20
15
10
5
0
Threshold (mV)
Figure 3: The threshold distribution of the chip after irradiation of
the bottom right and left part of the chip to 12 Mrad.
[6]

After the irradiation the output voltages of the DACs of the
chip were up to 40 mV lower than before due to the threshold
shift in the PMOS transistors [8]. For this reason the chip was
equipped with a reference DAC, which serves as reference for
the other DACs in the chip. After the irradiation the voltage
supplied by this reference DAC needed to be increased by 40
mV in order to obtain results as good as the results of the
pixel chip before irradiation. There is no significant difference
between the threshold map determined before and after the
irradiation. The threshold for rows 0-50 is slightly higher, due
to the fact that the reference DAC, as well as a two other
DACs that control the digital part of the chip, were optimised
for the irradiated pixels.
After the irradiation the minimum threshold at which the chip
can operate is unchanged (800 electrons), while the noise per
pixel is still below 110 ENC. The power consumption of the
chip is unaffected by the irradiation and is shown as a
function of the total dose in figure 4.
Current (mA)
400
300
200
100
0
Digital Supply Analogue Supply
0.01 0.1 1 10 100
Irradiated Dose (Mrad)
Figure 4: The current of the digital and analogue power supplies as a
function of the TID.
V. TEST WITH 150 GEV PIONS AT CERN
A number of assemblies were tested in a beam of 150 GeV
pions at the CERN SPS. Two different configurations were
used. First, one pixel assembly was tested together with
scintillators for triggering and efficiency determination (with
an uncertainty of about 1%). At a later stage more pixel
assemblies were added to be able to perform tracking and
therefore improve the efficiency determination. The results
given in this paper concern mainly the first configuration. The
results from the extended configuration will be presented at a
later stage. The efficiency was determined using four
scintillators which select a small area, several mm 2 , of the
chip. An efficiency of 100% means that for each trigger there
was a hit in our pixel assembly. First the efficiency was
studied as a function of the strobe delay.
Efficiency (%)
120
100
80
60
40
20
0
-150 -100 -50 0 50 100 150
Strobe Delay (ns)
Figure 5: Efficiency as a function of strobe delay
Threshold=215
Threshold=200
The strobe is generated by the scintillator trigger signal
and its duration could be varied for testing purposes from 100
to 200 ns. At the CERN SPS the particle bunches arrive
randomly with respect to the 10 MHz clock of the chip. The
strobe width was set at 120 ns, and the trigger delay was
changed in steps of 8 ns. The results are shown in figure 5.
Two different threshold settings were used, namely 200 and
215 which correspond to 2000 and 1000 electrons,
respectively. The shape of the curve is as expected, and
indicates a plateau of 20 ns. With a strobe width of 100 ns
there would no plateau. There is no significant difference
between the results for the different thresholds.
Furthermore the efficiency was studied as a function of the
detector bias voltage. The results are shown in figure 6. These
results show that the detector can be operated with full
efficiency, over a large voltage range.
Efficiency (%)
120
100
80
60
40
20
0
Threshold=175
Threshold=215
0 10 20 30 40 50 60 70 80 90
Detector Bias [V]
Figure 6: The efficiency as a function of detector bias voltage. The
curve with a threshold setting of 175 (approximately 4000 electrons)
is shown for illustration purposes only, the chip will be operated at a
threshold setting around 215, corresponding to 1000 electrons.
Additionally the efficiency and cluster size was studied as
a function of the incident angle of the particles. For this
purpose the assembly could be tilted using a remote controlled

stepping motor. The results are shown in figures 7 and 8 for
different thresholds. As mentioned before the chip will be
operated with threshold settings in the range of 200-215,
corresponding to 2000 to 1000 electrons, respectively.
6
5
4
3
2
1
0
Figure 7: Cluster size as a function of the angle of the assembly. At
zero degrees the substrate is perpendicular to the particle beam.
The data in figure 7 show an increase of the cluster size with
increasing assembly angle. For very high thresholds the
cluster size decreases as result of the decreasing charge
deposition per cell when more cells are traversed. There is
again no significant difference between the results with a
threshold setting of 2000 and 1000 electrons.
Efficiency (%)
Cluster Size
120
100
80
60
40
20
0
Threshold=175
Threshold=200
Threshold=215
0 5 10 15 20 25 30 35 40 45 50
Track Angle (Deg)
45 Deg
0 Deg
25 50 75 100 125 150 175 200
Global threshold (DAC units)
Figure 8: The efficiency as a function of the threshold setting for
zero and 45 degrees.
The data in figure 8 show that the efficiency in the operation
range (threshold setting between 200 and 215) is high, also at
a substrate angle of 45 degrees.
VI. CONCLUSIONS
The Alice1LHCb pixel chip was successfully tested for
total ionising dose and single event effects. It has been shown
that the performance of the chip does not degrade after a total
ionising dose of 12 Mrad. No SEGR and SEL were detected,
while the SEU cross-section was determined to be small,
(3×10 -16 cm 2 ). This cross-section would lead to the upset of 1
bit per 10 hours, of one digital analogue converter of one chip
for the complete ALICE pixel detector. The tests with 150
GeV pions show that the pixel assemblies perform well
concerning the timing resolution, the efficiency and the
cluster size.
VII. REFERENCES
1. K. Wyllie et al., “A pixel readout chip for tracking at
ALICE and particle identification at LHCb”, Proceedings of
the Fifth Workshop on Electronics for LHC Experiments,
Snowmass, Colorado, September 1999.
2. R. Dinapoli et al., “An analog front-end in standard 0.25µm
CMOS for silicon pixel detectors in ALICE and LHCb",
Proceedings of the Sixth Workshop on Electronics for LHC
Experiments, Krakow, Poland, September 2000.
3. F. Faccio, “COTS for the LHC radiation environment: the
rules of the game", Proceedings of the Sixth Workshop on
Electronics for LHC Experiments, Krakow, Poland,
September 2000.
4. G. Anelli et al., “Radiation Tolerant VLSI Circuits in
Standard Deep Submicron CMOS technologies for the LHC
Experiments: Practical Design Aspects”, IEEE Transactions
on Nuclear Science, Vol. 46, No. 6 (1999) 1690-1696.
5. M. Huhtinen and F. Faccio, “Computational method to
estimate Single Event Upset rates in an accelerator
environment”, NIM A 450 (2000) 155-172. F. Faccio: private
communication.
6. A. Morsch: private communication.
http://AliSoft.cern.ch/offline/
7. A. Badalà et al., "Geant Simulation of the Radiation Dose
for the Inner Tracking System of the ALICE Detector",
ALICE Internal Note, ALICE/ITS 99-01.
8. F. Faccio et al., “Total Dose and Single Event Effects
(SEE) in a 0.25 µm CMOS Technology”, Proceedings of the
Fourth Workshop on Electronics for LHC Experiments,
Rome, September 1998.
VIII. ACKNOWLEDGEMENT
We thankfully acknowledge two CERN summer students,
S. Kapusta and J. Mercado-Perez, who have been involved in
different aspects of the testing. Further more we would like to
thank F. Faccio for his advice and assistance with the
measurements of the SEU cross-section.

Progress in Development of the Analogue Read-Out Chip for Silicon Strip Detector
Modules for LHC Experiments.
J. Kaplon 1 (e-mail: Jan.Kaplon@cern.ch), E. Chesi 1 , J.A. Clark 2 , W. Dabrowski 3 , D. Ferrere 2 , C. Lacasta 4 ,
J. Lozano J. 1 , S. Roe 1 , A. Rudge 1 , R. Szczygiel 1,5 , P. Weilhammer 1 , A. Zsenei 2
1
CERN, 1211 Geneva 23, Switzerland
2
University of Geneva, Switzerland
3
Faculty of Physics and Nuclear Techniques, UMM, Krakow, Poland
4
IFIC, Valencia, Spain
5
INP, Krakow, Poland
Abstract
We present a new version of the 128-channel analogue
front-end chip SCTA128VG for readout of silicon strip
detectors. Following the early prototype developed in DMILL
technology we have elaborated a design with the main goal of
improving its robustness and radiation hardness. The
improvements implemented in the new design are based on
experience gained in DMILL technology while developing the
binary readout chip for the ATLAS Semiconductor Tracker.
The architecture of the chip and critical design issues are
discussed. The analogue performance of the chip before and
after the gamma irradiation is presented. The performance of
modules built of ATLAS baseline detectors read out by six
SCTA chips is briefly demonstrated. The performance of a
test system for wafer screening of the SCTA chips is
presented including some preliminary results.
I. INTRODUCTION
The SCTA chip has been developed from the beginning as
a backup option to the binary read-out chip ABCD [1] for the
ATLAS SCT, using the DMILL technology. Currently, SCTA
chips have found the following applications:
• Read-out of silicon strip detectors for the NA60
experiment.
• Production quality assurance testing of silicon strip
detectors for ATLAS SCT.
• Fast read-out chip for diamond strip detectors.
• Read-out of silicon pad detectors for HPD applications.
A first prototype of the SCTA chip [2] was designed and
manufactured in the early stages of stabilisation of the
DMILL process. In the meantime the DMILL process has
been improved and stabilised. The development of the ABCD
binary readout chip helped us to understand better and
quantify various aspects of the process like matching,
parasitic couplings through the substrate and radiation effects.
The conclusions from the work on the ABCD chip have been
implemented in the new design of the SCTA128VG chip with
the main goal of improving robustness and radiation hardness
of the new chip.
II. CHIP ARCHITECTURE
Figure 1 shows the block diagram of the SCTA128VG
chip. The SCTA128VG chip is designed to meet all basic
requirements of a silicon strip tracker for LHC experiments. It
comprises five basic blocks: front-end amplifiers, analogue
pipeline (ADB), control logic including derandomizing FIFO,
command decoder and output multiplexer. The detailed
architecture of the front-end amplifier based on a bipolar input
device has been discussed already in [3]. An advantage of this
solution, compared to a pure CMOS version being developed
for the CMS tracker [4], is significantly lower current in the
input transistors required for achieving comparable noise
levels.
Input pads from the detector
x 128
FE
DAC’s
& CAL
logic
128x128 ADB
ADB control logic
Command decoder
x 128
analogue
MUX
Readout
logic
Figure 1: Block diagram of the SCTA128VG chip.
The front-end circuit is a fast transimpedance amplifier
followed by an integrator, providing semi-gaussian shaping
with a peaking time of 16 to 24ns. This dispersion of peaking
times is for the full range of expected process variations. The
design peaking time for nominal values of resistors and
capacitors is 20ns. The peak values are sampled at 40 MHz
rate and stored in the 128-cell deep analogue pipeline (ADB).
Upon arrival of the trigger the analogue data from the
corresponding time slot in the ADB are sampled in the buffer
and sent out through the analogue multiplexer. The gain of the
front-end amplifier is about 50mV/fC. The gain of the output

uffer of the analogue multiplexer is in the range of 0.8[V/V].
Therefore the final gain of the whole read-out chain is roughly
40mV/fC. All figures in the paper showing the gain and
linearity refer to the full processing chain (front-end amplifier,
ADB and output multiplexer). The front-end circuit is
designed in such a way that it can be used with either polarity
of the input signal, however the full read-out chain (NMOS
switches in the analogue pipeline, output multiplexer) is
optimised for p-side strips. The dynamic range of the
amplifier is designed for 12fC input, which together with the
gain of 40mV/fC gives a full swing at the output of the chip in
the range of 500mV. The current in the input transistor is
controlled by an internal DAC and can be set within the range
0 to 320uA. This allows one to optimise the noise according
to the actual detector capacitance.
III. RESULTS FROM THE EVALUATION OF A
SINGLE CHIP
The basic parameters of the chip have been evaluated
using internal calibration circuitry. The internal calibration
circuitry provides a well-defined voltage step at the input of
the calibration capacitors connected to every channel. Since
the characteristic of the calibration DAC can be measured, the
inaccuracy of the electronic calibration is related only to the
deviation of calibration capacitors from the nominal value and
the mismatch of the resistors used for scaling of the
calibration voltage. For comparison with the results obtained
with the electronic calibration, the absolute calibration of the
chip in the set-up with a silicon pad detector and beta source
is also presented.
A. Basic parameters of the Front-End
amplifier.
The basic parameters of the amplifier are speed, gain,
linearity and noise performance. The pulse shape at the output
of the front-end amplifier has been evaluated by scanning the
delay of the calibration signal with respect to the 40MHzsampling
clock for the analogue pipeline. In order to
normalise the results to the absolute time scale the
measurement has been repeated for two consecutive values of
the trigger delay.
Amplitude [mV]
SCTA128VG, single channel
180
160
140
120
100
80
60
40
20
25ns
0
0 10 20 30 40 50
Calibration strobe delay (x1.17ns)
Figure 2: Pulse shapes at the output of the multiplexer obtained from
the delay scan for two consecutive trigger delays.
Figure 2 shows the example of the measurement done for
one typical channel of the SCTA128VG chip. The injected
charge was 3.5fC. The obtained 18ns peaking time is in the
expected range given by the technology process variation. The
distribution of the peaking times in one SCTA128VG chip is
shown in Figure 3. The RMS spread of the peaking times is in
the range of 0.6%.
Entries
30
25
20
15
10
5
SCTA128VG, Peaking Time distribution
PkTSpread
Nent = 128
Mean = 18.44
RMS = 0.1244
0
17 17.5 18 18.5 19 19.5 20
Peaking Time [ns]
Figure 3: Distribution of the channel peaking times in one
SCTA128VG chip. The RMS spread is about 0.6%.
Figure 4 shows the gain linearity for one channel in the
chip. The gain is 43mV/fC and a good linearity is kept up to
16fC, which is the maximum range of the calibration DAC.
The overall distribution of the gain in one SCTA128VG chip
is presented in Figure 5. The RMS spread of the gains is about
2%, which is very good for tracking applications.
Output [mV]
SCTA128VG, single channel
700
600
500
400
300
200
100
Offset = -3.1 mV
Gain = 43.3 mV/fC
0
0 2 4 6 8 10 12 14 16
Input charge [fC]
Figure 4: Gain linearity for one channel of the SCTA128VG chip.
The noise measurements have been done for the whole
chip working with a 40MHz clock sampling data to analogue
memory and for random readout of ADB cells. In this way
any pedestal variation between ADB cells will contribute to
the overall noise performance of the chip. The distributions of
the ENC in one particular SCTA128VG chip for various input
transistor biases are shown in Figure 6. For input transistor
current ranging from 120µA up to 300µA the equivalent noise
charge varies between 480 and 630e-. The RMS spreads of
the ENC are in the range of 2 to 2.5%.
In order to verify the measurements with the internal
calibration signal a set-up with a detector and beta source has
been built. The SCTA128VG chip was connected to a
SINTEF Silicon pad detector of thickness of 530µm. The
detector bias voltage was set to 400V, 265V above the
depletion voltage, providing sufficiently fast charge collection
from the pads. The SCTA128VG chip was operating under
nominal bias condition with input transistor current set to
200µA. Figure 7 shows the signal distribution from the
detector exposed to beta particles. The gain extracted from

this signal distribution, assuming the Landau peak
corresponding to a charge of 5.7fC, is in the order of
44.2mV/fC. This has to be compared with the gain of
45.6mV/fC measured with internal calibration circuitry for the
channel connected to a detector pad. A minor difference of
3% between the results of two measurements could be
explained not only by the tolerance of the calibration
capacitors and inaccuracy of the band-gap reference but also
by a ballistic deficit for charge collected from the detector.
The difference between charge collection time from the
detector and charge injected from the calibration circuitry is in
the range of 5ns, which is not negligible for a front-end
amplifier with 18ns peaking time.
Entries
25
20
15
10
5
SCTA128VG, Gain distribution
GainSpread
Nent = 128
Mean = 44.87
RMS = 0.9146
0
30 35 40 45 50 55 60
Gain [mV/fC]
Figure 5: Distribution of channel gains in one SCTA128VG chip.
The RMS spread is in the range of 2%.
Entries
60
50
40
30
20
10
SCTA128VG, ENC
Iinput = 120uA -> ENC = 485e-
Iinput = 200uA -> ENC = 560e-
Iinput = 300uA -> ENC = 630e-
0
400 450 500 550 600 650 700 750 800
ENC [e-]
Figure 6: Distribution of ENC in a single SCTA128VG chip for
different bias of the input transistor. The spread of the equivalent
noise charge is in the range of 2 to 2.5%.
Entries
350
300
250
200
150
100
50
SCTA128VG
Peak = 252 mV
0
0 100 200 300 400 500 600 700 800
Signal [mV]
Figure 7: Histogram of data taken with silicon pad detector and a
106 Ru beta source showing Landau peak at 252mV.
B. Performance of the analogue memory
(ADB).
One of the most important parameters of the analogue
memory, which will define its contribution to the overall
noise performance of the chip, is the uniformity of the DC
offsets (pedestals) between ADB cells.
Pedestal [mV]
SCTA128VG, ADB Pedestal Map
320
300
280
260
240
220
200
180
160
120
100
Cell Number
80
60
40
20
0
0
20
40
60
80
100 120
Channel Number
Figure 8: ADB pedestal map in one SCTA128VG chip.
Entries
SCTA128VG, Distribution of ADB Pedestal Spread
35
ADBSpread
30
Nent = 128
Mean = 1.11
25
RMS = 0.1765
20
15
10
5
0
-0.5 0 0.5 1 1.5 2 2.5 3
Pedestal RMS [mV]
Figure 9: Distribution of ADB pedestal spread in each channel, in
one SCTA128VG chip. The 1.1mV mean value of the distribution is
equivalent to 150e- ENC.
Figure 8 shows the pedestal map of 128x128 ADB cells in
one chip. From the presented figure one can extract the ADB
cell-to-cell variation for all channels of the chip. The
distribution of the ADB pedestal spreads for all channels in
one particular chip is shown in Figure 9. The 1.1mV mean
value of the distribution is equivalent to 150e- ENC of extra,
non-correlated contribution to the noise generated by the
front-end. For a low value of the input current and a low
detector capacitance the additional contribution is about 4%.
For higher detector capacitance this contribution becomes
negligible. One can notice the high channel-to-channel
uniformity of the analogue memory confirmed by a narrow
(RMS ~ 10%) distribution of the pedestal spreads (Figure 9).
IV. PERFORMANCE OF THE SCTA128VG CHIP
CONNECTED TO A SILICON STRIP DETECTOR.
To demonstrate the performance of the SCTA128VG chip
reading out long silicon strip detectors, several modules
equipped with 12.8cm ATLAS SCT type sensors have been
built. A 6 chip ceramic hybrid holding two silicon detectors of
size 6.3 x 6.4cm is shown in Figure 10.

The noise performance of the SCTA128VG chip may be
optimised according to the detector capacitance by adjustment
of the current in the input transistor. Figure 11 shows the
results of noise measurements of one module with SCTA
chips connected to 6.4 and 12.8cm long silicon strip detectors.
Figure 10: Photograph of 6chip, 12.8cm strip silicon detector
(ATLAS type) module.
The measurement has been done for various bias
conditions of the input transistor. It should be noted that the
noise performance of the chip connected to 12.8cm strips
could be improved by increasing the bias current of the input
transistor. The reduction of ENC is relatively smaller for high
current since the noise of the base spread resistance and the
noise of the strip resistance become limiting factors.
ENC [e-]
2200
2000
1800
1600
1400
1200
1000
800
600
400
SCTA128VG detector module
Ibias = 120uA ENC ~ 485 + 72e-/pF
Ibias = 200uA ENC ~ 560 + 62e-/pF
Ibias = 300uA ENC ~ 630 + 55e-/pF
6.4cm strips 12.8cm strips
0 5 10 15 20
Cinput [pF]
Figure 11: ENC for SCTA128VG chips connected to various length
silicon strip detectors.
Entries
3000
2500
2000
1500
1000
500
Signal/Noise SCT module (12.8cm.)
Peak = 11.4 ± 0.01
Sigma = 1.296
0
0 5 10 15 20 25 30 35 40 45 50
Signal/Noise
Figure 12: Signal over Noise histogram of data taken with 100GeV
pion beam for the 12.8cm detector module. Measurement done for
200µA input transistor current.
Figure 12 shows a Signal-over-Noise distribution of data
taken with 100GeV pion beam for the SCTA chip connected
to a 12.8cm long and 280µm thick silicon strip detector. The
SCTA128VG chip was operated under nominal bias
conditions with input transistor current set to 200µA. The
ENC of 1850e- extracted from Figure 12 has to be compared
with an ENC of 1700e- measured with the internal calibration
circuit. The difference may be explained by the ballistic
deficit and charge loss due to the inter-strip capacitances of
the detector.
V. RESULTS OF THE X-RAY IRRADIATION
Although the SCTA128VG chip is realised in DMILL
radiation hard technology the radiation effects in the devices
cannot be ignored. The critical issue is the noise in the frontend
amplifier. A second order effect is possible degradation of
matching which may affect the uniformity of the channels in
terms of gain, speed and the ADB performance.
Entries
70
60
50
40
30
20
10
SCTA128VG, ENC before & after irradiation
Before irradiation
ENC = 580e-
RMS = 24e-
After 10 MRad
ENC = 620e-
RMS = 25e-
0
400 500 600 700 800 900 1000
ENC [e-]
Figure 13: Distribution of ENC before and after 10Mrad. After
irradiation the ENC increases by about 6%. The measurement are
performed for 200µA input bias current.
The irradiations have been performed at CERN using a
facility providing 10keV energy X-Rays at two dose rates: 8
and 33kRad/min. No annealing has been applied. During the
irradiation we have evaluated the analogue parameters such as
gain, noise, peaking time, and ADB uniformity as well as
power consumption in the analogue and digital parts of the
circuit.
Entries
40
35
30
25
20
15
10
5
SCTA128VG, Gain before & after irradiation
Before irradiation
Gain = 44mV/fC
RMS = 0.9mV/fC
After 10 MRad
Gain = 41mV/fC
RMS = 1.2mV/fC
0
30 35 40 45 50 55 60
Gain [mV/fC]
Figure 14: Distribution of channel gains before and after 10Mrad.
After irradiation there is a noticeable drop of gain in the order of 7%,
and an increase of gain spread from 2 to 3%.
Figure 13 shows the distribution of ENC in one SCTA
chip before and after irradiation. The increase of parallel noise
due to the BJT beta degradation is as expected and could be
neglected in the case of a chip working on a detector module
when the serial noise due to the capacitive load is dominant.
Figure 14 shows the distribution of channel gains in the

SCTA128VG chip before and after irradiation. After
irradiation one can observe a 7% decrease of gain and an
increase of gain spread from 2 to 3%. The evolution of power
consumption during the irradiation is shown in Figure 15.
The small (8%) decrease in analogue power consumption
is due to the drift of the resistors in the internal band-gap
reference and could be compensated by a change of the bias
DAC setting. The peaking time and the uniformity of the
ADB pedestals were unaffected by the X-Ray irradiation.
Current [mA]
200
180
160
140
120
100
80
60
40
20
0
Power consumption vs total dose
Analogue power consumption
Digital power consumption
0 2 4 6 8 10
Dose [MRad]
Figure 15: Evolution of analogue and digital power consumption of
SCTA128VG chip during the X-Ray irradiation.
VI. WAFER SCREENING SYSTEM FOR
SCTA128VG CHIP.
In order to be able to qualify good dies a wafer screening
system has been developed. The system is based on an
automatic probe station with all movements programmed.
Using a standard probe card it was possible to test the SCTA
chips under nominal bias conditions and at full, 40MHz readout
speed. Results of all tests together with chip coordinates
are saved to file for off-line analysis. The presented system
provides the capability of evaluating all analogue parameters
like gain, noise, peaking time, ADB uniformity as well as chip
power consumption. The system enables one to do defect
analysis, which is a part of the design validation.
16
14
12
10
8
6
4
Wafer 8: Classification map
chips accepted
chips rejected
2
0
chips with one defect channel
0 2 4 6 8 10 12 14
Figure 16: Example of wafer map with chips classified according to
the number of defects.
Figure 16 shows an example of a typical wafer map with
SCTA128VG chips classified according to the number of
defects detected during analysis. The presented wafer shows
roughly 30% yield for perfect chips. The percentage of the
chips with single defects (channel gain out of specified 20%
range or single ADB pedestal out of the normal distribution)
was in the range of 15%. The SCTA chips with single defects
are usually used for the evaluation of the hybrids when we do
not require the 100% good channels as for the final detector
modules. Figure 17 shows the distribution of the chip gains on
one typical wafer. One can see good uniformity (in the range
of 5% RMS) of the mean value of the gains for SCTA128VG
chips over a whole wafer.
Gain [mV/fC]
50
40
30
20
10
0
16
14
12
10
Wafer 8: Gain
8
6
4
2
0
Figure 17: Distribution of the chip gains on a wafer.
0
2
4
6
8
10
VII. CONCLUSIONS
The SCTA128VG chip is an implementation of a full
analogue architecture satisfying the requirements of LHC
experiments. The analogue performance of the SCTA128VG
chip is adequate for the readout of LHC type Si strip detector
modules. Excellent uniformity of the analogue parameters on
the chip level as well as on the wafer level has been shown.
The results of the X-Ray irradiation show radiation hardness
of the SCTA128VG chip up to the ionising doses required by
LHC experiments. A system for wafer screening of the
SCTA128VG chip has been presented. It allows design
validation in terms of defect analysis as well as selection of
good dices to the users.
VIII. REFERENCES
[1] W. Dabrowski et al., Design and Performance of the
ABCD Chip for the Binary Readout of Silicon Strip
Detectors in the ATLAS Semiconductor Tracker. IEEE
Transactions on Nuclear Science, vol.47, no.6, pt.1, Dec.
2000, pp.1843-50.
[2] W. Dabrowski et al., Performance of a 128 Channel
Analogue Front-End Chip for Read-Out of Si Strip
Detector Modules for LHC Experiments. IEEE
Transactions on Nuclear Science, vol.47, no.4, pt.1, Aug.
2000, pp.1434-41.
[3] J. Kaplon et al., Analogue Readout Chip for Si Strip
Detector Modules for LHC Experiments. Sixth Workshop
on Electronics for LHC Experiments, Cracow, September
11-15, 2000, CERN/LHCC/2000-041.
[4] M. Raymond et al., The CMS Tracker APV25 0.25µm
CMOS Readout Chip. Sixth Workshop on Electronics for
LHC Experiments, Cracow, September 11-15, 2000,
CERN/LHCC/2000-041.
12
14

The ALICE on-detector pixel PILOT system - OPS
Kluge, A. 1 , Anelli, G. 1 , Antinori, F. 2 , Ban, J. 3 , Burns, M. 1 , Campbell, M. 1 , Chochula, P. 1, 4 ,
Dinapoli, R. 1 , Formenti, F. 1 ,van Hunen, J.J. 1 , Krivda, M. 3 , Luptak, M. 3 , Meddi, F. 5 ,
Morel, M. 1 , Riedler, P. 1 , Snoeys, W. 6 , Stefanini, G. 1 , Wyllie K. 1
1 CERN, 1211 Geneva 23, Switzerland
2 Istituto Nazionale di Fisica Nucleare, Sezione di Padova, I-35131 Padova, Italy
3 Institute of Experimental Physics, 04353 Kosice, Slovakia
4 Comenius University, 84215 Bratislava, Slovakia
5 Universita di Roma “La Sapienza, I-00185 Roma, Italy
6 on leave of absence from CERN, 1211 Geneva 23, Switzerland
Abstract
The on-detector electronics of the ALICE silicon pixel
detector (nearly 10 million pixels) consists of 1,200 readout
chips, bump-bonded to silicon sensors and mounted on the
front-end bus, and of 120 control (PILOT) chips, mounted on
a multi chip module (MCM) together with opto-electronic
transceivers. The environment of the pixel detector is such
that radiation tolerant components are required. The front-end
chips are all ASICs designed in a commercial 0.25-micron
CMOS technology using radiation hardening layout
techniques. An 800 Mbit/s Glink-compatible serializer and
laser diode driver, also designed in the same 0.25 micron
process, is used to transmit data over an optical fibre to the
control room where the actual data processing and event
building are performed. We describe the system and report on
the status of the PILOT system.
A. Detector
r/o
elec.
I. INTRODUCTION
pixel chip
2 ladders =
half stave
Figure 1: ALICE Silicon Pixel Detector
Two ladders (5 pixel chips each), mounted on a front-end
bus, constitute a half-stave. The complete detector consists of
120 half-staves on two layers, 40 half staves in the inner layer,
80 in the outer layer. The detector is divided into 10 sectors
(in φ-direction). Each sector comprises two staves in the inner
layer and four staves outer layer. Thus one detector sector
contains six staves. Fig. 1 illustrates the ALICE silicon pixel
detector. [1, 2]
B. Design considerations
Table 1 summarizes the main design parameters of the
readout system.
Table 1: System parameters
L1 latency 5.5 µs
L2 latency 100 µs
Max. L1 rate 1 kHz
Max. L2 rate 800 Hz
Radiation dose in 10 years < 500 krad
Neutron flux in 10 years 3 x 10 11 cm -2
Total number of pixels 9.8184 x 10 6
Occupancy < 2%
Although the L1 trigger rate and the L2 trigger rate are low
compared to other LHC experiments, the raw data flow yields
almost 1 GB/s.
The expected radiation dose and the neutron flux are at least
one magnitude of order lower compared to the ATLAS or
CMS experiments. However, commercial off-the-shelf
components can still not be used. Therefore, the ASICs have
been developed in a commercial 0.25-micron CMOS
technology using radiation hardening layout techniques [3].
Precautions have been undertaken to reduce malfunction due
to single event upset. A minimum of data processing is
performed on the detector, which subsequently simpifies
ASIC developments.
A. System overview
II. SYSTEM ARCHITECTURE
Fig. 2 shows a block diagram of the system electronics.
The 10 pixel chips of one half stave are controlled and read

out by one PILOT multi chip module (MCM). The PILOT
MCM transfers the data to the control room. In the control
room 20 9U-VME-based router cards, two for each detector
sector, receive the data. One router card contains six data
converter daughter boards, one for each half stave. The data
converters process the data and store the information in an
event memory. The router merges the hit data from 6 half
staves into one data block, processes the data and stores them
into a memory where the data wait to be transferred to the
ALICE data acquisition (DAQ) over the detector data link
DDL [4].
half stave 5
half stave 4 pilot MCM
half stave 3 pilot MCM
half stave 2
half stave 1
pilot MCM
pilot MCM
half stave 0 pilot MCM
pilot MCM
half stave 0
ixel chips
pixel
chips
half stave
sector 0 .. 19
pilot
chip
data converter 5
data converter 4
data converter 3
data converter 2
data converter 1
data converter 0
ALICE DAQ
router 0 .. 19
DDL
ALICE DAQ
detector
control room
pilot MCM
Glink
control
receive
Figure 2: System block diagram
pixel
pilot
core
pixel bus
data control
Figure 3: Read-out chain
pixel transmit
G-link
pixelcontrol
receive
router 0
data processing
data converter 5
data converter 4
data converter 3
data converter 2
data converter 1
data converter 0
link
receiver
control
transmit
0 data
encoding
opt.
link
opt.
links
link
receiver
pixelcontrol
transmit
router 0
data converter
pixel
converter
data processing
event
memory
converter and
control daughter card
L1, L2y, L2n,
testpulse, jtag
pixel
router
pilot MCM control room
B. PILOT logic and optical pixel transmitter
A. Kluge 28.8.01
Fig. 3 illustrates a block diagram of the read-out chain.
When the ALICE DAQ issues a L1 trigger signal, the pixel
router forwards the signal via the pixel control transmitter and
the pixel control receiver to the PILOT logic. The PILOT chip
asserts a strobe signal to all pixel chips [5], which stores the
delayed hit information into multi event buffers in the pixel
chips. Once a L2 accept signal (L2y) is asserted and
transmitted to the detector, the PILOT chip initiates the
readout procedure of the 10 pixel chips one after the other.
The 256 rows of 32 pixels of a pixel chip are presented
sequentially on a 32-bit bus. The read-out clock frequency is
10 MHz. As a result, the read-out of 10 chips takes about 256
µs.
clk10
clk40
cycle
event info
pixel data bus
data control
signal feedback
32 x 10 MHz
clk40
32
16
16
16
16
3
2
MUX 4:1
1
sel
0
cnt4
16 X 40 MHz
0 1 2 3 0 1 2 3 0 1
Figure 4: Transmission principle
The PILOT logic performs no data processing but directly
transmits data to the control room. This approach has several
advantages. The first is, that the on detector PILOT-ASIC
architecture is simple. Secondly, the system becomes more
reliable as the complex data processing units are accessible
during operation in the control room. Finally, if the detector
hit occupancy increases in the future, data compression
schemes can be adapted in the FPGA based control room
located electronics.
For the optical transmission of the data to the control room
the encoder-serializer gigabit optical link chip GOL [6] is
used. The GOL allows the transmission of 16 bit data words
every 25 ns resulting in an 800 Mbit/s data stream. The data
are encoded using the Glink [7] protocol. This chip has
already been developed at CERN.
The pixel data stream arrives from the pixel chips at the
PILOT chip on a 32-bit bus in 100 ns cycles. That means that
the transfer bandwidth of the GOL is twice as high as
required. The 100 ns pixel data cycle is split up into four 25
ns GOL transmission cycles. Fig. 4 shows the transmission
principle. In two consecutive GOL cycles, 16 bits of pixel
data are transmitted. The remaining two transmission cycles
are used to transmit data control and signal feedback signal
blocks. The control block contains information directly
related to the pixel hit data transmission, such as start and end
of transmission, error codes, but also event numbers. In the
signal feedback block, all trigger and configuration data sent
from the control room to the detector are sent back to the
router for error detection.
Upon receipt of a L2 reject (L2n) signal the corresponding
location in the multi event buffer in the pixel chips are cleared
and the PILOT initiates a short transmission sequence to
acknowledge the reception of the L2n signal.

C. Data converter
The serial-parallel converter receives the Glink data
stream and recovers the 40 MHz transmission clock using a
commercial component [8]. The implementation of the link
receiver is based on a commercial FPGA and storage devices.
Fig. 5 shows a block diagram of the data converter. The
received data is checked for format errors and zero
suppression is conducted before the data are loaded into a
FIFO. The expected occupancy of the detector will not exceed
2%. As a result, it is economic to encode the raw data format.
In the raw data format the position of a hit within a pixel row
is given by the position of logic ‘1’ within a 32-bit word. The
encoder transforms the hit position into a 5-bit word giving
the position as a binary number for each single hit and
attaches chip and row number to the data entry [9]. The output
data from the FIFO are encoded and stored in an event
memory in a data format complying with the ALICE DAQ
format [10]. There it waits until merged with the data from the
remaining five staves by the router electronics.
HDMP
1034 0 FIFO
Figure 5: Link receiver data converter
encode+
format
D. Pixel control transmitter and receiver
L1
L2y
L2n
test_pulse
reset
jtag signals
reset signals
pixelcontrol_receive
Figure 6: Pixel control block diagram
clk40
clock
data
pixelcontrol_transmit
RAM
L1
L2y
L2n
test_pulse
reset
jtag signals
reset signals
0 1 2 3 0 1 2 3 0
idle
L1, L2y,
L2n,reset,
reset_jtag
command
Jtag
Figure 7: Pixel control data format
tms tms tdi tdi
The pixel control transmitter and receivers are responsible
for the transmission of the trigger and configuration signals
from the control room to the detector. This includes the
following signals: L1, L2y, L2n trigger signals, reset signals,
a test pulse signal and JTAG signals.
The data must arrive at the detector in a 10 MHz binning,
since the on detector PILOT system clock frequency is 10
MHz. During data read-out of the detector the JTAG access
functionality is not required and vice versa. The link is
unidirectional since the return path for the JTAG system
(TDO) uses the Glink data link. The data protocol must be
simple in order to avoid complex recovery circuitry on the
detector in the PILOT chip. As a result, all commands must be
DC balanced. (The number of ‘1’s and ‘0’s in the command
code must be equal.)
The data transmission is performed using two optical
fibres, one carrying the 40 MHz clock and the other the actual
data.
The pixel control transmitter (see fig. 6) translates the
commands into a serial bit stream. A priority encoder selects
the transmitted signal in case two commands are active at the
same time. L1 is the only signal where the transmission
latency must be kept constant. Therefore, a L1 trigger
transmission must immediately be accepted by the pixel
control transmitter and, thus, has highest priority. A conflict
would arise if the transmitter were in the process of sending a
command at the same time as a L1 transmission request
arrives. In order to avoid this situation the L1 trigger signal
will always be delayed by the time duration, it takes to
serialize a command (200 ns). During this delay time, all
command transmissions are postponed to after the L1 signal
transmission. Thus, when the delayed L1 trigger signal arrives
at the transmitter, no other command can be in the
transmission pipeline.
Fig. 7 illustrates the data protocol. Four 40 MHz clock
cycles form a command cycle. At start-up 64 idle patterns are
sent to the receiver. The receiver synchronizes to this idle
pattern. Commands are always two transmit cycles (or eight
40 MHz cycles) long. The number of different commands
requires a two transmit cycle command length. After each
transmission of an idle word, a transmission command can
follow. Since the idle word is only 100 ns long, the
transmission of a command can be started in a 100 ns binning.
However, the duration of a command transmission is 200 ns
long [11].
E. Fast multiplicity
The pixel chips provide an analog fast multiplicity current
signal. This signal is proportional to the number of pixels
being hit. As it is a current signal, the sum of all 10 chips on a
half stave can be obtained by connecting the 10 fast
multiplicity outputs together. The use of this signal to
generate a multiplicity and vertex trigger for the ALICE
trigger system is currently under investigation [12].
For the read-out of this signal, two options exist. One
option is to use an A/D-converter and transmit the signal
using the PILOT system and the Glink interface. The other
option is to use an analog optical link [13] to transmit the
information independently from the digital data stream. The
draw back of the first option is the additional time delay when
inserting the signal into the Glink data stream, which prohibits
the use of the trigger signal in the L0 application in ALICE.
The disadvantage of the second option is the need of an
additional optical package. The available space for
components is very restricted, as described below.

III. PHYSICAL IMPLEMENTATION
A. Pixel bus and pixel extender
Fig. 8 shows the view from the side of the mechanical
assembly, fig. 9 from the top. On the bottom of fig. 8, a fibre
carbon structure and the cooling tube can be seen which holds
the detector components. The pixel chips and the sensor
ladders are bump-bonded and directly glued on top of the
fibre carbon structure. On top of the assembly the pixel bus is
glued. The pixel bus is an aluminium-based multi layer bus
structure, which provides both power and data to the chips.
The connections between the pixel bus and the ladder
assembly are made by wire bonds. Passive components are
soldered on top of the pixel bus. The PILOT MCM is attached
to the structure in a similar way. Two copper bus structures,
known as the pixel extenders, supply the pixel bus and the
PILOT MCM with power.
CAPACITOR
PIXEL BUS
DETECTOR
READOUT CHIP
Figure 8: Pixel bus and extender
15.5
13.9
13
R
EXTENDERS
Analogue Digital
PILOT PILOT
GOL
CARBON FIBER SUPPORT
ladder2 ladder1
C
C
Power
Pixel chip Pixel detector
12 mm
Pilot MCM
Opt
Receiver
Trans
Al pixel carrier
OPTICAL LINKS
COOLING TUBE
Flexible Extender
70.72 mm 70.72 mm
1000mm
Figure 9: Pixel bus and extender (top view)
B. PILOT MCM
Data
Controls
Clk
Cu extender 1&2
Fig. 10 shows a diagram of the PILOT MCM. Due to
mechanical constraints, the MCM must not exceed 50 mm in
length and 12 mm in width. Components can only be placed
in a 5 mm-wide corridor in the middle of the MCM. A special
optical package is being developed, which is less than 1.4 mm
in height and houses two pin diodes and a laser diode [14].
Due to the height constraints for components, all chips
will be directly glued and bonded onto the MCM without a
package. Fig. 10 shows the GOL, which must be in close
vicinity to the optical package in order to keep the 800 Mbit/s
transmission line short. The distance from the connector to the
GOL is less critical, as only 40 Mbit/s signals are connected
to the optical package. On the very left, the analog PILOT
chip is shown. It is an auxiliary chip for the pixel chips and
provides bias voltages.
2 mm
mm
.4 mm
IL
na
ILOT
igital
Figure 10: PILOT MCM
C. PILOT chip
0 mm
OL
aser +
Pin diodes
The PILOT chip layout can be seen in fig. 11. The chip
size of 4 x 6 mm is determined by the number of I/O pins. The
chip has been produced in a 0.25 micron CMOS technology
using special layout techniques to enhance radiation tolerance
[3]. A comprehensive description of the PILOT chip can be
found in [11, 15].
Figure 11: PILOT layout
D. GOL chip
The GOL chip has already been tested and its performance
is described in [6].
E. Single event upset
Although the expected neutron fluence is comparatively
low, design precautions have been undertaken to prevent
single event upsets from causing malfunctions. In both the
PILOT chip and the GOL chip, all digital logic has been
triplicated and all outputs are the result of majority voting.
Internal state machines are made in a self-recovering manner.
Fig. 12 shows the principle. In case a flip-flop in a state
machine changes its state due to a single event upset, the
correct state will be recovered using the state of the remaining
two state machines.

input
logic
block a
logic
block b
logic
block c
state
machine
_a
state
machine
_b
state
machine
_c
internal
voting gat e
Figure 12: SEU recovery architecture
F. PILOT system test board
output
voting
gate
output
A PILOT system test board has been developed. The
board is used to test the functionality of the PILOT chip. The
PILOT chip is directly glued and bonded onto the board. An
FPGA [16] provides the test patterns to the PILOT. The
FPGA contains functional models of the pixel control
transmitter, the ten pixel chips and the link receiver. The
outputs of the PILOT chip are stored in a 128k x 48 static
memory bank and can also be read back by the FPGA for
comparison with the model. Access to the board, the FPGA
and the RAM bank is via a JTAG port. Fig. 13 shows the
block diagram of the board. In a second phase, the test will
include the PILOT chip, the GOL transmitter chip and the
commercial Glink receiver chip [8]. Again, the output of the
data chain can be read into the FPGA and the memory bank.
In a third phase the pixel bus and its 10 pixel chips will be
connected to the board. This feature will allow qualification
of the entire data read-out chain.
pilot_in
clk_opt_in
data_opt_in
data_opt_out
clk_opt_out
clk40
50
pilot
50 44
clk_opt
da ta_
opt
FPGA
JTAG
Figure 13: PILOT system test board
IV. STATUS
GOL
tx
RAM
128k 48
Glink
rx
HP10 32
The GOL chip has already been tested and its performance
met the specifications. Another prototype run was launched in
order to enhance functionality for another application [6].
The PILOT chip has been received from the foundry [11,
15].
Tests of a prototype pixel bus have been started [17].
The link receiver [10, 11] and the router designs are in
progress.
V. CONCLUSION
All chip developments have been conducted using a 0.25micron
CMOS technology and layout techniques in order to
cope with the radiation dose. The on detector PILOT system
performs no data processing nor requires on-chip memory.
The entire data stream can be moved off the detector using the
encoder and serializer chip GOL. This has the advantage that
the on-detector electronics is independent from the detector
occupancy and future upgrades can be performed on the
FPGA based electronics located in the control room. The
transmission of data is performed using optical links. The
number of electrical read-out components is minimized, as the
available space for physical implementation is very limited.
VI. REFERENCES
[1] M. Burns et al., The ALICE Silicon Pixel
Detector Readout System, 6 th Workshop on
Electronics for LHC Experiments,
CERN/LHCC/2000-041, 25 October 2000, 105.
[2] ALICE collaboration, Inner Tracking System
Technical Design Report, CERN/LHCC 99 –12,
June 18, 1999.
[3] F. Faccio et al., Total dose and single event
effects (SEE) in a 0.25 µm CMOS technology,
LEB98, INFN Rome, 21-25 September 1998,
CERN/LHCC/98-36, October 30, 1998, 105-113.
[4] György Rubin, Pierre Vande Vyvre, The ALICE
Detector Data Link Project, LEB98, INFN Rome,
21-25 September 1998, CERN/LHCC/98-36.
[5] K. Wyllie et al., A pixel readout chip for tracking
at ALICE and particle identification at LHCb,
Fifth workshop on electronics for LHC
Experiments, CERN/LHCC/99-33, 29 October
1999, 93
[6] P. Moreira et al., G-Link and Gigabit Ethernet
Compliant Serializer for LHC Data Transmission,
N S S 2 0 0 0
P. Moreira et al., A 1.25 Gbit/s Serializer for
LHC Data and Trigger Optical links, Fifth
workshop on electronics for LHC Experiments,
CERN/LHCC/99-33, 29 October 1999, 194.
[7] R, Walker et al., A Two-Chip 1.5 GBd Serial
Link Interface, IEEE Journal of solid state
circuits, Vol. 27, No. 12, December 1992,
Agilent Technologies, Low Cost Gigabit Rate
Transmit/ Receive Chip Set with TTL I/Os,
HDMP-1022, HDMP-1024,

http://www.semiconductor.agilent.com, 5966-
1183E(11/99).
[8] Agilent Technologies, Agilent HDMP-1032,
HDMP-1034, Transmitter/Receiver Chip Set,
http://www.semiconductor.agilent.com, 5968-
5909E(2/00).
[9] T. Grassi, Development of the digital read-out
system for the CERN Alice pixel detector,
UNIVERSITY OF PADOVA – Department of
Electronics and Computer Engineering (DEI),
Doctoral Thesis, December 31, 1999.
[10] A. Kluge, Raw data format of one SPD sector, to
be submitted as ALICE note,
http://home.cern.ch/akluge/work/alice/spd/spd.ht
ml.
[11] A. Kluge, Specifications of the on detector pixel
PILOT system OPS, Design Review Document,
to be submitted as ALICE note,
http://home.cern.ch/akluge/work/alice/spd/spd.ht
ml.
[12] F. Meddi, Hardware implementation of the
multiplicity and primary vertex triggers from the
pixel detector, CERN, August 27, 2001, Draft, to
be submitted as ALICE note.
[13] V. Arbet-Engels et al., “Analogue optical links of
the CMS tracker readout system, Nucl. Instrum.
Methods Phys. Res., A 409, pp 634-638, 1998.
[14] Private communication with G. Stefanini.
[15] A. Kluge, The ALICE pixel PILOT chip, Design
Review document, March 15, 2001, to be
submitted as ALICE note,
http://home.cern.ch/akluge/work/alice/spd/spd.ht
ml.
[16] Xilinx, XC2S200-PQ208.
[17] Morel M., The ALICE pixel detector bus,
http://home.cern.ch/Morel/documents/pixel_carri
er.pdf
http://home.cern.ch/Morel/alice.htm

A Study of Thermal Cycling and Radiation Effects
on Indium and Solder Bump Bonding
S. Cihangir, J. A. Appel, D. Christian, G. Chiodoni, F. Reygadas and S. Kwan
Fermi National Accelerator Laboratory *
Batavia, IL 60510, USA
C. Newsom
The University of Iowa
Iowa City, IA 52242, USA
Email address of the corresponding author: selcuk@fnal.gov
Abstract
The BTeV hybrid pixel detector is constructed of readout
chips and sensor arrays which are developed separately. The
detector is assembled by flip-chip mating of the two parts.
This method requires the availability of highly reliable,
reasonably low cost fine-pitch flip-chip attachment
technology.
We have tested the quality of two bump-bonding
technologies; indium bumps (by Advanced Interconnect
Technology Ltd. (AIT) of Hong Kong) and fluxless solder
bumps (by MCNC in North Carolina, USA). The results have
been presented elsewhere[1]. In this paper we describe tests
we performed to further evaluate these technologies. We
subjected 15 indium bump-bonded and 15 fluxless solder
bump-bonded dummy detectors through a thermal cycle and
then a dose of radiation to observe the effects of cooling,
heating and radiation on bump-bonds.
I. TESTED COMPONENTS
The dummy detectors were single flip-chip assembles of
daisy-chained bumps. Measured channels were composed of
30 micron pitch indium bumps, a chain of 28 to 32; and 50
micron pitch solder bumps, a chain of 14 to 16. Figure 1
shows a schematic layout of a portion (8 channels) of an AIT
dummy detector. Each chain was connected to pads on each
end over which we measured the resistance to characterize the
channel. AIT detectors had 200 channels each, MCNC
detectors had 195 channels each.
II. THERMAL CYCLING AND RADIATION
Each detector was measured first for continuity before
thermal cycling and radiation. These measurements were
compared to the electrical resistance measurements done
about 12 months ago[1] to yield an understanding of “time
effect” on the bump-bonds. Then they were cooled to -10 o C in
* Work supported by U. S. Department of Energy under contract no. DE-AC02-76CH0300.
a freezer in an air tight container for 144 hours. Subsequent
measurements were compared to the measurements done
before cooling to understand any “cooling effect” on the
bump-bonds. This was followed by heating the detectors to
100 o C in vacuum for 48 hours. The detectors were measured
after heating and compared to the measurements done after
cooling to yield an understanding of any “heating effect”.
Finally, the dummy detectors were shipped to the University
of Iowa in three shipments to be radiated by a Cs-137 gamma
source to 13 MRad and measured again to understand any
“radiation effect”. A randomly selected sample of detectors in
each shipment was not radiated to give us an indication if the
detectors were affected during shipment. This way we
eliminated one of the shipments from consideration.
Figure 1: AIT Dummy Detector Bump Daisy Chain.
III. RESULTS
The effects we studied manifested themselves as large
increases in resistance on the channels measured. These
occurrences are described below.
A. Thermal Cycling
We categorize the problem occurrences after each step of
the thermal cycling as follows:

1. Indium Bumps:
Occurrence A: A good channel (1-2 Ohms average
resistance per bump) develops a high resistance (5-10
KOhms per bump) in 12 months.
Occurrence B: A good channel develops a high
resistance after cooling.
Occurrence C: A good channel develops a high
resistance after heating.
In most cases the high resistance is accompanied by
an average capacitance per bump of 2-10 picofarads.
2. Solder Bumps:
Occurrence A: A good channel (1-2 Ohms average
resistance per bump) is broken (a resistance of larger
than 20 MOhms) in 12 months.
Occurrence B: Cooling breaks a good channel.
Occurrence C: Heating breaks a good channel.
Table 1 shows the distribution of the occurrences in
indium bump detectors. No entry means no problem. The last
column indicates the number of channels having an open or
high resistance problem before the thermal cycling. There is a
correlation between the occurrences of new problems and the
original existence of problems. For instance, detectors E11
and E20 which originally had many problematic channels
developed more new problematic channels over the thermal
cycling.
Table 1: Indium Bump Problem Occurrence Distribution
Det-ID
E2
Occur-A Occur-B Occur-C Orig-Bad
E3
E4
1
E5
E8
1
E11 14 1 37
E13 1 6
E14 2
E15
E16
2 4
E20
E22
20 2 8 74
E23
E24
E25
1
Table 2 shows the distribution of the occurrences in solder
bump detectors. No entry means no problem. The last column
indicates the number of channels having a problem before the
thermal cycling. Here we also see a correlation between the
occurrences of new problems and the existence of problems
before the thermal cycling. For instance, detectors MCNC-24
and MCNC-27 which originally had many problematic
channels developed more new problematic channels over the
thermal cycling.
Table 2: Solder Bump Problem Occurrence Distribution
Det-ID Occur-A Occur-B Occur-C Orig-Bad
MCNC-10
MCNC-11
MCNC-12
MCNC-18
MCNC-19
7 1 1
MCNC-24 6 3 6 5
MCNC-27 1 7 12
MCNC-44 1
MCNC-50 1 1
MCNC-55 4 2
MCNC-59
MCNC-75
1
MCNC-76
MCNC-81
3
MCNC-86 4 1 5 3
We calculated the occurrences per bump based on these
observations and summarize the results in Table 3. The
correlation mentioned above can be a reason to exclude
detectors E11, E20, MCNC-24 and MCNC-27 from
consideration for the effects of thermal cycling. If we do that,
we then calculate the occurrence rates per bump as shown in
Table 4.
Table 3: Rate of Occurrences (per bump)
Occurrence Indium Bumps Solder Bumps
A 2.1 x 10 -4 4.0 x 10 -4
B 2.2 x 10 -5 1.4 x 10 -4
C 2.1 x 10 -4 6.3 x 10 -4
Table 4: Rate of Occurrences (per bump) without Problematic
Detectors
Occurrence Indium Bumps Solder Bumps
A 3.3 x 10 -5 2.6 x 10 -4
B 2.2 x 10 -5 4.6 x 10 -5
C 2.5 x 10 -5 3.3 x 10 -4
B. Radiation
On indium bump detectors, after the radiation we observed
that almost every first channel in groups of four channels (see
Figure 1) was at high resistance. The group of four channels is
a geometrical pattern of the construction of these detectors.
Having every first channel affected, rather than a random
distribution, suggests the occurrence may be not a result of
radiation but of some effect unknown at the moment. We will
further investigate the effect by x-ray study of a sample
detector.
On solder bump detectors, we observed that the
aluminium layers both on the strips and the pads were
extensively flaky and bubbly after the radiation. This may be

a result of accelerated oxidation with radiation. We observed
6 out of 2280 channels (each with 14 or 16 bumps) were
broken. This indicates a rate per bump of 1.8x10 -4 for the
radiation effect. We should point out that these 6 failures
might be due to breakage in the aluminium strips due to
radiation rather than the breakage on the bump-bonds. We can
not distinguish this effect at the present time for geometrical
and structural reasons, but will investigate in the future.
IV. CONCLUSIONS
The results of thermal cycling and radiation tests validate
the feasibility of bump-bonding technologies for hybrid pixel
detectors. They withstand extreme conditions. Heating to
100 o C, though, is more destructive than cooling to -10 o C,
while the radiation effect is minimal. There is a correlation
between the occurrences of problems due to these effects and
existence of problems when the detectors were first
assembled. The rates quoted are probably inflated due to the
fact that some failures are caused by damage to the strips and
pads due to repeated probing and radiation.
V. REFERENCES
[1] S. Cihangir and S. Kwan, talk presented at the 3 rd
International Conference on Radiation Effects on
Semiconductor Materials, Detectors and Devices, Florence,
Italy (June 28-30, 2000), to appear in Nuclear Instruments and
Methods A.

Beamtests of Prototype ATLAS SCT Modules at CERN H8 in 2000
A.Barr C , A.A.Carter Q , J.R.Carter C , Z.Dolezal P,$ , J.C.Hill C , T.Horazdovsky U , P.Kodys F&P , L.Eklund N ,
G.Llosa V , G.F.Moorhead M , P.W.Phillips R , P. Reznicek P , A.Robson R , I.Stekl U , Y.Unno K , V.Vorobel P ,
M.Vos T&V
Abstract
ATLAS Semiconductor Tracker (SCT) prototype modules
equipped with ABCD2T chips were tested with 180 GeV pion
beams at CERN SPS. Binary readout method is used so many
threshold scans at a variety of incidence angles, magnetic
field levels and detector bias voltages were taken. Results of
analysis showing module efficiencies, noise occupancies,
spatial resolution and median charge are presented. Several
modules have been built using detectors irradiated to the full
ATLAS dose of 3×10 14 p/cm 2 and one module was irradiated
as a complete module. Effects of irradiation on the detector
and ASIC performance is shown.
I. INTRODUCTION
Beam tests provide an important opportunity to study how
the detector systems fulfil what they have been designed for -
detecting particles. Compared to the radioactive source
measurements, beam tests much better simulate the realistic
environment, with many modules working together,
connected via long cables, etc.
In June and August 2000 two types of silicon microstrip
modules, barrel and forward have been tested with the pion
beams of 180 GeV/c at the CERN H8 SPS beamline [1].
The barrel modules were equipped with square silicon
microstrip sensors of a physical size of 64 mm long and 63.6
mm wide with strips in parallel at a pitch of 80 micrometers.
A module had a pair of sensors glued on the top and the other
glued on the bottom side of a baseboard of the module, being
angled at 40 mrad to have a stereo view. The strip length of a
ATLAS SCT Collaboration
C Cavendish Laboratory, Cambridge University, UK
F University of Freiburg, Germany
K KEK, Tsukuba, Japan
M School of Physics, University of Melbourne, Australia
N CERN, Geneva, Switzerland
P Charles University, Prague, Czech Republic
R Rutherford Appleton Laboratory, Didcot, UK
T Universiteit Twente, The Netherlands
U Czech Technical University in Prague, Prague, Czech Republic
V IFIC - Universitat de Valencia/CSIC, Valencia, Spain
$ corresponding author, e-mail: Zdenek.Dolezal@mff.cuni.cz
module was 12 cm by connecting the pair of sensors. The
forward modules (see Figure 1) were functionally very
similar, but they had quite different layout and hybrid
technology. Their strip length was similar, but they were
wedge-shaped with a fan geometry of strips with an average
strip pitch of about 80 micrometers.
Strips were connected to the readout electronics, near the
middle of the strips in the barrel module and at the end of the
strips in the forward modules. A module was equipped with
12 readout chips (prototype ABCD2T [2]), 6 on the top and 6
on the bottom side of the module. Chips were glued on
specially-designed hybrids. Several modules have been built
using detectors irradiated to the full ATLAS dose of 3×10 14
p/cm 2 with 24 GeV protons at the CERN proton synchrotron
and one module was irradiated as a complete module.
Figure 1: Expanded view of the forward module
The ABCD chip utilises on-chip discrimination of the
signal pulses at each silicon detector strip, producing a binary
output packet containing hit information sampled at the

40MHz clock frequency and corresponding in time to the
beam trigger. The threshold for discrimination is set on a
chip-by-chip basis using a previously determined calibration
between the threshold (in mV) and the corresponding test
input charge amplitude (in fC) which results in 50%
occupancy.
To obtain information on pulse heights, threshold scans
must be carried out. Our measurement program thus consisted
of multiple threshold scans, each at a certain combination of
settings of variables of interest which included:
• Detector bias voltage, generally covering the range
up to expected full charge collection, about +250V for
unirradiated detectors and +500V for irradiated detectors;
• Magnetic field, i.e. the state on or off of the 1.56T
magnetic field;
• Beam incidence angle, the modules being rotated
about an axis parallel to the detector strips reflecting the
ATLAS SCT barrel geometry with respect to the magnetic
field direction.
The readout was triggered with an external scintillator
system. For each trigger, we record binary information from
the modules under test, from anchor planes included for
reference and as control samples, and analogue information
from the 4 high-spatial-resolution silicon telescopes with
analogue readout. In addition, a 0.2ns resolution TDC is used
to record the timing of the (randomly arriving) beam trigger
relative to the 40MHz system sampling clock so that pulse
shape and timing characteristics can be recovered.
More detailed description of the measurement procedure
and results can be found at [3] and [4]
II. BEAMTEST SETUP
A sketch of the beamline setup in August 2000 is shown in
Figure 2. Ten SCT modules are mounted one after the other in
a cooled, light-tight environment chamber on a mechanical
system which allows each to be rotated about a vertical. This
Figure 2: Sketch of the SCT experimental setup at H8 during August
2000. *Barrel modules with irradiated detectors. **Fully irradiated
module, RLT4. Module RLK6 was used for reference, with fixed
threshold and bias.
chamber can be moved into the 1.56 T Morpurgo
superconducting dipole magnet. The field of this magnet is
highly uniform over the volume of the SCT modules, and is
directed vertically downward, parallel to the detector strips in
a configuration which mimics the design arrangement of the
SCT barrel modules with respect to particle trajectory, field
direction and detector.
Outside the environment chamber there are four telescope
modules and two anchor planes, positioned as shown in
Figure 2. The telescope have both X and Y sensors of 50 um
pitch, coupled to analogue readout.
In addition to the tracking telescopes we had two anchor
planes constructed from SCT barrel detectors and hybrids
with four ABCD2NT chips. These provide some additional
external track information with timing characteristics similar
to the modules under test.
The DAQ used for the beamtests was an extension of that
generally used for SCT module testing, a system of VME
units for control, readout and low-voltage power. The SCT
DAQ units include the CLOAC [5], SLOG [6] and
MuSTARD [7]. Low-voltage power and slow-control signals
came from SCTLV2 [8] low-voltage supplies, while high
voltage for detector bias came from linear supplies and from a
prototype CANbus-controlled SCT high-voltage power
supply. [9]. The DAQ software [10] is an extension of a
module testing system [11], a collection of C++ class libraries
used in conjunction with the ROOT [12] package running on
a PC under Windows NT 4.0.
III. MODULES
A. Overview of modules under test
6 barrel and 3 forward modules were tested in the beam.
Their positions and names are at Fig. 2. Barrel modules used
hybrids of two different technologies: thin film [13] and
copper/polyimide [14]. Forward modules were equipped with
Kapton-Carbon-Kapton hybrids [15]. They used strip
detectors of 3 different thicknesses (285, 300 and 325 μm)
from several vendors. Modules K3113, RLT9 and RLT10
have been built using detectors irradiated to the full ATLAS
dose of 3×10 14 p/cm 2 with 24 GeV protons at the CERN
proton synchrotron and module RLT4 was irradiated as a
complete module.
B. Calibration
We performed a number of in-situ calibration
measurements and other studies of all modules prior to,
between and after the beamtests to verify or correct the
module characterisations using a number of internallygenerated
test charges across the full charge range of interest,
as well as the identification of unusable channels. Last
versions of ABCD chip has an additional four-bit threshold
trim adjustment for each strip, which must be separately
optimised. All unusable channels are recorded and later
masked.

IV. MEASUREMENTS
A total of over a 1000 runs of 5000 events each were taken
at 5 incidence angles, 2 magnetic field levels and 6 detector
bias voltages. At each combination of these settings, a set of
threshold scans was performed with 12 charge settings
ranging from 0.9 to 4.5 fC chosen to cover in some detail the
design operating region near 1.0 fC as well as allowing a
study of the fall off at higher thresholds allowing an accurate
determination of the median charge collected.
These data are complemented by noise runs (taken in-situ,
but with no beam) and local calibration runs.
V. DATA ANALYSIS
In the course of data analysis, tracks are reconstructed
from the telescope signals. Events with one reconstructed
track are accepted only, to avoid ambiguities.
Binary hits in the module channels are classified to
‘efficient hits’ and ‘noise hits’ according to their proximity to
the extrapolated track position and timing. A hit is considered
‘efficient’ if found 100 μm from the track intersection of the
module plane. Hits found more than 1 mm from the track are
taken as noise hits. Bad channels known from lab and in-situ
calibrations and their neighbours are excluded from the
analysis. The analysis requires reference (anchor) planes to
be efficient for all events. Furthermore, cuts on χ 2 , dX/dZ and
dY/dZ are imposed.
In order to monitor the efficiency dependence on the
timing of each event, the trigger phase with respect to the 40
MHz system clock is measured using a TDC. Figure 3 shows
the efficiency dependence on the charge deposition moment,
as measured by the TDC. As the modules were read out in
efficiency
K3112 at perp. incidence, 1.56 T, 250 V
¢
1
¡
0.8
¡
0.6
¡
0.4
¡
0.2
¡
0¡
0
1.0 fC
©
1.2 fC
1.5 fC
2.5 fC
�
3.5 fC
4.5 fC
¢
10
£
20
¤
30
trigger phase
Figure 3: Efficiency dependence on trigger phase for the three
recorded clock cycles
ANYHIT compression where three time bin samples around
the central time are recorded, the original 25 ns interval (the
shaded area in the figure) can be extended on both sides using
the full hit pattern information. As expected, the efficiency is
seen to be a strongly varying function of the charge deposition
moment. As the discriminators in the ABCD were operated
with Edge Sensing OFF ("level" mode) the length of the
¥
40
¦
50
§
60
¨
70
interval in which the modules are efficient depends strongly
on the discrimination threshold. Analysis 1 reported here
selects a rather broad 12 ns trigger phase window, attempting
to minimise the effect on the efficiency while retaining as
much statistics as possible.
Three independent data analyses differing mainly in
treating the time bin and TDC information were performed,
yielding results which are largely identical [16], [17], [18].
Several important benchmark values are then extracted:
efficiency, noise occupancy and spatial resolution.
1) S-curves
VI. RESULTS
Figures 4 and 5 show the efficiency and noise results as a
function of threshold for unirradiated (K3112) and fully
irradiated (RLT4) barrel modules, respectively, for several
bias voltages. These data correspond to normal incidence in
1.56T magnetic field.
Figure 4: S-curves and noise occupancy in a 1.56 T field, normal
incidence for unirradiated barrel module K3112 at all detector bias
values studied.
In the non-irradiated modules, the efficiency is seen to be
nearly independent of bias voltage down to around 160 Volts.
Only at very low voltages (80 V) does the efficiency decay
significantly. The modules with irradiated detectors, on the
other hand, show a very strong dependence of efficiency on
the bias voltage. At 150 Volts virtually no signal is collected.
The signal increases slowly with bias voltages all the way up
to 500 Volts. The noise occupancies displayed in the same
figure were determined using off-track hits.

Figure 5: S-curves and noise occupancy in a 1.56 T field, normal
incidence for fully irradiated barrel module RLT4 at all detector bias
values studied.
2) Efficiency at 1 fC
Threshold of 1 fC presents a nominal value for ATLAS
running. Therefore, efficiency and noise occupancy at this
point is of our interest. Figure 6 shows the dependence of
efficiency on bias voltage averaged over all modules and all
incidence angles.
efficiency (%)
100
99.5
99
98.5
�
98
97.5
97
96.5
96
95.5
95
0 100 200 300 400 500
bias voltage (V)
Figure 6: Efficiency at 1 fC without field (left) and in a 1.56 T field
(right) for non-irradiated (filled circles) and irradiated detectors
(open circles)
Modules with non-irradiated detectors show only a marginal
decay of the efficiency at the lowest bias voltages, although
the charge loss is already considerable at 120 V. This result is
compatible with the 99% benchmark.
The modules with irradiated detectors, as expected, show a
very pronounced dependence on bias voltage. On average,
98% efficiency is reached above 300 V.
For other than perpendicular incidence, a net reduction of
the collected charge is observed, however, the efficiency at 1
fC at relatively high bias voltage is nearly unaffected for the
angle range from 16° to –14°.
3) Noise occupancy
Noise occupancies at the 1 fC nominal operating point
derived from the off-track hits do not change significantly
with any of the scanned variables. The table below gives a
global noise number, valid for all incidence angles, bias
voltages and magnetic fields, at 1 fC threshold, and also the
threshold at the specification noise level of 5×10 -4 .
From the table follows that unirradiated barrel modules
have no measured noise, and irradiated barrel modules are
still within or very close to specifications.
High noise of the forward modules has been subject to
extensive further investigations. Several effects have been
found, which can explain large part of the noise increase.
Forward modules were run at substantially higher hybrid and
chips temperature. This is known to have a strong influence
on the noise, but also on the threshold and calibration DACs,
hence the threshold scale of the forward modules was likely
wrong. Furthermore, large part of the noise can be attributed
to the common noise. This effect has been addressed in later
designs.
Table 1: Noise occupancy at 1 fC and lowest threshold setting which satisfies the SCT noise occupancy specification of 5×10 -4 .
module K3112 RLT5 SCAND1 FR153 FR152 K3113* RLT9* RLT10* RLT4**
Noise at 1 fC

K3112 front: residuals @ 1fC Chi2 /
�
Chi2 / ndf = 665.3 / 65
Constant = 506.6 ± �
Constant = 506.6 6.598
Mean = -2.582 ± 0.275
500
Sigma = 23.92 ± 0.1513
400
300
200
100
0
-200 -150 -100 -50 0 50 100 150 200
Residual (um)
X residual Chi2 / ndf = Chi2 / ndf = 350 / 86
Constant � 350 / 86
= 656.1 ± 9.065 �
Constant = 656.1
Mean = -1.584 ± 0.2163
600
Sigma = 19.4 ± 0.1585
500
400
300
200
100
0
-200 -150 -100 -50 0 50 100 150 200
X residual (um)
K3112 back: residuals @ 1fC Chi2 /
�
Chi2 / ndf = 717.4 / 56
Constant = 538.3 ± �
Constant = 538.3 6.854
Mean = 4.836 ± 0.2664
500
Sigma = 23.58 ± 0.1448
0
-200 -150 -100 -50 0 50 100 150 200
Residual (um)
Figure 7: Spatial resolution in u,v and X,Y of K3112, for
perpendicular incidence (at 250 Volt detector bias and a 1.56 T
magnetic field).
VII. CONCLUSIONS
Beamtests of an important sample of SCT modules of
both barrel and forward types representing near-final
designs with the ABCD2T readout chip were successfully
performed covering a wide range of irradiation states,
incidence angles, magnetic field states, and detector bias
voltages representative of expected operating conditions.
The modules met, or nearly met, most of the relevant
specifications of the Inner Detector TDR. An exception
was the number of bad channels which was mostly due to
the now-understood and addressed ABCD2T trim DAC
problem. The unirradiated barrel module prototypes tested
in the June and August beams satisfy the noise occupancy
specification (5×10 -4 ) down to 0.9 fC threshold. The
efficiency at 1 fC is around (99±1)% irrespective of
magnetic field and incidence angle. Only at the lowest bias
voltages does ballistic deficit of the shaper lead to
efficiency loss.
The forward modules were noisier than expected
compared to many laboratory measurements. Further
investigations attributed this fact to several effects
(substantially higher temperature leading to incorrect
calibration, common mode noise susceptibility, etc.) This is
being addressed in later designs. The efficiency at 1 fC is
similar to the barrel modules.
Three modules built with detectors irradiated to 3×10 14
p/cm 2 and one complete module irradiated to the same
fluence were tested. The modules with irradiated detectors
had higher noise, but still satisfied the ATLAS noise
occupancy specification at 1 fC. The fully irradiated
module required a threshold of 1.2 fC to meet the noise
specification.
Two out of three modules built with irradiated detectors
reach 98% efficiency at a bias voltage of around 350 V.
The slightly lower efficiency of the other, K3113, is not
fully understood but is probably due to an overestimation
of the calibration response, as indicated by the consistently
low median charge, and noise and efficiency at 1fC. Batch
to batch uncertainties in the ABCD2T calibration
capacitors of 10 to 20%, as well as temperature dependence
of the gain and calibration charge amplitude all contribute
to a systematic uncertainty in the response sufficient to
400
300
200
100
Y residual Chi2 / ndf = 395.5 / 92
250
200
150
100
50
Constant = 244.1 ± 3.262
Mean = -23.99 ± 8.797
Sigma = 769.9
± 5.627
0
-3000 -2000 -1000 0 1000 2000 3000
Y residual (um)
account for this discrepancy. Remarkable is the high
efficiency of the fully irradiated module, RLT4. This may
be due to the thicker detectors or the altered timing
characteristics of the front-end ABCD electronics after
irradiation. No charge collection plateau is reached in a bias
voltage scan to 500V.
VIII. REFERENCES
[1] http://atlasinfo.cern.ch/Atlas/GROUPS/GENERAL/
TESTBEAM
[2] "Project Specification: ABCD2T/ABCD2NT
ASIC", http://chipinfo.home.cern.ch/chipinfo
[3] A. Barr et al.,
http://atlas.web.cern.ch/Atlas/GROUPS/INNER_DETECT
OR/SCT/tbAug2000/note.pdf
[4] SCT Testbeam web site, follow links for June and
August 2000,
http://atlasinfo.cern.ch/Atlas/GROUPS/INNER_DETECT
OR/SCT/testbeam
[5] M.Postranecky et al., "CLOAC Clock and Control
Module", http://www.hep.ucl.ac.uk/atlas/sct/#CLOAC
[6] M.Morrissey, "SLOG Slow command generator",
http://hepwww.rl.ac.uk/atlas-sct/mm/Slog/
[7] M.Morrissey & M.Goodrick, "MuSTARD",
http://hepwww.rl.ac.uk/atlas-sct/mm/Mustard/
[8] J.Stastny et al, "ATLAS SCT LV Power Supplies",
Prague AS, http://wwwhep.fzu.cz/Atlas/WorkingGroups/Projects/MSGC.html
[9] http://wwwhep.fzu.cz/Atlas/WorkingGroups/Projects/MSGC/hvspec_0
1feb26.pdf
[10] G.Moorhead, "TBDAQ Testbeam DAQ",
http://home.cern.ch/s/sct/public/sctdaq/www/tb.html
[11] J.C.Hill, G.F.Moorhead, P.W.Phillips, "SCTDAQ
Module test DAQ",
http://home.cern.ch/s/sct/public/sctdaq/sctdaq.html
[12] http://root.cern.ch/
[13] A.A.Carter,
http://www.fys.uio.no/elab/oled/abcd2t.htm
[14] Y.Unno, "High-density, low-mass hybrid and
associated technology", LEB2000
[15] Forward Kapton Hybrid version KIII,
http://runt1.physik.unifreiburg.de/feld/sct/hybrid/index.htm
[16] M.Vos et al.,
http://ific.uv.es/~vos/tb2000/aug2000/aug2000.html
[17] P. Kodys et al., http://wwwrunge.physik.unifreiburg.de/kodys/TBAugust/TBAugust.html
[18] Y.Unno et al.,
http://atlas.kek.jp/managers/silicon/beamtests.html

Design and Test of a DMILL
Module Controller Chip for the ATLAS Pixel Detector.
Abstract
The main building block of the Atlas Pixel Detector is a
module made by a Silicon Detector bump bonded to 16
analog Front-End chips. All FE's are connected by a star
topology to the Module Controller Chip (MCC) with data
push architecture. MCC does system configuration, event
building, control and timing distribution. The electronics has
to tolerate radiation fluences up to 10 15 cm -2 1 MeV in
equivalent neutrons during the first three years of operation.
The talk describes the first implementations of the MCC in
DMILL (a 0.8 µm Rad-Hard technology). Results on tested
dices and irradiation results of these devices at the CERN PS,
up to 30 Mrad, will be presented. 8 chips were operating
during irradiation and allowed to measure SEU effects.
I. INTRODUCTION
The ATLAS pixel detector [2] is constituted of 3-barrel
layers and of 3 forward and backward disks. The barrels are at
5.05, 8.85 and 12.25 cm from the beam, with a tilt angle of
20° and a total dose of 30 Mrad for the innermost layer (B-
Layer) is expected after 3 years of operation. Each barrel is
organized into staves and each disk into sectors; both of them
are in turn composed of modules. 1744 identical modules will
be used in the whole detector.
The Module Controller Chip (MCC) is an ASIC, which
provides complete control of the Atlas Pixel Detector module.
Besides the MCC the module hosts 16 FE chips bump-bonded
to a silicon detector [3].
The talk is divided in three sections. In the first section we
describe the requirements that the MCC has to fulfil. Main
features of this device are the ability to perform event
building which provides some data compression on data
coming from 16 Front-End chips read out in parallel. Output
data stream is transmitted on one or two serials streams
allowing a data transfer up to 160 Mbit/s. The system clock
frequency is 40 MHz. First a prototype and then a full version
of the chip were designed and tested. The second section
describes the test set-up developed in Genova, which allows a
comparison between the actual chip, hosted in a VME board,
R. Beccherle
INFN Genova, Via Dodecaneso 33, Italy
Roberto.Beccherle@ge.infn.it
on behalf of the
Atlas Pixel Collaboration [1]
and a C++ model simulating the chip. Test results of both
chips will be presented in the third section. We focus on the
irradiation tests, which allowed us to operate the chip while
irradiating it, and this allowed performing detailed SEU
studies.
II. SYSTEM DESCRIPTION
16 analog FE chips and a digital Module Controller Chip
make the electronics part of the Atlas Pixel Detector. The
interconnections have been kept very simple, and all
connections that are active during data-takings use low
voltage differential signalling (LVDS) standards to reduce
EMI and balance current flows. The data link topology from
the 16 FE’s to the MCC in a module is a star topology using
unidirectional serial links. This topology has been chosen to
improve the tolerance of the whole system to individual FE
failure, as well as to improve the bandwidth by operating the
serial links in parallel.
FE chips electronics is organized in 18 columns and 160
rows of 50 × 400 µm 2 pixel cells. These chips provide 7-bit
charge information using a time-over-threshold front-end
design. Time over threshold information is digitised using the
40 MHz beam crossing rate. Event data coming from the FE
chips are already formatted and are provided as soon as
possible using data push architecture. This is done by the
digital End of Column logic built-in in each chip. MCC has to
perform event building collecting events from all 16 FE chips.
In order to be able to perform this task, data from each link
are buffered into a 21 × 32 bit deep FIFO. All FIFO’s are full
custom blocks, while the remaining part of the chip was built
using the DMILL standard cell library. As soon as one
complete event has been received from the FE chips and
stored in the FIFO’s, the MCC starts event building.
Formatted data are sent to the output using one or two serial
streams that can provide a total data transfer up to 160 Mbit/s.
Besides event building the MCC has also to perform
system configuration, by a serial protocol, being the only
electronics part of the module able to communicate with the
Read Out Driver (ROD). In order to perform this task a serial
command decoder has been implemented. This is a crucial
part of the chip and particular effort has been put into its

ealization in order to ensure a high tolerance to single bit
flips in the data being received. The protocol is divided in two
main classes, Data Taking mode and Configuration mode and
it is not possible to mix these two states, by construction, even
with single bit flip. This is especially important in case of a
noisy environment and for the B-layer, where high SEU
induced effects are expected. Another feature of the command
decoder block is the ability to reset its circuitry without the
need of a power up reset or a hard reset pin. Each FE chip is
independently accessible in order to be able to configure it
through a set of dedicated commands. MCC configuration
information is stored in a Register Bank.
The chip has also to ensure synchronization between all
events and to distribute Trigger commands to all FE’s.
Trigger and Timing Circuitry block (TTC) performs this task.
In case of any error in event reconstruction, due, for example,
to a data overflow in the internal FIFO’s, synchronization is
guaranteed and error words are added to the data stream in
order to correctly flag the failure.
In addition to the main functions also a self-testing
capability of all internal structures has been added to the chip.
This test capability is a key feature in order to be able to
build, test and operate with reliability a complex system such
as the ATLAS Pixel Detector module. As an example,
implemented test structures allow for testing the correctness
of event builder, writing FE events into the internal storage
structures as if they would come directly from the FE chips.
This is done using the serial data protocol. In order to verify
the correctness of event building, simulated events can be
downloaded to the MCC first and are then reconstructed and
formatted by the event builder and transmitted back to the off
detector electronics (ROD).
After a first chip, built using AMS 0.8 µm technology,
which was successfully used to build complete modules and
used in test beam, we decided to implement a rad-hard version
of the MCC [4]. The chosen technology was DMILL, a
0.8 µm rad-hard technology, for its similarities, in terms of
design rules, with the AMS one.
We developed two successive versions of the MCC called
MCC-D0 and MCC-D2. The first chip is a simple test chip
containing only one full custom FIFO, the complete command
decoder and the register bank. The main goal of this chip was
to understand eventual technology issues and to perform an
irradiation at the CERN PS proton irradiation facility. As
described later in the paper the chip was successfully
irradiated up to 30 Mrad. The second chip developed using
this technology (MCC-D2) is a full version of the module
controller chip and is therefore suited to build complete radhard
modules.
III. TEST SETUP
The main difficulties in testing a chip like the MCC is by
far the ability to fully debug, during the chip design phase,
and then to test the correctness of the event building algorithm
and all it’s possible exceptions. Also the verification of the
correctness of the Trigger distribution to the FE chips without
loss of synchronization presents many challenges. The MCC
has to distribute LEV1 triggers to the FE’s. Up to 16 Trigger
commands can be received by the MCC. Each time the MCC
receives a Trigger command a counter is incremented. As
soon as all FE’s have sent a complete event the counter
keeping track of the received triggers is decremented. If more
than 16 triggers have to be processed the trigger command is
dropped and an empty event is generated by the MCC in order
to keep up with event synchronization. Therefore the overflow
mechanism strongly depends on all 16 concurrent FE data
streams and is therefore very hard to recreate both in the
laboratory and in the Verilog simulation used to validate the
chip. In order to overcome these challenges we decided to
develop a VME based test board (MCC exerciser) that allows
us to completely simulate MCC input data. A C++, timing
oriented, simulation package that is part of a larger simulation
environment, developed in Genova, and called SimPix,
controls the board.
Figure 1: MCC exerciser board with two mounted memory cards.
The MCC exerciser board, see Figure 1, is a standard
VME board that can host a packaged version of the chip. On
the motherboard we can plug-in 10 smaller “memory cards”.
Each of them is equipped with two 8 Mbit deep memory
banks and can either store data to be transmitted to the MCC
or can sample data lines coming from the MCC. In a typical
laboratory test we use 16 channels to simulate FE data, one
channel to simulate data commands coming from the ROD,
and the last channel is used to sample one MCC output data
line. Two other channels are used to sample, for example,
other MCC I/O’s. The whole board is synchronous with a
system clock of 40 MHz. Up to 200 ms of operation can be
simulated with this set-up. SimPix provides input data to the
memory cards using a 32 bit wide VME bus interface.
SimPix is a modular simulation program, written in C++,
which allows us to simulate the whole ATLAS Pixel Detector
starting from physics data. A block diagram describing its
main features is presented in Figure 2. The input data to the
simulation can be provided both by random selected data and
by means of a GEANT simulation of the whole detector.
LEV1 triggers can be generated both randomly and according
to the ATLAS trigger specifications. Data produced by this
first step are then sent to 16 FE models which in turn produce

the correct inputs for the MCC. Data processed by the MCC
are then analysed by an automatic analysis tool that flags
possible mismatches. The peculiar aspect of this simulation
environment is the modular approach that allows one to
replace each component, FE or MCC model, with a similar
description that can be at a different level of accuracy. This is
very useful for example if one wants to simulate different
versions of the FE chip. Therefore different models are
provided in order to be able to simulate an ideal FE or a
model that follows, as closely as possible, the real hardware
implementation. Being the simulation time oriented, one can
simulate the input/output of each electronics component down
to the single clock cycle. In the case of the MCC this
approach is pushed forward and besides an ideal model and a
full C++ simulation of the chip one can actually replace the
MCC module with a Verilog simulation of the chip running
on a remote workstation. This is accomplished by some
routines that use TCP/IP to interface two different machines
on a network. This approach, in which one runs at the same
time the Verilog and the C++ model of the chip, allows to
quickly comparing results as the chip is being developed.
Another option is to directly interface the simulation software
to the MCC exerciser board previously described. In this case
the software interfaces to the VME crate hosting the actual
hardware. Using the same approach one can also interface
directly to a logic state analyser. This approach has been
proven very useful in order to perform both development and
test of the whole chip.
Figure 2: SimPix block diagram.
IV. TEST RESULTS
In this section we present the results of the tests performed
on both chips designed in Genova using the DMILL 0.8 µm
rad-hard technology. The design of both chips was done
starting with a Verilog behavioural model and using Synopsys
as synthesis tool to map the design to the standard cell library
provided by the foundry. Layout was performed using
Cadence Cell Ensemble. DRC and LVS were performed on a
completely flat design. The only step of the standard design
flow that was not performed was a simulation of the circuit
using extracted values for capacitance after the layout was
completed due to some problems in the provided design kit.
On both chips all the full custom blocks were hand placed and
the clock tree was done using a distributed buffer as a clock
tree generation tool was not provided.
Both chips were tested in the laboratory, after packaging
them, using the MCC exerciser board and a logic state
analyser. The MCC-D0 chip was also tested at the CERN PS
proton beam and irradiated up to 30 Mrad.
A. Tests of the MCC-D0
The first chip, MCC-D0, is a test chip developed in order
to test the new technology. This chip contains a 21 bit wide
and 32 words deep full custom FIFO designed using a
conservative 12 transistors layout. In addition to the FIFO a
command decoder and a register bank were implemented. Up
to 40 configuration bits can be stored in the register bank. The
main goal of this version of the chip was to irradiate it at the
CERN proton irradiation facility in order to be able to
perform SEU studies.
For this purpose some special functions were added to the
chip in order to maximize the test that could be performed
during irradiation. For example, the information of a detected
bad command is stored inside an error register during
irradiation. By reading such register we have been able to
quantify the effect of induced errors.
Figure 3: MCC-D0 test beam set-up. Data taking was active during
irradiation and this allowed for SEU studies.
In order to perform the irradiation test a dedicated test
system was built. This test set-up is shown in Figure 3. Up to
8 chips can be irradiated at the same time in the set-up. All
chips are mounted on support cards, which only have passive
components. These boards are connected to repeater cards,
located 5 m away from the beam. The repeater cards are
connected, by a 29 m long flat cable to the selector card that
essentially implements a multiplexer allowing selecting one of
the 8 support cards as being active. The selector board is

controlled by means of a standard VME bus by the MCC
exerciser that is in turn controlled by SimPix. This set-up
therefore allows addressing all 8 chips, only one being active
at a time.
Figure 4: The upper plot shows results for a 12 transistor based
memory cell, while the second one is for standard cell memory cells.
The CERN PS proton irradiation facility has a bunched
beam, with one or two 200 ms bursts every two seconds.
We synchronised our data taking with the start of burst in
order to be able to operate the chips during irradiation. We
performed two different tests, a dynamic one on the actual
active chip and a static one on the remaining 7 chips. After
each bunch the active chip was changed. The dynamic test
consists in continuously write, read and compare data in the
FIFO and configuration registers. After that we read out data
from the chip checking that all commands were correctly
recognized by the MCC and if some bit flipped inside the data
structures. Each read operation was performed three times, in
order to ensure that no transmission error occurred during the
readout phase. The static tests instead, consisted in writing a
known data configuration pattern in the MCC data structures
before each beam spill and in reading out data after the spill in
order to evaluate the bit flip probability. To select the 8 good
chips we performed a test in the laboratory on packaged chips,
because they were not tested at the production site. We tested
14 chips and 11 turned out to be working perfectly. During
this test we measured power consumption, maximum clock
frequency and checked that all writ able structures were
correctly addressable. Maximum working clock frequency
turned out to be ~90 MHz. All working chips were in perfect
agreement with synthesis and simulation results.
All chips were successfully irradiated up to 30 Mrad. After
irradiation all chips were perfectly working but after some
days of cooling down four of them stopped to respond to any
command. We also tried to anneal them in an oven at 100 C°
for one week without being able to make them working again.
We suppose that this problem is related to our full custom
LVDS I/O pads design that in fact showed no activity on the
non-working chips. We performed the same measurements
done before irradiating the chips on the four remaining chips
and compared the results. The only measured difference was a
reduction of the maximum clock frequency of about 40%.
Anyway, even after this frequency reduction, the chips where
still functional at the LHC working frequency of 40 MHz.
SEU measurements, presented in Figure 4, show almost no
errors in the dynamic test and a pure static bit flip probability
per burst of 1.2% for data stored inside a standard cell scan
flip-flop and a probability of 2% for the full custom, twelve
transistor design, FIFO memory cell.
B. Tests of the MCC-D2
The second chip developed by our group is a complete
version of the MCC that is compliant with the ATLAS Pixel
specifications. The goal of this second chip was to be able to
implement, together with a DMILL version of the Front End
chips, a rad-hard version of the ATLAS Pixel Detector
module. The foundry did not test these chips and therefore we
packaged 19 of them in order to be able to test them with our
test set-up. We performed three different types of tests on the
chips: first a DC test to measure static power consumption,
then a test with the logic state analyser in order to test some
simple patterns on the FIFO’s and on the Register Bank at
different clock speeds, and finally a functional test with the
MCC exerciser, in order to fully debug the event building
circuitry of the chip. Results of these tests are shown in
Table 1.
Table 1: Test results of MCC-D2: in the first column of the table
DC current measurements are shown while in the second one the
maximum working clock frequency is reported. The last two
columns show how many chips passed the logic state analyser and/or
the MCC exerciser test. Finally in the last row the total chip yield
after each test is shown. Both fully working chips passed all test only
operating them at a frequency of 33 MHz.
Chip # DC test Max ck LSA test MCC ex test
1 24 mA 74 MHz OK Failed
2 22 mA 72 MHz OK Failed
3 34 mA 73 MHz OK Failed
4 Failed - - -
5 21 mA 74 MHz OK Failed
6 21 mA 73 MHz Failed -
7 20 mA 72 MHz OK Failed
8 Failed - - -
9 20 mA 73 MHz OK Failed
10 Failed - - -
11 18 mA 73 MHz OK OK @ 33 MHz
12 30 mA 72 MHz OK Failed
13 22 mA 75 MHz Failed -
14 19 mA 74 MHz OK Failed
15 41 mA 73 MHz Failed -
16 21 mA 74 MHz OK Failed
17 18 mA 75 MHz Failed -
18 Failed - - -
19 21 mA 74 MHz OK OK @ 33 MHz
Yield 84% 58% 11%
DC measurements showed a power consumption of 20 to
40 mA, in agreement with expectations. The maximum
working clock frequency turned out to be in a range between
70 and 75 MHz that is in quite good agreement with synthesis

esults that predicted 78 MHz. One has to remember though,
that we did not perform a simulation of the chip after
extracting parasitic capacitor values from the layout and that
therefore we rely entirely on wire load models. It is worth to
remember that the test done with the logic state analyser did
not cover all possible timing paths in the chip; we expect it
covers ~10%. This test also allowed a detailed study of the
Command Decoder built in the chip that performed very well,
meeting all specifications. Also, by design, the Command
Decoder should be able to initialise itself into a well-known
state in order to be able to operate the chip without a hard
reset pin or a power-up reset, but only issuing a global reset
command. This feature worked flawlessly.
Figure 5: Trigger commands without and with bit flip. In the graph
we can see the 40 MHz system clock, the serial input line with of the
MCC the two Trigger commands. The last line shows the MCC
output line and one can see that the timing information between
commands is preserved.
Another implemented and tested feature was the ability to
distinguish between two consecutive Trigger commands and
to correctly detect correct timing information even in case of a
single bit flip in the input data line during the Trigger
command. This can be seen in Figure 5.
11 out of 19 chips passed these first two tests. The last
test, for which we calculated a system coverage of ~70% was
performed doing real event building using the MCC exerciser.
Results of these tests are also presented in Table 1 and one
can see that only 11% of the chips turned out to be fully
functional after these tests. One thing to note though is that
both working chips had to be operated at only 33 MHz in
order to get correct results. This discrepancy with synthesis
results can both be due to the lack of simulation of a netlist
that included parasitic capacitor extracted from the actual
layout or to an incorrect timing in the synthesis models.
As we can see the results of these test show an
unacceptable low yield and some problems in the design
technology and/or it’s modelling. Some rough calculations
made taking also in account DMILL forecasts for a digital
chip of this size should have provided a yield of 20, 30%.
Much more detailed studies on these results should have been
performed in order to accept this technology for our needs.
In our collaboration also two distinct versions of the
analogue Front End chip, also developed in DMILL, were
submitted within the same reticule and these chips turned out
to have a yield that was lower than 1%.
V. CONCLUSIONS
In this paper we presented test results of two chips that
were submitted by the Genova group of the ATLAS Pixel
Collaboration to DMILL, a 0.8 µm rad-hard technology. One
test chip was tested and successfully irradiated up to 30 Mrad
at the CERN PS proton beam facility. SEU studies have been
performed on this chip operating the chip while irradiating it.
Results showed that this technology, from the radiation
tolerance point of view, is suitable for the ATLAS Pixel
Detector even for the innermost layer. In addition we
presented test results of a full version of the ATLAS Module
Controller Chip. These results show some severe yield
problems (11% on 19 tested dices) and problems in the timing
models of the libraries that produced a chip working only at
33 MHz, despite of the synthesis results that showed 78 MHz.
This, connected to the fact that also the FE chip of our
collaboration, submitted on the same reticule of the MCC,
showed a very poor yield result (less than 1%) made our
collaboration decide to temporarily drop this technology in
order to explore the 0.25 µm technology, with rad-tolerant
layout techniques, developed at CERN. Therefore the
collaboration will submit a new version of both the FE and the
MCC in this technology in October this year.
VI. REFERENCES
[1] ATLAS Collaboration, Pixel Detector TDR,
CERN/LHCC/98-13, 1998
[2] G. Darbo, The ATLAS Pixel Detector System
Architecture, Proceedings of the “Third Workshop on
Electronics for LHC Experiments”, London,
CERN/LHCC/97-60 (1997), pp. 196-201.
[3] R. Beccherle, The Module Controller Chip (MCC) of
the ATLAS Pixel Detector, Proceedings of the
“Nuclear Science Symposium”, Montreal, Canada,
(1998).
[4] P. Natchaeva et al., Results on 0.7% X0 thick pixel
modules for the ATLAS detector, Proceedings of
“Pixel 2000”, Genova, Nuclear Instruments and
methods in Physics Research A 465 (2001),
pp. 204-210.

Radiation Tests on Commercial Instrumentation Amplifiers,
Analog Switches & DAC's a
J. A. Agapito 1 , N. P. Barradas 2 , F. M. Cardeira 2 , J. Casas 3 , A. P. Fernandes 2 , F. J. Franco
1 , P. Gomes 3 , I. C. Goncalves 2 , A. H. Cachero 1 , J. Lozano 1 , J. G. Marques 2 , A. Paz 1 ,
M. J. Prata 2 , A. J. G. Ramalho 2 , M. A. Rodríguez Ruiz 3 , J. P. Santos 1 and A. Vieira 2 .
1 Universidad Complutense (UCM), Electronics Dept., Madrid, Spain.
2 Instituto Tecnológico e Nuclear (ITN), Sacavém, Portugal.
3 CERN, LHC Division, Geneva, Switzerland.
agapito@fis.ucm.es
Abstract
A study of several commercial instrumentation
amplifiers (INA110, INA111, INA114,
INA116, INA118 & INA121) under neutron and
vestigial gamma radiation was done. Some parameters
(Gain, input offset voltage, input bias
currents) were measured on-line and bandwidth,
and slew rate were determined before and after
radiation. The results of the testing of some
voltage references REF102 and ADR290GR
and the DG412 analog switch are shown. Finally,
different digital-to-analog converters were
tested under radiation.
I. INTRODUCTION
The irradiations were performed using a
dedicated irradiation facility in the Portuguese
Research Reactor. The components under test
were mounted on several PCBs, in a simple
support placed inside a cylindrical cavity created
in one of the beam tubes of the reactor,
thermally conditioned. For these experiments,
the reactor was operated at the nominal power
of 1 MW. The fluence of 5 · 10 13 n · cm -2 in the
central PCB was reached in about 5 days, with
14 hours operation + 10 hours stand-by per day.
x 10 13 n·cm -2
12
10
8
6
4
2
0
450 550 650 750 850 950
X (mm)
Figure 1: Fluence of neutrons 2.001
A 0.7 cm thick boral shield cut the thermal
neutron component of the beam and a 4 cm
thick Pb shield was used to reduce the total
gamma dose below 2 kGy for the central PCB.
The neutron fission fluxes were measured with
Ni detectors placed at the centre of the boxes
that contained the PCBs.
A photodiode sensitive to neutrons was
placed in several boards, so that the neutron flux
was monitored online. A channel for monitoring
the gamma radiation was also implemented.
Integration dosimeters placed on the back of
first and last PCBs reveal, after completion of
the tests, a total gamma dose in the 1.3 - 2.7
kGy range.
II. INSTRUMENTATION AMPLIFIERS
All irradiated instrumentation amplifiers are
build in bipolar technology for the amplifying
and output stages. The main difference between
them is the input stage technology and the circuit
topology, designed to confer the specific
features of the device. Four samples of all devices
were tested on line under neutron radiation.
The INA110KP is a monolithic FET-input
instrumentation amplifier. Its current-feedback
circuit topology and laser trimmed input stage
provide excellent dynamic performance and
accuracy. And the INA111AP is a high speed,
FET-input instrumentation amplifier offering
excellent performance. Both amplifiers have an
extended bandwidth (450KHz at G=100).
The differential gain remains constant during
the irradiation period until a total accumulated
dose of neutrons of 1.25-1.5 · 10 13 n · cm -2 ,
500 Gy is reached. A slight decrease of less than
1% (Figure 2) precedes to the dramatic drop off
and the destruction of the amplifiers occurs
when the total dose reaches 6-7 · 10 13 n · cm -2
(2.4kGy).
a This work has been financed by the co-operation agreement K476/LHC between CERN & UCM, by the
Spanish research agency CICYT (TIC98-0737), and by the Portuguese research agency ICCTI.

There is no common behaviour for the input
offset voltage. There is a high increment of this
parameter for all devices. The highest measured
value is 5.5 mV. However, no increment of the
input bias currents was observed.
Figure 2: INA110. Differential. Gain
On the other hand, the bandwidth is reduced
drastically, and the harmonic distortion increased,
on both amplifiers (Table 1).
Table 1: INA110. Bandwidth and slew rate before
and after radiation
Flux(n ·
cm -2 )
B.W. MHz
(G=10)
B.W. kHz
(G=100)
S. R. V/μs
0 2.2 470 21
3.5 · 10 13
1.9kGy
1.55 200 6.2
5.1 · 10 13
2.2 kGy
1.2 130 4.8
6.8 · 10 13
2.4 kGy
0.83 62 3.0
The input-output dc voltage transfer characteristic
was measured before and after irradiation
(Figure 3). The voltage transfer characteristic
was asymmetrically altered for all devices,
and the positive and negative saturation voltages
decreased.
Figure 3: DC Voltage transfer for INA110 amplifier
with ±15 V power supply
The INA121PA is a low power FET-input
instrumentation amplifier, with a very low bias
current and a smaller bandwidth than the former
(50kHz G=100). The measured parameters were
altered in a similar way to the precedents with
the irradiation dose values reduced to a third.
This can be related both to the smaller bandwidth
and to the low power characteristics.
The INA114 is a low cost, general purpose
bipolar instrumentation amplifier offering excellent
accuracy. Two different models of the same
amplifier were tested, AP & BG (plastic and
ceramic package). The differential gain is constant
until a total dose of 1.5 10 13 - 1.8 · 10 13 n ·
cm -2 (1kGy) is reached, and then it increases up
to a 3% and is abruptly destroyed at 2.2 · 10 13 -
2.8 · 10 13 n · cm -2 (1.4kGy) (Figure 4).
Figure 4: Diff. Gain bipolar Inst. Amp. (INA114)
An almost linear ratio between the input offset
voltage and the accumulated total neutron
dose is detected (Figure 5). The input bias currents
increase slightly in all devices after
irradiation.
Figure 5: Input Offset Voltage vs. Neutron flux
A different behaviour of the two models was
observed. The BG device revealed a higher tolerance
to radiation, which can be attributed to
the difference in the packages [1], and also that
has lower values for bias currents and input offset
voltage.
The INA118P is a bipolar low power, general
purpose, instrumentation amplifier. Although
their bandwidth is higher than that of
INA114 these devices were destroyed earlier.
The total neutron dose was 2 - 3 · 10 12 cm -2
(200Gy). the input offset voltage increases up to
6 mV, and no variation in the input bias current
has been detected.
The INA116PA is a complete monolithic

FET-input instrumentation amplifier with extremely
low input bias current, DiFET inputs
and special guarding techniques. It was quickly
depredated, and were destroyed all devices with
a total dose of 2 · 10 12 cm -2 (200Gy). Although
DiFET operational amplifiers were revealed to
be the best radiation tolerant devices [2], this
can be attributed to the low bandwidth and micropower
design technology of this device.
III. VOLTAGE REFERENCES
Several items of REF102BP and ADR290
voltage references were exposed to neutron radiation.
A 15 V power supply was used for all
devices, externally loaded to assure the 50% of
the maximum current. The output voltage and
the bias supply current for each device were
measured on line. After irradiation the inputoutput
DC transfer characteristic was determined
for all surviving devices
A. REF102BP
REF102BP is a 10 V buried Zener diode
voltage reference, from BURR-BROWN. The
nominal output voltage error is less than
±0.05%, and the quiescent current is smaller
than 1.4 mA with a maximum output current of
10 mA. Eight devices of two different fabrication
series were irradiated with a total neutron
dose between 2 and 9.9 · 10 13 n · cm -2 and a
gamma residual total dose between 1400 and
2700 Gy.
Table 2: REF102BP. Minimum input voltage
Total Dose Min. Input Voltage
0 10.8 V
2.0· 10 13 n· cm -2 1.4kGy 10.8 V
2.6· 10 13 n· cm -2 1.6kGy 12.6 V
3.1· 10 13 n· cm -2 1.8kGy 17.0 V
3.5· 10 13 n· cm -2 1.9kGy 13.1 V
5.1· 10 13 n· cm -2 2.1kGy 19.9 V
The minimum voltage supply to get the
nominal output of 10 V varies with the total
accumulated dose as showed in Table 2
Table 3: REF102BP. Quiescent current
Total Dose Quiesc. Current (mA)
0 1.30
2.0· 10 13 n· cm -2 1.4kGy 0.90
2.6· 10 13 n· cm -2 1.6kGy 0.94
3.1· 10 13 n· cm -2 1.8kGy 0.75
3.5· 10 13 n· cm -2 1.9kGy 0.88
5.1· 10 13 n· cm -2 2.1kGy 0.55
The line regulation coefficient increased
with radiation. For those items, that suffered a
total neutron dose between 2.0 and 3.5 · 10 13 n ·
cm -2 (1.7 kGy), the value for the line regulation
changed from 10 μV/V to between 10 and 20
mV/V. On the other hand, the quiescent current
varied with the total neutron dose as shown in
Table 3. All these parameters seem to be independent
of the series production.
B. ADR290GR
The ADR290 is a 2.048 ± 0.006 V low
noise, micropower precision voltage references
that use an XFET (eXtra implanted junction
FET) reference circuit. The new Analog Devices
XFET architecture claims to offer significant
performance improvements over traditional
bandgap and Zener-based references.
Three samples were irradiated to a total neutron
dose between 4.2 and 11 · 10 13 n · cm -2 . All
devices were destroyed at a value between 5 and
7 · 10 12 n · cm -2 (400Gy). Fig. 6 shows the behaviour
of the output voltage with the radiation.
Figure 6: ADR290. Output Voltage vs. radiation
The output voltage exceeds the specification
limits (± 6 mV) at a neutron dose between 2.5
and 3.5 · 10 12 n · cm -2 , 200Gy. There is a small
decrease of it in all samples, and then a hard
drop off from 1.8 to 0.7 V. This is quite similar
to other traditional voltage references as was
previously reported (REF02) [3].
All the reported references use hard radiation
tolerant devices as Zener diodes or JFET
transistors as the first stage, and the amplifying
and power stages built in bipolar technology.
This suggests to be the cause of its degradation.
Finally, the bias current decreases as the output
voltage does
IV. ANALOG SWITCHES
DG412 is a four SPST normally open
CMOS analog switches from MAXIM. It can
operate with single or bipolar supply and is
TTL/CMOS compatible. Three devices were
exposed to a neutron radiation between 4.4 and
8.8 · 10 13 n · cm -2 , and a residual gamma radiation
about 2.000 - 2.700 Gy.
Analog switches are designed with two transistors
in parallel, NMOS and PMOS, so that

the equivalent resistance is almost constant for
any voltage applied to their edges [4].
Measurements of the on resistance, the
switching voltage and leakage currents with
several bias supply’s and logic levels were carried
out on every device for the four switches
before irradiation, and after the deactivation
period (1 month later). During the deactivation
period, these circuits remained unpolarized. The
on resistances and the leakage currents were
measured on line on the devices with a bias supply
of ± 15 V and a logic level VL = +5 V.
The on line measurements are shown on
Figure 7.
Figure 7: DG412. On resistance vs. radiation
The increase of the on resistance may be attributed
either to the decrease of the mobility
and concentration of carriers caused by neutrons
or to the change in the threshold voltage of any
of the MOS transistors. The latter effect (associated
to the residual gamma radiation) could explain
that the channel cannot be closed at the
window between 2.25 and 3 · 10 13 n · cm -2 , 700
and 900 Gy.
From the on line measurements a high increment
of the leakage currents was detected,
from nanoamps up to 2 mA. However, after the
deactivation period a new measurement revealed
that the leakage currents have disappeared.
This may be associated to some annealing
effect during the cooling period.
After irradiation the operating supply voltage
V+ - V- need to be higher than a value between
11.9V and 13.4V, according to the radiation,
and VL = VCC. This effect was not detected
during the on line periods, and all switches were
operating at Vsupply = ± 15 V and VL = 5 V. This
latter degradation of CMOS devices took place
during the cooling period after irradiation due to
the movement of charges in dielectric materials.
For those devices still in operation the characteristic
of resistance as a function of the input
voltage was highly modified. Figure 8 shows
this value for a ±10V supply voltage. For a
higher supply voltage this anomalous value of
the resistance with the input voltage decreases.
Since this characteristic is similar to that of a
switch with a single operating MOS transistor
(NMOS) [4], it can be assumed that the threshold
voltage of the PMOS transistor has been
strongly modified and consequently is always
operating as an open circuit.
Figure 8: DG412. Resistance vs. Input voltage.
Furthermore, the switching voltage was
measured, and Table 4 shows the switching
level for a device that suffered a total dose of
8.8 · 10 13 n · cm -2 and 2.7 kGy.
Table 4: DG412 Switching voltage (V L = V CC).
Supply Before exp. After exp.
Bipolar ±10 V 3.03 V 1.19 V
Bipolar ±15 V 4.08 V 2.72 V
Unipolar 0-15 V 4.24 V 2.71 V
V. DAC’S
Three different models were tested (AD565,
AD667 and AD7541). The first two models
were selected for their TTL technology, fast
response and that were reported to tolerate up to
3 kGy, the first, and more than 2 · 10 12 n · cm -2 ,
the second [5, 6]. The third model was selected
for its CMOS technology.
On line output voltages measurements were
carry out as the conversion to a digital sweep
from zero to 4095. Neither offset nor gain correction
were made. The neutron dose was between
3.1 and 3.4 · 10 13 n · cm -2 , and gamma
radiation about 1.8 kGy.
C. AD565AJD
The AD565A uses 12 precision, high-speed
bipolar current-steering switches, control amplifier
and a laser-trimmed thin-film resistor network
to produce a very fast, high accuracy analog
output current. The AD565A also includes a
buried Zener reference comparable to the best
discrete reference diodes. An external amplifier
was implemented to provide a unipolar 0 to +10
volt output.
Four samples were tested in two different
sessions. The offset error remains between 5
and 8 LSB. The gain error varies with the neu-

tron radiation (Figure 9). A change lower than 5
LSB in the gain error is measured as the radiation
increases from 0 up to 3.1 · 10 13 n · cm -2 ,
1.8 kGy. Since then, the converter malfunctions.
A day after the reactor stops it recovers and the
obtained values are close to normal.
Figure 9: AD565 Gain error.
NEFF remained during all the operation between
10.5 and 11 bits. Finally, the internal reference
voltage varied 10 mV at the final radiation
period. In one of the devices, there was an
interval where the reference voltage decreased
down to 7 V, but at the end recovered the nominal
value.
D. AD667
The AD667 is a complete voltage output 12bit
digital-to-analog converter including a high
stability buried Zener voltage reference and
double-buffered input latch on a single chip.
The converter uses 12 precision high speed bipolar
current steering switches and a laser
trimmed thin-film resistor network to provide
fast settling time and high accuracy.
Figure 10: AD667. Offset error
Two samples were tested on line with radiation
up to 3 · 10 13 n · cm -2 , 1.8 kGy. The initial
offset error was less than 1.5 LSB but at a dose
of 8 · 10 12 n · cm -2 (550Gy) increases abruptly
up to 50 LSB at 1.2 · 10 13 n · cm -2 (720Gy).
Then a decrease down to 30 LSB at maximum
radiation point takes place (Figure 10). The gain
error decreases from 15 down to 10 LSB, and
the internal voltage reference increases 10 mV
in 10 V at 3· 10 13 n· cm -2 . NEFF remain between
13 and 11 bits.
E. AD7541AKN & MX7541AKN
The AD7541A is a low cost, high performance
12-bit monolithic multiplying digital-toanalog
converter. It is fabricated using advanced,
low noise, thin film on CMOS technology.
An external amplifier was implemented
to provide a unipolar 0 to - 10 volt output.
One sample from Analog Devices and another
from Maxim were tested on line with radiation
up to 3 · 10 13 n · cm -2 , 1.8kGy. All of
them were destroyed at 1.3 · 10 13 n · cm -2
(780Gy). It was reported that this converter
could be destroyed at an accumulated gamma
radiation dose of 100 Gy [6].
The offset and gain errors were constant until
a dose 9 · 10 12 n · cm -2 (600Gy) was reached,
then they increase until a total destruction. NEFF
was constant at 11 bits until 4 · 10 12 n · cm -2
(270Gy), and then decrease down to 7 bits at 1.1
· 10 13 n · cm -2 (800Gy) and then to 0 abruptly.
VI. CONCLUSIONS
Micropower design seems to decrease the
radiation tolerance of instrumentation amplifiers.
On the contrary, broad bandwidth and JFET
inputs increase the radiation hardness.
The voltage reference REF102 can operate
up to 5 · 10 13 n · cm -2 and 2.2 kGy.
Gamma radiation modifies strongly the
characteristics of analog switches.
Some bipolar DAC’s can operate without a
significant degradation (EOff

Low Dose Rate Effects And Ionization Radiation Tolerance Of The Atlas Tracker
Front-End Electronics.
M. Ullán 1,3 , D. Dorfan 1 , T. Dubbs 1 , A. A. Grillo 1 , E. Spencer 1 , A. Seiden 1 , H. Spieler 2 , M. Gilchriese 2 ,
M. Lozano 3
1 Santa Cruz Institute for Particle Physics (SCIPP), University of California at Santa Cruz, Santa Cruz, CA 95064, USA
ullan@scipp.ucsc.edu
2 Lawrence Berkeley National Laboratory (LBNL), University of California at Berkeley, 1 Cyclotron Rd, Berkeley, California
94720, USA
3 Centro Nacional de Microelectrónica (CNM-CSIC), Campus UAB, 08193 Bellaterra, Barcelona, Spain
Abstract
Ionization damage has been investigated in the IC
designed for the readout of the detectors in the Semiconductor
Tracker (SCT) of the ATLAS experiment at the LHC, the
ABCD chip. The technology used in the fabrication has been
found to be free from Low Dose Rate Effects which facilitates
the studies of the radiation hardness of the chips.
Other experiments have been done on individual
transistors in order to study the effects of temperature and
annealing, and to get quantitative information and a better
understanding of these mechanisms. With this information,
suitable irradiation experiments have been designed for the
chips to obtain a better answer about the survivability of these
chips in the real conditions of the ATLAS detector.
I. INTRODUCTION
The specific characteristics of the silicon detectors to be
used in the Inner Detector of the ATLAS experiment that will
be installed in the Large Hadron Collider (LHC) at CERN,
together with the large amount of data required to be
processed in a very short period of time, force the 'front-end'
electronics designed to do this job to be placed very close to
the actual detectors. This means, in fact, that the ICs for the
immediate data acquisition and pre-processing of the signals
coming from the detectors will be working in the active area
of the experiment, very close to the collision point. The ICs
will, therefore, be operated in a very harsh environment due to
the amount of radiation in that area.
For this reason, radiation-hard microelectronic
technologies have to be used, and the radiation hardness of the
ICs should be verified previous to the installation in the
experiment. This is the framework of this work, in which the
radiation hardness of the two bipolar microelectronic
technologies that have been proposed for the experiment is
being evaluated, and the total ionization radiation damage
expected for the ICs measured.
A basic approach to test the radiation hardness of the ICs
designed for the experiment is, in principle, to irradiate them
in a short period of time up to the total dose expected in the
real case, and then measure their performance to see if their
parameters remain within specs. The problem, however, is
usually not so straightforward. In the last years it has been
reported that bipolar transistors can suffer more radiation
damage when irradiated at low rates than when irradiated at
high rates [1], [2]. This means that an irradiation experiment
done at higher dose rates than the actual rate can
underestimate the damage. These phenomena are called Low
Dose Rate Effects (LDRE) of the bipolar transistors.
Therefore, a more conservative approach for the test
would be to irradiate the chips in the real conditions of the
experiment. Then we would have the damage in the real case.
But this possibility, though achievable in some particular
cases due to the lower doses involved, is not realistic in the
majority of the high energy physics or astrophysics
applications, in which the long term operations of the
experiments lead to high energy depositions during the whole
life of the experiment but still at very low dose rates.
This is the case of the ATLAS experiment which is
intended to operate for 10 years with a total expected energy
deposition (considering the stopping periods) of 10
Mrads(SiO2), but at a dose rate of 0.05 rads(SiO2)/s [3]. In
these circumstances an experiment to check the radiation
hardness of the chips in the real conditions would take
approximately 6.5 years which is not practical.
Many different approaches have been tried to test dose
rate effects on a bipolar technology, and late studies have
shown that high temperature irradiations at high dose rates
can mimic the effects of low dose rate irradiations [4]-[6], but
no one approach has yet been presented which covers all the
possibilities and, therefore, there is still a lack of a universal
hardness assurance approach for bipolar technologies.
Nevertheless, it has been seen that these effects are strongly
technology dependent which means that, in many cases, some
devices will not suffer from LDRE for the particular
conditions of the experiment. In such cases the first approach
described above could be used for hardness assurance studies,
avoiding a lot of trouble in complicated and long term LDRE
studies.
In this work, the ionization radiation hardness of the IC
designed for the front-end readout of the detectors of the
ATLAS-SCT (ABCD chip) is evaluated taking into account
the possible presence of Low Dose Rate Effect in the
technology (DMILL).

II. TESTING PLAN
Four experiments have been devised in order to study the
LDRE in the DMILL technology and the ionization damage
characteristics on it:
i) Experiment 0, the sensitivity to LDRE of both
technologies is evaluated irradiating test structures at a wide
range of dose rates, but only to a dose that is reasonably
achievable at the interesting low rates, 1 Mrad in our case.
ii) Experiment A, after evaluating the sensitivity of these
technologies to LDRE, the actual value of these effects is
measured for the total dose of interest, and the final damage
on the transistors measured for the full total dose at the dose
rate of interest.
iii) Experiment B, the test structures are irradiated at a
high rate up to the total dose of interest and at different
temperatures in order to identify an appropriate temperature
(optimum temperature) for the accelerated tests which best
mimics the damage produced at a low rate irradiation.
iv) Experiment C, Accelerated tests are carried out on the
ICs at high dose rate and up to the total dose of interest using
the optimum temperature if necessary.
III. EXPERIMENTAL PROCEDURES
All irradiations have been done using three different Co60
sources which provide 1.2 and 1.3 MeV gamma radiation
which is widely used in ionization damage studies. A Pb+Al
shielding box has been used together with geometrical
considerations in order to avoid dose enhancement effects
according to standards [7], [8], guaranteeing less than a 20%
systematic error in the dosimetry. Thermoluminiscent devices
(TLD) have been used, also according to standards [9], in
order to identify the irradiation positions for the different dose
rates, obtaining a statistical deviation of less than a 5%. The
devices were kept biased during irradiation in order to be
closer to the real life conditions and low mass materials have
been used for the supporting boards. The temperature control
has been provided via resistive tape heaters and liquid cooling
for actuators. Thermocouples and Resistance Temperature
Detectors (RTD) in physical contact to the chips were used
for the measurements.
The Gummel Plots and common emitter current gains (β)
of the transistors have been extracted before and after
irradiation. Consecutive measurements have been made on
every transistor, right after the irradiation, and for several
weeks later until the annealing process has been completed.
Two main parameters have been used to characterize the
damage produced by radiation [9]: the excess base current
density (∆Jb), defined as the difference between the base
current density before and after irradiation at a base-emitter
voltage of 0.7 V; and the relative beta change (∆β%), defined
as the difference in the common emitter current gain, at the
same base-emitter voltage (0.7 V), before and after irradiation
normalized to the one before irradiation. Temperature has
been controlled during the measurements to make sure that it
stays within a ±2 °C margin. Still, a commonly used
correction for small temperature differences has been used for
the base current by applying a factor to the post irradiation
value which is equal to the ratio between the pre and post
irradiation value of the collector current (which is known not
to be affected by radiation).
Test structures containing sets of bipolar transistors from
the same technology in which the ABCD [10] chip is made
have been used. Two different transistor sizes have been used
for the irradiations and small differences have been seen
between the radiation damage for each. The sizes of the
transistors tested are 1.2 µm x 1.2 µm for the “minimum”
transistor and 1.2 µm x 10 µm, for the, so called, “primary”
transistor.
IV. EXPERIMENT 0: LDRE SENSITIVITY
The purpose of this experiment is to evaluate the
sensitivity of the DMILL technology to LDRE. This first step
is extremely important because it has been seen that LDRE
are strongly technology-dependent, and in many cases a
particular technology can be free of them or at least they
might not show in the range of dose rates of interest of the
experiment. In those cases tests of radiation damage can be
done directly at high dose rates saving a lot of effort in
complicated LDRE studies.
A first study of the annealing of the damage produced by
the radiation from the moment just following the irradiation
and the damage measured after a certain time has been carried
out in order to be sure that these effects don’t interfere with
the effects produced by the low dose rates [11]. The results
show that, in all the cases, he annealing, if it appears, is
beneficial (the damage is reduced), stops after at most three
weeks, and can not be accounted for the differences in the
damage for different dose rates. In the following all the data
points represents measurements taken at least three weeks
after irradiation.
For this experiment the transistors have been irradiated at
a very wide range of dose rates and all of them up to a total
dose of 1 Mrad(SiO2) in order to obtain data even for the very
low dose rates in a reasonable period of time. The dose rates
chosen cover a range of 4 full decades and the values are:
0.05, 0.28, 1.33, 31.1, 112, 575 rads(SiO2)/s.
Figure 1: Excess base current density (∆Jb) versus dose rate for
DMILL transistors from Experiment 0.

Figure 2: Relative beta change (∆β%) versus dose rate for DMILL
transistors from Experiment 0.
The results of this experiment are shown in Figure 1 and
Figure 2 for the DMILL transistors, in which both excess base
current density (∆Jb) and relative beta change (∆β%) are
shown versus dose rate, all for the same total dose of 1 Mrad.
All the data points correspond to the final measurement after
annealing has been completed. It can be seen that there is no
evidence of low dose rate effects in these transistors, or it is
negligible. Similar plots are shown in Fig. 3 and Fig. 4 for the
CB2 transistors. It is clear in these plots that these transistors
suffer total dose effects showing appreciably more damage at
low dose rates.
V. EXPERIMENT A: MAPPING OF THE DAMAGE VS.
TOTAL DOSE
In view of the results from Experiment 0, two main
consequences can be obtained. The first one is that it is
necessary to know if there are still no LDRE for the DMILL
technology at higher doses; and the second one is that an
estimation of the extent of these effects is necessary for the
CB2 transistors.
For both of these measurements long term, low dose rate
irradiations should be done up to the total 10 Mrads and at
0.05 r/s dose rate, which are the real conditions in ATLAS-
SCT. These experiments are not realizable because they
would take too long to give results. A solution to the problem
is to map out the damage on the transistors vs. the total dose
taking intermediate measurements of the damage for
increasing total doses up to 10 Mrads. This way one can
perform low dose rate irradiations up to a certain achievable
total dose and estimate the damage at the final total dose by
extrapolation. Furthermore, one can see if irradiations done at
different dose rates lead to a “rigid” shift of the curves or, on
the contrary, they change the shape or slope of them. If the
curves suffer rigid shifts for different dose rates, we can be
assured that the differences between low and high dose rate
irradiations are maintained for high total doses.
The conditions of the four different mapping experiments
that have been performed for this purpose can be seen in
Table 1.
Table 1: Conditions of the four mapping experiments.
In Figure 3 and Figure 4 we can see the results of these
experiments in terms of the excess base current density and
the relative beta change. It can be seen that for all dose rates
the excess base current density is linear vs. total dose for a
logarithmic plot on both axis (dependency type: ∆Jb ∝
(dose) a ; a = constant). The relative beta change follows also a
linear dependency with total dose but in this case for only a
logarithmic abscissas axis (dependency type: ∆β ∝ log(dose)).
It also can be seen that the graphs for all four irradiations are
parallel, and in fact superposed, meaning that the damage is
the same for all transistors regardless of the dose rate and for
the whole range of doses, indicating that there are no LDRE
for these transistors up to 10 Mrads.
Figure 3: Excess base current density (∆Jb) versus dose rate for
DMILL transistors from Experiment A.
Figure 4: Relative beta change (∆β%) versus dose rate for DMILL
transistors from Experiment A.

The results show that the figures for the total ionization
damage of the bipolar transistors of the DMILL technology
are 8 x 10 -10
A/cm 2
for the excess base current density and
-45% for the beta change, giving a final value of the
transistors current gain (for the emitter sizes used in the
experiments) around 90 to 125.
VI. EXPERIMENT B: TEMPERATURE
Given the fact that Experiment A has demonstrated that
the DMILL technology doesn’t suffer from LDRE at least up
to the conditions of interest for ATLAS-SCT, it can be
concluded that accelerated tests are not necessary for the
hardness assurance testing of the ABCD chip. Therefore it is
not necessary to find the optimum temperature for these
irradiations, which was the initial goal of Experiment B.
Figure 5: Excess base current density (∆Jb) versus temperature for
DMILL transistors from Experiment B.
Figure 6: Relative beta change (∆β%) versus temperature for
DMILL transistors from Experiment B.
Nevertheless, a set of experiments at different
temperatures has been carried out with the bipolar transistors
of this technology in order to obtain the variations of the
damage in the transistors for different temperatures of
irradiation. The actual working temperature of the chips in the
real ATLAS-SCT environment is not as yet fixed, and a low
optimum (worst case) temperature with a sharp slope in the
damage at low temperatures would make the hardness
assurance testing more difficult.
Different irradiations have been done of the bipolar
transistors all of them up to the total ATLAS-SCT dose of 10
Mrads and at a very high dose rate (575 rads/s). The
temperatures used in the study have been: 11, 37, 57, 70, 91,
and 110 °C.
Figure 5 and Figure 6 show the results of Experiment B
for the test structures of the DMILL technology. It can be
seen that the worst case temperature appears at around 90 °C
which is a high enough temperature for the slope to be smooth
at low temperatures. Nevertheless, it can be seen that de
different in the damage for an irradiation done at the expected
actual working temperature of the ICs at the ATLAS-SCT (10
°C), and an irradiation at room temperature is appreciable, and
should be taken into account in future irradiation tests of the
ABCD chips.
VII. EXPERIMENT C: FINAL TEST
The Results from Experiment A and Experiment B
demonstrate that the DMILL technology is free from LDRE at
the range of total doses and dose rates of interest in the
ATLAS-SCT experiment, and that the difference in the
damage for the actual operating temperature and room
temperature is low. This results validates the previous high
dose rate irradiation tests carried out by the collaboration with
that result that the ABCD chip remains under specifications
for the total life of operation [12].
Nevertheless, the actual ABCD chips have been irradiated
in order to obtain the figure the damage produced on them by
10 Mrads of ionization radiation. The irradiations have been
done at high dose rate (575 rads/s), up to the total dose of 10
Mrads and at room temperature. The results from these
irradiations are currently being analyzed.
VIII. CONCLUSION
The technology used in the fabrication of the ICs proposed
for the front-end readout of the ATLAS-SCT (DMILL) has
been tested for ionization damage and considering low dose
rate effects. The results show that this technology, used in the
fabrication of the ABCD chip, does not suffer from LDRE, or
at least by a negligible amount. This result indicates that
irradiations performed to test the radiation tolerance of the ICs
can be done at high dose rates without underestimating the
damage to the chips. This will save much effort in long term
irradiations or accelerated tests.
The results also show that the variation of the damage
produced on the chips for different irradiation temperatures
are not very large for the range of low temperatures, but still
should be considered if the chips are in the edge of their
survivability after the irradiation tests.
Finally, the non-existence of LDRE in the DMILL
technology validates and confirms the results of previous
irradiation tests within the collaboration indicating that the

ABCD chip will remain under specifications after he 10 years
of operation in the ATLAS-SCT environment.
REFERENCES
[1] E. W. Enlow, et al. “Response of Advanced Bipolar
Processes to Ionizing Radiation”, IEEE Trans. on
Nuclear Science, V.38, 1342 (1991)
[2] R. D. Schrimpf, “Recent Advances in Understanding
Total-Dose Effects in Bipolar Transistors”, IEEE Trans.
on Nuclear Science, June 96, p. 787.
[3] ATLAS Inner Detector Technical Design Report (TDR),
CERN/LHCC/97-16/17, April 1997.
[4] S.C. Witczac, et al., “Accelerated Tests for Simulating
Low Dose Rate Degradation of Lateral and Substrate
PNP Bipolar Junction Transistors”, IEEE Trans Nuclear
Science, Dec. 96, pg. 3151.
[5] O. Flament, et al., “Ionizing dose hardness assurance
methodology for qualification of a BiCMOS technology
dedicated to high dose level applications”, IEEE Trans.
Nuclear Science, Dec. 98, p. 1420.
[6] S.C. Witczac, et al., “Hardness Assurance Testing of
Bipolar Junction Transistors at Elevated Irradiation
Temperatures”, IEEE Trans. Nuclear Science, Dec. 97,
p. 1989.
[7] “Minimizing Dosimetry Errors in Radiation Hardness
Testing of Silicon Electronic Devices Using Co-60
Sources”, Annual Book of ASTM Standards, American
Society For Testing And Materials (ASTM), E 1249–93,
1993.
[8] “Standard Guide for Ionizing Radiation (Total Dose)
Effects Testing of Semiconductor Devices”, Annual
Book of ASTM Standards, American Society For
Testing And Materials (ASTM), F 1892–98, Nov. 98.
[9] “Application of Thermoluminiscence-Dosimetry (TLD)
Systems for Determining Absorbed Dose in Radiation-
Hardness Testing of Electronic Devices”, Annual Book
of ASTM Standards, American Society For Testing And
Materials (ASTM), E668–97, 1997.
[10] W. Dabrowski, et al. “Design and performance of the
ABCD chip for the binary readout of silicon strip
detectors in the ATLAS Semiconductor Tracker”, Proc.
of 1999 IEEE Nuclear Science Symposium, Seattle,
Washington, USA, Oct 1999.
[11] D. Dorfan, et al. “Measurement of Dose Rate
Dependence of Radiation Induced Damage to the
Current Gain in Bipolar Transistors”, IEEE Trans. on
Nuclear Science, Dec. 99, p. 1884.
[12] E. Chesi, et al. “Performance of a 128 Channel Analogue
Front-End Chip for Readout of Si Strip Detector
Modules for LHC Experiments”, IEEE Trans. on
Nuclear Science, Aug. 00, p. 1434.

Use of antifuse-FPGAs in the Track-Sorter-Master
of the CMS Drift Tube Chambers
R. Travaglini, G.M. Dallavalle, A. Montanari, F. Odorici, G.Torromeo, M.Zuffa
Abstract
The Track-Sorter-Master (TSM) is an element of the onchamber
trigger electronics of a Muon Barrel Drift Tube
Chamber in the CMS detector. The TSM provides the
chamber trigger output and gives access to the trigger
electronic devices for monitoring and configuration.
The specific robustness requirements on the TSM are met
with a partitioned architecture based on antifuse-FPGAs.
These have been successfully tested with a 60 MeV proton
beam: SEE and TID measurements are reported.
h
D = 23.7 cm Xcor
1
2
BTI
3
4
5
6
INFN and University of Bologna Italy
40137 v.le B.Pichat 6/2, Bologna, Italy
Riccardo.Travaglini@bo.infn.it
Out 0 Out 1 Out 2 Out 3 Out 4 Out 5 Out 6 Out 7 Out 8 Out 9 Out 10 Out 11
Kcor
7
8
TRACO
x
In 0 In 1 In 2 In3
TRIGGER SERVER
9
A
B
C
D
x 32
BTI
BTI
Outer
Layer
Inner
Layer
Outer SL
Inner SL
x 32
TRACO
TRACO
TRACO
TRACO
BTI
2
I. INTRODUCTION
The trigger electronics of a Muon Barrel Drift Tube
chamber [1] of the Compact Muon Solenoid (CMS) detector
is a synchronous pipelined system partitioned in several
processing stages, organized in a logical tree structure and
implemented on custom devices (Fig. 1).
The Track-Sorter-Master of the Trigger Server [2] is the
system responsible for the trigger output from the chamber
and for the trigger interface with the chamber control unit.
sel
TSS
Phi Trigger Board 1
BTI
Theta Trigger Board 1
9
previews
5
2
3
4
5
6
7
TST
2
2
9+2
previews
Server Board
TSMS
16
sel
25
full tracks
TSMD
TSMD
25
full tracks
Figure 1: CMS Drift Tube on-chamber trigger electronics overview. The upper right picture, named Server Board, is a block diagram
representation of the Track-Sorter-Master system.
30 bit
20 bit
To Sector
Collector

Since the TSM system is the bottleneck of the trigger
electronics of a muon chamber, a principal requirement it has
to fulfil is robustness; it should also be fast in order to
minimize the trigger latency.
Moreover, the system should stand the radiation dose
expected for 10 years of running of the muon chambers in
CMS at the Large Hadron Collider.
In the following we show that this can be achieved with a
highly partitioned architecture that utilizes antifuse-FPGAs.
A. Architecture
II. TRACK-SORTER-MASTER
ARCHITECTURE AND DESIGN
In order to match the robustness requirement, the system
is segmented in blocks with partially redundant functionality
(Fig. 2). We favour an architecture where the TSM consists of
three parts: a Selection (TSMS) block, two Data multiplexing
(TSMD) blocks (called TSMD0 and TSMD1, covering half a
chamber each). The TSMS receives Preselect Words (PRW)
carrying the information of the first stage of sorting performed
by the Track Sorter Slave (TSS) units [2]. The TSMDs have
as an input the full TRACO data of the track segments
selected by the TSSs.
Figure 2: Track-Sorter-Master block diagram. Architecture and
I/O signals are shown.
The TSM can be configured into two distinct
processing modes:
• Default processing: theTSMSperformsasasorter
while the TSMDs act as data multiplexers. The
TSMS can select two tracks in TSMD0 or two
tracks in TSMD1 or one track each.
• Back-up processing: the TSMS is inactive. Each
TSMD performs as sorter and as multiplexer on
data from a half chamber. Each TSMD outputs
one track.
The Default processing implements the full performance
and guarantees that dimuons are found with uniform
efficiency along the chamber. In case of failure of one TSMD,
the PRWs of the corresponding half chamber are disabled in
TSMS sorting, so that full efficiency is maintained in the
remaining half chamber.
The Back-up processing mode is activated in case of
TSMS failure. It guarantees full efficiency for single muons
and for open dimuon pairs (one track in each half chamber).
B. Design
In the hardware design the TSMS, TSMD0 and TSMD1
blocks are implemented as three distinct ICs. Each block has
independent power lines. Three separate lines, from the
chamber Controller, are used to provide enable signals
(nPWRenSort, nPWRenD0 and nPWRenD1) for the power
switches. When one IC is powered down, also all I/O lines to
the chip are disconnected via bus isolation switches driven
with the same enable signals. For this purpose highly reliable
switches with very large MTBF are used. Three independent
power fault signals are generated and reported to the
Controller when an overcurrent condition is detected in the
corresponding power net.
The TSM processing configuration can be changed from
the Controller by acting directly on the power enable signals.
The TSMS also receives the power enable state of the
TSMD0 and of the TSMD1, then it can change its processing
mode to select two tracks from the same TSMD, when the
other TSMD is powered off. Similarly each TSMD receives
the power enable state of both the TSMS and the other
TSMD, and it can switch to the back-up processing mode
when the TSMS is not powered. The system can still run in
the extreme scenario of only one functioning TSMD block
and its connections undamaged.
The processing mode is selected via configuration
registers in all three devices. Registers are also used for the
set-up of the sorting and the fake-rejection algorithms. Access
to the configuration registers is possible in two independent
ways: through a serial JTAG net for boundary scan and
through the DT parallel access bus with an ad-hoc protocol,
hereafter called Parallel Interface (PI).

Figure 3(a) shows the JTAG net through the three ICs: the
net can be configured to run only through the chips that are
powered on, using isolation switches controlled via the power
enable lines.
Figure 3(b) shows how the PI bus is distributed through
the TSM system; each IC has its own TSM address. The PI
commands from the chamber Controller are forwarded to the
other trigger boards in the same chamber (Fig. 1) through the
TSMS. The TSMS gives access to only one trigger board in
turn. In case of TSMS failure the trigger boards can still be
configured via their individual JTAG nets. The PI utilises the
same lines used for propagating the PRW data; the PRW bus
is bi-directional.
(a)
TDI
(b)
TMS
TCK
JADD(3:0)
BADD(3:0)
isol isol
nPWRenD0 nPWRenD0 nPWRenD1 nPWRenD1 nPWRenSort nPWRenSort
From Controller
PICD(7:0)
isol isol isol isol isol isol
TSMD0 TSMD1 Sorter
nProg,Strobe,nWrite
nPWRenD0 nPWRenD1
Figure 3: (a) TSM JTAG Net
(b) TSM Parallel Interface Net
isol isol isol
nPWRenD0
isol
nPWRenSort
isol
nPWRenD1
isol
A. Choice of technology
TSMD0
Sorter
TSMD1
Strobe_0
Strobe_6
nWrite
III. IMPLEMENTATION
The most important aspect is the choice of technology in
developing the TSMS and TSMD ICs.
There is one TSM system in each DT chamber, that is a total
of 250 TSMS and 500 TSMD ICs in the entire muon barrel
detector of CMS [1]. This is a too limited production volume
for justifying the risk of developing two ASICs
Boundary Scan JTAG
isol
nPWRenSort
Parallel Interface Data Flow
nPWRenSort
isol
isol
x 7
TD0
To TRB_0
To TRB_6
TSM addressing:
Global address, then
Individual address
The use of FPGAs has two advantages:
• The same type of device can be used for both the
TSMS and the TSMD, because the chosen

architecture requires a comparable number of pins
for both ICs.
• It leaves flexibility for fine-tuning of the sorting
and ghost rejection algorithms.
However standard FPGAs are disfavoured because of their
low level of radiation tolerance, which can easily result in
erasure and uncontrolled corruption of the programmed logic.
A solution is the antifuse-FPGAs, also called pASICs
(programmable ASICs). They are based on silicon antifuse
technology: silicon logic modules in a high density array are
interconnected using 3 to 4 metal layers where metal-to-metal
amorphous silicon interconnect elements (the antifuses) are
embedded between the metal layers. The antifuses are
normally open circuit and, when programmed, form a
permanent low-impedance connection. Once programmed, the
chip configuration becomes permanent, making it effectively
like an ASIC.
The Actel A54SX32 [3] device was chosen.
The small dimensions of the board constitute an other
design constraint. Therefore, we have built a full-functionality
prototype board (Fig. 4) with final dimensions (98x206 mm 2 ).
It has been possible to find a placement of the components
that allows efficient routing and good high-frequency
behaviour, using six signal layers and a standard 5 mils
routing technology. This final prototype is under test.
Figure 4: PCB prototype for the Track-Sorter-Master. The larger
chip on the right side is an A54SX32 programmed as TSMS. Places
to host both TSMDs are visible.
A. Program of tests
IV. IRRADIATION TEST
The Actel A54SX chips have been chosen for building the
TSM after a test of their radiation tolerance has been
performed. Samples have been exposed in the 59 Mev proton
beam of the Cyclotron Research Centre (CRC) at the
Universite Catholique de Louvain (UCL), in Louvain-la-
Neuve, Belgium, in October 2000. At this energy 10 10
protons/cm 2 correspond to a dose of 1.4 krads.
B. Test Setup
Four pASICs, each implementing a 450-bit register,
refreshed and monitored at 1 MHz, have been irradiated up to
40 krads/chip (one of them up to 70 krads). The register size
of 450 bits is similar to that of registers in both the TSMS and
TSMD chips.
Figure 5 shows the set-up used for these tests. Pattern Unit
(PU) [4] is a high-throughput VME board, acting as pattern
generator and as read-out module.
Figure 5: Irradiation test set-up.
C. Results
There has been no failure and no latch-up.
The Total Irradiation Dose (TID) result is summarised in
figure 6: no significant increase in current is observed for
doses well above that of a few krads expected for the CMS
barrel muon chambers in 10 years of LHC operation [5].
We have observed one Single Event Upset. The event has
been recorded and studied off-line. The 450 bit register dump
shows that in the event about 1/3 of the flip-flops have
changed state, with no obvious correlation in pattern. With the
help of Actel CAD tools, we have inferred that most probably
the internal clock distribution to the register cells has failed.
Because of this, we quote a SEU cross-section
measurement per chip instead of per bit. According to the

procedure established in [5], we can use this measurement for
estimating the SEU rate in CMS.
Icc (mA)
20
15
10
5
Actel A54SX32-3PQ208 TID test
Oct.2000
0
0 10 20 30 40 50 60 70
krads
Figure 6: Irradiation test set-up.
chip1 3.3 V
chip2 3.3 V
chip3 3.3 V
chip4 3.3 V
chip15V
chip25V
chip35V
chip45V
With one observed event and a total fluence of 1.4 10 12
protons/cm 2 , we calculate a SEU cross-section upper limit (at
90% c. l.) of
σSEU

Neutron Radiation Tolerance Tests of Optical and Opto-electronic Components for the
CMS Muon Barrel Alignment
Baksay, L. 1 Bencze, Gy. L. 3 Brunel, L. 4 Fenyvesi, A. 2 Molnár, J. 2 Molnár, L. 1 Novák, D. 5
Pszota, G. 1 Raics, P. 1 and Szabó, Zs. 1
1 Institute of Experimental Physics, Debrecen University, Debrecen, Hungary H-4001
2 Institute of Nuclear Research (ATOMKI), Debrecen, Hungary H -4001
(e-mail: jmolnar@atomki.hu)
3 Institute of Particle and Nuclear Physics, Budapest, Hungary H -1525
CERN, CH-1211 Geneva 23, Switzerland
4 Institute of Experimental Physics, Debrecen University, Debrecen, Hungary H-4001
CERN, CH-1211 Geneva 23, Switzerland
5 Royal Institute of Technology (KTH), SCFAB, S - 106 91 Stockholm, Sweden
Abstract
Neutron irradiation tests were performed with broad
spectrum p(18MeV)+Be neutrons (En

The optical and opto-electronic components will have to
work in a radiation environment, where the highest expected
flux of the neutron component is about 1.0E+03 n/cm2/sec,
and the estimated time of operation is 5.0E+10 sec.
The total expected neutron fluence is 2.6E+12 n/cm2 and
8.0E+13 n/cm2 for the Barrel Muon and ME1/1 chambers,
respectively [1]. Radiation damage induced by neutrons can
alter electrical and optical characteristics of the components
and thus the accuracy of the whole BAM system.
Our present paper addresses some key issues for the cost
effective use of COTS electronic components in radiation
environments that enable CMS Alignment system designers to
manage risks and ensure final success [3,4].
II. EXPERIMENTAL TECHNIQUES
A. Samples tested
LED light source
Low current high intensity point-like LED light sources
emitting at 660 nm were selected for construction of lighting
panels of BAM system, type: FH1011, Stanley Electric Co.
Ltd [5].
LED driver
The A6775 circuit is intended to use for LED -display
applications [6]. Each BiCMOS device includes an 8-bit
CMOS shift register, accompanying data latches, and eight
NPN constant-current drivers. The serial CMOS shift register
and latches allow direct interfacing with microprocessorsystem.
CMOS serial data output permits cascade connections
in applications requiring additional drive lines. The LED drive
current (max. 90mA) is determined by user’s selection of a
single resistor.
Microcontroller
The PIC16F84 is a high-performance, low cost, CMOS,
fully static 8-bit microcontroller [7] with 1kx14 EEPROM
program memory and 64-byte EEPROM data memory. The
high performance of the PIC16F84 can be attributed to
number of architectural features commonly found in RISC
microprocessors. The chip uses a Harvard architecture, in
which, program and data are accessed from separate
memories. This improves bandwidth over traditional von
Neuman architecture where program and data are fetched
simultaneously. Separating program and data memory further
allows instructions to be sized differently than 8-bit wide data
word. In PIC16F84, op-codes are 14-bit wide making it
possible to have all single word instructions. A 14-bit wide
program memory access bus fetches a 14 -bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution of instructions. Consequently, all instructions
execute in a single cycle except for program branches. The
PIC 16F84 has four interrupt sources and an eight-level
hardware stack. The peripherals include an 8-bit timer/counter
with an 8-bit pre-scaler, 13 bi -directional I/O pins and a
separate watchdog timer (WDT). The watchdog timer is
realised as a free running on-chip RC oscillator that does not
require any external components. That means that the WDT
will run, even if the clock on the oscillator pins of the device
has been stopped. A WDT timeout generates a device RESET
condition. The high current drive of I/O pins help reduce
external drivers and therefore, system cost.
Video camera
The VM5402 is a complete video camera [8] based on the
highly integrated VV5402 monochrome CMOS sensor chip
[9]. The module is suitable for applications requiring a
composite video signal with minimum external circuitry. The
camera incorporates a 388x295 (12micron x 12micron) pixel
image sensor and all necessary support circuits to generate
fully formatted composite video signal into a 75 Ohm load.
Automatic controls of exposure, gain and black level allow
use of a single fixed-aperture lens over a wide range of
operating conditions. Automatic exposure control is achieved
by varying pixel current integration time according to the
average light level on the sensor. This integration time can
vary from one pixel clock period to one frame period. Pixels
above a threshold white level are counted every frame, and the
number at the end of the frame defines the image exposure. If
the image is other than correctly exposed, a new value for
integration time is calculated and applied for the next frame.
Optical lens
The lenses were plano-convex single lenses made of BK7
glass without coating. Their nominal focal length was 30.7mm
and their diameter was 10 mm.
B. Irradiation circumstances
Neutron irradiations were done at the neutron irradiation
facility [10] at the MGC-20E cyclotron at ATOMKI,
Debrecen with p(18MeV)+Be reaction. Neutrons with a broad
spectrum (En

c) voltage ON/OFF alternating in ratio to 1/19 for testing of
the LED light-sources . The LED power rails were monitored
using digital multimeters equipped with serial communication
interface that allows automatic measurement of the LED
current. The nominal current were checked post irradiation if
any total dose degradation has occurred. Before and after
irradiation the optical properties (light yield, intensity
distribution, wavelength of the emitted light) of the diodes
were measured and evaluated with a commercial PC based
image analysing system.
In order to determine the radiation tolerance of the chip
itself the LED driver circuit was also investigated separately
from the PIC microcontroller. For this purpose the special setup
was constructed consisting of a Power -PC with serial RS-
232/I 2 C/RS-232 bus converter and interface for measuring the
current consumption of the circuit automatically. The current
source outputs of the LED driver were terminated using
radiation tolerant resistors as replacing of the LEDs. Using
special ON/OFF codes for up dating the content of the serial
8-bit register inside the chip resulted in a direct possibility to
detect bit errors by measuring the total current only.
The most important electronic component of the Barrel
Alignment Control system is the PIC16F84 microcontroller
that is an advanced highly scaled sensitive device. As it will
work in a radiation environment, its rad iation tolerance is one
of the most crucial questions. The errors and Single Event
Upsets (SEU) in these kind of systems may not be observed,
may cause data corruption, or may alter program flow
depending on the location of the upset [12]. The consequence
of these upsets is dependent on the criticality of the function
performed by the system.
The SEU characterisation of the microcontroller was
performed by using a special test set-up. The test system
based on the PC equipped with the whole necessary
measuring and communication devices was placed outside the
irradiation area in 30 -meter distance from the devices under
test. The special test code developed and run on the PC was
able to communicate with the controller trough the I 2 C bus
regularly sending special commands and data associated with
it. After a fixed irradiation time (1-10 minutes) the content of
the registers of the PIC was read back and compared to the
initial values. If the register content was changed by the
radiation, i.e. the expected and received values differed, the
errors with time stamps were registered in a report file before
the register was filled again in the next irradiation cycle.
The watchdog timer as one of the useful functions of the
microcontroller was intensively used during the irradiation as
basic indicator of the system general failure. The supply
current of the PIC was automatically measured and compared
to the reference value. In case of higher current consumption,
then the default value, i.e. due to the Total Ionising Dose
(TID) effect the test set-up was able to interrupt the
measurement by switching off the voltage.
The compact monochrome VM5402 video camera
together with the related circuits was tested on-line during the
full irradiation period. An automatic radiation damage
monitoring system was developed and used for
characterisation of the radiation tolerant ability of the device.
The system was based on a video-monitor and a videotape
recorder in order to record the video signal for off-line coding
and evaluation. In direct connection with the monitoring
system a PC equipped with a Frame Grabber card was used
for capturing and digitising of the video frames periodically in
every 1 minute. The actual current consumption of the camera
was measured to avoid the TID threshold of the device.
During the camera irradiation measurements different modes
of operation were investigated similarly to the LED’s tests.
D. Optical set-up and measurement
The focal length (and thus indirectly the refractive index)
and spectral transmission characteristics of the lenses was
measured before and after irradiation. A He-Ne laser was used
for focal length measurements. A high-pressure xenon arc
lamp was employed as light source for the spectral
transmission measurements. A calibrated Si-UV detector was
used to measure spectra.
III. RESULTS AND DISCUSSIONS
A. Electronic measurements
Low current high intensity point-like LED light sources
emitting at 660 nm were irradiated up to 2.6E+12 n/cm2.
Three modes of operation were studied: a) voltage ON
permanently, b) voltage OFF permanently and c) voltage ON
for 1 sec and OFF for 19 sec. For all of these modes of
operation, the light yield decreased almost linearly as a
function of the neutron fluence and approximately 50 %
decrease was observed at the end of the irradiation. No other
change in the electrical and spectral characteristics was
measurable (Figure 2).
P/P0
1.2
1
0.8
0.6
0.4
0.2
0
0 0.5 1 1.5 2 2.5 3
Neutron fluence [ x 10 12 cm -2 ]
Figure 2. Light yield of the LED vs. neutron fluence
LED current driver and controller electronics with
Microchip PIC16F84 microcontroller were irradiated up to
8.0E+13 n/cm2. Some 20 % loss of the output currents of the
LED controllers was observed at the end of the irradiation
(Figure 3).

Current (mA)
6
5
4
3
2
1
0
0.00E+00 2.00E+13 4.00E+13 6.00E+13 8.00E+13 1.00E+14
Neutron fluence (cm -2 )
Figure 3. Current of the LED driver vs. neutron fluence
The degradation of the current drivers was negligible
below 1.0E+11 n/cm2 (the expected fluence at the position of
operation of the device). Two microcontrollers were studied.
Both became damaged only after delivering ~ 2.0E+13 n/cm2
neutron fluence to them as the dramatically increased current
consumption of the electronics indicated (Figure 4).
Current (mA)
30
25
20
15
10
5
0
0.00E+00 2.00E+13 4.00E+13 6.00E+13 8.00E+13 1.00E+14
Neutron fluence (cm -2
)
I0
I0-I1
I0-I2
Figure 4. Current consumption of LED driver & controller
electronics vs. neutron fluence
I1
I2
VM5402 video cameras with VV5402 CMOS sensor
device were irradiated with a fluence up to 2.8E+12 n/cm2.
The radiation damage of the sensor resulted in the altered
nearly Gaussian distribution of the light sensitivity of the
individual pixels in all modes of operation. The mean values
decreased while the sigma values increased in all three modes
(a) voltage on per manently, b) voltage off permanently and c)
voltage on for 1 sec. and off for 19 sec (see Table 1).
Table 1. Homogenity of the video sensor (Parameters of the
nearly Gaussian distribution of the sensitivity of the individual
pixels)
DC
permanently
ON
DC
periodically
ON
(5 % in total)
DC
permanently
OFF
Before
irradiatio n
Mean
Sigma
230.18
1.20
211.85
1.31
238.09
0.81
After
irradiation
Mean
Sigma
153.22
2.58
158.45
2.06
210.39
1.51
Before/After
irradiation
Mean
Mean
66.6 %
74.8 %
88.4 %
The observed nonlinearity of the output signal vs. light
intensity was not radiation-dependent. Apart from the general
sensitivity loss, the spectral sensitivity of the sensor did not
change (Figure 5).
Figure 5. Typical picture of the video camera at the beginning
of the neutron test. Tracks of recoils could be observed
frequently

B. Optical measurements
Plano-convex single optical lenses were irradiated up to
8.0E+13 n/cm2. They were made of BK7 glass without
coating and their diameter was 10 mm. No measurable change
of the spectral transmission and the refraction (focal length)
was observed.
IV. CONCLUSIONS
Neutron radiation tolerance of COTS optical and optoelectronic
components to be used in the CMS Muon Barrel
Alignment system was studied with broad spectrum
p(18MeV)+Be neutrons (En

Radiation test and application of FPGAs in the Atlas Level 1 Trigger.
Abstract
The use of SRAM based FPGA can provide the benefits of
re-programmability, in system programming, low cost and
fast design cycle.
The single events upset (SEU) in the configuration
SRAM due to radiation, change the design's function obliging
the use in LHC environment only in the restricted area with
low hadrons rate.
Since we expect in the Atlas muon barrel an integrated
dose of 300 Rads and 5.65 . 10 9 hadrons/cm 2 in 10 years, it
becomes possible to use these devices in the commercial
version. SEU errors can be corrected online by reading-back
the internal configurations and eventually by fast reprogramming.
In the frame of the Atlas Level-1 muon trigger we
measured for Xilinx Virtex devices and configuration
FlashProm:
• The Total Ionizing (TI) dose to destroy the devices;
• Single Event Upset (SEU) cross section for logic and
program cell;
• An upper limit for Latch-Up (LU) event.
With the expected SEU rate calculated for our
environment we found a solution to correct online the errors.
System Description
The Atlas level-1 muon trigger [1],[7] is based on
dedicated, fast and finely segmented muon detectors (RPC).
V.Bocci (1) , M. Carletti (2) , G.Chiodi (1) , E. Gennari (1) ,
E.Petrolo (1) , A.Salamon (1) , R. Vari (1) ,S.Veneziano (1)
(1) INFN Roma, Dept. of Physics,
Università degli Studi di Roma “La Sapienza”
p.le Aldo Moro 2, 00185 Rome, Italy
(2) INFN Laboratori Nazionai Frascati,
Via Enrico Fermi 40, Frascati (Roma)
The system is segmented in 832 trigger and readout
modules (PAD) and 832 splitter modules used to fan-out the
FE signals located in the RPC zones.
The main components of the PAD are:
• The four coincidence matrix chip (CM)
• The Pad logic chip (PL)
• The fieldbus interface based on CANBus ELMB
• The optical link.
The CM chip selects muon with predefined transverse
momentum using fast coincidence between strips of different
planes.
The data from two adjacent CM in the η projection and
the data from the two corresponding CM chip in the
Figure 1. RPC location in the Atlas experiment.
φ projection are combined in the Pad Logic (PL) chip. After
the measurements of the characteristic of FPGA devices in a
radiation environment, we decided to use for the Pad Logic
chip. Pad logic chip, covers a region ∆ηx∆φ = 0.2x0.2,
associates muon candidates with a region ∆ηx∆φ=0.1x0.1

(RoI). It selects the higher triggered track in the Pad solves
overlap inside the Pad and performs the readout of the CM
matrix data.
I. RADIATION ENVIRONMENT
The radiation dose accumulated on the muon spectrometer
depends from the zone. The simulated radiation levels [2] for
ten years of operation of the Atlas muon detectors for various
RPC chamber without safety factor is given in table 1. The
Table 1: Table 1: Simulated radiation
environment in ten years of operation
SRLtid
SRLsee
(Gy 10y -1 ) (>20 MeV
h cm -2 10y -1 )
BMF 3.02E+00 4.69E+09
BML 3.04E+00 5.65E+09
BMS 3.03E+00 4.73E+09
BOF 1.19E+00 4.08E+09
BOL 1.33E+00 4.21E+09
BOS 1.26E+00 4.10E+09
simulated maximum value over 10 years of operation for TID
(Total Ionizing Dose) is 3.04 Gy (304 Rad) and a total flux of
5.65 . 10 9 hadrons.
II. XILINX VIRTEX AND FLASHPROM ARCHITECTURE.
The Xilinx Virtex devices [3] have a regular architecture
that comprises an array of configurable logic blocks (CLBs)
surrounded by programmable input/output blocks (IOBs).
CLBs interconnect through a general routing matrix
(GRM). The GRM comprises an array of routing switches
located at the intersections of horizontal and vertical routing
channels. The VersaRing I/O interface provides additional
routing resources around the periphery of the device. This
routing improves I/O routability and facilitates pin locking.
The configuration of each CLB and IOB and the
interconnection between different elements is programmed
using a substrate of SRAM cells. The Virtex devices are
custom built by loading configuration data into these internal
SRAM cells. The numbers of configuration flip-flop exceed
the number of logic flip-flops inside CLB and IOB of one
order of magnitude.
In the master and selectmap mode it is possible to program
the Virtex using an external nonvolatile memory with
programmed inside the custom built design.
The 18v02 memory devices are using CMOS FLASH
process for memory cell. The Flash process leaves the
possibility to reprogram the device and appear to be resistant
to SEU and TID. The high data bandwidth between the
Flashprom and the Virtex device give the possibility to
reprogram the FPGA in few milliseconds.
III. SEE TEST AT THE CYCLOTRON OF
LOUVAIN-LA-NEUVE
A. Measure of logic Flip/Flop hadrons cross
section.
The XCV200 Xilinx Virtex FPGA and the 18v02 Flashprom
[4] were irradiated with 60 MeV protons at the CYClotron of
LOuvain-la-NEuve (CYCLONE) of theUniversité Catholique
de Louvain, in Belgium. To perform such irradiation a special
prototype board containing a XCV200 and a flashprom 18v02
were used (Figure 3).
The main purpose was to study SEE effects on the logic flipflops
in the configuration area and in the flash memory.
Figure 3. XCV200 Bga352 prototype
board.
The Virtex was programmed (Figure 4.) with a 2048 bits
circular shift register at the reset loaded with a 1010…10
pattern.
A very small part of the logic was dedicated to correct SEU
errors and do detect such type of events
The circular shift circuit is very sensitive to SEU in the
program area any break in the flips-flops chain stop the
regular function.
Figure 4. The circular shift register circuit
used to determine the flip-flops logic cross
section.

Two devices were programmed with this circuit and
clocked using a 40 MHz clock. After an exposition to
Figure 5. SEU events in logic flip-flops. Zero
to One transition and one to zero transition.
6.14 . 10 10 protons/cm 2 we observed five SEU events like
Figure 5 and 23 events like figure 6.
The signature of events in Figure 5 is typical of a logic
Figure 6. The circuit stop after a SEU in
the program area.
flips-flops SEU instead the Figure 6 events shown a stop in
the normal behavioral of the circuit caused from an error in
the Virtex program. From this test the logic flip-flop
Xsection/bit=3.98*10 -14 cm 2 .
No Latch-up events were observed.
B. Measure of SEUs in the Flashprom.
A total fluence of 8 . 10 11 protons/cm 2 was divided among four
18v02 2 Mbit flashprom devices. No SEU was observed with
a limit for the Xsection/bit < 6 * 10 -19 cm 2 .
At about 2*10 11 protons (corresponding to a total dose of
28 Krad for protons of 60 Mev in silicon) the programming
feature stop to work.
C. Measures of SEUs in the Virtex program
memory.
Two devices were programmed with the circular shift
register and irradiated with the 60 Mev protons beam.
We perform a read back of the device using the fast
selectmap mode. We do the comparison between the read-
back stream and the original one, masking the meaningless bit
as specified from xilinx documentation [5].
integrated protons/cm2
1.80E+11
1.60E+11
1.40E+11
1.20E+11
1.00E+11
8.00E+10
6.00E+10
4.00E+10
2.00E+10
Number of wrong bits vs number of protons/cm2
y = 8E+07x
R 2 = 0.9991
0.00E+00
0 500 1000
number of wrong bits
1500 2000
Figure 7. Total fluence vs numbers of bits corrupted.
For each run we accumulate thousands of bits error to
have enough statistic. The results of various runs are shown in
the Figure 7.
The results were compatible with a Xsection of 1.25 . 10 -8
cm 2 per device that correspond at Xsection/bit of 1.25 . 10 -14
A total fluence 5.44 . 10 11 protons was divided among 2
devices. We collect one event with an architectural break
(wrong response from the read-back engine) the error was
recovered after a reset.
No Latch up was observed.
IV. TID (TOTAL IONIZING DOSE) TEST WITH A
60 CO GAMMA RAY SOURCE.
We use for the total ionizing dose the 60 Co source in the
Istituto Superiore di Sanita’ in Rome.
The source gives a rate of 380 Rad/min.
A. TID effects in Virtex FPGA
end_run data
data during 1st run
Linear (end_run data)
We tested tree devices, the first and the second device
were loaded with the circular shifter register instead the third
one was used to test the Xilinx without a loaded configuration
Table 2.

during communication with jtag tap.
The Tables 2,3,4 shows the data log of the currents sinked
from the devices.
The first device (xilinx1) worked correctly up to 73 Krad,
including a reconfiguration and read-back, the circuit continue
to work up to 83 Krad but at this value was impossible to
reprogram the device. We note a strong increment of the
current 150 mA instead of the 40 mA.
The second device (xilinx2) worked correctly up to 65
Krad but we note a factor two in the sinked current, 80 mA
instead of 40 mA,. The device stopped to work at 72 Krad
with the same behavioral of xilinx1.
In the xilinx3 we monitored only the current of the device
during the communication with the jtag interface without
configure the device.
This current was stable up to 92 Krad then started to
increase slowly, at 112 Krad was impossible to communicate
with the jtag machine and the device stopped to work.
Table 3.
Table 2.
All the devices work without any problem up to 60 Krad.
The Atlas requirement for the RPC zone is 4.2 Krad, that
include a 20 safety factor. The device meets very well the
requirement.
B. TID effects in the 18v02 Flashprom .
Two 18v02 flashprom were tested.
The behavioral of the two devices was very similar and
shown in the figure 8.
The current sinked from the device start to increase at 20
Krad at the 33 Krad was impossible to reprogram the device.
Also in this case the device meet the Atlas requirements.
The device stop to work with a total dose of 33 Krad in
this value is similar with our measurements with protons (28
Krad).
Figure 8. Current vs total dose for a 18v02
Flashprom.
V. ANNEALING AFTER IRRADIATION WITH 60 CO
GAMMA RAY SOURCE.
After the irradiation we put all the devices inside an oven
at 100 0 C. We log the current sinked from any device.
The xilinx after 12 hours of annealing restarted to work
correctly we note a big jump in the current reversing exactly
our TID measurements Figure 9.
Figure 9. current sinked from xcv200 during the
annealing.
The flashprom restarted to work after few hours and after
one day returns at the normal current Figure 10.
Figure 10. current sinked from the 18v02 flashprom
during the annealing.
All the devices working well after the annealing and the
process seem to delete any effects of TID.

VI. THE FPGA SUBSYSTEM.
After the resuts coming from the test we decide to implement
the pad logic using a subsystem based on a Virtex FPGA, two
Flashroms and a microcontroller is used to download and read
back the Virtex configuration.
The system is checked by a simple task running in the ELMB
CANbus microcontroller [6], capable of accessing these
devices via the ISP and JTAGbuses (Figure 11.).
Figure 11. FPGA subsystem to recover SEU in
program area.
The system reads back continuously frame by frame the
configuration inside the Xilinx using JTAG and checks the
consistency for each frame with a precalculated CRC value
stored in the SPI Flashrom (Figura 14). In case of error the
Figure 14. Flow chart of the FPGA initialisation and
check process.
microcontroller rewrites part of the configuration correcting
the wrong frame or reload the entire configuration.
In the Atlas radiation environment with the Xsect=1.25*10 -8
cm 2 and a flux of 5.65*10 9 hadrons/10 years we aspect 6.25
SEUs in one year
Using the ATLAS safety factors SFsim=5 for the
simulation uncertainty and SFlot=4 for the chip lot uncertainty
we have SEU with SF=6.25*5(SFsim)*4(SFlot)=125 in one
year.
VII. CONCLUSIONS
The XCV200 Xilinx Virtex FPGA and 18v02 Xilinx
Flashprom were irradiated with protons and gamma ray. The
SEU logic cross section is similar to other devices
with 0.25µm technology.
For the Xilinx Virtex XCV200 the measured logic
Xsection/bit= 3.98*10 -14 cm 2 and the measured configuration
Xsection/device= 1.25 . 10 -8 cm 2 .
The 18v02 Flashprom Xsection/bit < 6 * 10 -19 cm 2 .
The SEU coming from the configuration memory get worse
the problem of one order of magnitude respect to the pure
Asic design. The TID tolerance is more than Atlas LVL1
maximum requirements 4.2 Krad . All the XCV200 tested
devices worked without problem up to 60 Krad.
The 18v02 Flashprom program feature work up to 30 Krad
and the device steel work at 100 Krad.
The immunity of Flashprom technology to SEU can be used
for fast reprogramming of Xilinx configuration on board. The
availability of CPU power from DCS node can be used
to continuously check the Xilinx program.
References:
[1] Muon Spectrometer Technical Design Report.
1997 CERN/LHCC/97-22 ATLAS TDR 10.
[2] M.Shupe
Simulated Radiation Levels (SLR) version 18 Nov 2000.
http://atlas.web.cern.ch/Atlas/GROUPS/FRONTEND/W
WW/RAD/RadWebPage/RadConstraint/Radiation_Table
s_181100.pdf
(this document cancels and replaces the SRL tables given
in Appendix 1
of the ATLAS doc. ATC-TE-QA-0001, dated 21 July 00)
[3] Virtex 2.5V Xilinx Datasheet
DS003-1 (v2.5 ) April 2, 2001
Xilinx.
[4] XC18V00 Series of In-System Programmable
Configuration PROMs.
DS026 (v2.8) June 11, 2001.
Xilinx Datasheet.
[5] Virtex FPGA Series Configuration and Readback.
XAPP138 (v2.4) July 25, 2001
Xilinx application note.
[6] B.Hallgren et al.
The Embedded Local Monitor Board (ELMB)
in the LHC Front-end I/O Control System.
LEB 2001 Stockholm.
[7] V.Bocci et al.
Prototype Slice of Level-1 Muon Trigger Barrel Region
of the ATLAS Experiment.
LEB2001 Stockholm

A Radiation Tolerant Gigabit Serializer for LHC Data Transmission *
P. Moreira 1 , G. Cervelli, J. Christiansen, F. Faccio, A. Kluge,
A. Marchioro and T. Toifl 2
Abstract
In the future LHC experiments, some data acquisition and
trigger links will be based on Gbit/s optical fiber networks. In
this paper, a configurable radiation tolerant Gbit/s serializer
(GOL) is presented that addresses the high-energy physics
experiments requirements. The device can operate in four
different modes that are a combination of two transmission
protocols and two data rates (0.8 Gbit/s and 1.6 Gbit/s). The
ASIC may be used as the transmitter in optical links that,
otherwise, use only commercial components. The data
encoding schemes supported are the CIMT (G-Link) and the
8B/10B (Gbit-Ethernet & Fiber Channel). To guarantee
robustness against total dose irradiation effects over the
lifetime of the experiments, the IC was fabricated in a
standard 0.25 µm CMOS technology employing radiation
tolerant layout practices.
The device was exposed to different irradiation sources to
test its sensitivity to total dose effects and to single effects
upsets. For this tests, a comparison is established with a
commercial serializer.
I. INTRODUCTION
The high bunch crossing rate (40MHz) of particles
together with the large number of channels in the LHC
detectors will generate massive amounts of data that will be
transmitted out of the different sub-detectors for storage and
off-line data analysis. Trigger links will also be transmitting
large amounts of data to the trigger processors. The last type
requires low data latency and operation synchronous to the
LHC master clock. Low latency reduces the required amount
of storage memory needed inside the detectors while,
synchronous operation avoids complex synchronization
procedures of the data arriving to the trigger processors from
the different locations in the detectors. Economic
considerations as well as power budget, material budget and
physical space impose the use of high-speed links for data
CERN, 1211 Geneva 23, Switzerland
J. P. Cachemiche and M. Menouni
CPPM, Marseille, France
transmission. Consequently, optical links operating in the
Gbit/s range were chosen for these applications.
Modern day commercial components meet (or exceed) the
needs existing in the High Energy Physics (HEP)
environment. However, for the applications mentioned above,
the transmitters will be located inside de particle detectors and
will be subject to high doses of ionizing irradiation during the
lifetime of the experiments. In general, Commercial-Off-The-
Shelf (COTS) devices are not designed to withstand
irradiation. If the large number (~ 100K) of links planned for
LHC is taken into account, the few radiation-hardened devices
that exist on the market have prohibitively high prices. It was
thus considered necessary to develop a dedicated solution that
would meet the very special HEP requirements. Since only
the transmitters will be subject to irradiation, only they need
to be developed and qualified for radiation tolerance.
Adopting commercial components for all the other parts in the
chain reduces the development and maintenance costs.
Following this line of reasoning, a transmitter ASIC was
developed that is capable of operating with two of the most
common data transmission protocols. Several features of the
device are configurable so that different user requirements can
be accommodated. It was designed using radiation tolerant
layout practices that, when applied to CMOS sub-µm circuits,
guarantee tolerance to irradiation effects to the levels
necessary for the LHC experiments [1] and [2].
In this work, emphasis will be put on the radiation effects
on the circuit operation. A COTS serializer has also been
irradiated. The results of these tests will be discussed.
II. THE GOL ASIC ARCHITECTURE
The basic principles of the serializer operation have
already been discussed in previous publications [3] and [4]
and consequently will not be repeated here. Only a brief
discussion of the IC architecture will be made since it is
relevant for the understanding of the irradiation tests.
As shown in Figure 1 the ASIC “Data Interface” is
composed of a 32-bit bus and two data flow control lines
*
This work has been supported by the European Community Access to Research Infrastructure action of the Improving Human
Potential Programme, contract N. HPRI-CT-1999-00110
1
Email: Paulo.Moreira@cern.ch
2
Now with IBM Research, Zurich, Switzerland

(“dav” and “cav”). Depending on the transmission mode the
data bus operates either as a 16 (least significant bits only) or
as a 32-bit bus. Since the operation is synchronous with the
LHC clock (running at 40 MHz), these two modes result in
data bandwidths of 640 Mbit/s and 1.28 Gbit/s respectively.
Before serialization, data undergo encoding using either the
8B/10B [5] or the “Conditional-Invert Master Transition”
(CIMT) [6] line coding schemes. The encoding procedures
introduce two additional bits for each eight bits of data
transmitted resulting in serial data rates of 800 Mbit/s or
1.6 Gbit/s. Any combination of line coding and data rate can
be used. If CIMT encoding is employed, a G-Link receiver [7]
is required while if, 8B/10B coding is performed then either a
Gbit Ethernet [8] or a Fiber Channel receiver can be used
provided they are compatible with the data rates being
generated.
D(31:0)
16/32b
dav
cav
LHC
clock
I2C
JTAG
Config
Data
Interface
PLL &
Clock
Generator
Control &
Status
Registers
16b
CIMT
Encoder
8B/10B
Encoder
Serializer
20b
10b
Word
Multiplexer
Laser
Driver
50Ω
Line
Driver
out+
out-
Figure 1: IC architecture
For operation in the 32-bit mode, the “Data Interface”
performs time division multiplexing of the 32-bit input words
into two 16-bit words at a rate of 80 Mwords/s. No
multiplexing is done at this stage if the 16-bit mode is used.
During encoding, the 16-bit data words are transformed into
20-bit words that are further time-division multiplexed into
two 10-bit words by the “Word Multiplexer” before they are
fed to the “Serializer”. The “Serializer” converts them into the
final serial data stream and drives both the “Laser Driver” and
the “50Ω Line Driver”. The use of the output drivers is
mutually exclusive.
The several clock frequencies necessary to run the
different circuits of the serializer are internally generated by a
clock multiplying PLL that uses as a reference the LHC
master clock signal (40.08 MHz).
Due to radiation effects, it is expected that the threshold
current of the laser diodes will increase with time over the
lifetime of the experiments [9]. To compensate for this, the
laser-driver contains an internal bias current generator that
can be programmed to sink currents between 0 and 55 mA.
Programming the ASIC can be done using either an I2C [10]
or a JTAG [11] interface. External hardwired pins set the
main operation modes of the receiver. Although these two
interfaces are present in the ASIC they are not essential for its
operation. They have been added to allow additional
flexibility in the use of the serializer. The main modes of
operation are configurable by external hard-wired pins
allowing the ASIC to work standalone.
III. EXPERIMENTAL RESULTS
The ASIC was tested using the test setup shown in Figure
2. The transmitter card is composed of a reference clock
generator (40MHz), an FPGA that generates the test data to be
fed to the GOL serializer, an optical transmitter, and a laserdiode.
The same card, equipped differently, was used to test
both the CIMT and the 8B/10B modes of operation. The
optical transmitter used was the Infineon V23818-K305-V15
for 800 Mbit/s operation in the G-Link mode and the Stratos
MLC-25-8X-TL for 1.6 Gbit/s operation using 8B/10B
encoding.
FPGA
Clock
Generator
Receiver Board
Optical
Receiver
data
control
I2C
JTAG
Figure 2 : Test setup block diagram
GOL
Serializer
Configuration
G-Link or
Gbit-Ethernet
Deserializer
data
control
Optical
Transmitter
Transmitter Board
FPGA
Clock
Generator
The receiver board contains a reference clock generator,
an optical receiver, a de-serializer and an FPGA whose
function is the detection and counting of errors present in the
input data stream. The 8B/10B and the G-Link modes of
operation required the use of two different receiver boards but
their operation principle is the same. The two boards are
equipped with parallel ports that allow them to be connected
to either a computer or a logic analyzer for monitoring and
analysis of errors. One of the boards was setup as a G-Link
receiver operating at 800 Mbit/s and it is based on the Agilent
HPMD-1024 de-serializer. The other was setup as an 8B/10B
receiver operating at 1.6Gbit/s and the de-serializer used was
the Texas Instruments TLK2501.
This test setup was used both to perform the evaluation
tests and the irradiation tests (total dose and single event
effects).
data
control

A. Evaluation Tests
All the ASIC functions proved functional. However, the
ASIC laser driver displays levels of jitter incompatible with
the data rates being transmitted (mainly at 1.6 Gbit/s).
Because of that, all the Bit Error Rate (BER) tests reported
here refer to data transmission using an external laser driver
driven by the ASIC 50Ω line driver outputs.
An error free four days long BER test was done in the G-
Link mode at 800 Mbit/s. In addition, a 13-hour error free
data transmission test was made in the 8B/10B mode at
1.6 Gbit/s. The chip displays a power consumption of
300 mW and 400 mW at 800M Bit/s and 1.6 Gbit/s,
respectively (the power consumption includes a laser-diode
bias current of 26 mA). Both the JTAG and the I2C interfaces
proved fully functional.
B. Total Dose Irradiation Tests
The ASIC was irradiated with X-rays (10 KeV peak) in a
single step to a total dose of 10 Mrad (SiO2) at a dose rate of
10.06 Krad (SiO2)/min. A BER test was performed after
irradiation for 72 hours and no errors were observed. The data
transmission test was done using the G-Link mode at
800 Mbit/s. The power consumption remained the same after
irradiation.
C. Single Event Effects Tests
The ASIC was irradiated using heavy ions and protons at
the cyclotron Research Center (CRC) of UCL Louvain-la-
Neuve, to test its sensitivity to single event effects. The
irradiation tests consisted in irradiating the IC during normal
operation while at the same time monitoring the transmitted
data for errors (BER test). The tests were performed in all
cases at room temperature.
1) Proton Test
Two BER tests were made while irradiating the ASIC with
60 MeV protons. The tests were done for the G-Link and the
8B/10B modes of operation at 800 Mbit/s and 1.6 Gbit/s data
rates, respectively. Table 1 summarizes the experimental
conditions and results. No data transmission errors or PLL
losses of lock were observed during the experiment leading to
the limit cross sections of

3) Commercial Serializer
Using a transmitter board similar in functionality to the one
described above for the GOL transmitter, two samples of the
TLK2501 Texas Instruments transceivers were subject to
60 MeV protons irradiation.
For this test, the proton flux was fixed at 3.5 10 8 p/(cm 2 .s). At
a total proton fluence of 1.0 10 12 p/cm 2 , 8 events were
observed for the first device tested and 11 upsets for the
second device. Among those 19 events, 11 were found
corresponding to single word upsets and 8 to PLL losses of
synchronization. These result in cross-sections of 8 10 -12 cm 2
for the loss of lock event and 1.1 10 -11 cm 2 for single errors.
The transmitter board current consumption was monitored
during irradiation. The test was interrupted when the power
consumption reached a value 2.5 times higher than the preirradiated
value, at a fluence of 9.4 10 11 cm 2 . This increase is
surely due to total dose effects. The accumulated fluence
corresponds to a radiation dose of about 130 Krad.
Table 2 : Estimated error rates for four different CMS environments
Environment Pixel
Serializer [4]
Errors/(Chip
Hour)
GOL
800 Mbit/s
Errors/(Chip
Hour)
GOL
1.6 Gbit/s
Errors/(Chip
Hour)
R = 4 -
20 cm
1.4 10 -2
0
9.4 10 -3
Endcap
ECAL
R = 50 -
130 cm
1.9 10 -4
0
1.3 10 -4
Outer
Tracker
R = 65 -
120 cm
8.4 10 -5
0
5.8 10 -5
IV. ASIC UPGRADE
Exp.
Cavern
R = 700 -
1200 cm
3.1 10 -8
0
2.2 10 -8
As discussed before, the jitter levels on the laser driver
output exceed the values reasonable for error free
transmission. The causes for this problem were traced down
and a new version of the ASIC with modifications aimed at
solving this problem was submitted for fabrication. Besides
this, a few more modifications were introduced that were
requested by the CMS collaboration. A list of new features
and modifications follows:
� I/O input cells were redesigned to be TTL and 5V CMOS
compatible;
� An optional differential clock input was added. It is
compatible with LVDS and PECL voltage swings;
� An open fiber control safety logic circuit was introduced;
� The ESD protection circuits were improved;
� The input buffers of the I2C interface were replaced by
Schmitt trigger cells;
� The pinout was redefined.
V. SUMMARY
A configurable Gbit/s serializer (GOL) has been
developed and manufactured to address the HEP experiments
requirements. The device was experimentally validated to
comply with the levels of radiation tolerance required by the
LHC experiments. Both total dose and SEU irradiation tests
were realized. The SEU tests were made using 60MeV
protons and Heavy Ions. Using the SEU test results, an
estimate of the error rates for such a device in different CMS
environments was made. SEU results for a commercial
serializer were also presented for 60 MeV proton irradiation
tests. When compared to the commercial device, the GOL
ASIC displays higher tolerance in what concern tolerance to
total dose irradiation and single event upsets..
VI. REFERENCES
[1] G. Anelli, M. Campbell, M. Delmastro, F. Faccio, S.
Florian, A. Giraldo, E. Heijne, P. Jarron, K. Kloukinas, A.
Marchioro, P. Moreira, and W. Snoeys, “Radiation tolerant
VLSI circuits in standard deep submicron CMOS
technologies for the LHC experiments: practical design
aspects”, IEEE Trans. Nucl. Sci. Vol. 46 No.6, p.1690, 1999.
[2] K. Kloukinas, F. Faccio, A. Marchioro and P. Moreira,
“Development of a radiation tolerant 2.0V standard cell
library using a commercial deep submicron CMOS
technology for the LHC experiments” Proc. of the fourth
workshop on electronics for LHC experiments, pp. 574-580,
Rome, 1998
[3] P. Moreira, J. Christiansen, A. Marchioro, E. van der Bij,
K. Kloukinas, M. Campbell and G. Cervelli, “A 1.25Gbit/s
Serializer for LHC Data and Trigger Optical Links”,
Proceedings of the Fifth Workshop on Electronics for LHC
Experiments, Snowmass, Colorado, USA, 20-24 September
1999, pp. 194-198
[4] P. Moreira 1, T. Toifl, A. Kluge, G. Cervelli, F. Faccio, A.
Marchioro and J. Christiansen, “G-Link and Gigabit Ethernet
Compliant Serializer for LHC Data Transmission,” 2000
IEEE Nuclear Science Symposium Conference Record,
October 15 - 20, 2000, Lyon, France, pp. 9.6 – 9.9
[5] IEEE Std 802.3, 1998 Edition
[6] C. Yen, R. Walker, P. Petruno, C. Stout, B. Lai and W.
McFarland, “G-Link: “A chipset for Gigabit-Rate Data
Communication,” Hewlett-Packard Journal, Oct. 92.
[7] See for example the Agilent HDMP-1034 receiver chip
data sheet: http://www.agilent.com
[8] See for example the Texas Instruments TLK2501
transceiver chip data sheet: http://www.texasinstruments.com
[9] F. Vasey, C. Azevedo, G. Cervelli, K. Gill, R. Grabit and
F. Jensen, “Optical links for the CMS Tracker,” Proc. of the

fifth workshop on electronics for LHC experiments, pp. 175-
179, Snowmass, 1999
[10] “The I2C-BUS specification”, Philips Semiconductors,
Version 2.1, January 2000
[11] C. M. Maunder and R. E. Tulloss, “The Test Access Port
and Boundary-Scan Architecture,” IEEE Computer Society
Press, 1990
[12] M. Huhtinen and F. Faccio, “Computational method to
estimate Single Event Upset rates in an accelerator
environment”, Nuclear Instruments and Methods A, vol. 450,
pp. 155-170, 2000

Development of an Optical Front-end Readout System for the
LHCb RICH Detectors.
N.Smale, M.Adinolfi, J.Bibby, G.Damerell, N.Harnew, S.Topp-Jorgensen; University of Oxford, UK
V.Gibson, S.Katvars, S.Wotton; University of Cambridge, UK
K.Wyllie;CERN; Switzerland
Abstract
The development of a front-end readout system for the LHCb
Ring Imaging Cherenkov (RICH) detectors is in progress.
The baseline choice for the RICH photon detector front-end
electronics is a binary readout ASIC for an encapsulated
silicon pixel detector. This paper describes a system to
transmit the binary data with address ID and error codes, from
a radiation harsh environment while keeping synchronisation.
The total data read out for the fixed Level-0 readout period of
900ns is 32x36x440 non-zero-suppressed bits per Level-0
trigger, with a sustained Level-0 trigger rate of 1MHz.
Multimode fibres driven by VCSEL devices are used to
transmit data to the off-detector Level-1 electronics located in
a non-radiation environment. The data are stored in 512Kbit
deep QDR buffers.
I. INTRODUCTION
The baseline photon detector for the LHCb RICH [1] detector
is the CERN/DEP Hybrid Photon pixel detector (HPD) [1]
whose active elements comprise a photo-cathode, electrostatic
imaging system, encapsulated pixellated silicon detector and
binary readout ASIC [2]. There are 440 HPDs to be read out
in 900ns, each HPD has 32x32 pixel channels. Beam Count
ID, error information and parity checking information are
added to the data bringing the total transmission to
32x36x440 bits per Level-0 trigger.
32x32
Add Bcnt etc
LEVEL_0 ON DETECT0R
LEVEL_1 OFF DETECT0R
QDR 9Mb
4 BURST
MEMORY
ADDRESS 19
Data 16 wide
16x36
Parallel/serial.
Driver VCSEL
Control
Data 16 wide
ECS/TTCrx Parallel/serial. Driver VCSEL
XILINX
FPGA
CONTROLLER
ERROR CHK
ECS/TTCrx
16x36
FROM THE NEXT
HDMP-1034
HDMP-1034
HDMP-1034
AMPs
AMPs
AMPs
16x36 HDMP-1034 AMPs
DATA 4 BURST @ 18X36 20X36
16x36
16x36
16x36
HPD CHANNEL
20X36
20X36
20X36
M2R-25-4-1-TL
Figure 1: Illustrates the read-out chain for one HPD.
>100M
Multimode
Fibre.
The intention is to use a fibre-optic data transmission scheme
to export the data from the detector electronics located in a
radiation environment to the Level-1 electronics, located in a
non-radiation environment, the control room. A reliable and
cost effective solution, that allows a reasonable tolerance on
the available bandwidth is to use two fibres per HPD, each
operating at a data bandwidth 640Mbits/s.
Data from the binary readout chip are interfaced to the fibreoptic
link using a custom interface ASIC, the PInt chip. These
data are serialised, multiplexed and driven into fibres using
radiation hard Gigabit Optical Link (GOL) [3] and
VCSEL [4] chips. A fibre receiver converts the incoming
serial data stream to parallel data. The receivers, which are
currently being investigated, will be commercial off the shelf
(COTS) components. A FPGA controller checks the
incoming parallel data and stores them to quad data rate
(QDR) Level-1 buffers [5]. Control and synchronisation of
this system is achieved by using the TTCrx [6] and LHCb
Experiment Control System (ECS) [7] systems. Fig 1
illustrates the read-out chain to the Level-1 buffer for one
HPD. Component availability, radiation hardness, ease of
replacement, accessibility, synchronicity and cost
effectiveness all need to be considered and demonstrated
during the prototyping stages.
II. ENVIRONMENT
The Level-0 electronics will be situated in the ~30 Gauss
magnetic fringe field of the spectrometer magnet and will
experience radiation doses of 3Krad/year [8]. A shell of
ferromagnetic material provides shielding for the Level-0
electronics reducing the fields too less than 10 Gauss [9]. All
Level-0 electronics will be fabricated in a 0.25μm process
using radiation tolerant layout techniques to protect against
the radiation dose. The radiation tolerant layout employed
uses guardrings and enclosed MOS transistors that prevent
leakage currents in thick field oxides and reduces the
probability of single event latch up (SEL). However this does
not protect against a change in bit state or transient caused by
an ionising particle depositing energy in the gate region,
single event upset (SEU). To minimise the effects of SEU,
redundancy and error correction have been added to the
control logic. Protecting data against SEU effects is thought
not to be necessary if the SEU rate can be considered small.
The Level-1 electronics are situated in the counting room
~100m away from the Level-0 area in a non-radiation and
non-magnetic field region. The counting room can be

considered as an electronic friendly environment and
therefore standard COTS components can be used. This has
the advantage of availability, maintenance, and cost
effectiveness, with a broad range of products and allows the
use of FPGA devices. Error checking, error correction and
self test algorithms will be built into the Level-1 electronics
for ensuring that synchronisation is not lost and corrupt data
are not being transmitted either to or from the Level-1 region.
III. THE PIXEL INTERFACE (PInt) Chip
The HPD Binary Pixel chip requires an interface chip (PInt)
that generates chip biasing and calibration test levels, handles
the ECS (Experiment Control System) and TTC (Timing and
Trigger Control). The PInt chip adds error codes, addresses,
parity and bunch crossing ID to the data. The data are
synchronised into two Gigabit Optical Links (GOL). The PInt
is being developed using a Spartan II FPGA, and finally
ported into a 0.25μm CMOS radiation-hard ASIC. The PInt
chip controls a second level of multiplexing and serialisation
of the Level-0 data before fibre transmission, see sections IV
and V. Fig 2 shows the block diagram of the PInt and its
supporting blocks.
Analogue
Supplies,
DACs
and
Filters..
JTAG
Control
JTAG
PInt
Control.
State Machine
CMOS->GTL
TTCrx
TTC
Interface
Timing,
Test
And
Control
HPD BINARY CHIP
Link
Test
Pattern
16*12
FIFO=
BX Counter
+
ERRORS.
Figure 2: PInt block diagram.
GOL
+
Optical Driver
GOL
Control/
Synch
32Wide
DATA
Buffer.
GTL->CMOS
A. Pixel Chip Configuration
The 44 internal 8 bit DACs of the Pixel Chip needed for
setting the bias voltages and currents are configured using a
JTAG interface. The PInt interfaces the ECS to the test
access port (TAP) through a standard TAP state controller.
The TAP controller is a 16 state FSM that responds to the
control sequences supplied from the ECS.
B. Data Handling
The PInt translates all incoming signals to the Pixel chip I/O
standard of GTL and outgoing signals to CMOS. The TTCrx
bunch-crossing clock of 40.08MHz is used to synchronise the
PInt with the Pixel, GOL chip and the LHCb system. Data
coming from the HPD binary chip are of a binary format i.e. a
binary ‘1’ for a hit pixel. On a trigger Level-0 accept (average
trigger rate of 1MHz) 32x32 pixels are read out to the PInt
chip. A 12-bit bunch crossing ID, which is reset to zero every
3563 crossings, is taken from channel A of the TTCrx and
added as a header to the data. The bunch crossing ID is taken
over preference of the event ID because of the problem of
consecutive Level-0 triggers in LHCb [10]. Any error
conditions that the PInt chip may have identified are then
flagged in a 32bit error word. The ECS is also informed of
certain error conditions to enable a decision on what action to
take. Finally, the data, parity and trailer bits are added. The
parity check is a generated 32-bit number consisting of the
parity of each of the 32 bit wide data set.
32 BITS WIDE
HEADER
ERROR FLAGS
DATA 0
~~~~~~~~
DATA 31
PARITY
TRAILER
Figure 3: Event-building scheme.
The trailer is expected to use cyclic redundancy checking
(CRC) which is an error detection scheme in which the block
check character is the remainder after dividing all the
serialised bits in a transmission by a predetermined block
number. Simulations will be performed to find the most
efficient block size and predetermined binary number. Parity
and CRC together will show bit error location and in which
way the bit has changed allowing for correction at a later
stage. The PInt event-building scheme is shown in fig 3.
IV. PARALLEL TO SERIAL Data Transmission
The (GOL) [3] chip is a multi-protocol high-speed
transmitter. It is an ASIC fabricated in the 0.25um process
and is able to withstand high doses of radiation. The chip is to
be run in the G-Link mode at 800Mbits/s and is required to
transmit 20 bits of data in 25nS, 16 of which are data and the
remaining 4 are overhead bits for encoding. The CIMT
(Conditional Invert Master Transition) encoding scheme is
employed. Before being serialised the 20-bit encoded words
are time-division multiplexed into two 10-bit words. The two
10-bit words are serialised and transmitted via a VCSEL
(Vertical Cavity Surface Emitting Laser) and multimode fibre.
For this mode two GOLs per Pixel chip will be required. The
threshold of the laser driver can be adjusted during the
lifetime of the experiment with the GOL chip.
V. FIBRE OPTIC DRIVERS
VCSELs emit light perpendicularly to their p-n junctions.
High output luminosity, focussing and large spectral width
allows for easy coupling with multimode fibres. Wavelengths
are generally in the (650-850-1300) nm ranges [11] and
output power is typically 5mW for a multimode fibre. VCSEL
arrays can be easily incorporated into single ICs, which allow
for a much better multiple fibre package. The VCSELs have

een proven to be very robust in terms of radiation and
magnetic fields. The proposal is to use two VCSELs per pixel
chip and drive 800Mb/s of data through 100 metres of
multimode fibre to the LHCb counting room located in a low
radiation region.
VI. THE FIBRE OPTIC RECEIVER AND SERIAL TO
PARALLEL CONVERTER
The intention is to use COTS items in the counting room
region. The data are to be received by a pin diode receiver and
amplifier array package and de-serialised using a Hewlett
Packard HDMP1034 for the 16-bit data word. Fig 4 shows the
general scheme.
Evaluation of such a scheme, in the simplex transmission
mode, is currently under way using the ODIN S-Link package
[12]. In this mode studies on checking synchronisation,
identifying lost data etc. are being done.
M2R-25-4-1-TL
Pre-
Amp.
Post
Amp.
RX
RX-
Hewlett Packhard-HDMP-1034
(Later Texas- TLK2501IRCP)
Clock
Data
Recovery.
Clock
Generator.
Demux
Word
Align
Invert.
Decode.
Flag
DESCRM
RxReady.
Delay
Figure 4: Fibre Optic Receiver
Sync
Logic.
Output Latch
Rx(0-15).
RxFlag.
RxError.
RxData.
RxCntl.
RxDSlip.
ShfIn.
ShfOut.
SRQIn.
SRQOut.
PassEn.
The S-Link is a CERN specification for an easy-to-use FIFOlike
data link that can be used to connect front-end to read-out
at any stage in a data flow environment [13].
If the GOL functions reliably with 32 bit data words at
40 MHz the Texas Instruments TLK2501IRCP will be
considered as the receiver package. This will reduce the
number of required fibres by a factor of 2.
VII. LEVEL_1 BUFFER
Data arriving from each of the serial/parallel converters are in
a 16-bit wide, 36 word format, received at a rate of
640Mbits/s. The data contain header and error codes as
illustrated in fig 3. The data, event ID and error codes are
proposed to be time multiplexed and stored in the Level-1
buffer. The bunch ID is checked against the expected ID,
generated at the Level-1 region using another TTCrx, and the
resulting error condition carried with the event
Fibre Optic receiver and
Demux 1:16 @ 40MHz
16
16
16
16
TCCrx
Controller
FPGA
Addr
Data
ECS
Figure 5: Level_1 Buffer scheme
To DAQ
processor
QDR
The Level-1 buffer is implemented with a commercially
available QDR SRAM (Quad Data Rate SRAM) and is
controlled by the FPGA QDR controller. Fig 6 shows the
general scheme with the support blocks.
A. QDR SRAM
The QDR SRAM is a memory bank of 9Mbits and can store
up to 3.5K events from two HPDs pending the Level-1 trigger
decision. The LHCb trigger architecture presently requires a
buffer of at least 2K events. One QDR will store the data from
four fibres or two HPD Pixel chips. Data can be read in and
read out on the same clock edge at a rate of 333Mbits/sec. The
QDR architecture is shown in Fig 6 and the key points of this
device are:
a) 9-Mbit Quad Data Rate Static RAM. (migration to 64Mb).
b) Manufacturers: Cypress, IDT, Micron and NEC.
c) Separate independent read and write data ports support
concurrent transactions.
d) 4-word burst for reducing address bus frequency.
e) 167MHz clock frequency (333MHz data rate).
Migration to 250MHz (500MHz data rate).
Figure 6: QDR SRAM Architecture
m
e
m
o
r
y
Memory/fibre
can store upto
3.5K events
The QDR is a four-burst device and requires only one write
address to be generated to store four 18-bit words. This
therefore means that addresses are generated at a rate of
40MHz while the data are being transferred at 160MHz. This
allows a data word from each of the four receivers to be

stored in one bunch crossing. Reading of the data is a similar
process but the read address has to be on an alternative K
clock edge to the write address, where the K clock is the QDR
clock (80MHz).
More detail on the timing is given in section B below. As the
data from the receivers are in 16 bit words and the QDR
accepts 18-bit words, the remaining 2x36 bits of the memory
can be used for error flagging and data validation in the
following processing stages. The transmission check will
consist of a coded 1x36 bit word that is stamped onto the side
of an event.
B. QDR Controller
A Xilinx Spartan-II XC2S200 FPGA is used as the controller
chip. The device offers 284 I/Os with access times of
200MHz, internal clock speeds of 333MHz, 1176 control
logic blocks and 5292 logic cells and is a low cost item.
Internal Delay Lock Loops (DLL) are used for clock
multiplication. The Spartan-II is programmable directly by
JTAG or PROM.
Figure 7: Write state machine.
The Level-1 buffer logic is built around two state machines: a
write machine shown in fig 7; and a read machine, which is
very similar in operation but receives different control signals.
The “One Hot” state machines ensure the correct timing of the
QDR read/write signals by forcing a read/write on a rising
edge of the QDR K clock (80MHz) and then passing data
from/to the QDR on every edge of the K clock for four edges.
The state machine operates at 160MHz.
The write machine is activated on the 40MHz clock and the
RXREADY flag when data are ready to be stored. Every time
the write machine is activated a wrap around counter is
incremented by 1. This counter is used for the QDR write
address. Two counters generate the read address. The “offset
counter” counts in multiples of 36 on every Level-1 trigger to
ensure that the read pointer starts at the beginning of an event.
On receipt of a Level-1 trigger accept the read machine is
activated and cycles 36 times consecutively, incrementing the
“sub counter” each time. The “sub counter” is reset after
reading out one complete event. Logic has been incorporated
into the design to ensure the read and write pointer cannot
overtake each other.
The Level-0 trigger has a 1MHz sustainable rate whereas the
level-1 trigger is a variable ~40KHz rate. For this reason the
write machine always has the priority over the read machine.
To allow for this, Level-1 triggers and decisions are buffered.
Fig 8 shows a simulation of data flow to and from the QDR
for a condition where continuous write and read signals are
requested. After an initial one K clock delay for both read
and write the four 18-bit data words are read in and out of the
device in one bunch crossing. The cursor is at the beginning
of a write sequence. With the rising edge of K and
“NOT wpsbar” the write address is taken from the input port
“sa”. On the following rising edge of K and for three
consecutive edges thereafter, data are stored to the QDR. Data
read from the device use the same principle as the write
procedure but “rpsbar” is the control signal. The “wpsbar”
and “rpsbar” signals should not appear on the same rising
edge of the K clock. The data in this simulation are arbitrary.
C. TTCrx and ECS
Figure 8: QDR wave-from
Both the QDR and Spartan-II have boundary scanning
facilities that will be used in production tests. The Spartan is
also programmable via a JTAG interface. The ECS will be
used to deliver the configuration signals.
The controller chip requires a bunch-crossing clock, reset,
bunch ID and Level-0 and Level-1 trigger information from
the TTCrx. For the Level-0 information the TTCrx is used in
the same way as for the Level-0 board (see Section III) but
instead of the local bunch ID being added as a header it is
compared against the header on the incoming Level-0 event
for transmission checks. The local Level-0 bunch ID will be
stored in 16 deep derandomiser buffers to track the on
detector Level-0 process. The resulting bunch ID header
check is stored as part of the 1x36 bit error word (see Section
VII-A).

The short broadcast port of the TTCrx will be used for trigger
information, reset and event ID. This has a limited number of
bits (~8) that can be sent but does support the necessary
bandwidth (~2MHz). Six bits of the eight are user
configurable and are being defined by the LHCb collaboration
according to the experiment requirements. Two bits have been
allocated for event ID so that they can be compared with the
two LSBs of a locally generated event ID to ensure that the
Level-1 buffers have not lost any fragments or
synchronisation.
VIII. TEST BED
Test boards have been built to check timing, chip
programming, TTCrx compatibility and QDR functionality.
The test bed has been made in a modular fashion, utilising a
Spartan-II demonstration board [14] and two PCB’s. One
PCB is for interfacing to the TTCrx test board and the other
for the QDR.
The demonstration board is equipped with a Spartan-II
XC2S100 in a PQ208 package. The speed performance does
not differ from the proposed final chip, XC2S200, but the
packaging limits the amount of I/Os that can be made
available to the user, in this case 196. For this reason only the
essential ports of the TTCrx have been utilised and the
number of data-in ports have been limited. To emulate the
event data coming from the receivers a pattern generator is
used for one of the 16-bit wide ports, the other three ports
have fixed binary numbers set internally on the chip.
Figure 9: Spartan/QDR/TTCrx test board
A mezzanine board has been produced and locates on top of
the FPGA I/O connector. This board has a QDR on it along
with all the necessary power supplies and termination
required for running the QDR chip. The QDR controller
FPGA has its I/O configured as HSTL to suit the I/O voltage
level of the QDR device.
The TTCrx used at this design stage was delivered premounted
to a test board [15]. The test board contains the
TTCrx IC, an integrated detector and preamplifier, a serial
configuration PROM (XC1736D) and a fibre optic postamplifier.
Unfortunately the test board is not compatible with
the Spartan-II demonstration board user area that route 30 of
the FPGAs I/O to a breadboard area. Therefore a TTCrx test
board fan out PCB has been produced to translate to the
Spartan-II demonstration board.
Fig 9 shows the assembled modules. Testing these boards is
now in progress.
IX. FUTURE PLANS
A complete prototype HPD to Level-1 readout system for one
HPD will be constructed over the next year. The prototype
will, as closely as possible, match the specifications of the
final design. This will allow full testing of a complete unit and
show compatibility of the selected components.
IX. REFERENCES
[1] LHCb TP CERN/LHCC 98-4 LHCC/P4, 20 Febuary 1998
[2] LEB 1999 CERN 99-09 CERN/LHCC/99-33
[3] GOL REFERENCE MANUAL, Preliminary version
March 2001 CERN-EP/MIC, Geneva Switzerland
[4] http://www.lasermate.com/transceivers.htm
[5] http://www.cypress.com/press/releases/200216.html
[6] http://micdigital.web.cern.ch/micdigital/ttcrx.htm
[7]http://lhcb-elec.web.cern.ch/lhcbelec/html/ecs_interface.htm
[8] CERN/LHCC/2000-0037 LHCb TDR3, 7 September 2000
[9] CERN/LHCC 98-4 LHCC/P4, 20 February 1998
[10] TTC USE, Jorgen Christiansen, MICRO
ELECTRONICS GROUP, CERN, http://lhcbelec.web.cern.ch/lhcb-elec/html/ttc_use.htm
[11] Hewlett Packard fbre-optic technical training manual.
[12]H.C. van der Bij et al, “S-LINK, a Data Link Interface
Specification for the LHC Era”,
http://his.web.cern.ch/HIS/link/introduce/introduce.htm, Sept.
1997
[13] Eric Brandin, “Development of a Prototype Read-Out
Link for the Atlas Experiment”, Master Thesis, June 2000.
[14] http://www.insightelectronics.com/solutions/kits/xilinx/spartan-ii.html
[15] TTCrx Reference Manual, CERN-EP/MIC, Geneva
Switzerland, October 1999 Version 3.0

A Radiation Tolerant Laser Driver Array for
Optical Transmission in the LHC Experiments
Giovanni Cervelli, Alessandro Marchioro, Paulo Moreira, and Francois Vasey
Abstract
A 3-way Laser Driver ASIC has been implemented in
deep-submicron CMOS technology, according to the CMS
Tracker performance and rad-tolerance requirements. While
being optimised for analogue operation, the full-custom IC is
also compatible with LVDS digital signalling. It will be
deployed for analogue and digital transmission in the 50.000
fibre link of the Tracker. A combination of linearization
methods allows achieving good analogue performance (8-bit
equivalent dynamic range, with 250 MHz bandwidth), while
maintaining wide input common-mode range (±350 mV) and
power dissipation of 10 mW/channel. The linearly amplified
signals are superposed to a DC-current, programmable over a
wide range (0-55 mA). The latter capability allows tracking of
changes in laser threshold due to ageing or radiation damage.
The driver gain and laser bias-current are programmable via a
SEU-robust serial interface. The results of ASIC qualification
are discussed in the paper.
I. INTRODUCTION
Data connection to the CMS Tracker Front-Ends is
provided by a large number of optical fibre links: 50.000
analogue for readout and 3.000 digital for trigger, timing, and
control signals distribution [1]. The Front-End components
must withstand the harsh radiation environment of the
Tracker, over the planned detector lifetime of 10 years (total
ionising dose and hadron fluence exceeding 10 MRads and
10 14 neutron-equivalent/cm 2 respectively) [2]. The baseline
technology for ASIC developments in the Tracker is a
0.25 µm CMOS, 3-metals, commercial technology (5 nm
oxide thickness) [3, 4, 5]. The intrinsic radiation tolerance of
this technology is increased to the required levels, by using
appropriately extended design-rules and self-correcting logic.
The use of this technology for analogue applications was
carefully evaluated before employing it for the design of the
Front End chips.
A Linear Laser Driver (LLD) array for the CMS Tracker
links had been already developed and implemented in a nonradiation
tolerant BiCMOS technology [6]. The design was
then translated in the 0.25 µm CMOS technology at an earlier
stage of the Tracker design [7]. A new LLD has now been
implemented in the same technology, appropriately matching
the Tracker modularity and functionality requirements for
both analogue and digital links.
Section II explains the device functionality and major
specifications. Section III describes the electrical circuit and
CERN, EP Division, 1211 Geneva 23, Switzerland
Giovanni.Cervelli@cern.ch
layout. Section IV reports on the measurement results and
device qualification.
II. FUNCTIONALITY
Figure 1 shows the block diagram of the new LLD chip.
The laser driver converts a differential input voltage into a
single ended output current added to a pre-set DC current. The
DC current allows correct biasing of the laser diode above
threshold in the linear region of its characteristic. The
absolute value of the bias current can be varied over a wide
range (0 to 55 mA), in order to maintain the correct
functionality of laser diodes with very high threshold currents
as a consequence of radiation damage. The laser diode-biasing
scheme (current sink) is compatible with the use of commonanode
laser diode arrays.
SCL
SDA
Adr (5)
I2C Interface
Reg (3)
-Idc0
Bias
(7)
Gain (2)
V0-
+ + +
-Idc1
-Idc2
LD0 LD1 LD2
V0+
to lasers
100 Ω 100 Ω 100 Ω
V1-
Figure 1: Block diagram.
V1+
from Mux
Input signals are transmitted to the laser driver using some
0-30 cm of 100 Ω matched transmission lines. The driver is
optimised for analogue operation in terms of exhibiting good
linearity and low noise. However, input voltage levels are
compatible with the digital LVDS standard (±400 mV into
100 Ω). The gain can be chosen from 4 pre-set values. Gain
control provides an extra degree of freedom for optimally
equalising the CMS Tracker readout chain. A system-level
simulation of the fibre link performance achievable with a
four-gain equalisation is presented in [8].
The IC modularity is 3 channels per chip. About 20
thousand 3-way laser drivers will be used for the CMS
Tracker readout and control links. The total power dissipation
of individual chips must remain constant regardless of the
modulation signal to minimise cross-talk and noise injection
in the common power supplies.
V2-
V2+

The channels can be individually addressed via a serial
digital interface (Philips Semiconductors I2C standard), which
allows individual power down, gain control, and pre-bias
control. Robustness to Single Event Upsets is achieved by
tripling the digital logic in the interface and by using a
majority voting decision scheme. The power-up I2C register
configuration is read from a set of hard-wired inputs. Thus it
is possible to insure that the optical links are correctly biased
at power-up.
III. CIRCUIT AND LAYOUT
The Linear Laser Driver consists of a Linear Driver and a
laser-diode bias generator (Figure 2).
dummy
output
Vdd
Vdd
Vdd Vdd
V1 V2
Vss Vss Vss Vss
Vss
I1
r
active
bulk
I2
Figure 2: Circuit diagram.
Vdd
gain
control
I1-I2 IOUT
gain
control
The Linear Driver consists of a degenerated PMOS
differential pair and a push-pull output stage. The degenerated
differential pair, in comparison to alternative solutions, is
conceptually simple and offers good dynamic and noise
performance with limited power dissipation. The PMOS
version is bulk-effect-free, thus allowing a larger input
common-mode range. The required linearity is obtained by
combining two source-degeneration methods: a parallel
source-degeneration resistor, and a source-bulk crossconnection
between the transistors of the differential pair. The
use of both methods allows keeping the degeneration resistor
to a value compatible with the required input common-mode
range. The push-pull output stage mirrors the currents in the
differential pair branches and subtract them at the output
node. Three switched output stages can be activated in
parallel, to provide four different selectable gains. In order to
keep the power supply current constant, a dummy output
stage dumps the complement of the modulation current
directly into the power supplies.
The laser-diode bias generator circuit consists of an array
of current sources and sinks. The enabling logic allows them
to be switched on and off as appropriate in order to generate a
current linearly variable between 0 and 55 mA. A regulated
cascode scheme [9] has been used to keep the output
impedance high and the compliance voltage low (

A. Static performance
Figure 4 shows the pre-bias current for 5 chips differently
processed (different σs). The measured LSB is 0.45 mA and
the highest current that can be generated on-chip is 57 mA.
The transfer characteristics (differential and common-mode)
and output characteristic of the LLD have been measured with
a Semiconductor Parameter Analyser. Figure 5 shows the
differential transfer characteristics of the LLD, for four
different gains (and different σs). The measured
(transconductance) gain values are 5.3 mS, 7.7 mS, 10.6 mS,
and 13.2 mS (5% above their nominal design values).
MODULATION CURRENT [mA]
PRE-BIAS CURRENT [mA]
60
50
40
30
20
10
σ = -3.0
σ = -1.5
σ = 0
σ = +1.5
σ = 3.0
0
0 16 32 48 64
I2C REGISTER
80 96 112 128
10
8
6
4
2
0
-2
-4
-6
-8
GAIN = 5mS
GAIN = 7.5mS
GAIN = 10mS
GAIN = 12.5mS
Figure 4: Pre-bias current.
-10
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
DIFFERENTIAL INPUT VOLTAGE [V]
Figure 5: Differential transfer characteristic.
Figure 6 shows the linearity error, for different input
common mode voltages (Vcm = 0 and Vcm = ±625 mV). The
linearity error is calculated as the absolute difference between
the real output current and its (least-square) linear fit, and is
expressed as a percentage of the specified operating range
(integral linearity deviation). In absence of common mode,
the error is less than 0.5% over the whole linear operating
range (±300 mV). The common-mode has an impact on
linearity. However, performance degradation is negligible for
an input common mode between ±350 mV. Figure 7 shows
the integral linearity deviation as a function of the input
common mode.
INTEGRAL LINEARITY DEVIATION [%]
INTEGRAL LINEARITY DEVIATION [%]
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
3
2.5
2
1.5
1
0.5
VCM = -625mV
VCM = 0V
VCM = +625mV
-0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25
DIFFERENTIAL INPUT VOLTAGE [V]
Figure 6: Linearity error.
σ = -3.0
σ = -1.5
σ = 0
σ = +1.5
σ = +3.0
0
-0.75 -0.625 -0.5 -0.375 -0.25 -0.125 0 0.125 0.25 0.375 0.5 0.625 0.75
COMMON MODE INPUT VOLTAGE [V]
Figure 7: Common-mode impact on linearity error.
The Common Mode Rejection Ratio at DC is inferred
from the common-mode transfer characteristic. The DC-
CMRR is 40 dB in the worst case (maximum laser-bias) and
becomes as high as 70 dB at low biases. The output
impedance (inferred from the output characteristic) of the
LLD varies between 3 kΩ and 10 kΩ, depending on the prebias,
and is in all cases much higher than the typical dynamic
impedance of the laser diode (

B. Dynamic performance
The dynamic performance of the LLD has been evaluated
with laser emitters, which are representative of the ones to be
used in the final application. A wide-bandwidth optical head
is used for receiving the optical signal and converting it back
to electrical for compatibility with standard instrumentation.
The pulse response of different chips and for different gains is
shown in Figure 8. The response exhibits little overshoot and
ringing. The measured rise and fall times are below 2.5 ns.
The measured settling times (to within 1% of the final value)
are of 10-12 ns, which leaves (for a 40 MHz sampled system)
13-15 ns for correctly sampling the output signal.
OUTPUT VOLTAGE [V]
x 10-3
12
10
8
6
4
2
0
-2
-5 0 5 10 15 20 25 30 35 40 45
TIME [ns]
Figure 8: Pulse response.
GAIN = 5mS
GAIN = 7.5mS
GAIN = 10mS
GAIN = 12.5mS
The frequency responses (differential and common-mode)
are shown in Figure 9. The analogue bandwidth has been
measured with a network analyser and was found to be
250 MHz. The equivalent input noise into this bandwidth is
gain and laser bias dependent. The measured noise is in all
cases below 1 mVrms. The CMRR is shown in Figure 10 as a
function of frequency (15 mA bias current). Cross-talk
between channels has been also measured and is below –
60 dB.
TRANSFER FUNCTION [dB]
-30
-40
-50
-60
-70
-80
10 1
-90
10 2
FREQUENCY [MHz]
Figure 9: Frequency response.
GAIN = 5mS
GAIN = 7.5mS
GAIN = 10mS
GAIN = 12.5mS
CMRR [dB]
45
40
35
30
25
20
15
10
5
0
10 1
-5
10 2
FREQUENCY [MHz]
GAIN = 5mS
GAIN = 7.5mS
GAIN = 10mS
GAIN = 12.5mS
Figure 10: Common Mode Rejection Ratio.
C. Radiation hardness
The circuit has been tested for total ionising dose effects
using an X-ray source, to investigate possible performance
degradation related to ionising effects (charge trapping in
oxide interface states). The experiment has been carried out
according to ESA/SCC recommendation for IC qualification
with respect to total dose effects [10]. The chip has been
irradiated in three steps to 1 Mrad, 10 Mrad and 20 MRad
(SiO2), at a constant dose rate of 21.2 Krad/min. After
irradiation the chip was annealed for 24 hours at room
temperature, followed by 168 hours at 100°C (accelerated
life). The full set of static measurements was carried out after
each step in order to assess any change in performance. The
chip was under nominal bias during irradiation with the three
channels switched on at maximum pre-bias.
The results of radiation and accelerated life testing show
that the LLD will operate within specifications all during the
experiment lifetime (10 years). The overall radiation effects
are negligible or acceptable. The laser-bias current shows an
increase of 5%, 10% and 15% for three different channels in
the same chip (see Figure 11).
PRE-BIAS CURRENT [mA]
70
60
50
40
30
20
10
0Rads
1MRads
10MRads
20MRads
24h @ 25°C
168h @ 100°C
0
0 16 32 48 64
I2C REGISTER
80 96 112 128
Figure 11: Pre-bias during irradiation.

This is attributed to the NMOS type VT-referred current
reference and is compatible with the previously measured
threshold variations in NMOS devices. There is no significant
change in the LLD differential or common-mode transfer
characteristics nor in the output characteristics.
The LLD robustness to SEU needs to be tested and an
experiment is being planned before the end of the year.
V. CONCLUSIONS
A Linear Laser Driver array has been developed and
implemented in a commercially available 0.25 µm CMOS
technology. The device has been designed to comply with the
stringent CMS requirements for analogue optical transmission
in the Tracker readout. It is however also compatible with
digital optical transmission modes in the Tracker slow control
system. Sample devices have been tested and shown to be
fully functional. The switched gains can be used to equalise
the significant insertion loss spread expected from the 50.000
analogue optical links. The pre-bias current is programmable
over a wide range, with 7-bit resolution, allowing tracking of
optical source degradation during detector lifetime. The LLD
array has a modularity of three channels. However, since the
channels can be individually disabled any modularity below
that can also be chosen without a power penalty. The
extensive set of measurements showed that the device
matches or exceeds the required analogue performance.
Integral linearity deviation is better than 0.5% over an input
common mode range of ±350 mV. Input referred noise is less
than 1 mV in an analogue bandwidth of 250 MHz. Power
dissipation at maximum pre-bias is below 110 mW per
channel. The radiation testing of one device showed that the
analogue performance would also be maintained after a total
ionising dose comparable with the one expected during the
experiment lifetime. The parameters spread and yield for the
tested devices are very good. Twelve devices have been tested
and shown to be fully functional. The new chips will be
packaged in a 5 mm x 5 mm LPCC case for ease of testing
and installation in the Tracker readout and control hybrids.
VI. ACKNOWLEDGEMENTS
The precious contribution to this work from Gulrukh
Kattakh of Peshawar University, Pakistan, and from Robert
Grabit and Cristophe Sigaud of CERN, Geneva, is
acknowledged.
VII. REFERENCES
[1] F. Vasey, V. Arbet-Engels, J. Batten et al., Development
of radiation-hard optical links for the CMS tracker at
CERN, IEEE Transactions on Nuclear Science (NSS
1997 Proceedings), Vol. 45, No. 3, 1998, pp. 331-337.
[2] CMS Collaboration, The Tracker Project, Technical
Design Report, CERN/LHCC/98-6, 1998.
[3] A. Rivetti, G. Anelli, F. Anghinolfi et al., Analog Design
in Deep Sub-micron CMOS Processes for LHC,
Proceedings of the Fifth workshop on electronics for
[4]
LHC experiments, CERN/LHCC/99-33, Snowmass,
1999, pp. 157-161.
P. Jarron, G. Anelli, T. Calin et al., Deep sub-micron
CMOS technologies for the LHC experiments, Nuclear
Physics B (Proceedings Supplements), Vol. 78, 1999, pp.
625-634.
[5] G.Anelli et al., “Radiation tolerant VLSI circuits in
standard deep-submicron CMOS technologies for the
LHC experiments: practical design aspects”, IEEE
Transactions on Nuclear Science, Vol. 46, No. 6, 1999.
[6] A. Marchioro, P. Moreira, T. Toifl and T. Vaaraniemi,
An integrated laser driver array for analogue data
transmission in the LHC experiments, Proceedings of
the Third workshop on electronics for LHC experiments,
CERN/LHCC/97-60, London, 1997, pp. 282-286.
[7] G. Cervelli, A. Marchioro, P. Moreira, F. Vasey, A
linear laser driver array for optical transmission in LHC
eperiments, 2000 IEEE Nuclear Science Symposium
Conference Record, Lyon, October 2000.
[8] T.Bauer, F.Vasey, A Model for the CMS Tracker
Analog Optical Link, CMS NOTE 2000/056, September
2000.
[9] E. Säckinger, W. Guggenbühl, A high-swing highimpedance
MOS cascode circuit, IEEE Journal of Solid-
State Circuits, Vol. 25, No. 1, February 1990.
[10] Total Dose Steady-State Irradiation Test Method,
ESA/SCC (European Space Agency / Space
Components Co-ordination Group), Basic Specifications
No. 22900, Draft Issue 5, July 1993.

Quality Assurance Programme for the Environmental Testing of CMS Tracker
Optical Links
Abstract
The QA programme is reviewed for the environmental
compliance tests of commercial off-the-shelf (COTS)
components for the CMS Tracker Optical link system. These
environmental tests will take place in the pre-production and
final production phases of the project and will measure
radiation resistance, component lifetime, and sensitivity to
magnetic fields. The evolution of the programme from smallscale
prototype tests to the final pre-production manufacturing
tests is outlined and the main environmental effects expected
for optical links operating within the Tracker are summarised.
A special feature of the environmental QA programme is the
plan for Advance Validation Tests (AVT's) developed in close
collaboration with the various industrial partners. AVT
procedures involve validation of a relatively small set of basic
samples in advance of the full production of the
corresponding batch of devices. Only those lots that have
been confirmed as sufficiently rad-tolerant will be purchased
and used in the final production.
I. INTRODUCTION
Final production of the CMS Tracker optical links will begin
in 2001 and continue until 2004. Approximately 40000 unidirectional
analogue optical links, and ~1000 bi-directional
digital optical links will be produced. Quality Assurance (QA)
procedures have been developed in order to guarantee that the
final links meet the specified performance and are produced
on schedule. A detailed QA manual has been written[1] and in
this paper we focus on the part of the QA programme
concerning environmental testing of components.
The CMS Tracker environment is characterised by the high
levels of radiation, up to ~2x10 14 /cm 2 fluence and 100kGy
ionizing dose for the optical link components over the first 10
years of operation[2]. The particle fluence at the innermost
modules of the Tracker is dominated by pions and photons,
with energies ~100MeV, and by ~1MeV neutrons at the
outermost modules. In addition to resisting the radiation
environment the components must operate in a 4T magnetic
field and at temperatures close to -10°C.
The basic elements of the optical link system are illustrated in
Fig. 1[1]. Both analogue and digital optical links for the CMS
Tracker share the same basic components, namely 1310nm
InGaAsP/InP multi-quantum-well edge-emitting lasers and
InGaAs p-i-n photodiodes coupled to single-mode optical
fibre. The optical fibre is in the form of buffered single-way
fibre, ruggedized 12-way ribbon fibre cable, and dense,
ruggedized 96-way multi-ribbon cable. MU-based single-way,
and MT-based multi-way, optical connectors are used at the
various optical patch panels.
K. Gill, R. Grabit, J. Troska, F. Vasey and A. Zanet
CERN, 1211 Geneva 23, Switzerland
karl.gill@cern.ch
Detector
Hybrid
CCU
CCU
A-Opto -Hybrid
D-Opto -Hybrid
Analogue Readout
40000 links @ 40MS/s FED
96
Rx Module
12
Digital Control
1000 links @40MHz
12
96
FEC
Front-End Back-End
Figure 1: Optical link systems. Components at the front-end are
exposed to radiation, a 4T magnetic field, and will operate at -10°C.
All of the elements listed above are either commercial off-theshelf
(COTS) components or devices based on COTS. In an
extensive series of sample tests, which was carried out in the
development phase of the project, the sensitivity of the
various link components to the expected Tracker environment
has been thoroughly investigated[3]. These data have allowed
identification and selection of suitable components and have
also allowed tailoring of the link specifications to compensate
for unavoidable effects, e.g. radiation damage, now that the
effects have been well quantified.
Despite having restricted the final choice of candidate
components to those that have passed the sample tests, the use
of COTS means that environmental QA testing must continue
into the production phase of the project. This is simply
because the radiation resistance of the COTS components can
not be guaranteed by the vendors as the devices are not
manufacturer-qualified for the CMS Tracker environment.
It is clear that we must avoid, if possible, any situation where
a delivered production batch of fully assembled components
is found to be non-compliant with the Tracker environment.
Diagnosing and remedying such a problem would incur a
substantial delay in the already tight production schedule.
We propose a programme of QA procedures, outlined in the
following section, that will guarantee that the final optical
links will meet the specified functional performance and
environmental resistance, whilst also avoiding the possibility
of rejecting fully assembled devices due to non-compliance
with the Tracker environment. A particular requirement of the

programme is that we must validate laser diodes, fibre and
photodiodes in special 'Advance Validation Tests' (AVT's).
The AVT procedures are described in detail in this paper, and
for details of other QA issues and requirements the reader is
referred to the full QA manual[1].
II. QA PROCEDURES
From the development of the first prototypes to large-scale
production, a wide range of QA procedures has been, and will
be, implemented as shown in Fig. 2[1].
Following extensive testing of early prototypes[3], the first
formal step in the QA procedure was the technical
qualification of suppliers in the framework of CERN market
surveys. Market surveys for semiconductor lasers (MS2690)
and optical connectors (MS2691) were issued in 1999.
Market surveys for optical fibre, ribbon and cable (MS2811)
as well as for receiver modules (MS2810) were issued in
2000. In all of these surveys, evaluation samples were
requested from the companies interested in tendering, and
subjected to a sample validation procedure described in the
next section. Based on the results of this sample-validation
procedure, manufacturers were qualified and those that were
successful were invited to tender for the production of final
components or assemblies.
Prototyping
Prototype Validation
Publications
Market Survey
Sample-Validation
Invitation to Tender
Pre-production
Purge + Test
by Manufacturer
Qualification
Advance
rad-hardness
validation
Production
Purge + Test
by Manufacturer
Lot validation
Figure 2: QA procedures during various project phases.
A. Sample validation
Assembly
Full test
Evaluation samples sent to CERN in the framework of market
surveys were validated according to the procedure sketched in
Fig. 3. For the semiconductor lasers (MS2690), the irradiation
consisted of both gamma and neutron tests, while for the
connectors (MS2691) and fibres/cables (MS2811) it consisted
only of gamma tests. These choices of radiation sources
reflected the types of effects that were observed in the earlier
tests[3]. No CERN-specific environmental tests (B-field or
irradiation) were performed on the Rx modules (MS2810),
which will be operated in the counting room, away from the
radiation and magnetic field. Results of Sample-Validation
tests made within the Market Surveys were published in
confidential reports, with a copy sent to the manufacturer.
Thorough environmental tests have also been made within the
CERN EP/MIC group on samples of the electronic chips,
namely the laser driver[4]and digital receiver chip[5], that will
be used in the optical links and located within the Tracker.
B-field
Functionality
Irradiation
Functionality
No Yes
S upplier D isqualified Success?
Figure 3: Sample validation procedures.
B. Pre-production qualification
S upplier Q ualified
Qualification of the pre-production will involve rigorous
testing of fully-assembled devices sampled from the preproduction
delivery in order to qualify the devices and
manufacturing processes in preparation for full production.
This includes evaluating the compliance of the components
and assemblies to their specifications whilst, or following,
exposure to conditions representative of the Tracker
environment, as illustrated in Fig. 4. Results of pre-production
qualification tests will be archived in the EDMS database,
with a copy sent to the manufacturer.
Repeat
Interact. with
manufacture
Failure analysis
Manufacturer
qualification
N
Sampling
Success?
Y
Functionality
Environmental
Annealing
Functionality
Accelerated ageing*
N
Success?
Y
Final Production clearance
* in some cases only
Advance Production clearance
Figure 4: Flow chart of the pre-production qualification procedure.
C. Advance Validation Test (AVT)
The primary aim of the AVT procedure is to avoid the
problems caused by the possible rejection of whole batches of
assembled devices because of non-compliance with the
Tracker environment. This would clearly benefit both the
component suppliers and the CMS groups responsible for the
optical links.
The AVT procedures will be applied to the lasers,
photodiodes and optical fibre. These elements of the optical
links are recognised as being the most sensitive to the Tracker
environment, particularly the strong radiation field.

The advance validation procedure is outlined in Fig. 5. Where
AVT overlaps with pre-production qualification of the same
components, it should be possible to streamline significantly
the pre-production qualification procedure. As with the other
QA tests, results will be archived in the EDMS database, and
a copy sent to the manufacturer.
Repeat
Procure new lot
Interact. with
manufacturer
Failure analysis
N
N
Sampling
Environmental
Testing
Annealing
Success?
Y
Accelerated ageing *
Success?
Y
Final clearance
Figure 5: Flow chart of the advance validation procedure.
* in some cases only
Advance clearance
One or more AVT's per component type will take place
during the pre-production and extending into the final
production period where necessary. Final device assembly
will proceed only after samples from laser and photodiode
wafers and naked fibre lots have passed the AVT.
A close working relationship is clearly necessary with the
various suppliers of these components, to ensure that the AVT
steps are achievable. The precise AVT procedures, actions,
and schedule will be agreed in the final contracts.
D. Lot validation
Once pre-production components and assemblies have been
fully qualified, production can be launched. Lot validation
involves sample testing of every delivered batch, as in Fig. 6,
with the outcome of either accepting or rejecting the tested
lot.
Results of lot validation tests will be archived in the EDMS
database, with a summary sent to the manufacturer. The lot
validation step does not include environmental testing and the
description here is only given to complete the brief outline of
the overall QA procedures. All the environmental QA tests
will be covered in the AVT and pre-production qualification
steps.
Interact. with
manufacturer
Failure analysis
Lot rejection
Procure new lot
N
Sampling
Functionality
(reduced test)
Success?
Figure 6: Flow chart of the lot validation procedure.
Y
Lot acceptance
III. ENVIRONMENTAL QA TEST PLANS
The procedures described in this section focus mainly on
radiation damage testing, since this is the most important
aspect of the environment affecting the optical links. The
Tracker will also operate at a temperature close to -10 °C and
in a 4T magnetic field. The atmosphere will be constantly
flushed, dry nitrogen. Concerning these the thermal aspect of
the Tracker environment, all the link components are already
specified for operation above -20°C. In addition, components
with magnetic packaging have been excluded and recent tests
have confirmed that the link performance is not affected by a
magnetic field of 4T[6].
A. Radiation damage effects
A brief summary of the radiation damage effects[3] observed
in tests carried out on all link components, during the
development phase of the project, are listed in Table 1.
Table 1: Summary of the effects of radiation damage in the optical
link components to be used in the CMS Tracker.
Component Radiation damage effects
Laser Threshold current increase and efficiency decrease.
Significant annealing of both effects.
No effect on wearout rate.
Photodiode Leakage current increase and responsivity loss. Some
annealing of leakage current but no significant
annealing of responsivity loss.
No effect on wearout rate.
Sensitive to SEU.
Optical fibre Increased attenuation. Significant annealing of damage.
No mechanical degradation.
96-way
Attenuation in the optical fibre.
Optical cable
No mechanical degradation.
Optical
No degradation.
connector
Laser driver
chip
Digital
receiver chip
No degradation.
No degradation.

B. Lab simulation of the radiation environment
In order to validate components for radiation hardness within
the production schedule we are forced to carry out accelerated
tests. For radiation effects testing this means using only a
limited number of radiation sources, and irradiating the
samples with fluxes or dose rates in excess of those expected
in the Tracker.
For each type of radiation damage mechanism, namely
ionization, displacement, or single event effect (SEE), we
therefore assume that the radiation damage effects from
different incident particles (or from particles of different
energy) can be compared at some basic level. Under this
assumption all validation for a given component, in terms of
testing each damage mechanism, can then be made with just
one type of radiation source per mechanism. We therefore
propose to use photon sources ( 60
Co, or X-ray) for ionization
damage tests, neutron sources for displacement damage tests
and proton sources for SEE tests. Suitable radiation sources
are identified in the QA manual[1].
The accelerated testing extends to measurements of annealing
and wearout degradation. These effects are usually thermally
activated and can be accelerated by increasing the
temperature. In all of the validation tests the effects expected
over the lifetime of the components within the Tracker are
then determined by extrapolation of the results from the
accelerated tests to the conditions expected at a given location
in the tracker.
C. Device-specific tests
A summary of the device-specific environmental QA tests is
given in Table 2. The most unusual aspect of the testing
programme, which is the advance validation testing, is
detailed in the following section with procedures for laser,
photodiode and optical fibre AVT.
The reader is referred to the QA manual[1] for full details of
the other environmental tests (and functionality) tests that are
foreseen.
Table 2: Summary of environmental tests to be performed on optical link components.
Tests in Italics involve other groups and are still to be finalised.
Optical link element Link system Pre-production qualification Advance validation
Laser diode chip Analogue and Digital - total dose, fluence and annealing
accelerated ageing
Laser transmitter Analogue and Digital magnetic field -
Laser driver Analogue and Digital total dose and annealing
accelerated ageing
SEE
-
Optohybrid substrate Analogue and Digital to be decided to be decided
Analogue optohybrid Analogue total dose, fluence and annealing
SEE
magnetic field
accelerated ageing
-
PIN photodiode receiver Digital magnetic field total dose, fluence and annealing
accelerated ageing
Digital receiver amplifier Digital total dose and annealing
accelerated ageing
SEE
-
Digital optohybrid Digital total dose, fluence and annealing
SEE
magnetic field
accelerated ageing
-
Optical fibre Analogue and Digital - total dose and annealing
Buffered fibre Analogue and Digital total dose -
Optical fibre ribbon Analogue and Digital total dose -
Ruggedized ribbon Analogue and Digital total dose -
Dense multi-ribbon cable Analogue and Digital total dose -
Optical connectors Analogue and Digital total dose
magnetic field
-

(i) Laser AVT.
At least 20 lasers will be irradiated from each candidate
wafer, then aged along with 10 unirradiated lasers in advance
of the final production of packaged devices from the given
wafer. All the samples should be packaged in the final form,
to facilitate mounting and testing, and will have already been
burned-in prior to delivery.
The lasers will be irradiated under bias, with gamma rays and
then neutrons, up to the worst-case equivalent doses and
fluences. Both gamma and neutron irradiations will be made
at room temperature with in-situ monitoring of the laser L-I
and V-I characteristics at periodic intervals before, during and
after irradiation. The rates of degradation and annealing of the
threshold current and output efficiency can therefore be
determined and the results of the damage and annealing tests
can then be extrapolated to the conditions of damage and
annealing expected in the Tracker.
In the accelerated ageing step the devices will be operated at
80°C for at least 1000 hours to measure any potential wearout
degradation. The inclusion of both irradiated and unirradiated
samples allows a control of any possible degradation
mechanisms that are due to radiation damage. Measurements
of the laser L-I and V-I characteristics will be made at
periodic intervals during the ageing test. In between
measurement cycles, the lasers will be biased at 60mA. This
represents the maximum current available with the final laser
driver.
Any failure will be analysed post-mortem, in order to
establish the cause of failure. Only failures that are intrinsic to
the device-under-test will be counted in the statistics of the
test. For example, any failure of wire-bonds from the laser to
the test-board will not be counted.
Proposed acceptance criteria for pre-production qualification
and advance validation are such that 90% of the lasers should
remain within all the operating specifications for the system,
under the worst-cases of radiation damage exposure, and any
additional wearout degradation, when extrapolating to the full
10year lifetime of the links.
(ii) Photodiode AVT.
20 photodiodes will be irradiated from a given wafer, and then
aged along with 10 unirradiated photodiodes. The devices
should be packaged in the final form and have been burned-in
before delivery.
The photodiodes will be irradiated under bias, with gamma
rays and then neutrons, up to the worst-case equivalent doses
and fluences. Both the gamma and neutron irradiations will be
made at room temperature with in-situ monitoring of the
photodiode leakage and response characteristics made at
periodic intervals before, during and after irradiation. The
rates of degradation and annealing can therefore be
determined.
The devices will be aged at 80 °C for at least 1000 hours to
determine the rate of long-term wearout degradation. In-situ
monitoring will be used to make measurements of the
photodiode leakage and response characteristics at periodic
intervals during the ageing test. The photodiodes will be
biased constantly at -2.5V.
A similar type of failure analysis, acceptance criteria and
rejection action will apply for the photodiodes as for the laser
diodes.
(iii) Optical fibre AVT.
Bare optical fibre samples from each preform will be tested
by advance validation to ensure that it is suitable for use in the
CMS Tracker, before it is integrated into the final production.
The same type of bare fibre is used in all parts of the links: the
buffered fibre for pigtails and ribbonized fibre for the
ruggedized 12-way cables and the 96-way cables.
Two 100m long samples of optical fibre per preform will be
irradiated with gamma rays and neutrons up to the maximum
dose and fluence expected inside the Tracker. In-situ
measurements of the radiation-induced attenuation in the fibre
and the subsequent annealing will be performed in these tests.
The proposed acceptance criterion for the preforms tested in
the advance validation is that the loss will be no more than
50dB/km. This would be equivalent to a loss of 0.5dB over
~10m of fibre per link channel situated inside the Tracker.
IV. CONCLUSION
All of the components in the CMS Tracker optical links are
either commercial off-the-shelf (COTS) components, or
devices based on COTS. It is therefore necessary to extend
environmental validation tests from the development phase all
the way into the production phase of the project.
This document reviewed some of the various test procedures
related specifically to compliance of the various components
with the CMS Tracker environment, particularly the intense
radiation field.
Advance validation test (AVT) procedures have been
introduced as a special measure within the QA programme.
These procedures should allow the problems associated with
the possible rejection of fully assembled batches of noncompliance
of COTS components to be avoided.
V. ACKNOWLEDGEMENTS
The success of the QA programme depends upon a good
working relationship between the optical link development
team and the various suppliers. We gratefully acknowledge all
the suppliers and their valuable contributions to this work.
VI. REFERENCES
[1] CMS Tracker Optical Links Quality Assurance Manual.
K. Gill, J. Troska and F. Vasey (2001).
[2] CMS Tracker Technical Design Report. CERN LHCC 98-
6 (1998).
[3] A full list of publications of radiation damage tests carried
out within the framework of the CMS Tracker Optical Links
Project (1996-2001), is available at:
http://cms-tk-opto.web.cern.ch/cms-tk-opto/rad_pubs.html
[4] G. Cervelli et al., "A linear laser driver array for optical
transmission in the LHC experiments", Proceedings of
IEEE/NSS conference, Lyon (2000).
[5] F. Faccio et al., "Status of the 80Mbit/s Receiver for the
CMS digital optical link", 6th LEB Workshop Proceedings,
299 (2000).
[6] T. Bauer et al., CMS Note in preparation.

Design and Performance of a Circuit for the Analogue
Optical Transmission in the CMS Inner Tracker
M.T. Brunetti, G.M. Bilei, F. Ceccotti, B. Checcucci, V. Postolache, D. Ricci, A. Santocchia
Abstract
A new circuit for the conversion of analogue electrical
signals into the corresponding optical ones has been built
and tested by the CMS group of Perugia. This analogue
opto-hybrid circuit will be assembled in the readout
electronic chain of the CMS tracker inner barrel. The
analogue opto-hybrid is a FR4 (vetronite) substrate
equipped with one programmable laser driver chip and 2 or
3 laser diodes, all being radiation tolerant. The description
of the circuit, production flow and qualification tests with
results are reported and discussed.
I. CIRCUIT LAYOUT
The analogue opto-hybrid circuit designed and built by
the Perugia CMS group [1] will be employed in the
analogue optical link of the TIB (Tracker Inner Barrel) and
TID (Tracker Inner Disks) parts of the CMS tracker [2]. A
similar circuit has been prototyped for the TOB (Tracker
Outer Barrel) and TEC (Tracker End Caps) at CERN. The
schematic of the analogue optical link is reported in Figure
1.
Patch
panels
2 or 3
12
Opto-Hybrid
12
8 x 12
~ 65m
Receiver Module
Control
A
D
C
TIMING
INFN Sez. di Perugia, Via A. Pascoli, 06123 Perugia, Italy
MariaTeresa.Brunetti@pg.infn.it
Detector PLL Hybrid Delay
Link
Interface
TT
MUX
2:1
amplifiers
pipelines
128:1 MUX
APV
processing
buffering
compression
TTC
Figure 1: The tracker analogue optical link.
R L
Control
VME
DAQ Control
Detector
Front End
Back End
FED
Readout
memory
The analogue opto-hybrid converts the differential input
voltage, coming from silicon microstrip detectors and
sampled by the APV chips, into analogue optical signals
transmitted via optical fibres to the back-end electronics.
Each fibre will carry the multiplexed signals of 256 silicon
detector microstrips. A total of 4000 analogue opto-hybrids
for the TIB/TID system is required.
The dimensions of the PCB are 30 x 22 mm 2 and 0.5
mm in thickness. Figure 2 shows the upper side of the optohybrid
circuit housing the connector, the un-packaged laser
driver chip [3,4] and passive components.
Figure 2: Connector side view of the analogue opto-hybrid.
COTS (Commercial Off-The-Shelf) components are
used extensively in the opto-hybrid circuit for cost saving
strategy. Laser diodes and the coupled optical fibres are
located in the backside respect to the Figure 2. The laser
driver chip is programmable via the I 2 C interface and biases
the laser diodes in their linear operational region. Input
signals from the front-end amplifier directly modulate the
bias current and are converted into optical signals
(wavelength 1310 nm) by commercially available InGaAsP
edge-emitting laser diodes. They are then transmitted to
InGaAs photodiodes located at the receiver side for optical
to electrical conversion. The number of laser diodes (fibres)
is 2 or 3 depending on the opto-hybrid position in the
detector. Both laser driver and laser diodes are glued to the
substrate with a thermally conductive resin (Epo-Tek
T7110) and the electrical contact is made through
ultrasonic wedge-to-wedge aluminium wire bonds.
Actually, PCB has to be redesigned to house next version
of laser driver that will be packaged.

II. PRODUCTION FLOW
In the production phase (2002-2004), the analogue
opto-hybrid circuit will be assembled by following the
scheme reported in Figure 3.
Figure 3: Production flow of the analogue opto-hybrid.
The opto-hybrid substrate is produced in industry, while
the active devices (laser driver and laser diodes) are
procured by CERN. All these subcomponents are 100%
tested. The assembly of the circuit using COTS and active
devices is done by the manufacturing industry that will take
care of the test on 100% of the production. Perugia will
receive the opto-hybrids and will test a sample (see the
following paragraph). The circuits will then be sent to CMS
tracker sub-assembly centers in order to be mounted in the
front-end modules. At present, about 30 opto-hybrid
circuits have been produced by the manufacturing industry
and delivered to the CMS group of Perugia.
III. CHARACTERISATION
A series of tests to characterise the opto-hybrid circuit
have been defined in the specifications for the CMS tracker
optical link [5]. Electrical tests, thermal cycles and
irradiation tests are some of those required for the circuit
qualification. Table 1 reports the complete list of the tests
to be done both by the manufacturer (i.e. the manufacturing
industry) and the Perugia CMS group for TIB/TID. The
main effort in the test activity is foreseen before production
during product qualification when extensive measurements
are required. In the subsequent production phase, the
industry will be provided with an ATE (Automatic Test
Equipment) by CERN for the lot validation tests. Test
centres are charged with the lot acceptance tests on a
sample of the production.
Table 1:
Specification to be
Manufacturer CMS Institute in charge
tested Product Lot validation Product
Lot
qualification (before delivery qualification acceptance
Number of channels ♦ ♦ ♦ ♦
Gain ♦ ♦ ♦
Peak signal to noise ratio ♦ ♦ ♦
Integral linearity deviation ♦ ♦ ♦
Bandwidth ♦ 1 ♦ 1 ♦ 1
Settling time to ±1% ♦
Skew ♦
Jitter ♦
Crosstalk ♦
Max. operating input
♦ ♦ ♦
voltage range
Input voltage range ♦ ♦ ♦
Input impedance ♦
Quiescent operating point ♦ ♦ ♦
Quiescent operating point
after reset
♦ ♦ ♦
Hardware Reset ♦ ♦ ♦
Power supply ♦
Power
ratio
supply rejection
♦
Power dissipation
Wavelength
♦
Output power range ♦ ♦ ♦
Pre-bias output resolution ♦ ♦ ♦
Magnetic field ♦
Hadronic fluence ♦
Gamma radiation dose ♦
Temperature ♦
Operating humidity ♦
* rise time and fall time measurements
A. Electrical Tests
Some of the electrical tests reported in Table 1 have
been done on 5 out of 30 analogue opto-hybrids already
delivered to Perugia. Before starting the tests, each laser
diode has to be biased at its working point, i.e. the current
value corresponding to the linear response region (typically
a few mA). This is achieved through the programmable
laser driver that permits also to set the gain of the signal
between 5 mS and 12.5 mS. These features are used to
compensate changes in laser characteristics caused by the
tracker radiation environment. Since the bias current
depends on the temperature, the electrical specifications are
referred to 25 °C. The electrical tests reported in this paper
are the link gain measurements, the noise, the deviation
from linearity and the bandwidth. The set-up is shown in
Figure 4, except for the bandwidth measurement, where a
network analyzer is employed. The input signal is
generated by an AWG (Arbitrary Waveform Generator)
and is converted into a differential signal for input to the
analogue opto-hybrid. The test card is connected to the
opto-hybrid by a kapton cable and provides the power
supply and the inputs (data and clock lines) to the circuit.
The opto-hybrid output signal carried by the optical fibres
is converted into an analogue electrical signal by a
prototype of the optical link receiver [6]. The output is
digitized by the 16 bit ADC and data are stored in the
computer which runs Labview.

Figure 4: Set-up for electrical tests of the analogue optohybrid.
1)Link Gain
The gain of the laser driver chip is configurable via the
I 2 C interface. The nominal values are 5, 7.5, 10 and 12.5
mS. The link gain, G, is estimated by measuring the link
transfer characteristic. A 100 step input voltage ramp (staircase)
between –500 mV and 500 mV is generated by the
AWG and the output is acquired by the 16-bit resolution
ADC. Figure 5 reports the link transfer characteristic of a 3channel
opto-hybrid at the lowest laser driver gain value.
Output voltage (V)
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
OH12Ch0
OH12Ch1
OH12Ch2
-0.8 -0.4 0.0 0.4 0.8
Differential input voltage (V)
Figure 5: Output voltage as a function of the differential
input voltage for a typical 3-channel opto-hybrid.
The link gain G is then calculated from a linear
regression fit over a range extending from –300 up to 300
mV. Values between 0.9 and 1.2 have been found for tested
opto-hybrids. These values are higher than the
specifications, but the receiver used has a greater gain
respect to its final version.
2)RMS-Noise
The RMS-noise dY(X) has been measured with the
oscilloscope for each level of the voltage ramp generated
by the AWG. For ease of comparison the measured RMS
noise is referred to the link input to obtain the Equivalent
Input Noise (EIN):
dY(X)
EIN =
G
Specifications on the optical link require 2.4 mV as the
maximum value for EIN in the interval between –300 and
300 mV. Figure 6 reports the EIN for the 5 tested optohybrids.
Equivalent Input Noise (V)
5.0x10 -3
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8
Differential input voltage (V)
Figure 6: Equivalent Input Noise for the measured optohybrid
channels.
Almost all of tested opto-hybrids have the EIN value inside
the specification. A 2-channel opto-hybrid shows a higher
noise
3)Deviation from linearity
The link transfer characteristic measurement is also
used to determine the deviation from linearity of the optohybrid
response. The linear regression fit is used to
calculate the Equivalent Input Non Linearity, EINL(X),
defined as:
Y(X) − GX
EINL(X) =
G
where Y(X) is the measured output voltage and GX is the
linear fit. The specification limits to EINL are stated as
follows: 9 mV in any 100 and 200 mV window within –300
and 300 mV, 18 mV in any 400 mV window within the
same range. The equivalent input non linearity (EINL) for
some of the tested opto-hybrid channels is reported in
figure 7. Results are within the specifications given above.
4)Bandwidth
The bandwidth of the optical link has been measured by
a network analyser. Values found for the tested optohybrids
are around 90 MHz, slightly lower than
specifications. These results are, nevertheless, in agreement
with those found for the laser driver itself. Higher values of
the bandwidth will be achieved in the future with a speeder
laser driver.

4.0x10 -2
Equivalent Input Non Linearity (V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
Input voltage range (V)
Figure 7: Equivalent Input Non Linearity for the measured
opto-hybrid channels.
B. Thermal qualification
The nominal operating temperature of the CMS tracker
is –10 °C. The thermal qualification of the opto-hybrid
equipped with all its parts follows some preliminary
validation tests on single components. As an example, the
choice of the resin type for the gluing of the laser driver
and laser diodes to the substrate is heavily affected by its
thermal response. Outgassing during the resin cure time is
strongly unwanted, since it likely damages optoelectronic
components.
A total of 100 consecutive cycles has been currently
used for a preliminary test on the CTE (Coefficient of
Thermal Expansion) matching between the opto-hybrid
substrate, the resin and the components. At this stage, only
dummy optoelectronic components have been used. The
temperature cycle generated by the climatic chamber used
for the thermal qualification is reported in Figure 8. The
thermal qualification of the fully populated opto-hybrid
circuit will be the scope of future tests.
Figure 8: Temperature cycle generated by the climatic chamber.
C. Irradiation qualification
The radiation environment corresponding to 10 years of
LHC life has to be reproduced in irradiation facilities with
beams of nucleons and gammas in order to check the
radiation hardness of the opto-hybrid circuit. A first survey
was done by irradiating with low energy neutrons (

Status Report of the ATLAS SCT Optical Links.
D.G.Charlton, J.D.Dowell, R.J.Homer, P.Jovanovic, T.J. McMahon, G.Mahout
J.A.Wilson
School of Physics and Astronomy, University of Birmingham, Birmingham B15 2TT, UK
N. Kundu, R.L.Wastie, A.R.Weidberg
Physics Department, Oxford University, Keble Road, Oxford, OX1 3RH, UK,
t.weidberg@physics.ox.ac.uk
S.B. Galagedera, J. Matheson, C.P. Macwaters, M.C.Morrissey,
CLRC Rutherford Appleton Laboratory, Chilton, Didcot, Oxon, OX11 OQX, UK
Abstract
The ATLAS SCT optical links system is reviewed. The
assembly and testing of prototype opto-harnesses are
described. Results are also given from a system test of the
SCT barrel modules, including optical readout.
I. INTRODUCTION
Optical links will be used for the readout of the ATLAS
SCT and Pixel detectors [1]. The specifications for the links
are summarised briefly in section II. The radiation hardness
of the system is briefly reviewed in section III. The
assembly and test results of the prototype barrel optoharness
are described in section IV and a similar discussion
is given for the forward fibre harness is given in section V.
Some results from the SCT barrel system test are given in
section VI. Conclusions and future prospects are discussed
in section VII.
A.Rudge, B. Skubic
CERN, CH-1211, Geneva 23, Switzerland
M-L.Chu, S.C.Lee, P.K.Teng, M.J.Wang, P.Yeh
Institute of Physics, Academia Sinica, Taipei, Taiwan 11529.
II. LINKS SPECIFICATIONS
The SCT links transfer digital data from the SCT
modules to the off-detector electronics (RODs) at a rate of
40 Mbits/s. Optical links are also used to transfer Timing,
Trigger and Control (TTC) data from the RODs to the SCT
modules. Biphase mark encoding is used to send the 40
Mbit/s control data for a module on the same fibre as the 40
MHz bunch crossing clock.
The architecture illustrated in Figure 1 below, contains
immunity to single point failure to maximise the system
robustness[1]. If a TTC link to a module fails, the TTC data
can be routed to a module from the opto-flex of its
neighbour module. 12 modules are connected in a
redundancy loop. One data link reads out the data from the
6 ABCDs on one side of the module. If one of the two data
links for a module fails, the corresponding data can be
routed through the other data link.

Figure 1 SCT links architcture.
III. RADIATION HARDNESS
The radiation hardness and lifetime after irradiation of
the PIN diodes has been demonstrated up to a fluence of
10 15 1MeVneq/cm 2 [2].The radiation hardness and lifetime
after irradiation of VCSELs produced by Truelight have
been tested with good results[3]. The radiation hardness
and lifetime of the front-end ASICs VDC and DORIC4A
have been shown to be sufficient for the SCT
application[4]. The pure silica core step index fibre has
been shown to be extremely radiation hard[5]. The effects
of Single Event Upsets on the system have been studied
and shown to be acceptable for the SCT operation in
LHC[6].
IV. BARREL OPTO HARNESS
The barrel opto-harness provides all the electrical and
optical services for 6 barrel SCT modules. A harness
contains 6 opto-flex kapton cables connected to 6 sets of
low mass Aluminium tapes to bring in the electrical power.
The VCSEL/PIN opto-package and the DORIC4A and
VDC ASICs[4] are die bonded to the opto-flex and then
wire bonded as shown in Figure 2 below. The single fibres
from the pig-tailed opto-package are protected by 900 um
diameter furcation tubing. The two data fibres from each
opto-flex are fusion spliced to a 12 way ribbon and the 6
TTC fibres are fusion spliced into a 6 way ribbon. The data
and TTC ribbons are terminated with MT 12 and MT8
connectors.
Figure 2 Opto-package and ASICs wire bonded to optoflex.
Figure 3 Opto-flex and Aluminium low mass cables with
three fibres in furcation tubing.
The completed harness is shown in Figure 4 below.
Figure 4 A prototype barrel opto-harness.
The average coupled power of the VCSELs was measured
as a function of the drive current and the results are shown
in Figure 5 below.

Figure 5 LI curves for VCSELs on a opto-harness. The
mean DC power is measured at 50% duty cycle.
The BER of the data links were measured by sending 40
Mbits/s psuedo-random data to the VDC ASICs[4] and
receiving the optical signal with 4 channel PIN arrays and
the DRX-4 receiver ASIC. The results for the BER scan as
a function of the DAC value, which controls the DRX
discriminator level, is shown in Figure 6 below. From this
it can be seen that there is a wide range of DAC values for
which the system can be operated without any errors.
Figure 6 BER scan for the 12 data links on a harness as
function of the DAC value that sets the discriminator
value for the DRX-4 ASIC.
The BER of the TTC links was measured in a similar
way. The BPM-4 ASIC was used for biphase mark
encoding of the 40 Mbits/s control data signal with the 40
MHz clock and used to drive VCSELs. The optical signal
was taken to the PIN diode on the opto-package and the
resulting electrical signal decoded by the DORIC4A
ASIC[4] on the opto-flex cable. The BER was measured by
comparing the recovered data with the sent data. The BER
was measured as a function of the DAC value, which
controls the amplitude of the optical signal. The results for
one harness are shown in Figure 7 and demonstrate that
there is a large range of DAC values for which the system
works reliably.
Figure 7 BER scan for the 6 TTC links on a optoharness
as a function of the DAC value which sets the
current for the VCSELs.
Four such prototype barrel opto-harnesses have been
assembled and tested. These opto-harnesses are being used
in the barrel SCT system test at CERN (see section VI).
V. FORWARD FIBRE HARNESS
The services for one of the forward SCT disks is
illustrated in Figure 8 below.
Figure 8 Forward SCT services
The electrical and optical services for the forward SCT
are separated. The optical services consist of 6 optopackages
assembled on a PCB with a 6 pin connector. The
PCB plugs into a connector on the main forward SCT
hybrid and the DORIC4A and VDC ASICs are mounted on
the hybrid. A photograph of one of these forward opto
plug-in packages is shown in Figure 9 below.

Figure 9 photograph of a forward SCT plug-in optopackage.
The individual fibres are protected by the same
furcation tubing as for the barrel. The individual fibres are
spliced into 12 way and 6 way ribbons in the same way as
for the barrel opto-harness. A photograph of a completed
forward fibre harness is shown in Figure 10 below.
Figure 10 A forward fibre harness containing 6 plug-in
opto-packages.
Six of these forward fibre harness have been assembled.
Equivalent tests as those performed for the barrel fibre
harness have been performed and they are all fully
functional.
VI. BARREL SYSTEM TEST
The four barrel opto-harnesses have been used in the
SCT barrel system test at CERN. A photograph of 15 barrel
SCT modules mounted on a carbon fibre sector with three
of the the four opto-harnesses is shown in Figure 11 below.
Figure 11 The barrel SCT system test.
The system test has been used to perform many studies
and full information is available[7]. One of the key tests
performed was to measure the noise of modules in the
system test and compare this with the noise values
measured for individual modules on an electrical test stand.
The results shown in Figure 12 below show no evidence for
any excess system noise.
Figure 12 Measured noise for modules measured with
optical readout at the system test compared with
measurements of the same modules on an electrical test
stand.
One of the key performance specifications for a binary
system is the noise occupancy. The results of noise
occupancy measurements for the 12 ASICs on the 15 barrel
modules are shown in Figure 13 below and are generally
lower than the system specification of 5 10 -4 .

Figure 13 Measured noise occupancy for the 15 barrel
SCT modules in the system test as a function of chip
number on the module.
Another interesting measurement from the point of view
of the optical links is the use of the redundant TTC links.
This requires sending the TTC signals to a relatively long
way to a neighbour module. Since these lines run parallel to
the silicon strips there is a potential pick-up problem. To
test this 12 modules were mounted on neighbouring
harnesses. The redundant TTC links were used for 8 out of
the 12 modules (those for which the redundant TTC links
were functional). The noise was measured for this
configuration and compared with the noise measured with
the modules receiving their normal TTC data (local TTC
data). The data shown in Figure 14 below show no
evidence for any significant increase in noise.
Figure 14 Measured difference in noise for modules
read out using the redundant TTC links compared to
the noise measured using the normal TTC links.
VII. CONCLUSIONS AND OUTLOOK
Prototype barrel and forward SCT harnesses have been
successfully assembled and tested. The barrel harnesses
have been used in the barrel SCT system test at CERN. The
results are very encouraging for the operation of the
system. Slightly modified prototype harnesses are now
being assembled to take into account the new round cooling
pipe. A further round of system tests will be required for
these harnesses as well as a forward SCT system test.
The prototyping for the on-detector components should
be completed this autumn and production started early in
2002.
VIII. ACKNOWLEDGEMENTS
Financial help from the UK Particle Physics and
Astronomy Research Council is acknowledged.
IX. REFERNCES
1. ATLAS Inner Detector TDR, CERN/LHCC/97-
16.
2. J.D. Dowell et al., Radiation Hardness and
Lifetime Studies of the Photodiodes for the
Optical Readout of the ATLAS SCT, Nucl. Instr.
Meth. A 456 (2000) 292.
3. Information available on www at url:
http://hepmail.phys.sinica.edu.tw/~atlas/radiation.
html
4. D.J. White et. al., Radiation Hardness Studies of
the Front-end ASICs for the Optical Links of the
ATLAS SemiConductor Tracker, Nucl. Instr.
Meth. A457 (2001) 369.
5. G. Mahout et al, Irradiation Studies of multimode
optical fibres for use in ATLAS front-end links,
Nucl. Instr. Meth. A 446 (2000) 426.
6. J.D. Dowell et. al., Single Event Upset Studies
with the optical links of the ATLAS
semiconductor tracker, accepted for publication in
Nucl. Instr. Meth. A.
7. Information available on www at url:
http://asct186.home.cern.ch/asct186/systemtest.ht
ml.

Prototype Analogue Optohybrids for the CMS Outer Barrel and Endcap Tracker
J. Troska, M.-L. Chu † , K. Gill, A. Go ∗ , R. Grabit, M. Hedberg, F. Vasey and A. Zanet
CERN, CH-1211 Geneva 23, Switzerland
∗ Department of Physics, National Central University, Taiwan
†
High Energy Physics Laboratory, Institute of Physics, Academia Sinica, Taiwan
jan.troska@cern.ch
Abstract
Prototype analogue optohybrids have been designed and
built for the CMS Tracker Outer Barrel and End Cap
detectors. The total requirement for both types in CMS is
12900 that will be assembled between 2002 and 2004. Using
very close to final optoelectronic and electronic components
several optohybrids have been assembled and tested using
standardised procedures very similar to those to be
implemented during production. Analogue performance has
met the specifications in all cases when operated in isolation
and when inserted into the full prototype optical readout
system.
I. INTRODUCTION
The CMS Tracker readout system consists of ~10 million
individual detector channels that are time-multiplexed onto
~40000 uni-directional optical links for transmission between
the detector and ~65m distant counting room[1]. Data are
transmitted in analogue fashion for digitisation at the Front-
End Driver (FED) Boards located in the shielded counting
room. Thus only the transmitting elements of the analogue
optical links are located in the radiation area of the
experiment. All electro-optical components of the optical
transmission system have been proven to function within
specifications after exposure to radiation levels beyond those
expected in the CMS Tracker[2,3]. A system-level diagram
of the CMS Tracker readout system is shown in Figure 1.
Hybrid circuits are required to carry the electro-optical
components (linear laser driver and 2 or 3 laser diodes) to be
situated in close proximity to the detector hybrids distributed
throughout the CMS Tracker. A block diagram highlighting
the required interfaces of the analogue optohybrid is shown in
Figure 2. The requirement for such Optohybrids matches the
number of detector hybrids one-to-one, yielding a total
number for the whole Tracker of approximately 17000.
Responsibility for the design and procurement of optohybrids
has been split according to the destination of the optohybrids
within the Tracker: HEPHY Wien (Austria) has the
responsibility to supply the 12900 optohybrids for Tracker
Outer Barrel (TOB) and Tracker EndCap (TEC); while INFN
Perugia (Italy) will supply the remaining fraction for Tracker
Inner Barrel (TIB) and Tracker Inner Disks (TID).
The Tracker Optical Links group at CERN has developed
several prototype optohybrids suitable for use by TOB and
TEC. The prototype development was carried out by CERN
as the responsibility for the final supply was only recently
apportioned. This paper will describe the prototype circuit,
the test methods used to characterise its performance and the
results obtained from this characterisation.
Patch
Panels
Control
2 or 3
12
Optohybrid Detector PLHybrid L Delay
12
~ 65m
8 x 12
Receiver Module
Link
Interface
R L
TTC
TT
MUX
2:1 amplifiers
pipelines
128:1 MUX
APV
Front End
(Radiation zone)
Back End
(Counting Room)
FED
ADC processing
buffering
compression
Control
VME
Timing DAQ Control
Detector
Readout
Memory
Figure 1: CMS Tracker Readout System, with Analogue Optical
Link highlighted on left-hand side.
Differential
signal inputs
from
APV 2
Mux
Electrical
connector
i/o control
hybrid (I 2 C) Reset
Driver
Lasers
Fibre clamp
0.3 to 3m
Fibre bundle to
distributed patch panel
Figure 2: Analogue optohybrid block diagram.
II. ANALOGUE OPTOHYBRID DESIGN
The major design-driver of the optohybrid substrate layout
was the physical size of the final object, as the optohybrid
must integrate into the mechanical structure of the Tracker
system were space is at a premium. Effort was placed in
achieving a design which meets both TOB and TEC
requirements and a solution was found which is adapted to
both sub-systems by simple differential assembly – the
electrical interface connector is mounted on the componentside
for the TOB and the reverse-side for the TEC. In all
other respects the two optohybrid types are identical.
The electrical design and layout of the prototype
TOB/TEC optohybrid was done at CERN and the PCBs were
subsequently produced in Taiwanese industry. The board
layout is shown in Figure 3, which also shows the dimensions

of the PCB: 23 × 30 mm. The PCB thickness is 0.5mm,
leading to an overall thickness of a populated TOB optohybrid
of 3mm and of a populated TEC optohybrid of 6mm. The
prototype optohybrid design is specific to the first version of
linear laser driver ASIC realised in 0.25µm technology, but
can host two types of laser diode from candidate
manufacturers. Attachment points have been added to meet
the requirements of TOB and TEC in terms of cooling as well
as mechanical restraint.
Of the 30 optohybrid substrate PCBs produced, 10 were
populated with passive components in Taiwan, while the
remaining 20 of the prototype batch were fully assembled at
CERN. In all cases the ASIC and laser diodes were glued and
wire-bonded at CERN. Examples of fully populated TOB and
TEC optohybrids are shown in Figure 4.
1
NAIS Header
VDD
____
Iout
Laser Driver
A
A C
A C
C A
C A
C
C
A
Laser
Figure 3: Layout of CERN-design Analogue Optohybrid, showing
connector header on left-hand side, driver ASIC in the center and
lasers on right-hand side.
Figure 4: TOB (top) and TEC (bottom) optohybrids with MU optical
connector.
Half of the total prototype run of 30 optohybrid substrates
have been assembled with connector sockets for use as TECtype
optohybrids, with the other half having been assembled
with connector headers for use as TOB-type optohybrids.
Eleven TEC-type optohybrids have been assembled with a
full complement of three laser diodes using four different
prototype configurations of laser diode- and optical connector
type. The remaining four TEC-type optohybrids were used as
mechanical samples. Eight TOB-type optohybrids have to
date been assembled with three laser diodes of the latest
generation of close-to-final laser packaging configuration and
MU-type optical connectors as shown in Figure 4.
It should be noted that the optohybrids produced could be
used in CMS but for the fact that the ASIC design has
changed sufficiently to require a PCB layout change. This is
partly due to the fact that the laser driver will be placed in a 5
× 5 mm LPCC package, which will simplify the assembly of
the optohybrid by reducing the number of wire-bonds
required during assembly and allow pre-testing of the ASIC.
III. TEST METHODS
Testing of the prototype optohybrids has been carried out
in-system by measuring the performance via pre-prototype
optical receivers. The test methods used have previously
been described in detail[4], but will be outlined here.
Static characterisation of optical links containing
optohybrids is carried out as follows: (Refer to Figure 5)
1. A fast ramp (staircase) is injected at the optohybrid
input
2. This ramp is measured at the output of the optical
receiver using a 12-bit ADC to obtain the transfer
characteristic
3. A slow ramp (staircase) is injected at the optohybrid
input
4. At each DC level of the ramp the AC-coupled output is
sampled with an oscilloscope to obtain the noise
GPIB
Arbitrary
Wavefunction
Generator
AOH
Computer
MU
MPO
Rx
Trigger 1
Trigger 2
GPIB
VME
ADC
Oscilloscope
Figure 5: Analogue OptoHybrid (AOH) Static Characterisation setup.
The linearity performance of the optohybrid under test can
be calculated as the deviation from a straight-line fit to the
static transfer characteristic. To assess the performance the
deviation from linearity is referred to the input of the optical
link to yield the Equivalent Input Non-Linearity (EINL). The
system specification for EINL is better than 12mV, which
corresponds to 2% integral non-linearity over the input
operating range of 600mV.
In order to assess the noise performance of the optohybrid
under test the measured raw noise is also referred to the input
to yield the Equivalent Input Noise (EIN). System
specification for EIN is better than 2.4mV over the optical
link input range 600mV, to allow for a system peak Signal to
Noise Ratio >256:1.
Dynamic characterisation of the prototype optohybrids
was carried out by measuring the pulse response of the optical
link system. A periodic input pulse train of ±400mV at
10MHz was used for this test. The rise time of the input
signal was below 1ns. The rise time of the output signal as
well as the output pulse shape was used to infer the dynamic
response of the optohybrid.

Crosstalk between channels on the prototype optohybrid
was measured by injecting the same signal used for dynamic
characterisation into one of the three channels on the
optohybrid under test and measuring the output of the other
channels using a separate receiver. In this way any receiver
crosstalk effects are removed from the measurement results.
All measurements (unless otherwise stated) were carried
out with the optohybrid under test located in a temperature
controlled chamber at 25°C.
The experience gained from optohybrid testing has been
used to define the test sequences for use during final
production and to provide a basis for the implementation of an
automated production test station for optohybrids.
IV. RESULTS
Of the 20 optohybrids fully populated with laser diodes to
date, 11 have been characterised using the methodology
described above. The same receiver channel has been used
throughout the characterisation series to facilitate comparison
between optohybrids without possible variations due to the
receiver. It should be noted that the receiver used for this
characterisation was a previous prototype design based on
discrete components[5] whereas the amplifier array foreseen
for use within CMS is a 12-channel ASIC. The gain of the
receiver used for these comparative tests is higher than that of
the final one, so that comparisons of the gain values obtained
here with the nominal optical link system gain of 0.8V/V must
be undertaken with caution. A further minor point is that the
voltage output of the prototype can be both positive and
negative and has a widely variable offset. In contrast the final
receiving amplifier has more limited offset adjustment and
only outputs positive signals.
The static characteristics of each optohybrid were
measured for all four possible gain settings (5.0mS, 7.5mS,
10.0mS & 12.5mS) of the laser driver. These measurements
yield a results-set such as the one shown in Figure 6 for each
optohybrid measured. The transfer curve Figure 6 (top) is
fitted with a straight line over the operating input range
(±300mV) and the resulting deviation of the data from the fit
computed to yield the non-linearity plotted in Figure 6
(middle), referred to the input by division by the measured
gain. The input referred noise (Figure 6 – bottom) completes
the basic results-set. The shaded areas in Figure 6 represent
the operating range (±300mV) and maximum input range
(±400mV) of the optical link, thus showing that the
measurements are carried out over a wider input range. The
nominal input to the optical link is 100mV per Minimum
Ionising Particle and the APV operating range is 600mV.
Figure 6 (bottom) shows the effect of gain on this
computed measurement: the measured raw noise being very
similar in magnitude for all gain settings. It is therefore
advantageous in terms of noise to operate the laser driver at
higher gain settings.
Link Output (V)
EINL (mV)
EIN (mV)
1.2
0.8
0.4
0.0
-0.4
-0.8
-1.2
12
10
8
6
4
2
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0mS
7.5mS
10.0mS
12.5mS
-0.8 -0.4 0.0 0.4 0.8
Differential Input (V)
5.0mS
7.5mS
10.0mS
12.5mS
-0.8 -0.4 0.0 0.4 0.8
Differential Input (V)
5.0mS
7.5mS
10.0mS
12.5mS
-0.8 -0.4 0.0 0.4 0.8
Differential Input (V)
Figure 6: Typical results-set for static characterisation of an analogue
optohybrid: (top) transfer curve; (middle) Equivalent Input Nonlinearity;
and (bottom) Equivalent Input Noise.
In order to more easily represent and compare the
performance of many optohybrids the static characteristics are
used to compute four figures of merit:
1. Link Gain: the slope of the straight line fit to the
data within the operating range.
2. Link linear range: the input range over which the
EINL is below the specified value of 12mV.
3. Average EIN: the mean value of EIN over the
operating range.
4. Input range within noise spec: the input range
starting at Vin = -300mV before EIN exceeds the
specified value of 2.4mV
The last figure of merit picks out channels which show
spikes in the noise characteristic (e.g. Figure 9) even where
the average EIN is below the specified value of 2.4mV.
Figure 7 shows the four figures of merit for the complete
results-set for eleven optohybrids at the four different gain
settings. Also marked on the figures are the relevant
specification levels for linear range, average EIN and input

ange within noise spec. It is clear that the majority of the
channels and gain settings measured meet the specified target
levels of performance and that good performance has thus
been achieved for this first prototype analogue optohybrid
design.
Link Gain (V/V)
Average EIN (mV)
4
3
2
1
0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1 2 3
AOH channel number
1 2 3
AOH channel number
Link linear range (V)
Input range within noise spec. (V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
5.0mS 10.0mS
7.5mS 12.5mS
1 2 3
AOH channel number
1 2 3
AOH channel number
Figure 7: Figures of Merit for eleven prototype analogue optohybrids
measured using standardised test procedures.
Dynamic measurements carried out on the prototype
analogue optohybrids show that the pulse response of the laser
driver ASIC is not degraded by its placement on the
optohybrid. Rise times in the range 3.8 – 4.2 ns were
obtained from pulse response measurements carried out.
These values translate to slightly lower bandwidth values than
the target of 90MHz, but are consistent with those carried out
on the laser driver ASIC itself. The speed of the laser driver
which will be used to equip future versions of the optohybrid
will be increased.
The measurement of crosstalk on the prototype optohybrid
yielded results comfortably within the specified value
(adjacent channel) of -55dB. The values obtained were
consistently below -60dB for the nearest neighbour channel
and dropped to below -70dB for the furthest neighbour
channel.
V. REFERENCE CHAIN OPERATION
In addition to the standalone characterisation of the
prototype analogue optohybrid described in the previous
section, some examples were included in a test of the full
optical link chain. In this investigation the prototype
optohybrids were inserted into a reference chain that
contained the final type- and number of optical connections
and approximately the final fibre lengths as foreseen for the
optical link system in CMS (Figure 1). Four TEC-type
optohybrids were placed on a carrier board which was placed
inside an environmental chamber so that the ambient
temperature during operation could be varied (see Figure 8).
The twelve optical channels (MU optical connectors) were
connected to a single-fibre to ribbon fan-in (sMU to MPO
connectors), then via ~100m ribbon fibre to a pre-final
prototype 12-way receiver module (MPO receptacle) housed
on a VME card.
Figure 8: Four optohybrids (ringed) on test board during reference
chain operation.
The static measurements described earlier were carried out
for all channels at both room temperature (25°C) and the
nominal optical link operating temperature when it is installed
in the CMS Tracker (-10°C). The results-set is shown in
Figure 9. For these measurements the gain setting at the laser
driver was chosen to give an overall channel gain as close to
the nominal value of 0.8 as possible, with the laser bias setting
then chosen to match the gain setting. The laser bias setting is
chosen so as to operate the optical link above the laser
threshold while keeping the bias current as low as possible.
Minimising the bias current ensures that the noise
performance over the entire input range of the optical link
(±400mV) is adequate – higher bias currents leading in
general to higher laser noise. The bias setting was revised to
take into account the lower laser threshold when operating at -
10°C, although for ease of comparison the gain setting was
not varied as the temperature changed.
Overall, the figures of merit obtained from the reference
chain measurements (Figure 10) are very encouraging. The
noise measured in the final-form optical link is lower than for
the measurements presented in the previous section. Linearity
remains good for all cases.
The figure of merit most systematically affected by the
change in operating temperature is the gain, which increases
for all channels at lower temperature. This is believed to be
largely due to changes in the coupling efficiency between
laser die and optical fibre within the small form-factor laser
diode package. It is clear that very good noise performance is
achieved especially at the lower temperature, while the gain
spread is tolerable[6].
As well as obtaining the same typical values of risetime as
for the measurements of the prototype optohybrids described
in the previous section, the final system was exercised using a
simulated APVMUX data-stream. An arbitrary waveform
generator was used to mimic the data that will be transmitted
through the final optical link in the CMS Tracker, where each
optical channel will be used to transmit the output stream of
one APVMUX channel. The data-stream as transmitted via a
typical optical link channel of the reference optical link chain
is shown in Figure 11. In the transition between temperatures
the laser bias setting was changed as described above.

Link output (V)
EINL (mV)
EIN (mV)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
12
10
8
6
4
2
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
25°C
-10°C
-0.8 -0.4 0.0 0.4 0.8
Differential Input(V)
25°C
-10°C
-0.8 -0.4 0.0 0.4 0.8
Differential Input(V)
25°C
-10°C
-0.8 -0.4 0.0 0.4 0.8
Differential Input(V)
Figure 9: Static characteristics of all reference chain channels at
room and operating temperatures: (top) transfer curve; (middle)
Equiv. Input Non-Linearity; and (bottom) Equiv. Input Noise.
Link Gain (V/V)
Average EIN (mV)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2 4 6 8 10 12
Receiver channel number
2 4 6 8 10 12
Receiver channel number
Link linear range (V)
Input range within noise spec. (V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
25°C
-10°C
2 4 6 8 10 12
Receiver channel number
2 4 6 8 10 12
Receiver channel number
Figure 10: Figures of Merit for all reference chain channels.
V out (V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
1
2
3
4
Time (µs)
25°C
-10°C
Figure 11: Simulated APVMUX data-stream at the output of the
prototype optical link with very close to final components.
VI. CONCLUSIONS
Approximately 20 prototype analogue optohybrids
suitable for use in the Outer Barrel and Endcap of the CMS
Tracker have been assembled from a common PCB design.
They have been populated with close-to-final electronic and
opto-electronic components and tested using standardised
procedures which will form the basis of production testing of
the final quantity of 12900.
The performance of the prototype optohybrids has been
reported to be within specifications for the majority of cases,
while the outliers of the distribution are not far from meeting
the required criteria. Figures of merit have been used to
reduce the large raw dataset to ease the comparison of many
devices. These provide an immediate overview of the key
analogue optohybrid performance parameters of gain,
linearity and noise.
With the successful testing of the first prototype analogue
optohybrids confidence has been gained that the transmitting
components of the analogue optical link for the CMS Tracker
can be successfully embedded into the overall system. Future
testing will put the prototypes described here into a larger test
of the full readout system including detector modules in their
final mechanical structures.
VII. REFERENCES
[1] Addendum to the CMS Tracker TDR, CERN/LHCC 2000-
016, CMS TDR 5 Addendum 1 (2000)
[2] “Radiation Damage and Annealing in 1310nm
InGaAsP/InP Lasers for the CMS Tracker”, K.Gill et al.,
SPIE Vol. 4134 (2000)
[3] “Radiation effects in commercial off-the-shelf singlemode
optical fibres”, J.Troska et al., SPIE Vol. 3440,
p.112 (1998)
[4] “Evaluation and selection of analogue optical links for the
CMS tracker - methodology and application”, F.Jensen et
al., CMS Note 1999/074
[5] “A 4-channel parallel analogue optical link for the CMS-
Tracker”, F.Vasey et al., Proc. 4 th LEB Workshop, Rome,
pp. 344-348 (1998)
[6] “A model for the CMS tracker analog optical link”,
T.Bauer et al., CMS Note 2000/056
5
6
7
8

An Optical Link Interface for the Tile Calorimeter in ATLAS
C. Bohm, D. Eriksson, K. Jon-And, J. Klereborn and M. Ramstedt
Abstract
An optical link interface has been developed in Stockholm
for the Atlas Tile-Calorimeter. The link serves as a readout for
one entire TileCal drawer, i.e. with up to 48 front-end
channels. It also contains a receiver for the distribution of
TTC clocks and messages to the full digitizer system.
Digitized data is serialized in the digitizer boards and supplied
with headers and CRC control fields. Data with this protocol
is then sent via G-link to an S-link destination card where it is
unpacked and parallelised with a specially developed Altera
code. The entire read-out part of the interface has been
duplicated for redundancy with two dedicated output fibers. The
TTC distribution has also been made redundant by using two
receivers (and two input fibers), both capable of distributing
the TTC signal. To decrease the sensitivity to radiation, the
complexity of the interface has been kept at a minimum. This
is also beneficial to the system cost. To facilitate the
mechanical installation, the interface has been given an Lshape
so that it can be mounted closely on top of one of the
digitizer boards without interfering with its components.
I. INTRODUCTION
Particle
Fiber
Module
Tile Calorimeter
Drawer
Figure 1: Schematic diagram of the Tile Calorimeter
A. The Tile Calorimeter Digitizer
The Atlas Tile Calorimeter Digitizer [1] digitizes signals
from about 10000 PMTs, which record the light generated
when particles are absorbed in the calorimeter. The detector
electronics is located in "drawers" in the base of each of the
256 calorimeter modules (Fig 1). Each drawer is responsible
for reading out 45 PMT channels (32 in the outer calorimeter
University of Stockholm, Sweden, October 2001
PMTs
daniel.eriksson@physto.se
sections). The PMT channels are digitized by 8 digitizer
boards, each capable of reading out 6 channels.
To achieve a high degree of fault tolerance for the readout,
the digitizers use Low Voltage Differential Swing, LVDS for
the data transmission, and are electrically organized in a star
formation, though mechanically mounted sequentially to
reduce the number of loose cables (Fig. 2). The 8 boards are
mounted so that they are read out from the end towards the
middle where the optical read-out interface is located. The
boards are connected with purpose designed flat cables made of
flexible capton films, "flex foils", in order to provide
impedance matched transmission lines.
TTC-rx
Tile_DMU Tile_DMU
TTC-rx
Tile_DMU Tile_DMU
TTC-rx
Tile_DMU Tile_DMU
interface
optical fiber
TTC-rx
Tile_DMU Tile_DMU
Tile_DMU Tile_DMU Tile_DMU Tile_DMU Tile_DMU Tile_DMU Tile_DMU Tile_DMU
TTC-rx TTC-rx TTC-rx TTC-rx
Figure 2: The data flow along a chain of digitizer boards
This, of course, makes the interface a very vulnerable part
of the read-out chain.
B. The Optical Link
An optical link read-out interface (Fig. 3) has been
designed and tested at Stockholm University. It is designed to
fit the over-all design philosophy of the digitizer system as
well as the mechanical constraints of the TileCal drawers.
Its task is to read out the data from 8 boards and to receive
and distribute TTC signals [2] to the digitizer boards. Each
board has 4 serial output lines and one clock input.
V CSEL
O/ E rec
V CSEL
Amplifier
Fan-out
Amplifier
O/ E rec Fan-out
TTC-r x
TTC-r x
MUX
Select ion
G-link MUX
G-link MUX
Figure 3: Schematic design of the link
LVDS LV DS
receiver rec
LVDS LV DS
receiver
rec
From digit izers 1-4
To digit izers 1- 4
From digit izers 5-8
To digit izers 5- 8
To 3- in-1
In order to match the fault tolerance it is necessary to avoid
single point failure modes in the design. Duplicating the
interface board was considered too expensive and not consistent
with the space requirements. However, the boards are designed
with two parallel systems that operate independently and have

separate fibers for transmission and reception. Both channels
transmit continuously, leaving the decision of which channel
to use to the link destination card. This design is based on the
dual G-link [7] concept developed for the Liquid Argon
Calorimeter.
The only functions that are not duplicated are the LVDS
receivers, the TTC multiplexers and the decision mechanism
that decides which of the two outgoing TTC channels should
be transmitted to the digitizers. One error among the LVDS
receivers will at worst kill the data from one digitizer board
since each receiver serves one board. An error among the TTC
multiplexers will at worst kill four boards. For the TTC
decision mechanism, the intended solution is to use the PLL
lock signal in one of the modules. There are provisions for
testing this method in the present design. There will also be a
circuit to ensure a long absence of lock before switching. An
error in this mechanism will at worst freeze the choice of TTC
channel.
II. READOUT
The readout design is intentionally made very simple. The
principle is to move the logic components away from the
interface card into the receiver card, whenever possible, thus
avoiding costly radiation tolerance. The receiver is responsible
for all operations on the data content, such as unpacking the
data, checking the CRC, choose which channel to use, and
reformatting the data for the appropriate application.
The readout uses the HDMP-1032 G-link from Agilent
Technologies. This is a 16 bit serial interface for transmission
rates up to 1.12 Gbit/s (32 bits at 35 MHz). This corresponds
to a transmission rate of 1.4 Gbaud, since the G-link adds 4
encoding bits. The link is presently run at 800 MBaud (20.04
MHz), which is the likely readout speed. However, it may be
possible that it will run at 1.6 GBaud (40.08 MHz), which
exceeds the specifications, but this has not yet been tested.
The data is first received by 8 LVDS to TTL converters,
each chip receiving 4 bits, corresponding to two TileDMUs.
This is the only connection between the redundant readout
channels, and a failure here will affect both channels. But since
there are 8 chips for the LVDS reception, a chip failure will at
most affect only two TileDMUs.
The data is then split to both readout channels, where it is
multiplexed to the 16 bit input of the G-link. By latching the
data on both rising and falling edge, there is no need for a
faster clock. The output from the G-link is designed to
transmit PECL swings directly into 50 ohm.
The transmission lengths between the TileDMUs and the
interface differ from board to board. To synchronize the data,
the TTC clocks on each digitizer board is shifted by using the
TTCrx [2] clock deskew function.
III. TTC DISTRIBUTION
The interface card is also responsible for distributing the
TTC signal to the digitizers. This distribution uses the same
concept as the readout. Two channel redundancy with separate
receivers and fibers, and a low level of complexity.
The TTC signal received by each channel is first split in
four by a 4-port LVDS repeater. One signal for the 3-in-1
system [3], one for the channel’s own TTCrx, and two for the
digitizers. The latter signals are then split again, also using 4port
LVDS repeaters, two for each channel, for transmission
to the 8 digitizer boards. By using the high impedance feature
of the repeaters, the transmission lines can be driven by either
of the two channels.
For the channel selection, an analog band pass filter with
discrete components was first intended, and implemented on
the card, but a second solution, using the TTCrx READY
signal will also be tested. The READY signal is set when the
TTCrx PLL locks on to the incoming signal. With the second
solution, channel switching will only occur if the TTCrx
cannot establish lock. This solution may also include a delay
to avoid unnecessary switching, depending on how robust the
TTCrx READY signal is.
IV. IMPLEMENTATION
There are a number of constraints to be considered in the
design of the interface card. It has to fit into the drawer, use
only 3.3 V and have a low cost.
Since the interface is mounted on top of a digitizer, there
is a height limitation. Adding to the limitation are the 6 PMT
connectors on the digitizer boards. To be able to mount the
interface card directly on top of the digitizer, granting the
interface more height, and still have easy access to the PMT
connectors, the interface has been given an L shape (Fig. 4).
The direct mounting of the card has the added advantage of
eliminating one flex foil connection.
Figure 4: L-shaped card
The disadvantage is that it creates a heat problem, since
both the interface card and the digitizer boards have
components radiating large amounts of heat, especially the
TTCrx and the G-link. To avoid a heat pocket between the
boards, the critical components on the interface card are placed
on the topside, where they can make better use of the cooling
system in the drawer.
A. The platform card
The L shape also creates a problem with the optical
transceivers. The shape is too narrow for standard commercial
components, and there are no cheap miniature transceivers for
3.3 V, and none at all for 1300 nm reception and 850 nm
transmission. To solve this, separate receivers and transmitters
have been specially built for the interface, with one end of the
card dedicated to the optical communication, with the diodes
mounted in ST houses, chosen for size, prize and availability.

Not using integrated components means that the
connection between diode/VCSEL and amplifier can be up to 1
cm in length. This is a critical point, for while the circuits on
the PCB are matched for impedance, the diode pins are not. To
bring the amplifiers closer to the headers, making the diode
pins as short as possible, a platform card (Fig. 5) containing
the amplifiers, is mounted on top of the interface card. Using a
platform card also makes it easier to surface mount the diode
pins, greatly improving the impedance match.
Figure 5: Platform card
B. The transmitter
The transmitter is a standard solution from MAXIM, using
the MAX3286 laser amplifier. The MAX 3286/96 series is
optimized to drive lasers packaged in standard TO-46 headers,
and consequently the VCSEL used, Zarlinks MF444, is
packaged in a TO-46 header. This solution is compact and
inexpensive.
The G-link output is designed to deliver PECL into 50
ohm. Since the differential MAX 3286 input accepts PECL
swings, the connection between these circuits is a straight
forward AC coupling with 100 ohm differential termination.
C. The receiver
The receiver is a PIN diode, Zarlink MF432, with a
transimpedance amplifier (TIA), Philips TZA3033. Since the
connection between the PIN diode and the TIA is critical to the
performance, the preferable solution would have been to use a
PIN-TIA combination, i.e. a PIN diode with a TIA mounted
inside the header. Since there are no PIN-TIAs for this
application, the PIN diode and TIA are separate. Since the
input current is about 7-8 mA, and obviously very sensitive to
noise, special attention has been paid to the layout around the
input pin of the TIA. The input capacitance is minimized by
surface mounting the diode pins and by removing the power
planes beneath the input pins of the TIA.
Also critical to capacitance is the reverse voltage across the
diode. Presently the diode uses a reference voltage from the
TZA 3033, which is only 2.25 V. Tests will be made with the
VCC pin directly connected to the power plane. This will
increase the reverse voltage but may introduce too much noise.
The TZA features an automatic gain control loop, AGC,
which maintains a stable output at 110 mV for a wide range of
input currents. This means that no extra amplification is
needed and that the output can be directly fed to the LVDS
repeater, using only biased termination for the DC level.
V. THE LINK DESTINATION CARD
The currently used link destination card (LDC) is a single
G-link simplex with an S-link output format [4]. This card is
only designed for 20.04 MHz operation and can only receive
one channel. For full speed testing, a double G-link simplex
with 40.08 MHz capacity is needed. Also, it must have a large
FPGA, since much of the link data processing has been moved
to the destination card. Since there are no commercially
available solutions for 40.08 MHz readout, a new destination
card would have to be developed if a full speed link is desired.
However, if readout speed remains 20.04MHz, the ODIN
double G-link destination card [5] could be used, provided that
it is fitted with a large enough FPGA.
VI. PROJECT STATUS.
The interface link is presently being used in the testing of
the digitizer boards. For these tests, there is no need for the
link destination card to have two channel capacity. The
operation has been reliable during these production runs, but
further tests will be made to determine the optimum
performance, including bit error tests and radiation tests.
As of September 2001, a Chicago built interface card is
baseline link for TileCal, making the Stockholm interface card
an alternative solution. However, a certain development of the
Stockholm interface will continue until the Chicago solution
is proven. This may include building a version using the
CERN developed Gigabit Optical Link (GOL). Such a design
would lead to further simplification (eliminating the input
multiplexers) better radiation tolerance (the GOL is made in
DMILL [6]) and 40 MHz operation.
VII. ACKNOWLEDGEMENTS
We would like to thank Stefan Rydström and Mark Pearce
at the Royal Institute of Technology, Section of Experimental
Particle Physics, for their help with the design of the
transmitter.
VIII. REFERENCES
1 The ATLAS Tile Calorimeter Digitizer, S. Berglund, C. Bohm,
M Engström, S-O. Holmgren, K. Jon-And, J. Klereborn, B.
Selldén, S. Silverstein,, K. Anderson, A. Hocker, J. Pilcher,
H. Sanders, F. Tang and H. Wu, Proceedings of the Fifth
Workshop on Electronics for LHC Experiments, Snowmass,
Colorado, 1999, p. 255.
2 http://www.cern.ch/TTC/intro.html
3 Front-end electronics for ATLAS Tile Calorimeter, K.
Andersson, J.Pilcher, H.Sanders, F.Tang, S.Berglund,
C.Bohm, S-O.Holmgren, K.Jon-And, G.Blanchot,
M.Cavalli-Sforza, Fourth Workshop on Electronics for LHC
Experiments, Rome 1998, p. 239.
4 http://hsi.web.cern.ch/HSI/s-link/products.html#S- LINK
5
http://hsi.web.cern.ch/HSI/s-link/devices/odin/
6 Final acceptance of the DMILL Technology Stabilized at
TEMIC/MHS, M. Dentan, et. al., Fourth Workshop on
Electronics for LHC Experiments, Rome 1998, p. 79.
7 Redundancy or GaAs? Two different approaches to solve the
problem of SEU(Single event upset ) in a Digital Optical
Link, B. Dinkespiler, R. Stroynowski, S. Xie, J. Ye, M-L.
Andrieux, L. Gallin-Martel, J. Lundquist, M. Pearce, S.
Rydstrom, and F. Rethore

Development and a SEU Test of a TDC LSI for the ATLAS Muon Detector
Yasuo Arai 1 , Yoshikazu Kurumisawa 2 and Tsuneo Emura 2
Abstract
A new TDC LSI (AMT-2) for the ATLAS Muon detector
has been developed. The AMT-2 chip is a successor of the
previous prototype chip (AMT-1). The design of the chip was
polished up for aiming mass production of 20,000 chips in
year 2002. Especially, power consumption of the chip was
reduced to less than half of the previous chip by introducing
newly developed LVDS receivers.
The AMT-2 was processed in a 0.3 µm CMOS Gate-Array
technology. It achieved 300 ps timing resolution and includes
several data buffers, trigger matching circuit, JTAG interface
and so on.
First SEU test by using a proton beam was recently
performed. Although the test results are very preliminary at
present stage, we get very low SEU rate safely used in
ATLAS environment.
I. INTRODUCTION
ATLAS precision muon tracker (MDT) requires highresolution,
low-power and radiation-tolerant TDC LSIs
(called AMT: ATLAS Muon TDC). Total number of TDC
channels required is about 370 kch.
The AMT chip is developed in a 0.3 µm CMOS Gate-
Array technology (TC220G, Toshiba Co.). Block diagram of
the chip is shown in Fig. 1. It contains 24 input channels, 256
words level 1 buffer, 8 words trigger FIFO and 64 words
readout FIFO. Both leading and trailing edge timings can be
recorded. The recorded data are matched to trigger signal
timing, and the matched data are transferred through 40 Mbps
serial line. By using an asymmetric ring oscillator [1] and a
Phase Locked Loop (PLL) circuit, it achieved 300 ps RMS
timing resolution.
A prototype chip, AMT-1, was successfully tested and
reported in the last LEB workshop [1]. Already 500 AMT-1
chips were produced and mounted in front-end PC boards
with ASD (Amp/Shaper/Discri) chips [2]. These boards are
being tested with MDT chambers in several laboratories.
AMT-2 chip is a successor of the AMT-1 chip and
regarded as a prototype for mass production. Major
improvement of the AMT-2 is reduced power consumption.
The AMT-1 consumes about 800 mW of which 470 mW is
consumed in LVDS receivers. We have developed a new lowpower
LVDS receiver and proceeded to low power design of
logics. Thus the power consumption of the AMT-2 is reduced
to 360 mW.
1 KEK, National High Energy Accelerator Research Organization,
Institute of Particle and Nuclear Studies, (yasuo.arai@kek.jp)
2 Tokyo University of Agriculture and Technology
In addition, the chip testability was enhanced. This is very
important for mass production. Mass production chips will be
mainly tested at LSI testes of the manufacturer. Only very
small fraction of the chip will be tested in our laboratory.
Since the LSI testers runs only at 10 MHz, special care must
be taken to verify 40 MHz operation. We think reduced
voltage test will certify the operation. To verify the stability of
the PLL, internal counter is prepared to count 80 MHz PLL
clock. After a fixed time, the counted value will be checked.
Photograph of the AMT-2 chip is shown in Fig. 2. The
chip is packaged in a 144 pins plastic (ceramic) QFP with 0.5
mm pin pitch. About 110k gates are used in a 6 mm by 6 mm
die.
The chip must be qualified to have adequate radiation
tolerance in ATLAS environment. Gamma-ray irradiation to
measure Total Ionization Damage (TID) was already done to
the same process [3]. Recently we executed a first experiment
of the Single Event Upset (SEU) test by using a proton beam.
Preliminary results are described in section IV.
Fig. 1 Block diagram of the AMT-2 chip.

Fig. 2 Open view of the AMT-2chip. The die size is about 6 mm by 6
mm. The photograph is ceramic packaged chip. Plastic packaged
ones are used in circuit tests and beam tests.
II. AMT-2 CIRCUIT DESCRIPTION
Main specification of the AMT-2 chip is summarized in
Table. 1. Since the detailed description of the AMT chip is
available in other documents [4, 5], only new features are
presented here after brief explanation of the chip operation.
Table. 1 AMT-2 Specification (@40MHz System Clock)
Least Time Count 0.78125 ns/bit
Time Resolution 300 ps RMS
Dynamic range 13 (coarse) + 4 (fine) = 17 bit
Max. Trigger Latency 16 bit (51 µsec)
Int./Diff. Non Linearity < 80 ps RMS
No. of Channels 24 Channels
Level 1Buffer 256 words
Read-out FIFO 64 words
Trigger FIFO 8 words
Double Hit Resolution 99.8%@400kHz(two edge)
Hit Input Level LVDS
Data output LVDS Serial (10 - 80 Mbps)
or 32 bit parallel.
CSR access JTAG or 12 bit control bus.
General I/O ASD control l (5 pins) and general out
(12 pin) and in (3 pin).
Power 3.3+-0.3V, ~360 mW
Process 0.3 µm CMOS Sea-of-Gate
Package 144 pin plastic QFP
A. AMT-2 Operation
The asymmetric ring oscillator produces a double
frequency clock (80 MHz) from a LHC beam clock (40MHz).
By dividing the 12.5 ns clock period into 16 intervals in the
oscillator, a time bin size of 0.78 ns is obtained.
A hit signal is used to store fine time and coarse time
measurement in individual channel buffers. The time of both
leading and trailing edge of the hit signal (or leading edge
time and pulse width) can be stored. Each channel has a 4word
buffer where measurements are stored until they can be
written into the common level 1 (L1) buffer.
The L1 buffer is 256 hits deep and is written into like a
circular buffer. Reading from the buffer is random access
such that the trigger matching can search for data belonging to
the received triggers.
Trigger matching is performed as a time match between a
trigger time tag and the time measurements them selves. The
trigger time tag is taken from the trigger FIFO and the time
measurements are taken from the L1 buffer. Hits matching the
trigger are passed to the read-out FIFO.
The data are transferred to a Chamber Service Module
(CSM) [6] through a serial data interface. The serial interface
supports both DS-protocol and simple data-clock output. The
data transfer speed is selectable between 10 MHz to 80 MHz
(40 MHz will be used in the MDT).
There are 15 control registers and 6 status registers. These
registers are accessible from JTAG interface. A total parity of
the control registers is stored in the status register. If a SEU
occurs in the control register, a parity error is caused and
notified through an Error signal or an Error packet.
The chip has JTAG boundary scan circuit, which is used
to scan I/O pins, the control and status registers, internal
circuit registers for debugging purpose, and BIST (Built-In
Self-Test) for the level 1 buffer and FIFOs. The channel
buffer and the level 1 buffer have a parity bit for each word to
detect SEU. In the AMT-2, ASD control function through the
JTAG is also added (see section II-C).
B. New LVDS Receiver
We used existing Toshiba design of the LVDS receiver in
the AMT-1. The power consumption of the LVDS receiver
(15.5 mW) does not cause much problem if the number of the
receiver is small. However we need 26 (30 in AMT-1)
receives, and the total power consumption becomes large
(470mW). Thus a new low-power LVDS receiver was
required.
Although the available transistor size is very limited in I/O
pad area in a Gate-Array, a low-power LVDS receiver was
successfully developed while keeping adequate performance.
Fig. 3 shows performance of the previous and new LVDS
receivers. The propagation time is even improved while
reducing the constant current. This was mainly achieved by
reducing the size of input transistors.

Idd[mA]
Tpd[ns]
7
6
5
4
3
2
1
0
0.0
6
5
4
3
2
1
0
0.0
(a)
(b)
0.5
0.5
Old
New
Old
New
1.0 1.5
Vicm[V]
1.0 1.5
Vicm[V]
∆Vin=100mV
2.0
Tpd(LH)
Tpd(HL)
2.0
2.5
2.5
Fig. 3 Comparison of previous and new LVDS receiver
characteristics (simulation). (a) Constant current (Idd) vs. input
common mode voltage (Vicm), (b) propagation delay (Tpd) vs. Vicm.
LH and HL denotes Low to High and High to Low transition of the
output.
C. ASD Control
The ASD chip has many registers to keep shaping time,
threshold DAC value etc. A Xilinx chip is used to control
these ASD registers from JTAG signal in the present frontend
board.
This Xilinx chip consumes additional power and area, and
it also must be qualified for radiation. Since the power and the
area are very tight, it was decided to move the ASD control
function into the AMT-2. Fig. 4 shows the principle
connection between the AMT and the ASD. Five signal lines
are used between the ASD and the AMT-2.
Main protocol is almost same as JTAG boundary scan cell.
Data are shifted from ASDOUT to ASDIN through 3 ASD
chip. The shifted data are stored in shift cells and copied to
shadow cells when ASDLOAD signal is asserted.
In addition to the ASD control, 12 output and 3 input pins
are prepared as a general purpose I/O pins. These pins can be
used when additional control lines are needed in the front-end
board.
Fig. 4 ASD internal circuit and control signals from the AMT-2.
A. PLL
III. MEASUREMENT RESULTS
Jitter of the ring oscillator was measured by time
distribution between input clock edge and PLL clock edge
(Fig. 5). The jitter at operating point (3.3V, 80MHz) is 150 ps
RMS. This value is sufficiently low compared with
digitization error of 225 ps. Total timing resolution for a
single edge measurement will be about 300 ps. This satisfies
the required resolution of 0.5 ns in the MDT.
Fig. 6 shows the jitter variation to the oscillating
frequency (Fosc) and the power supply voltage (Vdd). This
indicates enough margins around the operating point.
Fig. 5 PLL output clock (upper curve, 80MHz) and timing
distribution (histogram) triggered with external clock (lower curve,
40MHz).

Jitter[ps]
2.5
300
250
200
150
100
50
0
0
2.7
20
2.9
40
Vdd[V]
3.1 3.3
60 80
Fosc[MHz]
3.5
Operating Point
100
3.7
vs Fosc
vs Vdd
Fig. 6 PLL jitter variation for oscillating frequency (@Vdd=3.3V)
and supply voltage (@Fosc = 80 MHz).
B. Power Consumption
Total power consumption of the chip is measured at
several operating conditions and shown in Fig. 7. In a very
severe condition (100kHz hit rate and 100 kHz Trigger rate)
power consumption is about 15 mW/ch. Compared with
previous chip (AMT-1) we could reduce 18 mW/ch. This is
achieved mainly by using the new LVDS receiver and
reducing the number of LVDS receiver from 30 to 26.
Power(mW/ch)
40
30
20
10
0
LVDS Only
100 Ohm T
10MHz Clk
AMT-1
AMT-2
20MHz Clk
30MHz Clk
40MHz Clk
Start
-18mW
Fig. 7 Power consumption of the AMT-1 and the AMT-2 chips for
different operating conditions. Conditions are changed from left to
right; powered to LVDS circuit only, 100 ohm termination resistors
were connected to LVDS drivers, external clock (10-40 MHz) is
applied, measurement started, 100 kHz hit signals are applied, then
finally a 100kHz trigger signal is applied.
IV. SEU TEST
Radiation tolerance of the present process for Total
Ionization Damage (TID) was already measured and shows
adequate tolerance to gamma ray [3]. Furthermore CMOS
process is not sensitive to neutrons in estimated level of the
MDT environment.
100kHz Hit
120
100kHz Trig
3.9
140
Remaining issue is Single Event Effects (SEE) caused by
energetic hadrons (> 20 MeV) [7]. To measure the SEE, we
need to perform beam test to the chip.
There are several single event effects in which Single
Event Latch up (SEL) and Single Event Upset (SEU) are
important for CMOS process. We have done first test of SEU
by using a proton beam.
We used an AVF cyclotron at the Cyclotron and
Radioisotope Center (CYRIC) of the Tohoku University,
Japan. The Cyclotron was recently upgraded and has
maximum proton energy of 90 MeV.
We have done a first beam test by using a 50 MeV proton
beam, and irradiated 2 AMT-2 chips. Beam intensity was
around 1 nA and the beam size was monitored visually to
have 2 cmφ. During the irradiation, beam intensity was
monitored with two plastic scintillators, but no special device
was used to measure its distribution.
AMT-2 has 180 bits in the CSR registers, and a total of
11,360 bits in the L1, the trigger and the readout buffers. The
CSR register was composed of Flip-Flops, and the buffer
memories are composed of 6 transistors static memory cell.
Both circuits has almost complimentary circuit for positive
and negative logic signals, so we assume the SEU rate may be
same regardless of the contents of memory.
Unfortunately we cannot directly read and write the
contents of the buffers. Instead we used Built-in Self-Test
(BIST) circuit to detect the SEU. The BIST circuit performs
two kinds of 13N marching pattern test. The results are
compressed in a 36-bit Linear Feedback Shift Register. If one
or more error occurs in this test sequence, final result has
different value.
We step forward the BIST sequence until writing all '1's
(or '0's) to all memory location. Then irradiate the chip to the
beam. After the irradiation, we continue the BIST sequence
and read out the final value. These measurements were
repeated several times. Since the SEU rate is very low, it is
very rare to occur more than 2 SEU during one measurement.
We have observed 3 SEU in 18 measurements.
As for the CSR, the contents are directly written and read
through JTAG lines. Before the irradiation '0's and '1's were
written to the CSRs, then after the irradiation the contents
were checked for SEU. We have not observed any bit flip in
the CSR test.
Fig. 8 shows leakage currents of the chip for gamma ray
and proton. Horizontal scale is adjusted to fit both curves.
Since the proton irradiation was paused during the
measurement, annealing was occurred during the each
measurement. Therefore the proton data are discontinuous at
the boundary of measurement. Assuming the leakage current
depend only on energy deposit in Si, proton flux is estimated
to be about 2x10 9 protons/sec/cm 2 . This is consistent with the
value estimated from the beam intensity and its size.
The SEU test results are summarized in Table. 2.
Assuming a Poisson distribution of the SEU event, we get
upper limits of the cross section in 90% confidence level.

σ SEU (CSR) < 5.6x10 -15 cm 2 /bit
σ SEU (buffer) < 2.7x10 -16 cm 2 /bit
Calculated fluence of hadrons with an energy >20MeV is
~10 10 1/cm 2 /10year in MDT location [7]. Applying number of
bit in total MDT system, SEU rates (R SEU) will be,
R SEU (CSR) < 0.1 upset/day
RSEU (buffer) < 0.3 upset/day.
Thus less than 1 upset in the CSR for 10 days of operation
in MDT system. Furthermore there was no latch up during the
experiments for both chips.
Although these results are very preliminary, we feel
relieved in very low SEU rate in both control registers and
data buffers. This is mainly because the transistor size is
relatively large in Gate-Array, so large charge is required to
upset the memory.
Although the leakage current was useful to estimate the
proton flux, but the large leakage current might cause damage
to the chip. Therefore it is better to irradiate less fluence to a
chip, and accumulate more statistics by irradiating many chips.
Further experiment are being planed.
Idd[mA]
0
300
250
200
150
100
50
0
0
100
Gamma Irrad.
(Upper Axis)
200
Gamma Dose[krad]
200
Proton Irrad.
(Lower Axis)
400
600
800
Proton Irradiation time[sec]
300
Annealing
1.4x10 12
protons/cm 2
1000
1200
Fig. 8 Leakage current of the AMT-2 chip for gamma ray and proton
irradiation. Data for proton is not continuous since the irradiation
was stopped in each measurements and annealing was occur in each
measurement.
Table. 2 Number of observed SEU in the proton irradiation
experiment.
Proton
Fluence
Chip 1 1.4x10 12
Chip 2 1.0x10 12
Chip 1+2 2.4x10 12
No. of
meas.
SEU
in CSR
SEU in
buffers
σ SEU
buffers
8 0 1 6.3x10 -17
10 0 2 1.8x10 -16
18 0 3 1.1x10 -16
V. SUMMARY
A production prototype chip (AMT-2) was successfully
developed for ATLAS MDT detector. The chip fulfils
required performance and being tested with MDT chambers.
A new LVDS receiver is developed and the power
consumption of the AMT-2 chip is reduced to 45% of the
previous chip.
Preliminary test of SEU rate by using a proton beam was
performed and shows low enough rate to be safely used in the
MDT. Latch up was not observed in this test.
VI. ACKNOWLEDGEMENTS
I would like to thank to O. Umeda, I. Sakai, M. Takamoto,
K. Tsukamoto and T. Takada (Toshiba Co.) for their technical
support. I also thank to T. Shinozuka (CYRIC) who managed
to prepare beam time for us and M. Fujita (CYRIC) who gave
us many technical support for the beam test.
VII. REFERENCES
[1] Y. Arai and T. Emura, " Development of a 24 ch TDC LSI
for the ATLAS Muon Detector", Proceedings of the 6th
Workshop on Electronics for LHC Experiments,
CERN/LHC/2000-041, pp. 471-475.
[2] C. Posch, E. Hazen, and J. Oliver, "MDT-ASD, CMOS
front-end for ATLAS MDT", ATLAS Note, ATL-COM-
MUON-2001-019.
[3] Y. Arai, "Performance and Irradiation Tests of the 0.3 µm
CMOS TDC for the ATLAS MDT", Proceedings of the
Fifth Workshop on Electronics for LHC Experiments,
Snowmass, 1999. CERN/LHCC/99-33, pp 462-466.
[4] Y. Arai, "Development of Frontend Electronics and TDC
LSI for the ATLAS MDT", Nucl. Instr. Meth. A. Vol. 453,
pp. 365-371 (2000).
[5] ATLAS-Japan TDC group web page.
http://www-atlas.kek.jp/tdc/.
[6] CSM Design & User Manual,
http://atlas.physics.lsa.umich.edu/docushare/
[7] Atlas policy on radiation tolerant electronics.
http://www.cern.ch/Atlas/GROUPS/FRONTEND/radhard.
htm

Anode Front-End Electronics for the Cathode Strip Chambers of the CMS Endcap Muon
Detector
N. Bondar* a), T. Ferguson**, A. Golyash*, V. Sedov*, N. Terentiev**.
*) Petersburg Nuclear Physics Institute, Gatchina, 188350, Russia
**) Carnegie Mellon University , Pittsburgh, PA, 15213, USA
a) bondar@fnal.gov
Abstract
The front-end electronics system for the anode signals of
the CMS Endcap Muon Cathode Strip Chambers has been
designed. Each electronics channel consists of an input
protection network, amplifier, shaper, constant-fraction
discriminator, and a programmable delay with an output
pulse width shaper. The essential part of the electronics is an
ASIC consisting of a 16-channel amplifier-shaperdiscriminator
(CMP16). The ASIC was optimized for the
large cathode chamber size of up to 3.4 x 1.5 m 2 and for the
large input capacitance (up to 200 pF). The ASIC combines
low power consumption (30 mW/channel) with excellent
time resolution (~2 ns). The second ASIC provides a
programmable time delay which allows the alignment of
signals with an accuracy of 2.5 ns. The pre-production
samples of the anode front–end boards with CMP16 chips
have been successfully tested and the mass production has
begun.
I. INTRODUCTION
The purpose of the anode front-end electronics described
in this paper is to receive and prepare the anode wire signals
of the Cathode Strip Chamber (CSC) of the CMS Endcap
Muon (EMU) system for further logical processing in order
to find the location of charged particle with a time accuracy
of one bunch crossing (25 ns) [1].
Special features of the CSC are a six-plane twocoordinate
measuring proportional chamber, a large chamber
size (the largest one is 3.4 x 1.5 m 2 ) and a large detector
capacitance (up to 200pF), created by joined together anode
wires. Expected anode signal rate is about 20 kHz/channel.
Total number of anode channels is more than 150000. The
electronics is spread over the EMU detector with limited
maintenance access. Estimated radiation dosage integrated
over 10 LHC years is about 1.8 kRad for ionizing particles
and about 10 12 neutrons per cm 2 [1].
The electronics must satisfy the following requirements:
-Able to determine the timing of the track hit with an
accuracy of one bunch crossing with a high efficiency;
-Match the chamber features to achieve optimal detector
performance.
-Be reliable during for 10 LHC years
-Have sufficient radiation hardness
-Have low power consumption [1].
II. ANODE ELECTRONICS STRUCTURE
A. Anode electronics specification
To achieve accordance between a large detector size and a
large detector capacitance on one hand and high sensitivity
and time accuracy on the other hand, a relatively large
shaping time of 30 ns for the anode signals, together with
two-threshold constant-fraction discriminator, were proposed.
This shaping time allows us to collect about 12% of the initial
charge. Together with the discriminator threshold as low as
20 fC, the efficiency plateau starts at 3.4kV [2]. The nominal
operating point of the chamber is set at 3.6 kV and the
average collected anode charge is about 140 fC.
To achieve a minimum stable threshold level of anode
electronics as low as 20 fC with the minimum possible crosstalk,
a standard structure of the anode electronics channel was
split into three parts located on three different boards. See
Figure 1 for reference. Also, the amplifier-chamber signal
connection and the chamber grounding and shielding were
carefully planned and executed.
Figure 1: Anode electronics structure. Protection board (Prot.) is a
part of the chamber assembly, AFEB - Anode Front-End Board is a
16-channel board, ALCT –Anode Local Charge Track finder logic
board.
Two 16-channel ASICs were designed to produce the
anode structure. The first one is a 16-channel amplifiershaper-
discriminator with an LVDS driver for output signals,
named CMP16, and the second one is an LVDS-receiver -
control-delay - pulse-width-shaper, named DEL16. This
solution allows us to simplify the electronics board and
increase the electronics reliability and maintainability, as well

as minimise power consumption. Standard BiCMOS and
CMOS technologies were used for designing the ASICs,
giving us a relatively low price and sufficient radiation
hardness.
B. Chamber ground and shielding. Protection
Board.
The chamber anode wires, cathode planes, protection
boards and even the cathode amplifier input connections are
all parts of the anode amplifier input circuit. To obtain
optimal performance of the chamber, we have to observe the
following rules: The anode amplifier input impedance must
be close to the anode wire structure characteristic impedance
(~50 Ohm). The cathode input impedance must be close to
the characteristic impedance of the cathode strip structure.
The detector-amplifier ground connection should be as short
as possible and as wide as possible in order to have the
minimum possible inductance for the connection [3].
Each chamber plane has a solid metal cathode plate. This
plate is a natural chamber signal ground for the plane. Both
anode and cathode amplifiers input ground terminals are
connected to this plane. The chamber’s outer copper foil
along with the chamber metal frame and side covers create
the detector RF case. The RF case and the signal ground are
connected together at the amplifier side of the chamber to
avoid a ground loop through the signal ground plate and
along the amplifier input ground circuit.
The protection board (PB) has two functions. The first
one is to fan-in the chamber anode signals and adapt them to
a standard 34-pin connector. The protection board collects
signals from two chamber planes (8+8) and provides a proper
ground connection between the chamber signal ground and
the amplifier input ground The second function of the PB is
to protect the inputs of the amplifier against accidental sparks
in the chamber. The full protection network consists of two
resistor-diode stages. The first protection stage is placed on
the protection board in order to minimize the emergency
current loop for better protection, and the second stage is on
the input of the anode front-end board.
C. Anode Front-End Board (AFEB)
On the basis of the CMP16 chip, the 16-channel Anode
Front-End Board (AFEB) AD16 is designed. This board
receives the anode signals from the chamber wire groups,
amplifies the signals, selects the signals over the preset
threshold with precise time accuracy and transmits the logic
level signals to the further stage with the LVDS levels
standard. Since the EMU system contains almost 10,000
AD16 boards, we have designed the AFEB in the simplest
and cheapest way. There is only one CMP16 chip with the
necessary minimum service components on it as well as a
small voltage regulator to keep the “on-board voltage” stable,
well filtered and independent of the power supply voltage.
The board has a 34-pin input connector and a 40-pin output
connector. Normally, this board is connected to the
chamber’s protection board and fixed on the chamber side
cover with a special bracket, providing a reliable and proper
junction. A 20-pair twisted-pair cable connects the AFEB
with the ALCT board. Since the functions to serve the AFEB
are delegated to the ALCT board, this cable is used both to
transmit output signals to the ALCT and to supply the board
with power voltage, threshold voltage and test pulses. The
DEL16 ASIC is a signal receiver at the very input of the
ALCT .The ALCT provides the following AFEB services: a
power supply voltage distribution circuit, a “power-ON/OFF”
command driver for each AFEB, a threshold voltage source
for each AFEB and a few test pulse generators to test the
AFEB through its internal capacitance or through a special
test strip on the cathode plane to inject input charge directly
onto the anode wires [4].
III. AMPLIFIER ASIC CMP16
he main component of the AFEB is an amplifierdiscriminator
ASIC. The chip parameters are specially
optimized for the Endcap EMU CSC to obtain optimal
performance from the chamber. The ASIC has the following
electrical characteristics:
Input impedance 40 Ohm
Transfer function 7 mV/fC
Shaper peaking time 30 ns
Shaped waveform Semi-gaussian with
Two-exponent tail cancellation
Amplifier input noise 0.5 fC @Cin=0
1.7 fC @Cin=200 pF
Non-linearity

Input
Figure 2: Schematic diagram of an anode amplifier-discriminator channel.
IV. DELAY ASIC DEL16
The anode pulses to the ALCT have a big variation of
phase for various reasons, including different length of cables
to the input of ALCT. The total time variation may be up to
20 ns. To align the input pulse phases, a special 16-channel
control delay chip was designed. The structure of one channel
of this chip is presented in Figure 3. Each channel consists of
an input LVDS-to-CMOS level converter; four stages of
delay with 1, 2, 4, and 8 steps; an output width pulse shaper.
Also, the chip has the possibility to generate a test level at
each output. This option is used for testing chip-to-chip
connections. The chip has a serial interface to control the
delay and set the output test level.
Id
LVDS/TTL
Pinp
Out
Ninp
CLRB
CLK
DIN
CHSB
SHIFT_REG
T1
T2
T3
T4
DOUT
DOUT
Vg - Artificial Ground
Ofst - voltage reference
Treshold - relative threshold voltage
+
A1
I_discr - initial discriminator current
+
-
3.4pF
10K
-
2.185pF
-
+
Preamplifier Detector tail
+
120K
1.46pF
-
+
-
+
6K
-
A1
+
Cancellation
Delay channel parameters:
Input signal level LVDS standard
Output signal 3.3 V CMOS
Minimum delay 20 ns
Delay step 2 ns (adjustable with an external
current)
Delay steps 15 maximum
Delay nonlinearity +/- 1 ns
Output pulse width 40 ns (adjustable with an external
current)
Power supply voltage 3.3 V
Power consumption 0.2 W
Diff_d
d26
Id
Inp Out d28
Id
Inp Out d30
Id
Inp Out d32
Id
Inp Out d34 Diff_W d36
Id
T_out
In Out
T1
T-del
Cnt C_t
d27 T2
T-del
Cnt C_t
d29 T3
T-del
Cnt C_t
d31 T4
T-del
Cnt C_t
d33
C_t
0.03pF
75K
+
-
-
+
14K
-
+
1.0pF
7K
-
+
-
+
-
30K
"Two Pole" shaper
0.1pF
0.5pF
-
+
Vg
+
-
A1
+
30K
-
1.0pF
"Bipolar signal"
shaper
Amplifier x 6 High level discriminator
With base line
restorer (A_p)
"Enable" pulse
0.232pF
0.506pF
Figure 3: Schematic diagram of one delay channel
12K
+
+
-
+
-
-
+
0.5pF
30K
30K
A1
+
-
-
+
75K
-
10K
A_p
+
-
-
+
Vg
+
A1
Ofst
30K
-
x6
Threshold
10pF
-
+
A2
"Zero threshold"
discriminator
With zero threshold
restorer (A_p)
+
-
A2
A_p
I_discr
AD
Id
AD
Id
Iw
Enable
Output buffer
LVDS levels
In_p
Out_buff_d
0.5pF
OutN
OutP
D
Out
d37
+
-
OutN
OutP
Out

The chip was designed using the AMI CMOS 0.5-micron
technology. The chip was made in the AMI foundry via the
MOSIS Service. The chip is packaged in a plastic 64-pin
Quad Flat Pack with a pin pitch of 0.5 mm. The chip size is
10 x 10 mm 2 .
V. ANODE ELECTRONICS TEST
A. Chamber performance
The CSC with the anode electronics has been tested on
the Cosmic Muon Stand at FNAL. We have reached a
minimum discriminator threshold for the anode electronics
installed on the chamber as low as 10 fC. We assume that 20
fC threshold is a normal operational value. A standard CSC
in that case has an efficiency plateau with a gas mixture of
Ar+CO 2 +CF 4 =40+50+10, starting at 3.4 kV.
A full-scale prototype CSC, completely equipped with
electronics, was tested in a beam at CERN at the Gamma
Irradiation Facility. The CSC performance was within the
baseline requirements. In Figure 4, the final result of the
bunch tagging efficiency is shown [2].
Figure 4: Bunch crossing tagging efficiency (in 25 ns gate) vs GIF
rate.
B. Reliability test
To measure the reliability of the AFEB AD16, we put 100
AD16 boards (1,600 amplifier-discriminator channels) into
an oven at a temperature of 110 O C. We assume that for each
20 degrees the failure rate increases about two. The boards
were supplied with power and the thresholds on the boards
were set to minimum to start self-oscillation. Total test time
in the oven was 4000 hours. This time corresponds to about 7
years of real operation at 30 O C. Every two weeks we
measured the board parameters. During the test, we have no
failures and there were no visible changes in the electrical
characteristics.
C. Radiation test
Since the AFEB contains both BiCMOS and bipolar
components we had to test the Total Ionizing Dose (TID),
Displacement and Single Effect Event (SEE) damages. [3] A
few samples of the AFEB were irradiated with a 63 MeV
proton beam at the University of California, Davis to test the
electronics for TID and SEE damages. No latch-up or spikes
or any changes in the static parameters were observed. At the
required TID level of 5-6 kRad all changes of gain and
slewing time were practically negligible [5].
To test the electronics for possible Displacement damages
the same boards were irradiated with 1 MeV neutrons from a
reactor at Ohio State University. Total neutron fluence up to
2x10 12 n/cm 2 was accompanied with a significant flux. The
boards also received a TID of 50-60 kRad. Two boards were
found working 40 days after the irradiation and others after
one week of heating in an oven at 100 O C [5].
D. AFEB mass production test
A special automated test setup and test methods has been
developed to measure the CMP16 chip and the AD16 board
parameters, as well as delay chip DEL16 parameters. The test
stand schematic structure is illustrated in Figure 5.
Figure 5: Test stand block structure.
There is a specially designed pulse generator for
producing test pulses with the necessary accuracy and shape.
The second main unit is a LeCroy 3377 TDC. We have
designed three special adapters to match the different devices
to be tested with the test setup.
We use the following procedure for testing the parameters of
the AFEB: Discriminator threshold is set at one of two
standard levels, about 20 or 40 fC. The input pulse amplitude
is increased in steps to supply the amplifiers with an input
charge from 0 fC to 100 fC for threshold testing and from 0
fC to 500 fC for time slewing testing. The generator sends
400 pulses at each step. The TDC measures the number of
AFEB’s output pulses and propagation time of the CMP16
versus the amplitude of the input signal. The resulting curves
of “output pulse count versus input amplitude” for two
different thresholds (threshold test) are used to derive the
required CMP16 parameters. Amplifier noise is calculated
from the curve slope. For the amplifier gain calculation and
getting threshold calibration, we use two curves, one at 150
mV threshold voltage, and the second at 400 mV. The

esulting curve of “propagation time versus input amplitude”
(timing test) is used to estimate the CMP16 slewing time.
We use a multi-step test procedure for AFEB verification.
The first step is a selection of good chips for assembly on the
board. A special clamp-shell adapter for two chips is used.
The chip under test has normal power voltage of 5V,
threshold voltage of 150 mV (about 20 fC of input charge);
the amplifier input capacitor of 0 pF. The test pulse amplitude
is ramped up to provide an input charge through the chip’s
internal capacitance from 0 fC to 200 fC. A good chip must
satisfy the following requirements: a noise level less than 0.8
fC @ Cin=0 pF; a threshold uniformity better than +/-10%; a
deviation of propagation time should be within 4ns for all
channels of the chip for input signals from 50 fC to 200 fC.
The assembly company performs a test on the assembled
board according to our test procedure and using our
equipment.
All assembled boards are put through a burn-in procedure.
We keep the boards for 75 hours in an oven at 100 C with the
power on and with an input test pulse. After the burn-in
procedure, all boards are given a final test, calibration and
certification.
A special adapter for testing and calibrating boards was
designed. The adapter has a special injection circuit and 200
pF input capacitance for each amplifier’s input. Injection
circuit accuracy is better than 2% after calibration. The final
test and calibration procedure has four test runs with the
following conditions:
1 -low threshold, external injection circuit,
2 -high threshold, external injection circuit,
3 -low threshold, the chip internal capacitance as an injection
circuit,
4 -low threshold, time measurement.
The following parameters are collected from the data:
- Threshold level as a function of threshold voltage,
- Threshold uniformity for each chip,
- Noise level at Cin=200 pF,
- Propagation time as a function of the input signal
amplitude,
- Propagation time uniformity,
- Chip time resolution,
- Chip’s internal test injection capacitance.
The raw test data and the final results are stored in a
database. We intend to keep the board calibration and
certification results in a database for further experimental
needs
E. Delay chip mass production test
A special clamp-shell adapter for two chips was designed
in order to use the existing test setup for delay chip testing.
The following test procedure is used: The test program scans
the delay code in the DEL16 chip in steps of “one” from
delay code “0” to the maximum delay code “15”. The test
generator sends 100 input pulses for each delay step, and the
propagation time for each step is measured by the TDC. The
output test level generating option is measure by switchingon
this option for each channel and measuring the chip output
voltage for that channel.
A good chip must satisfy the following conditions: the
control interface can switch on a test level at the chip outputs,
the maximum delay and output pulse width should meet the
specifications, and the delay step variation between channels
must be less than half of the delay step.
VI. CONCLUSION
The anode front-end electronics for the Endcap Muon
CSC and the electronics layout on the chamber were carefully
designed and arranged to obtain the best chamber
performance. The CSC test results show us that the chamber
equipped with the electronics meets the baseline
requirements.
Special equipment and necessary procedures were
designed for testing and calibrating the electronics at every
stage of the mass production and the CSC final assembly.
The electronics calibration and test results will be available
for the duration of the experiment.
The electronics mass production has started.
VII. REFERENCES
1. CMS The Muon Project Technical Design Report
CERN/LHCC 97-32 CMS TDR 3 1997.
2. D. Acosta et al, “Large CMS Cathode Strip Chambers:
design and performance.” Nucl. Instrum. Meth. A453:182-
187, 2000.
3. N. Bondar, “Design of the Analog Electronics for the
Anodes of the Proportional Chambers for the Muon Detector
of the GEM Unit” Preprint EP-3-1994-1945, PNPI, 1994.
4. J. Hauser et al, “Wire LCT Card” at http://wwwcollider.physics.ucla.edu/cms/trigger/wirelct.html.
5. T. Ferguson, N. Terentiev, N. Bondar, A. Golyash, V.
Sedov “Results of Radiation Tests of the Anode Front-End
Boards for the CMS End-Cap Muon Cathode Strip
Chambers”, in these proceedings.

Results of Radiation Tests of the Anode Front-End
Boards for the CMS Endcap Muon Cathode Strip Chambers
Abstract
We report the results of several radiation tests on preproduction
samples of the anode front-end boards for the CMS
endcap muon system. The crucial components tested were the
16-channel amplifier-shaper-discriminator ASIC (CMP16) and
the voltage regulator TK112B. The boards were exposed to
doses up to 80 kRad in a 63 MeV proton beam, and to a neutron
fluence up to 2x10 12 n/cm 2 from a nuclear reactor. The static
and dynamic characteristics were measured versus the radiation
dose. The boards were found operational up to a total ionizing
dose (TID) of 60 kRad.
I. INTRODUCTION
The Anode Front-End Boards (AFEB) [1] are designed for
the Cathode Strip Chambers (CSC) [2] of the CMS Endcap
Muon System [3]. The AFEB amplifies and discriminates
signals from the CSC anode wires which are grouped in bunches
from 5 to 16. Their main purposes are to acquire precise muon
timing information for bunch crossing number identification at
the Level-1 trigger and to provide a coarse radial position of the
muon track for the offline analysis. Radiation tolerance and
reliability are important issues for the CMS electronics,
including the endcap muon CSC anode front-end electronics.
The peak luminosity of LHC, 10 34 cm -2 s -1 , combined with the 7
TeV beam energy, will create a very hostile radiation
environment in the detector experimental hall. The most severe
conditions in the CMS muon endcap region are in the vicinity of
the ME1/1 CSC chambers. Here, the neutron fluence and the
total ionizing dose (TID) accumulated during 10 years of LHC
operation (5x10 7 s) are expected to be about 6-7x10 11 n/cm 2 (at
En>100 keV) and 1.8-2 kRad, respectively [4-5]. For locations
other than the ME1/1 chambers the doses are at least 10 times
lower.
As BiCMOS devices, the AFEB’s ASIC chip and voltage
regulator TK112B are affected by exposure to both ionizing
radiation (TID) and to neutrons (Displacement damage),
yielding degraded performance and even failure if the doses are
T. Ferguson, N. Terentiev a)
Carnegie Mellon University, Pittsburgh, PA, 15213, USA
N. Bondar, A. Golyash, V. Sedov
Petersburg Nuclear Physics Institute, Gatchina, 188350, Russia
a) teren@fnal.gov
sufficiently high. The corresponding effects are cumulative. The
other major category is the Single Event Effects (SEE) which
are caused by the nuclear reactions of charged hadrons and
neutrons. From these, the relevant effect is Single Event Latchup
(SEL) which results in a destructively large current draw.
The plan of our measurements [6-7] was to test the
performance of the anode front-end boards, with pre-production
chips, CMP16F (1.5 micron BiCMOS AMI technology), on
them, up to a level of 3 times the doses mentioned above, and to
observe the presence of single-event effects such as latch-up, at
higher doses. The boards were irradiated with a 63 MeV proton
beam at the University of California, Davis in June, 2000 to test
them for TID and SEL effects. The results are presented in
Section II. The purpose of the test with 1 MeV neutrons from a
reactor at the Ohio State University was to expose the boards to
possible displacement damage (Section III). The radiation test
results are summarized in Section IV.
II. TESTS WITH 63 MEV PROTONS
The description of the 63 MeV proton beam test facility can
be found in [8]. The beam current can be regulated from 2 pA
up to 100 nA, with a profile almost flat over a radius of 35 mm.
Four powered anode front-end 16-channel boards with CMP16F
chips on them were tested at an incident beam angle of 0
degrees with respect to the normal to the board. The beam
covered all elements of the board including the ASIC chip
itself, the input protection diodes, the voltage regulator and
passive elements. Boards #8 and #9 received 7 successive
exposures for approximately 1 min each, for a total TID of
14 kRad. Two other boards (#5 and #7) received
correspondingly 7 (10) successive exposures for a total TID of
80 kRad (74 kRad) for approximately 1-2 minutes per
exposure. One more board was placed out of the beam and
tested in parallel with the irradiated boards to provide
monitoring of the test conditions.
The static parameters (voltages on the amplifier and
discriminator of the ASIC and on the regulator TK112B) were

measured during each exposure. The measurements of the
threshold, noise, gain, discriminator offset, resolution time and
slewing time were done during 10-20 minutes after each
exposure with the use of the ASIC test stand [9]. For each chip
the results were averaged over all channels and normalized to
their initial values obtained before the first exposure.
No latch-ups or spikes or any changes in the static
parameters were observed. However, the dynamic parameters
such as gain, offset, threshold and slewing time were slightly
sensitive to the radiation. The observed threshold Qthr measured
in terms of input charge decreased with the TID (Figure 1) due
Figure 1: Normalized threshold versus dose.
Figure 2: Normalized gain versus dose.
to changes in the amplifier gain (Figure 2) and the discriminator
offset 1 (Figure 3). The overall effect for Qthr is rather small,
about 15% for a TID of 60 kRad. The noise increased by less
than 10% from its initial value of about 1.7 fC. The resolution
time of 1 ns was not affected. The slewing time ST showed a
maximum increase of 40% at a TID of 60 kRad (Figure 4). At
the required 3 times level of TID (5-6 kRad), all changes were
practically negligible. However, at a TID of 65-70 kRad, two
boards failed (no output signal) showing large changes in the
amplitude and the shape of the pulse after the shaper. About a
month later, though, these boards had become operational again.
Figure 3: Normalized discriminator offset versus dose.
Figure 4: Normalized slewing time versus dose.

III. NEUTRON IRRADIATION OF THE ANODE BOARDS
Six boards with CMP16F chips on them were exposed in
October, 2000 to a reactor neutron fluence up to 2x10 12 n/cm 2
at a neutron energy of around 1 MeV. The exposure was 14 min
long. The boards also received a TID of about 50-60 kRad from
γ’s [10] which accompanied the reactor neutrons. Prior to the
test with neutrons, in August 2000, the same boards have been
irradiated in the 63 MeV proton beam at the UC Davis with a
total ionizing dose of 5 kRad delivered during 2.5 min. The
boards were powered in both exposures. The static parameters
of the boards were monitored during the irradiation tests. No
changes of static parameters were recorded in the 63 MeV
proton beam. In the neutron irradiation, the board regulator
output voltage and the voltages of the preamplifier and
discriminator increased by only 2-5% at the end of the
exposure.
The dynamic characteristics of the boards were measured
on the ASIC test stand at Fermilab [9] prior to the test in the
proton beam, and before and after the neutron irradiation. The
set of data obtained after the neutron irradiation includes five
measurements made at intervals of one to two weeks, with the
first measurement taken about 40 days after the neutron
irradiation. The last three tests included two periods of one
week each and one period of four weeks of heating the boards
in an oven at 110 O C. The corresponding changes, averaged
over 16 channels, of Qthr , gain and discriminator offset relative
to their initial values for the six boards are presented in Figures
5 – 7. The initial values of Qthr, gain and offset were in the
ranges of 12 – 22 fC, 9 – 10 mV/fC and 10 – 80 mV
respectively. The noise increased by less than 10% from its
initial value of 2 fC.
Figure 5. Normalized Qthr versus time. The arrows show the
days of proton and neutron irradiations. The dash line presents
the days of heating.
Figure 6. Normalized gain versus time.
Figure 7. The discriminator offset changes versus time.
All boards survived unchanged after the irradiation by the 63
MeV proton beam. This confirms the results obtained earlier in
the proton beam. However, only two boards (68,70) from the
six were working in the first test taken 40 days after the neutron
irradiation. The rest came to life after one week of heating in the
oven at 110 O C. All boards showed moderate changes in their
dynamic characteristics after irradiation by neutrons. Note that
these changes are opposite to the effects observed during proton
irradiation (Section II). Five more weeks of heating brought the
parameters of the boards closer to their values measured before
the proton test.

IV. CONCLUSIONS
The radiation tests of the anode front-end boards performed
in a 63 MeV proton beam show that the boards are operational
up to TID of 60 kRad. At the required 3 times level of TID (5-6
kRad) the dynamic characteristics of the boards remain
unchanged.
The measurements with the neutrons were complicated by
the presence of a significant γ flux. In addition to the nominal
neutron fluence up to 2x10 12 n/cm 2 , the boards received a TID
of 50 – 60 kRad. Only two boards from the six were working in
the test taken 40 days after the neutron irradiation 2 . The rest
become operational after one week of heating in the oven at
110 O C. From our results, we can roughly estimate that for the
test doses given above the annealing time is about a few months
at room temperature. Since the LHC rate of real radiation
exposure is much slower than this, and assuming that the
observed effects were cumulative, we can conclude that the
anode front-end boards should not show 2
any significant
radiation damage during the 10 years of normal LHC operation.
V. ACKNOWLEDGEMENTS
We would like to thank M. Tripathi and B. Holbrook of the
University of California, Davis, and B. Bylsma and T.Y. Ling
of the Ohio State University for their valuable help.
This work was supported by the U.S. Department of
Energy.
VI. REFERENCES
1. N. Bondar, T. Ferguson, A. Golyash, V. Sedov, N.
Terentiev,"Anode Front-End Electronics for the Cathode Strip
Chambers of the CMS Endcap Muon Detector", in these
proceedings.
2. D. Acosta et al, "Large CMS Cathode Strip Chambers:design
and performance." Nucl.Instrum.Meth. A453:182-187, 2000.
3. CMS Technical Design Report - The Muon Project,
CERN/LHCC 97-32 (1997).
4. M. Huntinen, CMS COTS Workshop, Nov. 1999.
Calculations are posted at
http://cmsdoc.cern.ch /~huu /tut1.pdf.
5. F. Faccio, M. Huntinen, G. Stefanini, "A global radiation
test plan for CMS electronics in HCAL, Muons and
Experimental Hall",
http://cmsdoc.cern.ch/~faccio/ presprop. pdf.
6. T.Y. Ling. "Radiation tests for EMU electronics",
http://www.physics.ohio-state.edu/~ling/elec/rad_emu_proc.pdf
7. B. Bylsma, L.S. Durkin, J. Gu, T.Y. Ling, M. Tripathi,
"Results of Radiation Test of the Cathode Front-End Board for
CMS Endcap Muon Chambers", Proceedings of the Sixth
Workshop on Electronics for LHC Experiments, 231-235,
Cracow, Poland, 11-15 Sep. 2000, CERN/LHCC/2000-041
8. R.E. Breedon, B. Holbrook, W. Ko, D. Mobley, P. Murray,
M. Tripathi, "Performance and Radiation Testing of a Low -
Noise Switched Capacitor Array for the CMS Endcap Muon
System", Proceedings of the Sixth Workshop on Electronics for
LHC Experiments, 187-191, Cracow, Poland, 11-15 Sep.
2000, CERN/LHCC/2000-041
9. N. Bondar, A. Golyash, "ASIC Test Stand", a talk given by
A.Golyash on EMU meeting at Fermilab, Feb. 19-20, 1999,
http://www-hep.phys.cmu.edu/cms/TALKS/talks.html
10. B. Bylsma, private communication.
VII. FOOTNOTES
1. The gain and offset were calculated from the following
equation: Gain x Qthr + Offset = Ud , where Ud is the
discriminator setting.
2. Two other boards with CMP16F chips were found working
after neutron irradiation up to 1.2x10 12 n/cm 2 and 1.8x10 12 n/cm 2
in a preliminary test made in July 2000.

CMOS front-end for the MDT sub-detector in the ATLAS Muon Spectrometer -
development and performance
C. Posch 1 , S. Ahlen 1 , E. Hazen 1 , J. Oliver 2
1 Boston University, Physics Department, Boston, USA
2 Harvard University, Department of Physics, Cambridge, USA
Abstract
Development and performance of the final 8-channel
front-end for the MDT segment of the ATLAS Muon
Spectrometer is presented. This last iteration of the readout
ASIC contains all the required functionality and meets
the design specifications. In addition to the basic
"amplifier-shaper-discriminator"-architecture, MDT-ASD
employs a Wilkinson ADC within each channel for
precision charge measurements on the leading fraction of
the muon signal. The data will be used for discriminator
time-walk correction, thus enhancing the spatial resolution
of the tracker, and for chamber performance monitoring
(gas gain, ageing etc.). It was also demonstrated that this
data can be used for performing particle identification via
dE/dX. A programmable pulse injection system which
allows for automated detector calibration runs was
implemented on the chip. Results of performance and
functionality tests on prototype ASICs, both in the lab and
on-chamber, are presented.
I. INTRODUCTION
The ATLAS muon spectrometer is designed for standalone
measurement capability, aiming for a P T resolution
of 10% for 1 TeV muons. This target corresponds to a
single tube position resolution of < 80 �m which translates
into a signal timing measurement resolution of < 1 ns. The
maximum hit rate is estimated 400 kHz per tube.
The ATLAS Monitored Drift Tube (MDT) system is
composed of about 1200 chambers with each chamber
consisting of several layers of single tubes. In total, there
are about 370'000 drift tubes of 3 cm diameter, with
lengths varying from 1.5 to 6 m.
The active components of the MDT on-chamber readout
electronics are the MDT-ASD chip, which receives
and processes the induced anode wire current signal, the
AMT time-to-digital converter (TDC), which measures the
timing of the ASD discriminator pulse edges, and a data
concentrator/multiplexer/optical-fiber-driver (CSM) which
merges up to 18 TDC links into one fast optical link and
transmits the data to the off-detector readout driver
(MROD).
II. CIRCUIT DESIGN
The MDT-ASD is an octal CMOS Amplifier-Shaper-
Discriminator which has been designed specifically for the
ATLAS MDT chambers [5]. System aspects and
performance considerations force an implementation as an
ASIC. A standard commercial 0.5�m CMOS process is
used for fabrication.
The analog signal chain part of the MDT-ASD has been
described and presented previously [3] and will therefore
be addressed only superficially in this article.
The MDT-ASD signal path is a fully differential
structure from input to output for maximum stability and
noise immunity. Each MDT connects to an "active" preamplifier
with an associate "dummy" pre-amp. The input
impedance of the pre-amps is 120 �, the ENC of the order
of 6000 e -
RMS, with a contribution of 4000 e -
from the
tube termination resistor [2].
Following the pseudo-differential pair of pre-amps is a
differential amplifier which provides gain and outputs a
fully differential signal to two subsequent amplifier stages.
These amplifiers supply further gain and implement the
pulse shaping. In order to avoid active baseline restoration
circuitry and tuneable pole/zero ratios, a bipolar shaping
function was chosen [8][6].
The shaper has a peaking time of 15 ns and area balance
of < 500 ns. The sensitivity at the shaper output is
specified 3 mV/primary e -
, or 12 mV/fC, with a linear
range of 1.5 V or 500 primary e -
. The nominal
discriminator threshold is 60 mV, corresponding to 20
primary e -
or 6 �noise .
The bipolar shaping function in conjunction with the
tube gas Ar/CO2 93/7 with its maximum drift time of 800
ns and significant "R-t" non-linearity can cause multiple
discriminator threshold crossings from a single traversing
particle. The MDT-ASD uses an "artificial deadtime"scheme
to suppress these spurious hits.
In addition to the basic amplifier-shaper-discriminatorarchitecture,
the MDT-ASD features one Wilkinson
charge-to-time converter per channel, programmability of
certain functional and analog parameters along with a
JTAG interface, and an integrated pulse injection system.
1� )
1� *
2HA=� F
2 H A = � F
* E = I � 9
2 H A = � F 5 D = F A H
6DHAID��@
, ) , ) , ) ! , ) "
6 E� E� C , EI? HE� E� = J� H
0 OIJAHAIEI
9 E�� E� I� � ) , +
1�4K�@�M �
6 D H A I D � � @ / = JA
1� JA C H= JE� � / = JA/
A � A H = J � H
, A=@JE� A
� KJFKJ � KN
� 8 , 5
+ D = H C A ) , + � K J F K J
Figure 1. MDT-ASD channel block diagram
+ D=��A� � �@A
+ DEF � �@A
The shaper output is fed into the discriminator for
leading edge timing measurement and into the Wilkinson
ADC section for performing a gated charge measurement
on the leading fraction of the tube signal (Figure 1). The
information contained in the MDT-ASD output pulses,
namely the leading edge timing and the pulse width
encoded signal charge, are read and converted to digital
data by a TDC [1].
� 7 6 )
� 7 6 *

A. Wilkinson ADC
The Wilkinson dual-slope charge-to-time converter
operates by creating a time window of programmable
width at the threshold crossing of the tube signal,
integrating the signal charge onto a holding capacitor
during that gate time, and then discharging the capacitor
with a constant current. The rundown current is variable in
order to adjust to the dynamic range of the subsequent
TDC.
The Wilkinson cell operates under the control of a gategenerator
which consists of all-differential logic cells. It is
thus highly immune to substrate coupling and can operate
in real time without corrupting the analog signals.
The main purpose of the Wilkinson ADC is to provide
data which can be used for the correction of time-slew
effects due to signal amplitude variations. Time slewing
correction eventually improves the spatial resolution of the
tracking detector and is necessary to achieve the specified
80�m single tube resolution. In addition, this type of
charge measurement provides a useful tool for chamber
performance diagnostics and monitoring (gas gain, tube
ageing etc). Measurements of the Wilkinson conversion
characteristics as well as the noise performance and nonsystematic
charge measurement errors of the Wilkinson
ADC are shown in sections III.C and III.D.
The feasibility of the MDT system to perform particle
identification via dE/dX measurement using the Wilkinson
ADC was evaluated. The results of a simulation study on
energy separation capability of the MDT system are
published in [4].
B. Programmable parameters
It was found crucial to be able to control certain analog
and functional parameters of the MDT-ASD, both at
power-up/reset and during run time. A serial I/O data
interface using a JTAG type protocol plus a number of
associated DACs were implemented on the chip.
1) Timing discriminator
The threshold of the main timing discriminator is
controllable over a wide range (up to > 4 times nominal)
with 8-bit resolution. The discriminator also has adjustable
hysteresis from 0 to 1/3 of the nominal threshold.
2) Wilkinson converter control
The integration gate width can be set from 8 ns to 45 ns
in steps of 2.5 ns (4-bit). This setting controls what
fraction of the leading part of the signal is used for
conversion. The nominal gate width is 15 ns which
corresponds to the average peaking time t p of the preamplifier.
It can be demonstrated that the time slewing is
only correlated to the leading edge charge and not to the
total signal charge of the MDT signal. ADC measurements
with a gate > 2 � t p thus can not be used to further improve
the spatial resolution of the system [6][7]. However for
dE/dX measurements for particle identification, longer
gates are desirable [4]. The current controlling the gate
width is set by a binary-weighted switched resistor string.
The discharge (rundown) current of the integration
capacitors is controlled by a 3-bit current DAC. This
feature allows the ADC output pulse width to be adjusted
to the dynamic range of the TDC (e.g. 200 ns @ at a
resolution of 0.78125 ns for AMT-1 [1]).
The end of one Wilkinson conversion cycle is triggered
by a second variable-threshold discriminator. The setting
of this threshold also affects the width of the Wilkinson
output pulse but in principle does not influence the ADC
performance significantly and is primarily implemented
for troubleshooting and fine-tuning purposes.
3) Functional parameters
The deadtime setting defines an additional time window
after each hit during which the logic does not accept and
process new input. It can be set from 300 to 800 ns in
steps of 70 ns (3 bit). The nominal setting is 800 ns
corresponding to the maximum drift time in the MDT.
This feature is used to suppress spurious hits due to
multiple threshold crossings in the MDT signal tail and
thus reducing the required readout bandwith.
A number of set-up bits are designated to control global
settings for single channels and the whole chip. For
diagnostic (boundary scan interconnect testing etc.) and
troubleshooting purposes, the output of each channel can
be tied logic HI or LO. The chip itself can be set to work
either in ToT (Time-over-threshold) or ADC mode (the
output pulse contains the pulse-width encoded charge
measurement information).
Table 1 summarizes the programmable parameters.
Table 1. MDT-ASD programmable parameters
PARAMETER NOMINAL RANGE LSB UNIT
DISC1 Threshold 60 -256 � 256 2 mV
DISC1 Hysteresis 10 0 � 20 1.33 mV
Wilkinson integration gate 14.5 8 � 45 2.5 ns
DISC2 Threshold 32 32 � 256 32 mV
Wilkinson discharge current 4.5 2.4 � 7.3 0.7 �A
Dead-time 800 300 � 800 70 ns
Calibration channel mask – – – –
Calibration capacitor select – 50 � 400 50 fF
Channel mode ON ON, HI, LO – –
Chip mode ADC ADC, ToT – –
C. Calibration pulse injection
In order to facilitate chip testing during the design phase
as well as to perform system calibration and test runs with
the final detector assembly, a differential calibration/test
pulse injection system was implemented on the chip. It
consists of two parallel banks of 8 switchable 50 fF
capacitors per channel and an associated channel mask
register. The mask register allows for each channel to be
selected separately whether or not it will receive test
pulses. The capacitors are charged with external voltage
pulses, nominal 200 mV swing standard LVDS pulses,
yielding an input signal charge range of 10 � 80 fC. The
pulse injection system enables fully automated timing and
charge conversion calibration of the MDT sub-detector.
Calibration runs are required for example after changes in
certain setup parameters.

III. TEST RESULTS
The MDT-ASD has been prototyped extensively. The
last iteration, ASD01A, is a fully functional 8-channel
prototype and is considered to be the final production
design. Results of functionality and performance tests on
this prototype, indicate that the ATLAS MDT front-end is
ready for mass-production 1 .
A. Pre-amp - Shaper: Sensitivity
Figure 2 shows oscilloscope traces of the shaper output
at the threshold coupling point. The measurements were
taken with a calibrated probe using well defined input
charges. The peaking time of the delta pulse response
(time between the arrows) is 14.4 ns. There is a probe
attenuation of 10:1 which is not accounted for in the peak
voltage values in the left hand column. Due to the
differential architecture, the voltages have to be multiplied
by a factor 2 to obtain the total gain (Figure 3).
Figure 2. Shaper output for 40, 60, 80 and 100 fC input charge.
The peak voltages translate into the sensitivity curve below by
multiplying with a factor of two (single-ended to differential)
and taking into account a probe attenuation of 10:1.
shaper peak voltage [mV]
1000
800
600
400
200
20
40
60
input charge [fC]
W_coef={27.067,10.042}
W_sigma={5.47,0.0882}
Gain = 10.042 mV/fC
Figure 3. Sensitivity of the analog signal chain (Pre-amp to
shaper) for the expected input signal range. The gain amounts to
10 mV/fC, exhibiting good linearity.
1
Aspects of radiation tolerance have not been addressed in this
article, however results of radiation tests on the process and the
prototype chips indicate that ATLAS requirements are met.
80
100
B. Discriminator time slew
Due to the finite rise time of the signal at the
discriminator input, different signal amplitudes with
respect to the threshold level produce different threshold
crossing times. This effect is called time slew. Figure 4
shows the time slew as measured for a constant threshold
by varying the input charge. The time slew over the
expected muon charge range (~ 20 – 80 fC) is of the order
2 ns. Comparing this number to the requirements, it
becomes obvious that slew correction through charge
measurement is an essential feature of the MDT-ASD.
time slew [ns]
10
8
6
4
2
0
20
40
60
input charge [fC]
Figure 4. Time slew of the MDT-ASD signal chain. The data
display the timing of the discriminator 50% point of transition as
a function of input signal amplitude for a 20 mV threshold.
C. Wilkinson ADC performance
The transfer characteristic of the Wilkinson charge
ADC is plotted in Figure 5. The traces show the non-linear
relation between input charge and output pulse width for 4
different integration gates. The advantage of this
compressive characteristic is that small signals which
require a higher degree of time slew correction gain from a
better charge measurement resolution. The disadvantage is
an increased number of calibration constants. The dynamic
range spans from 90 ns (8 ns gate) to 150 ns (45 ns gate).
Wilkinson pulse width [ns]
200
150
100
50
20
40
60
input charge [fC]
80
80
Gate time:
8 ns
15 ns
25 ns
45 ns
Figure 5. Wilkinson ADC output pulse width as a function of
input charge for 4 different integration gate widths
100
100

D. Noise performance and non-systematic
measurement errors
The timing information carried by the ASD output signal
is recorded and converted by the AMT (Atlas Muon TDC)
time-to-digital converter. The AMT can be set to provide a
dynamic range for the pulse width measurement of 0 - 200
ns with a bin size of 0.78 ns [1]. If the ASD is
programmed to produce output pulses up to a maximum of
200 ns, then the combination of the ASD and the AMT
chip represents a charge-ADC with a resolution of 7 - 8
bits.
Non-systematic errors in the timing and charge
measurement due to electronic noise in the ASDs and
AMTs and quantization errors set a limit to the
performance of the system. The following two sections
present test results on the noise performance of the MDT-
ASD and determine how the noise introduces error and
degrades the accuracy of the measurements.
1) Time measurement
Figure 6 shows the measured RMS error of the leading
edge time measurement at the output of the ASD as a
function of signal charge. The lower curve gives the noise
for floating pre-amplifier inputs while the upper curve
includes the effect of the 380 � tube termination resistor.
The threshold is set to its nominal value of 60 mV
(corresponding to ~ 5 fC). The horizontal axis gives the
charge of the input signal applied through the test pulse
injection system. Typical muon signals are expected to be
in the range of 20 - 80 fC, resulting in a RMS error of the
order of 200 ps.
The time-to-digital conversion in the AMT shows a
RMS error of 305 ps, including 225 ps of quantization
error [1]. The resulting total error of the time
measurement, covering all internal noise sources from the
front-end back to the A/D conversion, will typically be of
the order of 360 ps RMS.
σ (leading edge) [ns]
1.0
0.8
0.6
0.4
0.2
0.0
20
40
60
input charge [fC]
no termination
380 Ohm TR
Figure 6. RMS error of the leading edge timing measurement
vs. input charge for a fixed discriminator threshold (set to its
nominal value of 60 mV or 5 fC). Typical muon signals will be
of the order of 40 - 50 fC. Bottom curve: floating pre-amp input,
top curve: with 380 � tube termination resistor.
80
100
2) Charge measurement
Measurement errors in the pulse width at the ASD
output are typically below 600 ps RMS, depending on
signal amplitude and integration gate width. Figure 7
shows the ASD Wilkinson noise versus signal amplitude
in percent of the measured charge for 3 short integration
gate widths. The pulse width conversion (two independent
pulse-edge conversions) in the AMT exhibits a RMS error
of 430 ps including quantization error. Hence, the
resulting total error, covering all internal noise sources
from the front-end back to the A/D conversion, stays in
the range of under 800 ps RMS. This number corresponds
to a typical error of well below 1% of the measured charge
for the vast majority of signals.
The effect of the tube termination resistor can be seen in
Figure 8. Contributing about 4000 e - ENC, this termination
resistor constitutes the dominant noise source of the readout
system.
σ (pulse width) [% of measured charge]
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
20
40
60
input charge [fC]
Integration Gate [ns]
80
380 Ohm TR
11
13.75
17.5
Figure 7. RMS error of Wilkinson pulse width at the output of
the ASD as a function of input signal charge for a fixed
discriminator threshold (nominal), given in percent of the
measured charge. Note the decrease in noise for growing
integration gate widths.
σ (pulse width) [% of measured charge]
2.0
1.5
1.0
0.5
0.0
20
40
integration gate: 11 ns
60
input charge [fC]
no termination
380 Ohm TR
Figure 8. Effect of the 380 � tube termination resistor on the
charge measurement error.
80
100
100

All systematic charge measurement errors e.g. due to
converter non-linearities or channel-to-channel variations
can be calibrated out using the ASD`s programmable testpulse
injection system.
IV. ON-CHAMBER TESTS WITH A COSMIC RAY
TEST SETUP
A cosmic ray test stand has been set up at Harvard
University. The system with one Module-0 endcap
chamber (EIL type) and a trigger assembly of 4 scintillator
stations records > 1 GeV cosmic muons. The read-out
electronics employs an earlier 4-channel prototype of the
ASD, mounted on "mezzanine" boards, each of which
services 24 tubes. This earlier ASD version does not
contain a Wilkinson ADC or a test-pulse circuit, but for
the purposes of this test it is functionally equivalent to the
latest prototype. An extensive description of this test stand
and presentation of the analysis methods and results are
the subject of a forthcoming ATLAS note by S. Ahlen.
A histogram of TDC values for single-muon 8-tube
events is shown in Figure 9. The maximum drift time is
seen to be about 1000 channels (780 ns).
Figure 9. TDC spectrum produced on the cosmic ray test stand.
A track fitting program to evaluate chamber resolution
has been developed. The procedure first obtains fits using
the four tubes of each multilayer. These fits determine the
most likely position of the global trajectory relative to the
drift tube wire by considering all 16 possibilities for each
multilayer. Then a global 8-tube straight-line-fit is done
using this information, and then the two most poorly fit
tubes are rejected and a final 6-tube fit is accomplished.
This last step rejects delta rays, poor fits for near-wire hits,
and large multiple scatters. With no additional data cuts a
single tube tracking resolution of about 100 µm (and
nearly 100% efficiency) is obtained.
By requiring consistency of the slopes of the 4-tube fits
in the two multilayers (4 mrad) more multiple scatters and
delta rays are rejected. The result of this cut is that the
single tube spatial resolution improves to about 70 µm
with about 45% efficiency.
Figure 10. shows the distribution of the residuals
representing the distances from the fitted track line to the
time circles around the wires.
Figure 10. Spatial resolution of the EIL chamber on the cosmic
ray test stand (horizontal axis in mm)
More detailed studies of the MDT resolution are
underway at several sites, but these initial results suggest
that the ASD-based front-end electronics can provide the
required precision under operational conditions.
V. CONCLUSIONS
Development, design and performance of the 8-channel
CMOS front-end for the MDT segment of the ATLAS
Muon Spectrometer has been presented. The device is
implemented as an ASIC and fabricated using a standard
commercial 0.5 �m CMOS process. Irradiation data on the
fabrication process and on the prototype chip exist and
indicate that ATLAS radiation hardness standards are met.
Results of functionality and performance tests, both in
the lab and on-chamber demonstrate that the ATLAS
MDT front-end is ready for mass-production.
VI. REFERENCES
[1] Y.Arai, Development of front-end electronics and TDC
LSI for the ATLAS MDT, NIM in Physics Research A
453 (2000) 365-371, 2000.
[2] J. Huth, A. Liu, J. Oliver, Note on Noise Contribution of
the Termination Resistor in the MDTs, ATLAS Internal
Note, ATL-MUON-96-127, CERN, Aug. 1996.
[3] J. Huth, J. Oliver, W. Riegler, E. Hazen, C. Posch, J.
Shank, Development of an Octal CMOS ASD for the
ATLAS Muon Detector, Proceedings of the Fifth
Workshop on Electronics for LHC Experiments,
CERN/LHCC/99-33, Oct. 1999.
[4] G. Novak, C. Posch, W. Riegler, Particle identification
in the ATLAS Muon Spectrometer, ATLAS Internal
Note, ATL-COM-MUON-2001-020, CERN, June 2001.
[5] C. Posch, E. Hazen, J. Oliver, MDT-ASD, CMOS frontend
for ATLAS MDT, ATLAS Internal Note, ATL-
COM-MUON-2001-019, CERN, June 2001.
[6] W. Riegler, MDT Resolution Simulation - Front-end
Electronics Requirements, ATLAS Internal Note,
MUON-NO-137, CERN, Jan. 1997.
[7] W. Riegler, Limits to Drift Chamber Resolution, PhD
Thesis, Vienna University of Technology, Vienna,
Austria, Nov. 1997.
[8] W. Riegler, M. Aleksa, Bipolar versus unipolar shaping
of MDT signals, ATLAS Internal Note, ATL-MUON-
99-003, March 1999.

"The MAD", a Full Custom ASIC
for the CMS Barrel Muon Chambers Front End Electronics
Abstract
To meet frontend electronics needs of CMS barrel muon
chambers a full custom ASIC, named "The MAD", has been
first developed by INFN of Padova and then produced in
80.000 pieces to equip the 180.000 drift tubes[1].
The task of this IC is to amplify signals picked up by
chamber wires, compare them against an external threshold
and transmit the results to the acquisition electronics.
The chip, built using 0.8 µm BiCMOS technology,
provides 4 identical chains of amplification, discrimination
and cable driving circuitry. It integrates a flexible channel
enabling/disabling feature and a temperature probe for
monitoring purposes.
The working conditions of the detector set requirements
for high sensitivity and speed combined with low noise and
little power consumption. Moreover, as the basic requirement
for the frontend is the ability to work at very low threshold to
improve efficiency and time resolution, a good uniformity of
amplification between channels of different chips and very
low offset for the whole chain are needed.
The ASIC has been extensively and deeply tested resulting
in good performances; particularly, big effort was put in
testing radiation (neutron, gamma rays and ions) tolerance and
ageing effects to check behaviour and reliability in LHC
environment.
A. General
I. ASIC DESCRIPTION
The analog frontend electronics for the muon chambers of
CMS barrel has been integrated in a full custom ASIC, named
"The MAD", developed by INFN of Padova using 0.8 µm
BiCMOS technology from Austria Mikro Systeme. Each chip
provides the signal processing for 4 drift tubes in a 2.5x2.5 mm 2
die, housed in a TQFP44 package.
Figure 1 shows the block diagram of the ASIC: the 4
identical analog chains are made of a charge preamplifier
followed by a simple shaper with baseline restorer, whose
output is compared against an external threshold by a latched
discriminator; the output pulses are then stretched by a
programmable one-shot and sent to an output stage able to
drive long twisted pair cables with LVDS compatible levels.
Control and monitoring features have been included in the
chip: to mask noisy wires each channel can be disabled at the
F. Gonella and M. Pegoraro
University and INFN Sez. of Padova, 35131 Padova, Italy
franco.gonella@pd.infn.it, matteo.pegoraro@pd.infn.it
shaper input resulting in little crosstalk to neighbours. A fast
disable/enable feature, controlled via LVDS levels acting on
the output driver of left and right channel pairs, allows the
simulation of tracks perpendicular to the detector. An absolute
temperature probe has been integrated in order to detect
electronics failures and monitor environmental changes.
Two separate power supplies (5 V and 2.5 V) are used in
order to reduce power drain and minimize interference
between input and output sections. The layout and routing
have been particularly cured and many pins have been
reserved for power, input ground and analog ground.
To prevent latch-up events and improve crosstalk
performances guard ring structures have been largely used to
isolate sensitive stages like the charge preamplifier or
complementary MOS devices.
In1
A_EN1
A_EN2
In2
GNA
VCC
GNA
In3
A_EN3
GNA VCC T_OUT T_EN W_CTRL GND D_ENL1 D_ENL2 VDD
PA
PA
PA
OUTP1
OUTN1
BYP
A_EN4
In4 PA
BLR
SHAPER
DISCR LATCH
ONE
SHOT
LVDS
DRIV
GND
OUTN4
OUTP4
GNA
VCC
SHAPER
BLR
BLR
SHAPER
TEMP
PROBE
SHAPER
BLR
VTH
DISCR
DISCR
DISCR
Figure 1: Block diagram of the ASIC.
B. Analog section
LATCH
LATCH
WIDTH
CTRL
LATCH
ONE
SHOT
ONE
SHOT
ONE
SHOT
LVDS
DRIV
LVDS
DRIV
BIAS
LVDS
DRIV
VREF GND D_ENR1 D_ENR2 VDD
GND
OUTN2
OUTP2
OUTP3
OUTN3
The preamplifier uses a single gain stage with a GBW
product in excess of 1 GHz (from simulation) and a feedback
time constant of 33 ns. Input pads, derived from standard
ones, were modified to enhance ESD protection by integrating
series resistor and large diodes connected to analog ground.
Power dissipation for this stage is about 2.5 mW.
The shaper is a low gain integrator with a small time
constant: the noninverting input is connected to the
preamplifier while the inverting one allows to put this stage
inside the feedback loop of a low offset OTA; this
combination implements a time invariant baseline restorer

acting as a high pass filter for the signal path. Tests performed
on this circuit show that the quiescent level of the shaper
output can be set anywhere between 1.0 and 3.5 V even in the
presence of worst-case parameters for fabrication process and
operating conditions of the IC. The pin VREF, common to the
four OTAs, is used to control the quiescent level from outside.
The output of the shaper is directly connected to the
noninverting input of a fully differential discriminator with 2
gain stages. The other input of the comparator is connected to
the external threshold pin VTH, common to all channels. The
input section uses no special technique, except a careful
layout, to obtain low offset with high speed; a hysteresis of
about ±1 mV helps in avoiding autoscillation and in speeding
up commutation with slow input signals. Common mode input
voltage ranges from 1.2 to 3.8 V. Finally, a buffer prevents
switching noise from the following sections to propagate
backwards to sensitive paths.
All previously described blocks share a single +5 V supply
for about 12 mW power drain.
C. Output section
The buffered output of the discriminator is capacitively
coupled to a one-shot that is very similar to a classical astable
multivibrator; its differential output, when active, stores the
status of comparator in the latch so producing a non
retriggerable pulse whose width is inversely proportional to
the current sunk from W_CTRL pin, again shared by all
channels. Critical parameters of this section are propagation
delay, which sets the ability to catch narrow pulses produced
by signals just over threshold, and the time it takes to fully
recover after the falling edge of a pulse.
The same lines that activate the latch are used to feed the
output driver, again a differential one capable of driving a 100
Ω load at voltage levels compatible with LVDS standard.
Voltage driving has been chosen because NPN bipolar
transistors are faster than PNP and PMOS devices and also
because this turns out to be a power convenient choice when
the load is a cable terminated at both ends. The working
conditions of the driver are a compromise between speed and
power drain: rise and fall time are below 2.5 ns and, to reduce
external components, terminating resistors are integrated in
the pads. To reduce consumption, the supply voltage is the
lowest possible, 2.5 V, yielding power dissipation, including
the one-shot, of about 12 mW.
D. Temperature sensor, channels masking and
biasing
Temperature sensing is based on the voltage difference
between base emitter junctions operated at different current
densities. Voltage output is 7.5 mV/°K and power drain about
1 mW from 5 V. The output is always available at pin
while at pin T_OUT a unity gain buffer, enabled by a TTL
high level (pin T_EN), allows the multiplexing of more chips
on the same net.
Each frontend channel can be masked by a TTL high level
applied to pins A_EN(1-4), in this case recovery to normal
operation requires about 10 μs. Channels 1 & 2 (left channels)
can be enabled or disabled in about 30 ns by a differential
signal, LVDS or 3.3 V PECL, applied to pins D_ENL(1-2);
the same for right channels 3 & 4 via pins D_ENR(1-2).
A bias circuit controls the current generators of the whole
chip and supplies voltage for one-shot sections. Its output is
connected to pin BYP for bypassing with a capacitor to GNA.
II. ASIC PERFORMANCES
We have verified ASIC performances on bare chips using
a specific test board with minimal stray capacitance to reduce
measurements errors. The same measurements have been
carried out on chips mounted on FEB, the final boards in
which the frontend electronics of the CMS barrel muon
chambers is organized.
First of all power dissipation is very low, about 25 mW/ch
with little variation with temperature and input signal rate.
A. General tests
Since no test pads were foreseen in the chip, tests on the
analog section are based on the statistics of output response to
δ−like charge pulses, injected by a voltage pulse generator via
a series capacitor of about 1pF.
In order to measure the gain, two different values of
charge, 3 and 9 fC, have been injected: the resulting threshold
distributions for the bare chip have mean values of 10.7 and
33.6 mV, respectively, with r.m.s. of 0.34 and 0.42 mV (see
figure 2). This little spread is due to gain variations among
chips, caused by the tolerance of feedback capacitor in charge
preamplifier, and by the discriminator and baseline restorer
offset.
Resulting gain is 3.8 mV/fC in average, about 10% higher
than simulated because of a process parameter (capacitor
oxide thickness) out of specification in the preserie wafer
(results shown are from preserie devices). Sensitivity is
constant up to 500 fC input with less than 1% integral
nonlinearity and saturation occurs at about 800 fC. Uniformity
is very good, r.m.s. about 0.01 mV as chips belong to the
same wafer.
# channels
18
16
14
12
10
8
6
4
2
0
events: 32
mean: 3,77
std.dev: 0,01
min: 3,73
max: 3,80
3.70 3.70
3.74 3.74
3.78 3.78
3.82 3.82
3.86 3.86
Sensitivity (mV/fC)
# channels
16
14
12
10
Figure 2: Sensitivity and noise of bare ASIC.
8
6
4
2
0
events: 32
mean: 1318
sdt.dev: 65
min: 1230
max: 1548
1100 1100
1250 1250
1400 1400
1550 1550
1700 1700
Noise (electrons)
Other key characteristics for low threshold operation are
noise and crosstalk: bare chips exhibit ENC 1320 electrons

(slope of 45 e/pF) and a value below 0.1% for the latter. Once
mounted on the PCB these two figures increase to 1900
electrons (slope of 60 e-/pF) and 0.2% because of the external
protection network mounted on FEBs in order to withstand a
full discharge of one drift tube.
Figure 3 shows the time walk characteristics versus the
input charge overdrive (amount of charge over the threshold)
for the bare ASIC in two different configurations. In the first
case the input pins are directly connected to the charge
generator, while in the second one a 40 pF capacitor is added
to simulate the detector capacitance (about 10 pF/m, so this
value represents the worst case). Since the estimated average
charge is about 50÷100 fC, the deterioration on time walk
performances is acceptable.
Delay (ns)
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
TIME WALK
Cd=0, Thr=3fC
Cd=40pF, Thr=4fC
1 10 100 1000
Input Charge overdrive (fC)
Figure 3: Time walk of the bare chip with 2 input configurations.
Temperature sensors integrated in the ASIC were also
tested for chips mounted on the FEBs: at an ambient
temperature of 23±1 °C, we obtain an average value of 27 °C,
with a maximum error of ±3 °C and a heating of 4 °C respect
to ambient.
The conversion factor of 7.5 mV/°K has been measured
for few ASICs in a climatic chamber in the range 0÷100 °C.
In the same chamber we have verified specifications as a
function of temperature. All performances, except for output
width, exhibit little variations against temperature and the
output levels comply with LVDS standard in the 0÷100 °C
range and for supply voltage tolerances of ±10%.
B. July 1999 and 2000 Test Beam results
A prototype chamber with a final design of the cells and
equipped with MAD chips, was installed inside the M1
magnet of the CERN H2 zone and exposed to high-energy
muon beams in July 1999[4] and in the same period of
2000[6].
The results obtained were very satisfactory: efficiency
higher than 95.5% and resolution of 200 μm were reached in
all operating conditions with safety values of drift tubes
voltages.
In detail figure 4 shows the meantimer resolution for
different beam positions along the wires[5] and different wire
amplification: degradation of signals coming from the
opposite end of the wire (respect to FEB) account for a
resolution worsening limited to 0.5 ns in real conditions.
Figure 4: Meantimer resolution for different beam positions along
the wires and different amplification.
III. ASIC RELIABILITY
About 45000 ASICs are located inside the gas volume of
the CMS detector in a hardly accessible environment and
must operate for a long time (at least 10 years) with no or
minimal maintenance.
Electronics reliability is therefore a crucial point and
specific tests were performed to check the ASIC against
radiations, ageing and HV discharges.
A. Radiation tests
Besides usual considerations about wear out of electronics,
big concern must be devoted to radiation tolerance: in the
barrel muon stations only the neutron flux (5 10 10
n/cm2 for 10
years of LHC activity, 10% thermal), can generate problems
(the iron yoke is a shield against other radiation type) mainly
due to SEU and SEL (Single Events Upsets and Latch-up).
The first item accounts for trigger and readout noise while the
second one can cause device burn out.
The spectrum of neutron flux in CMS ranges from thermal
up to high-energy. To meet these specifications, we have
performed tests at INFN Legnaro National Laboratory (for
thermal and fast neutrons up to 10 MEV) and at the Universitè
Catholique of Louvain-la-Neuve laboratory (for fast neutrons
up to 60 MeV)[2].
Low energy neutrons were produced using a graphite
moderator with a deuterium beam accelerated up to 7 MeV by
the Van de Graaff accelerator of LNL while fast neutrons up
to 10 MeV were obtained from the same beam on a thick
beryllium target. In a same way, the Louvain facility provides
a wide neutron spectrum, roughly flat in the range 20-60
MeV, using a protons beam of energy up to 65 MeV.
For all radiation tests a suitable acquisition system was
implemented in order to monitor supply currents and
temperature of the ASIC to detect latch-up events; SEU
events at different threshold levels have been acquired to

verify the dependence using counters on single channels.
Also, at the end of exposure, all devices were deeply re-tested
to verify changes in static and dynamic characteristics.
Being basically a charge sensitive device, this ASIC is
naturally affected by SEU: we are interested in checking if the
associated rate is compatible with detector efficiency.
The neutron cross-section per readout channel is plotted in
Figure 5 showing a roughly exponential dependence on the
threshold. We can see the not-negligible contribution of slow
neutrons to cross-section (only one measure at 20 fC
threshold). From these results we can estimate few thousands
spurious counts for the whole detector activity: a very safe
value.
Cross section (cm2/channel)
1,E-07
1,E-08
1,E-09
1,E-10
Cross Section vs Threshold
0,00
1,E-06
20,00 40,00 60,00 80,00 100,00
MAD Louvain (60MeV) MAD LNL (10Mev)
MAD LNL (Thermal)
Threshold charge (fC)
Figure 5: Fast and slow neutrons cross-section versus threshold.
In all tests performed with neutrons no LATCH-UP events
were detected. Also performances tests done after irradiation
have shown no significant changes.
For better SEL characterization of the chip, we decided for
a test with heavy ions, as the energy deposition is quite
larger[3]. Measurements have been performed in April 2000
at the Tandem accelerator of INFN LNL. The ion beams were
set to obtain fluxes (monitored on line with silicon diodes) of
10 4 -10 5 ions/cm 2 s -1 in order to achieve an integrated fluence
of some units/μm 2 in the die. Table 1 shows the ions used,
selected to cover a useful range of LET values.
Table 1: LET (MeVcm/mg) and energy
(MeV) of ions beams used.
Ion Energy LET
79 Br 242 39,4
79 Ag 267 54,7
127 I 277 61,8
The irradiated ASIC was a sample of the final production,
housed in a ceramic package without cover in order to expose
directly the silicon die.
Figure 6 shows SEU cross-section versus threshold
measured in 2 different condition: the largest figures have
been obtained enabling the amplifying section of all channels,
while in the second case only the output circuits were enabled
resulting in much lower values, independent on threshold.
We found little difference in cross-sections ranging from
4·10 -4 to 7·10 -4 cm 2 /ch with ions type. Also in this case no
latch-up event was detected.
Hence results from irradiation with heavy ions show little
ASIC sensitivity to SEU and immunity to LATCH-UP, in
agreement with previous neutron tests.
Cross Section (cm2/ch)
0.0008
0.0007
0.0006
0.0005
0.0004
0.0003
0.0002
0.0001
0
Heavy Ions Cross Section vs. Threshold
Br (242MeV - 39MeVcm/gm) Br (Masks ON)
Ag (267MeV - 54.7MeVcm/gm) Ag (Masks ON)
I (277MeV - 61.8MeVcm/gm) I (Masks ON)
0.0 50.0 100.0 150.0 200.0 250.0 300.0
Threshold (fC)
Figure 6: Heavy ions cross-section versus threshold.
Last check was performed with gamma rays: few
prototypes have been exposed to a Cobalt source up to 80
Krad dose in Bologna facility: static and dynamic
characteristics measured before and after irradiation have not
shown any significant change.
B. HV discharges test
Whenever a spark occurs in a drift tube a very large
charge, stored in the 470 pF decoupling capacitor, moves into
the sensitive input pins of the chip. To preserve the ASIC
from this potentially destructive event a protection circuit was
added on FEB: a 39 Ω series resistor and a double diode to
ground, all in parallel with 100 μm gap limiting voltage to
about 500 V. Tests have shown that with this configuration
the ASIC inputs can withstand more than 10 5 sparks at full
wire potential (~3.6 KV) and still work.
C. Ageing test
Another important parameter concurring to system
reliability is MTBF (mean time before failure). The practical
method to measure it, is to let electronics operate in stress
conditions (high temperature and supply values) for a long
time, resulting in accelerated ageing, and detect failures
versus time.
A test was performed on 10 prototypes, keeping them into
an oven at 125 °C for 2000 hours in order to simulate 10 years
of CMS activity. Test ended with no faults; extensive tests on
whole frontend electronics, FEBs and service boards, are now
in progress having simulated several years of activity with no
faults.
IV. CONCLUSIONS
The MAD ASIC, now produced in about 80.000 tested
pieces, shows very good performances at low power
consumption as summarized in the table below. Also
temperature probe and masking features work properly.
The chip was extensively and successfully tested with
muon beam at H2 CERN facility.

COMPASS, a HEP experiment under construction at the
Super Proton Synchrotron (SPS), has used some thousands
MAD chips for its multiwires proportional chambers and
preliminary results confirm good performances.
The ASIC shows good MTBF characteristics, low SEU
rate and immunity to latch-up events in spite of using a
standard and not too expensive technology. Safe and reliable
operation in CMS environment can be assumed with a
reasonably low rate of background events and failures.
V. REFERENCES
[1] F. Gonella, M. Pegoraro, A prototype ASIC for the
readout of the drift tubes of CMS Barrel Muon Chambers,
Proceedings of the Fourth Workshop on Electronics for LHC
experiments, CERN LHCC 98-36, 1998 p. 257.
Table 2: Summary of ASIC performances (preserie).
[2] S. Agosteo et al., First evaluation of neutron induced
Single Event Effects on the CMS barrel muon electronics,
CMS Note 2000/024.
[3] L. Barcellan, F. Gonella, D. Pantano, M. Pegoraro and
J. Wyss, Single Events Effects induced by heavy ions on the
frontend ASIC developed for the muon chambers of CMS
barrel, LNL Annual Report 2000, pag. 248.
[4] M. Aguilar-Benítez et al., Construction and Test of the
final CMS Barrel Drift Tube Muon Chamber Prototype,
accepted for publication in Nucl. Instr. And Meth. A (2001).
[5] S. Paoletti, A study of the CMS Q4 prototype chamber
for different beam positions along the wires, CMS IN
2000/021.
[6] M. Cerrada et al., Results from the Analysis of the Test
Beam Data taken with the Barrel Muon DT Prototype Q4,
CMS Note 2001/041.
power ≅ 25 mW/channel @ +5 V & +2.5 V threshold range 0÷500 fC with < 1% nonlinearity
Zin ≅ 100 Ω (5÷200 MHz) crosstalk < 0.1%
noise ≅ 1300 e - ± 5% @ C D = 0; slope ≅ 45 e - /pF propagation delay ≅ 4 ns
sensitivity ≅ 3.77 mV/fC ± 0.5% time walk ≅ 3.5 ns @ C D = 0
BLR + discriminator offset < 0.13 fC r.m.s. output pulse width 20÷200 ns (5% r.m.s. @ 50 ns)
max input signal before saturation ≅ 800 fC one shot dead time ≅ 9 ns
input rate without loss of accuracy > 2 MHz @ 800 fC output t r & t f < 2.5 ns
No latch up events detected for neutrons up to 60 MeV
Figure 7: Microphoto of the definitive die bonded to a ceramic case.

Status of the CARIOCA Project
W. Bonivento 1,2 , D. Moraes 1,3 , P. Jarron 1 , W. Riegler 1 , F. dos Santos 1
1 CERN, 1211 Geneva 23, Switzerland
2 Instituto Nazionale di Fisica Nucleare,Sezione di Cagliari, Italy
3 LAPE – IF/UFRJ, CP 68528 Cidade Univ., Ilha do Fundão BR-21945970 Rio de Janeiro, Brazil.
Walter.Bonivento@cern.ch, Danielle.Moraes@cern.ch
Abstract
CARIOCA is an amplifier shaper discriminator chip,
developed in IBM 0.25µm CMOS for the readout of the
LHCb muon wire chambers. Four prototype chips were
designed and fabricated over the last two years with a step
by step approach testing the different functionalities of
the chip. In this paper the design and test results of a
positive polarity and negative polarity amplifier, as well
as a shaper circuit, are discussed.
I. INTRODUCTION
The LHCb muon system will use 80,000 wire
chamber channels of negative (wire readout) and positive
(cathode readout) polarity. Figure 1 shows the block
diagram for one readout channel.
Figure 1: Block diagram of one readout channel
The chamber signal, with a fast rising edge and a long
1/t tail, is amplified and shaped to a unipolar narrow pulse
in order to cope with the high rate expected in the
experiment. A baseline restoration circuit is needed to
compensate for baseline shifts and fluctuations. The
circuit is fully differential from the shaper on.
To this date the positive and negative amplifiers as
well as shaper and discriminator have been designed and
fabricated. The results of a 4-channel version of the
positive polarity amplifier are presented in [1], together
with the chip specifications. In this report we present
measurements of a 14-channel positive amplifier chip and
results of the negative polarity amplifier and the shaper.
II. THE 14-CHANNEL POSITIVE POLARITY
AMPLIFIER
The main purpose of the 14-channel chip was to test chip
uniformity and crosstalk. The individual channels show
linearity up to an injected charge of 200fC (delta input),
with a non-linearity error of about 1%. The measured
sensitivity is 8mV/fC up to a detector capacitance of
140pF and we find an equivalent noise charge of
ENC=867e - + 36e - /pF. The sensitivities of all 14-channels
were found to be within 10%. The noise and threshold
variation was measured to be 7% R.M.S. The crosstalk is
smaller than 1%. The power consumption of about 18mW
per channel is dominated by LVDS driver.
III. THE NEGATIVE POLARITY AMPLIFIER
A. Design
The design of the negative polarity amplifier follows
closely that of the positive one [1]. Figure 2 shows a
simplified schematic. The input stage is a cascode
structure (N1) with a large input transistor that is
followed by a voltage to current converter (N0) and a
current mirror (N2). The mirror feeds the current to the
output stage (N4) and back to the input stage. The output
current is finally converted into voltage that is driven to
the chip pad by an analog buffer. The size of the
transistors N3 and N4 determines the current gain of
about 6.
Figure 2: Simplified schematic of the negative
polarity amplifier.

From CADENCE simulation the bandwidth was
found to be 16MHz and 23MHz for the negative and
positive amplifier, respectively. The input impedance is
below 50Ω within the bandwidth.
B. Measurements
The circuit displays linearity within 1% up to 200fC.
Results of peaking time, sensitivity and noise
measurements vs. detector capacitance, together with
CADENCE simulation, are shown in Figure 3, 4 and 5,.
The fit to the points of figure 5 gives a noise of
ENC=951e-+31e-/pF.
Figure 3: Measured (black dots) and simulated (white
dots) peaking time vs. detector capacitance for the
negative polarity amplifier.
Figure 4: Measured (black dots) and simulated (white
dots) sensitivity vs. detector capacitance for the negative
polarity amplifier.
Figure 5: Measured equivalent noise charge vs. detector
capacitance for the negative polarity amplifier.
C. Design
IV. THE SHAPER
The shaper is a differential amplifier in a folded cascode
configuration with common mode feedback. A simplified
schematic is shown in Figure 6. The shaper is designed
with a speed such that the amplifier peaking time is not
significantly degraded. Therefore the dominant high
frequency pole is located at 160MHz. The 1/t tail
cancellation is performed by a double pole/zero
compensation network [2][3] displayed in Figure 7.
Figure 6: Simplified schematic of the shaper circuit.

Figure 7: Schematic of the pole/zero compensation
network.
D. Measurements
The prototype chip uses two positive polarity amplifiers
followed by the shaper. The differential shaper output
was equipped with two analog buffers and only one of
them was read out during the tests.
Figure 8 and 9 show the measured peaking time
and noise versus detector capacitance for two different
bias currents configurations. For high bias current a noise
performance of ENC=1290e-+40e- is achieved.
The offset ENC is higher than that of the
positive amplifier alone due to the presence of two
amplifiers at the shaper input. The slope is consistent with
that of the positive amplifier chip but higher than that of
the negative amplifier due to the large bandwidth of the
shaper.
Figure 8: Measured (black symbols) and simulated (white
symbols) peaking time of the shaper chip as a function of
detector capacitance for a delta input. The triangles and
dots correspond to two different bias current
configurations.
Figure 9: Measured equivalent noise charge of the shaper
chip as a function of detector capacitance. The triangles
and dots correspond to two different bias current
configurations.
A quasi-1/t current injector, realised with four
parallel RC circuits, was used to simulate a detector
pulse. Figure 10 shows the output pulse from the negative
amplifier and displays a long tail. Figure 11 shows the
output pulse from the shaper with the same time scale of
Figure 10 indicating that the tail is to large extent
suppressed.
Figure 12 shows the peaking time versus detector
capacitance with the 1/t injector.
The pulse width (at 20% amplitude) was found
to be less than 30ns after shaping up to 200pF detector
capacitance.
Figure 10: Output of the negative polarity amplifier for a
1/t current pulse input.

Figure 11: Shaper output for a 1/t current pulse input.
Figure 12: Measured (black dots) and simulated (white
dots) peaking time of the shaper chip as a function of
detector capacitance for a 1/t current pulse input.
V. CONCLUSIONS AND FUTURE PLANS
Four prototype chips of the CARIOCA front-end have
been produced during the last two years. Positive and
negative amplifier and shaper circuits were tested and
their characteristics satisfy the requirements for operation
in LHCb. A final prototype, including a baseline
restoration circuit, will be submitted in November 2001.
The overall goal is to start chip production by the end of
2002.
VI. ACKNOWLEDGEMENT
This work has been partially supported by Conselho
Nacional de Desenvolvimento Científico e Tecnológico
(CNPq-Brazil) and by the European Commission
(contract CT1 * - CT94 - 0118).
VII. REFERENCES
[1] D.Moraes, “CARIOCA – a fast binary front-end
implemented in 0.25um CMOS using a novel currentmode
technique for the LHCb Muon detector”,
presented at LEB2000.
[2] R.A.Boie et al., “Signal shaping and tail cancellation
for gas proportional detectors at high counting rates”,
Nucl. Instr. and Meth. 192 (1982) 365.
[3] M. Newcomer, “Progress in development of the
ASDBLR ASIC for the ATLAS TRT”, presented at
LEB1999.

TTCPR: A PMC Receiver for TTC
John W. Dawson, David J. Francis*, William N. Haberichter,
and James L. Schlereth
Abstract
The TTCPR receiver is a mezzanine card intended for use
in distributing TTC information to Data Acquisition and Trigger
Crates in the ATLAS Prototype Integration activities. An
original prototype run of these ~cards was built for testbeam and
integration studies, implemented in both the PMC and PCI form
factors, using the TTCrx chips from the previous manufacture.
When the new TTCrx chips became available, the TTCPR was
redesigned to take advantage of the availability and enhanced
features of the new TTCRX(1), and a run of 20 PMC cards was
manufactured, and has since been used in integration studies and
the testbeam. The TTCPR uses the AMCC 5933(2) to manage
the PCI port, an Altera 10K30A(3) to provide all the logic so
that the functionality may be easily altered, and provides a 4K
deep FIFO to retain TTC data for subsequent DMA through the
PCI port. In addition to DMA's which are mastered by the Add
On logic, communication through PCI is accomplished via
mailboxes, interrupts, and the pass-through feature of the 5933.
An interface to the I2C bus of the TTCRX is provided so that
internal registers may be accessed, and the card supports
reinitialization of the TTCRX from PCI. Software has been
developed to support operation of the TTCPR under both
LynxOS and Linux.
I. History of the TTCPR
The TTCPR was developed in response to a need for
TTC(4) information in the Data Acquisition from TileCal
Modules in the ATLAS Test Beam. Specifically, it was desired
to have EventID, Bunch Counter, and Trigger Type available
from TTC in the data records. It was useful to have the TTC
information available to processors in the Data Acquisition
crates through PCI ports, and to have the data transferred to the
processor's address space via an externally mastered DMA.
Accordingly, the TTCPR was designed as a mezzanine card in
the PMC form factor. The original cards utilized the older nonradhard
version of the TTCRX, because the new radhard version
was not available at that time.
Argonne National Laboratory, Argonne, IL 60439 USA
jwd@hep.anl.gov, wnh@hep.anl.gov, jls@hep.anl.gov
*CERN, 1211 Geneva 23, Switzerland
David.Francis@cern.ch
When it became clear that the new TTCRX would be
available soon and also that it would not be possible to obtain
any more of the older TTCRX chips, the TTCPR was
redesigned, and enhancements were added to take advantage of
the features of the new TTCRX. This new TTCPR was
produced and has been used successfully in data acquisition at
the ATLAS Test Beam. The card has also been implemented in
the PCI form factor. The TTCPR in the PMC version is shown
in Figures 1 and 2.
Figure 1. View of TTCPR.
II. Architecture of the TTCPR
A block diagram of the TTCPR is shown in Figure 2. The
TTC information is received on a fiber by an optical receiver,
amplified, and passed to the TTCRX. The TTCRX uses an onboard
serial prom for initialization. All external signals
available to the user from the TTCRX are passed to an Altera
10k30A FPGA, which also configures from an on-board serial
prom. The FPGA has the ability to read/write a bank of FIFO
which is 4 bytes wide and 8k deep, and for versatility the FPGA
writes on a 16-bit bus and reads on a 32-bit bus. The interface
to PCI is managed by an AMCC 5933 PCI Controller, and
hardware supports both add-on and pass through transfers, and

supports also add-on bus mastering for DMA's. The hardware
supports also the ability to interact with the TTCRX registers
via the I2C port using passthrough transfers.
Figure 2: Block Diagram TTCPR.
III. Programming for the TTCPR
The TTCPR has the ability to access to all the TTC
information received by the TTCRX. The operation of the
TTCPR is governed by the configuration of the on-board FPGA
and the user can choose any variation desired by configuring the
FPGA. Configuration code for the FPGA is contained in the
serial PROM on the card, and for our applications has been
generated using the Altera MAX+II software package.
Interaction between the host processor and the TTCPR
utilizing the PCI port is through the AMCC 5933 PCI Bridge.
The 5933 is initialized from the serial NVRAM, which must be
programmed once as described in the AMCC 5933 Guide and
contains the PCI vendor and device identification, the
configuration space size and type, and other parameters. Data
transfers through PCI may use the mailbox registers, the 5933
FIFO's, or the pass-through data path. Software to support
operation of the TTCPR in either a polled or interrupt driven
mode has been developed in C++ at Argonne. This software
has thus far been ported to LynxOS on PowerPC platforms, and
to Linux on Intel platforms.
IV. Operation of the TTCPR
Our use of the TTCPR has been to bring TTC information
to the data acquisition system for the TileCal setup in the
ATLAS test beam. In this application the TTCPR initiates data
transfer to a PCI target address specified by the user. The 5933
utilizes Add-on initiated bus mastering to accomplish the
transfer. The user supplies an event threshold count and a PCI
target address which the Add-on logic in the FPGA stores until
the requested number of events has been accumulated in the
FIFO, and then initiates the transfer.
In our application the TTCPR buffers the EventID, BCID,
and trigger type associated with each L1Accept. These results
are made available to the PCI bus when the event threshold
count is reached. Interaction between PCI and the Add-on bus
is mediated by writing and reading the 5933 mailboxes and
registers. Commands such as Reinitialize the TTCRX and Clear
Busy, and data such at the Event Threshold and PCI target
address for the Add-on mastered DMA are passed by mailboxes.
Configuration information and transfer parameters, such as PCI
transfer count and Add-on interrupt source are passed by
registers.
V. Summary
The TTCPR has been developed by the Argonne group and
used to provide TTC information the Data Acquisition system in
the TileCal setup in the ATLAS Test Beam. Our objective was
to develop a module that could have general application in
making available TTC information to processors in the LHC
environment. Accordingly the module has access to all TTC
information passed to the TTCRX, and may be adapted to
transfer any of this information to PCI by reconfiguring the
FPGA.
VI. References
[1]. TTCRX Reference Manual Version 3.2, J. Chrisiansen, A.
Marchioro, P. Moreira, and T. Toifl, CERN-EP/MIC,
February 2001
[2]. AMCC PCI Products Data Book, Applied Micro Circuits
Corporation, San Diego, CA.
[3]. Altera Flex 10K Application Guide.
[4]. http://ttc.web.cern.ch/TTC/intro.html
VII. Acknowledgement
The authors wish to acknowledge the advice and assistance
of Paulo Moreira and Bruce Taylor of CERN.

A PROTOTYPE FAST MULTIPLICITY DISCRIMINATOR
FOR ALICE L0 TRIGGER
Leonid Efimov 1 , Vito Lenti 2 and Orlando Villalobos-Baillie 3 .
FOR THE ALICE COLLABORATION
1 JINR-Dubna, Russia
2 Bari, Italy, Dipartimento di Fisica dell'Università and Sezione INFN
3 Birmingham, United Kingdom, School of Physics and Astronomy, The University of Birmingham
Presented by Vito Lenti
Contact-person: Leonid.Efimov@cern.ch
Abstract
The design details and test results of a prototype
Multiplicity Discriminator (MD) for the ALICE L0
Trigger electronics are presented.
The MD design is aimed at the earliest trigger decision
founded on a fast multiplicity signal cut, in both options
for the ALICE centrality detector: Micro Channel Plates
or Cherenkov counters.
The MD accepts detector signals with an amplitude
range of plus-minus 2.5 V, base duration of 1.8 ns and
rise time of 300-400 ps. The digitally controlled threshold
settings give an accuracy better than 0.4% at the
maximum amplitude of the accepted pulses. The MD
internal latency of 15 ns allows for a decision every LHC
bunch crossing period, even for the 40 MHz of p-p
collisions.
1. INTRODUCTION
A functional scheme for the MD as an element of
ALICE L0 Trigger [1,2] Front-End (F.E.) electronics is
shown in Figure 1, for the proposed MCP based option.
In the scheme shown in the figure [3,4,5], fast passive
summator F.E. electronic units Σ [6], integrated in the
detector, are used for linear summation of isochronous
signals coming from pads belonging to an MCP disk
sector. These signals, whose amplitude is proportional to
the sampled multiplicity, are fed to the MD. The
discriminator produces a multiplicity trigger PTM (Pre-
Trigger on Multiplicity) according to programmable
threshold codes delivered by a Source Interface Unit
(SIU), through the ALICE Detector Data Link (DDL).
Left Detector Disc Right Detector Disc
Fast Sum
Figure 1: General layout of the Multiplicity Discriminator (MD) within ALICE L0 Trigger Front-End
Electronics (TTCR = the LHC Timing, Trigger and Control Receiver; TD = Time Discriminator; TDC = Time to
Digital Converter; QDC = Charge to Digital Converter; PLD = Programmable Logic Device).
PTMi
1 PTTi
2
8
∑
TD
M D
PLD S
hit I DDL
TDC F U
start
I
F
QDC O
T
T
C
R
from TTC

Each i-th FEE card has to produce PTM i in conjunction
with another, time trigger signal PTT i (Pre-Trigger on
Time of Flight) needed to provide a precise time mark for
the measured particles collision time T0. Pipe-line
memories are needed to store the T0 and charge
information, for each MCP sector, at the 40 MHz rate of
the LHC clock.
All MD’s PTM i as well as all PTT i are collected
together, within fast programmable logical units (not
shown), to compare the signals from different sectors and
produce a L0 centrality trigger.
2. THE MD CONCEPTUAL DESIGN
AND SCHEMATICS
The functional scheme for the prototype MD is
presented in Figure 2. The approach used in the MD
design was to implement a leading edge discriminator by
a proper combination of a voltage comparator and a
digital-to-analog converter. Inputs InA and InB for analog
signals with positive and negative polarities have been
foreseen.
InA
UF Voltage Comparator
+ threshold
Figure 2: Functional scheme of the prototype MD.
C1
Input Digital-to-Analog
ECL
PTM
NIM
Code Converter
Shaper
Output
InB
- threshold
UF Voltage Comparator
C2
An Ultra-Fast (UF) ECL-compatible voltage comparator
AD96685BQ from Analog Devices [7] has been selected
as the basic MD component. This comparator has a
typical propagation delay of 2.5 ns and a high precision
differential input stage with a common-mode signal range
from -2.5 V to +5 V,.
To provide the required accuracy for multiplicity
discrimination, within the dynamic range of the fast
preamplifier 0 ÷ ±2.5V, an 8 bit DAC, with control
settings of 10 mV threshold resolution, is sufficient [1].
This DAC, realized on the AD558KD-DACPORT base
[8], delivers an output voltage from 0 to ±2.56V with an
accuracy of ± 1/4 LSB (1LSB = 0.39% of full scale), that
corresponds to 0.1% of the device dynamic range. The
ECL shaper is implemented using a high-speed Motorola
MECL 10KH D-trigger [9] and a series of logical gates
[10] to achieve the correct form and the width of the
output signal needed. The NIM level converter provides a
standard output signal of 16 mA for 50 Ohm load. The
total latency of the PTM trigger output, referred to the
leading edge of fast input signals, is about 15 ns; the
PTM pulse width can be adjusted from a minimum of 10
ns up to 20 ns, using a potentiometer.
Two operational amplifiers from NS [11] provide the
comparator inputs with a differential unbalance of 5÷10
mV, to avoid exciting the circuit with noise under zero
threshold. The prototype MD board is mounted in a
double-width NIM module. Two high frequency 50 Ohm
coaxial BNC-type connectors, isolated from the module
frame with an analog ground, and a miniature LEMO,
with a standard grounded case, are placed on the front
panel for analog inputs and logical output signals
respectively. Two hexadecimal constant register switches,
also mounted on the front panel, allow for the setting of
binary threshold codes.
3. IN-LAB TESTS OF THE MD
PROTOTYPE
Tests were performed on the MD in Bari and Dubna.
The aim of these tests was to study the MD sensitivity to
fast input signals and to obtain a calibration curve for the
MD thresholds. S curves were also performed to evaluate
the width of the MD transition gap near threshold.
A STUDY OF THE MD SENSITIVITY TO INPUT
SIGNALS
It is essential, for a correct use of the MD, to study the
correlation between preset and effective thresholds. In
fact a minimum input signal amplitude Ueff should be
applied in order for the comparator to be triggered at the
preset DAC reference UDAC. It is a known that, when
handling very fast and low-amplitude signals, the shorter
and the smaller the input pulses, the bigger is the
difference between the applied and the effective threshold
values [16]. This circumstance could be explained due to
a certain minimum of effective charge Qeff, which must
be accumulated at the MD input capacity Cin, to reach
UDAC and then to trigger the comparator by some
additional charge Qtr :
Q eff = C in UDAC + Q tr (1) .
Pulses of smaller integrated area require more and
more extra-charge compensation and for the MCP, which
produces signals of almost fixed width, this compensation
can be achieved only by increasing the pulse amplitude.
In order to obtain a calibration curve for the
comparator thresholds and to study the sensitivity of the
MD to input signals, a series of measurements has been
performed using a LeCroy 9211 [12] programmable pulse
generator. The pulse generator time parameters were
chosen and fixed such as to simulate MCP output signals.
So we used the minimum available value of 0.9 ns for
leading and trailing edges (Te), and a pulse width of 2.5
ns base (Tb), at a selected repetition rate of 40 MHz.
The fine and high stabilized tuning of the generated
pulse amplitudes, with 5 mV programmable steps, made
it feasible to investigate effective thresholds precisely
over the full prototype MD linear range. Here we present
some results of these measurements, corresponding to
DAC voltage values in the reduced range 0 to 500 mV,
with 50 mV steps.

In Figure 3 we present, as a function of the DAC
threshold values, the effective voltage thresholds
(squares) obtained and the absolute difference between
effective and DAC voltage thresholds (triangles).
700
600
500
400
300
200
100
0
mV
U eff
Ueff - UDAC
0 50 100 150 200 250 300 350 400 450 500
UDAC , mV
Figure 3: Effective vs. DAC thresholds for 500 mV
sweep of signals with 1.6 ns FWHM and 0.9 ns edges.
The percentage of this difference, with respect to the
DAC values is given in the figure 4, where an increase for
signals of smaller amplitude is clearly observed, going
from 31% needed at 500 mV DAC threshold up to
60% at 50 mV.
(Ueff - UDAC) / UDAC , %
60
50
40
30
20
10
Figure 4: Relative effective over DAC thresholds
prevailing for 500 mV sweep of signals with 1.6 ns
FWHM and 0.9 ns edges.
An estimation of the sensitivity of the electronic
scheme proposed for the MD prototype, would involve a
measurement or calculation of the effective charge Q eff
according to (1). This is hard to perform directly but
can be roughly achieved using the measured data on U eff
and the known time parameters settings of the LeCroy
pulse generator.
In fact, by fitting the LeCroy 9211 output pulses with
an isosceles trapezium-like shape (Figure 5), it is possible
to calculate the full electric charge Qpef carried by every
pulse with amplitude Ueff, time base Tb and equal Te
edges, as an integral of the pulse current ip(t):
T
eff pef ∫0 p
0
0 50 100 150 200 250 300 350 400 450 500
UDAC , mV
b
Q ~ Q = i ( t) dt= ( T − T ) U ( U )/ R
b e eff DAC S
where Rs=150 Ohm is the total equivalent schematics
resistance limiting the current charging Cin .
Ueff
Te
Tb
Te
FWHM = 1.6 ns
Figure 5: Approximate shape of the generated
pulse, indicating the quantities Te = 0.9 ns and Tb =
2.5 ns.
The calculated effective charge values versus DAC
voltage thresholds are shown in Figure 6. The implicit
linear Q(U) dependence is evident from the fit presented
in the figure, corresponding to the analytical expression:
Q = 0.0136U + 0.2557.
Qeff , pC
7
6
5
4
3
2
1
Q = 0.0136 U + 0.2557
0
0 50 100 150 200 250 300 350 400 450 500
UDAC , mV
Figure 6: Effective charge vs. DAC thresholds
for 500 mV sweep of signals with fixed 1.6 ns FWHM
and 0.9 ns equal edges.
A comparison of this formula with the equation (1)
allows some considerations:
- the input capacity C in plays an especially important
role because the lower the C in value, the smaller Q eff is for
a given UDAC and the faster this value can be achieved;
- for our prototype MD C in = 0.0136 pC/mV=13.6 pF,
and, keeping in mind C in= C c+C m, where C c = 2 pF is the
comparator input capacity, a parasitic input capacity of
the MD mounting Cm of 11.6 pF must be considered;
- a Q tr value of about 0.26 pC can be inferred from
(1). This value should be considered as the minimum of
over DAC threshold pulse charge to trigger the scheme,
i.e. the MD sensitivity.
B S CURVES
In order to test the MD performance, S-curves were
produced, at 3 different threshold values, to evaluate the
width of the MD transition gap, near threshold.
Extremely precise, fixed width pulses (3.5 ns FWHM)
were sent simultaneously to the MD and to a reference
LED-type discriminator, set at its minimum threshold
over noise (20 mV). The pulse height of the generated
signal was varied in steps of 2.5 mV.

The results are shown in figure 7. The MD shows a
good threshold accuracy, reaching ≈ 100% efficiency in
short threshold ranges: ≈ 3 mV at 360 mV and less then
10 mV at 1080 mV threshold. These plots give, for all 3
settings, an almost constant ratio of (threshold
359 0
361.5 Counts Ratio 18.8 at 360 mV Threshold Setting
364N / Nmax (%)
93.15
366.5 110
98.55
369 100
100
90
80
70
60
50
40
30
20
10
0
356.5 359 361.5 364 366.5 369 371.5
Input Pulse Amplitude, mV
Figure 7: S curves for 360, 720 and 1080 mV threshold setting.
4. IN-BEAM TESTS OF THE MD
PROTOTYPE
A first test of the prototype MD was performed in the
CERN experimental area PS/T10, with muon beams of
7.5 GeV/c. This test was planned to study he time
resolution and the efficiency of different micro channel
and micro sphere plate-based vacuum sectors for the
ALICE T0 / Centrality detector [13]. Several modules of
fast electronics, including high-speed amplifiers and
discriminators were also tested.
MCP sector
∼5 m
MD
gap/threshold setting) not exceeding 1%, and
uncertainties which are, in any case, smaller then the
minimum setting step (10 mV).
The MD module was plugged in a front-end electronics
rack used for time-of-flight measurements, during 10
runs, in place of specialized fast timing discriminators,
such as Constant Fraction, Double Threshold- [14] and
Pico-Timing [15] - type schemes, at a distance of about
5 m from the tested detectors. The experimental setup
for a single channel of the electronics is shown in Figure
8. Various combinations of new specialized ultra-fast
SMD devices [6] with a different gain, in the range 7÷30,
were tested to search for the best signal/noise ratio. A
LeCroy 2228A TDC of 50 ps LSB was used for Time-to-
Digital conversion.
Figure 8: Experimental arrangement of the prototype MD tests with PS CERN / T10 setup facilities.
.
The experimental aim of this test was two-fold:
The fitted curve of figure 9 reproduces well the shape
a) to simulate a study of multiplicity / centrality versus of a single particle distribution (figure 10), showing the
the prototype MD threshold.
correct operation of the MD with short and fast pulses.
b) to test the timing properties of the prototype MD;
In figure 9 we show an experimental plot giving the
ratio D/Dmax VS different values of relative MD threshold
settings UDAC/UDAC(max) , where D = NTDC-stop/NTDC-start. D / Dmax
1
0.8
0.6
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1
Relative MD threshold setting UDAC / UDAC, max
Figure 9: Relative TDC start/stop counts ratio VS the
MD relative threshold setting.
715 0
717.5 Counts Ratio 9.9at
720 mV Threshold Setting
720
N 722.5 / Nmax (%)
725 110
47.85
79.8
96.7
727.5
100
90
80
70
60
50
40
30
20
10
0
100
712.5 715 717.5 720 722.5 725 727.5 730
Input Pulse Amplitude, mV
Scintillator Counters
Start
delay Stop
1075 0
1077.5 Counts 9.45 Ratio at 1080 mV Threshold Setting
1080 34.15
N / Nmax (%)
1082.5 57.4
1085 110
76.65
1087.5
100
1090
91.9
100
TDC
0
1073 1075 1078 1080 1083 1085 1088 1090 1093
Input Pulse Amplitude, mV
Figure 10: Single and multiparticle distributions
(p-Pb and Pb-Pb)
90
80
70
60
50
40
30
20
10

Another experimental result is presented in figure 11,
where a TDC histogram of 5115 accepted events is
shown. The fit gives a resolution of about 120 ps, a
rather good result for a discriminator not optimized for
timing applications.
Figure 11: Example of events over TDC channels
distributions from the prototype MD tests at CERN
PS (1 TDC channel = 50 ps).
5. CONCLUSIONS
A prototype amplitude discriminator, for the ALICE L0
multiplicity Trigger, has been designed, elaborated and
tested. The discriminator was designed to stand short
nanosecond signals coming from the ALICE
T0/Centrality detector, based on Micro Channel Plates.
Commercially available, inexpensive and fast
components have been used to implement the MD
prototype. It features an input signal range from 0 to
±2.5V, a programmable threshold control with 8 bits
resolution, and an output signal latency of 15 ns.
The minimum input signal charge, to trigger the
comparator over the DAC threshold, has been found in
about 0.26 pC.
Experimental tests of the prototype multiplicity
discriminator, using an MCP-based detector, have been
carried out at the CERN PS beam facilities. While
applying the discriminator for timing in MIPs time-offlight
measurements, a resolution of ~120 ps has been
obtained. The MD was also tested by studying the
response to real MCP signals as a function of the
discriminator threshold.
Further development of the multiplicity discriminator
in terms of schematics and PCB design could still be
made in order to improve parameters and overall
performance, e.g. to reduce input capacity currently
evaluated at 13.6 pF and to integrate the unit with other
elements of the ALICE L0 Trigger electronics.
REFERENCES
1. N.Ahmad et al. ALICE Technical Proposal CERN /
LHCC / 95-71, LHCC / P3,
15 Dec. 1995, chapters 7, 9, 10.
2. H.Beker et al. The ALICE Trigger System.
Proceedings of the Second Workshop on Electronics for
LHC Experiments, Balatonfüred, Sept. 23-27, 1996,
CERN / LHCC / 96-39, 21 October 1996, p. 170-174.
3. L.G.Efimov and O.Villalobos-Ballie. Design
Considerations for Fast Pipelined Front-End Trigger
Electronics.
ALICE / 95-40, Internal Note/ Trigger, Nov.17, 1995.
4. L.G.Efimov et al. Fast ALICE L0 Trigger.
Proceedings of the Second Workshop on Electronics for
LHC Experiments, Balatonfüred, Sept. 23-27, 1996,
CERN / LHCC / 96-39, 21 October 1996, p. 166-169.
5.L.G.Efimov et al. Fast Front-End L0 Trigger
Electronics for ALICE FMD-MCP.
Tests and Performance. Proceedings of the Third
Workshop on Electronics for LHC Experiments,. London,
Sept. 22-26, 1997,
CERN / LHCC / 97-60, 21 October 1997, p. 359-363.
6. A.E.Antropov et al. FMD-MCP Forward Multiplicity
Detector based on MicroChannel Plates.
Preliminary Technical Design Report, ISTC Project #345-
Biennal Report, St.Petersburg State University,
St.Petersburg, Feb.1999
7. http://www.analog.com/pdf/96685_87.pdf
8. http://www.analog.com/pdf/ad558.pdf
9. http://onsemi.com/pub/Collateral/mc10h131rev6.pdf
10. http://onsemi.com/pub/Collateral/mc10h101rev6.pdf
11. http://www.national.com/ds/LF/LF351.pdf
12. http://www.lecroy.com/Archive/TechData/
9200_data/9200.html
13. G.A.Feofilov et al. Results from In-Beam Tests of the
MCP-based Vacuum Sector Prototype for ALICE
T0/Centrality Detector. Proceedings of the Vienna
Conferente on Instrumentation VCI-2001, February 2001
(to be published).
14. C.Neyer. A Discriminator Chip for Time of Flight
Measurements in ALICE.. Proceedings of the Third
Workshop on Electronics for LHC Experiments, London,
Sept. 22-26, 1997,
CERN / LHCC / 97-60, 21 October 1997, p. 238-241.
15. http://www.ortec-online.com/electronics/disc/
9307.htm
16. E.A.Meleshko Nanosekundnaya elektronika v
eksperimentalnoy fizike (in Russian). -
Moscow, Energoatomizdat, 1987, p.57-61.

TIM ( TTC Interface Module ) for ATLAS SCT & PIXEL Read Out Electronics
Jonathan Butterworth ( email : jmb@hep.ucl.ac.uk )
Dominic Hayes [*] ( email : Dominic.Hayes@ra.gsi.gov.uk)
John Lane ( email : jbl@hep.ucl.ac.uk )
Martin Postranecky ( email : mp@hep.ucl.ac.uk )
Matthew Warren ( email : warren@hep.ucl.ac.uk )
University College London, Department of Physics and Astronomy, London, WC1E 6BT, Great Britain
[*] now at Radiocommunication Agency, London, E14 9SX, Great Britain
Abstract
The design, functionality, description of hardware and
firmware and preliminary results of the ROD ( Read Out
Driver ) System Tests of the TIM ( TTC Interface Module )
are described.
The TIM is the standard SCT and PIXEL detector
interface module to the ATLAS Level-1 Trigger, using the
LHC-standard TTC ( Timing, Trigger and Control ) system.
TIM was designed and built during 1999 and 2000 and
two prototypes have been in use since then ( Fig. 1 ). More
modules are being built this year to allow for more tests of the
ROD system at different sites around the world.
Fig. 1 First TIM-0 module
I. INTRODUCTION
The SCT ( or PIXEL ) interface with ATLAS Level 1
receives the signals through the Timing, Trigger, and Control
( TTC ) system [ 1 ] and returns the SCT ( or PIXEL ) Busy
signal to the Central Trigger Processor ( CTP ). It interfaces
with the SCT ( or PIXEL ) off-detector electronics [ 2 ], in
particular with the Read-Out Driver ( ROD ), and is known as
the SCT ( or PIXEL ) TTC system .
The SCT ( or PIXEL ) TTC system consists of the
standard TTC system distributing the signals to a custom TTC
Interface Module ( TIM ) in each crate of RODs.
This paper and the accompanying diagrams describe
some hardware details of the TIM and their functionality. This
paper should be read in conjunction with the original TIM
paper presented in 1999 [ 3 ] and other specification
documents [ 4 ], [ 5 ] , [ 6 ], [ 7 ] and [ 8 ].
A. Functionality
TTC
input
TTC¡ rx
TTC
interface
II. TIM
TIM Functional
Model
JBL/TJF
UCL
7/8/99
7/9/99
External
Trigger Input
Internal
Timing,
Trigger
and
Control
generator
L1ID BC ¢ ID TY £ P ¤ E L1ID BC ¢ L1
ID TYP
� A BC ¢ R ECR CAL
Event
queue
and
serialiser
BC
16
Seria ¦ l ID
Seria ¦ l TT
FE § R
spa
¦ re
CL � K
CL� K
BC
A L1�
R BC¡
R EC¡
CA
� L
R FE�
re spa©
Backplane
mapping
¥
8
¥
8
BC clocks TTC bus
¥
8
TTC
sequencer
VME
commands
¤ E
VME
download
BUSY
mas ¨ ked
OR ROD
Cra© te
16 Busy
ROD Bu� sys
Fig. 2 : TIM Functional Model
The diagram ( Fig. 2 above ) shows the functional model
of the TIM, and illustrates the principal functions of the

current TIM-0 modules :
• To transmit the fast commands and event ID from the
TTC system to the RODs with minimum latency. The
clock is first transmitted to the Back-Of-Crate optocards
( BOC ) , from where it is passed to the RODs
• To pass the masked Busy from the RODs to the CTP in
order to stop it sending triggers
• To generate and send stand-alone clock, fast commands
and event ID to the RODs under control of the local
processor
In addition to these main functions, the TIM has also the
following capabilities :
• The TIM has programmable timing adjustments and
control functions
• The TIM has a VME slave interface to give the local
processor read and write access to its registers [ 9 ]
• The TIM is configured by the local processor setting up
TIM’s registers. They can be inspected by the local
processor
The TTC information, required by the RODs and by the
SCT or PIXEL FE ( Front End ) electronics, is the following :
Clock : BC Bunch Crossing clock
Fast command : L1A Level-1 Accept
ECR Event Counter Reset
BCR Bunch Counter Reset
CAL Calibrate signal
Event ID : L1ID 24-bit Level-1 trigger number
BCID 12-bit Bunch Crossing number
TTID 8-bit Trigger Type ( + 2 spare bits )
The TIM outputs the above information onto the
backplane of a ROD crate with the appropriate timing. The
event ID is transmitted with a serial protocol and so a FIFO
( First In First Out ) buffer is required in case of rapid triggers.
An additional FER ( Front End Reset ) signal, which may
be required by the SCT FE electronics, can also be generated,
either by the SCT-TTC or by the TIM. At present, it is
proposed that FER is carried out by the ECR.
The optical TTC signals are received by a receiver
section containing a standard TTCrx receiver chip, which
decodes the TTC information into electrical form.
The TIM can also generate all the above information
stand-alone at the request of the local processor. It can also be
connected to another TIM for stand-alone multi-crate
operation for system tests in the absence of TTC signals.
The TIM produces a masked OR of the ROD Busy
signals in each crate and outputs the overall crate Busy to a
separate BUSY module. A basic ROD BUSYs monitoring is
also available on TIM. It may be possible to implement more
sophisticated monitoring functionality, on an additional FPGA
device on each TIM, if this proves desirable.
B. Hardware Implementation
The TIM has been designed [ 10 ] as a 9U, single width,
VME64x module, with a standard VME slave interface.
A24/D16 or A32/D16 access is selectable, with the base
address A16 – A23 ( or A16 - A31 ) being either preset as
required, or set by the geographical address of the TIM slot in
each ROD crate. Full geographical addressing ( GA ) and
interrupts ( eg. for clock failure ) are available if required.
On the TIM module, a combination of FastTTL, ECL,
PECL and LV BiCMOS devices is used, requiring +5V, +3V3
and -5V2 ( or +/- 12V to produce this –5V2 ) voltage supplies.
The TTC interface is based on the standard TTCrx
receiver chip, together with the associated PIN diode and
preamplifier developed by the RD12 group at CERN, as
described elsewhere [ 11 ]. This provides the BC clock and all
the signals as listed in section A above. On the TIM modules,
the TTCrx mezzanine test board ( CERN Ref: ECP 680-1102-
630A ) [ 12 ] is used to allow an easy replacement if required.
The latest version utilizes the rad-hard TTCrx3 DMILL
BGA144 version of the receiver chip.
The BC clock destined for the BOCs and RODs, with the
timing adjusted on the TTCrx, is passed via differential PECL
drivers [ 13 ] directly onto the point-to-point parallel
impedance-matched backplane tracks. These are designed to
be of identical length for all the slots in each crate to provide a
synchronised timing marker. All the fast commands are also
clocked directly, without any local delay, onto the backplane
to minimise the TIM latency budget [ 14 ].
Most of the logic circuitry required by TIM is contained
on a number of CPLDs ( Complex Programmable Logic
Device ), with only the programmable delays and the
buffering of the various inputs and outputs being done by
separate integrated circuits. This makes TIM very flexible, as
it allows for possible changes to the functionality by
reconfiguring the firmware of CPLDs, while keeping the
inputs and outputs fixed ( Fig. 3 below ).
This family of devices was chosen during the first design
stage of the prototype TIM modules in 1998 because of
familiarity with their use and capabilities, thus minimizing the
time required for completion of the design. It is proposed to
use VHDL to transfer the design to one or more FPGA
devices for the final production versions of TIM to reduce
costs.
In total, ten of the Lattice ( formerly Vantis / AMD )
Mach4 and Mach5 devices are used on the TIM-0. A
proprietary Vantis / AMD compiler has been used to design
the on-chip circuitry and they are all in-circuit programmable
and erasable using a Lattice software via a fully-buffered J-
TAG interface connected to a PC parallel port. A full,
synchronously-clocked simulation of each CPLD circuit can
be performed to verify the design, and a limited timing
verification is also possible, including a report of all
propagation times through the CPLD.

FRONT PANEL
36 x L� EDS
NIMINPUTS
ECLIN� PUTS
NIMOUTPUTS
ECLOUTPUTS
TT� C
RES� ET
SW
TRIGGER
SW
8�
9�
5�
9�
6
36
3�
8�
9�
6�
5�
3�
TIM - DISCRE� TE VS. PLDS
STAN�
PLD2
D-
ALONE
6�
TTC
rx
Reg� . 0A
SWITCH
DIL�
CLOCK
DEL� AY
1 - 8
Reg� . 08
PLD� 3
STAND-
ALONE
VARIABLE
TRIGGER
OSCILLATOR
ECR / FER
OSCILLATOR
PLD 9
TTC
INTERFACE
PLD7
SEQUENCER
+
SINK
PLD5
SERIALISER
PLD6 MAPPING
MP/TJF UCL 03
�
September 2001
SEQ.
RAM
SINK
RAM
FIFO
ID�
TT
FIFO
PLD4A
L1ID
BCI�
PLD4B
D +
TTID
Fig. 3 CPLDs versus Discrete Components
Fig. 4 CPLDs Arrangement on TIM-0
1�
9�
PLD8
PLD1
VME
INTERFACE
8�
BUSY
ROD�
8 x
F / F
8 x
F / F
BACKP� LANE
9 x P� ECL
CLOCK O� UTPUTS
16
16
8�
8�
16
8 x P� ECL
16
D (0� -15)
VM� E
31
31 A (1-31)
TTC(0-7)A
TTC(0-7)B

The CPLD devices used on TIM-0 ( Fig. 4 above ) and their
allocation to the individual functional blocks [ 15 ] are shown
below, together with the percentages of their I/O pins
( including 4x8-bit spare buses ) and macrocells utilization :
Main Function Device I/O pins Macrocells
PLD1 VME Interface M5-384/184-7HC 88 18
PLD2 Stand-alone A M5-512/256-7AC 59 70
PLD3 Stand-alone B M5-384/184-7HC 64 38
PLD4a L1ID M5-384/184-7HC 61 21
PLD4b BCID & TTID M5-384/184-7HC 67 23
PLD5 Serialiser & FiFos M5-384/184-7HC 79 29
PLD6 Output Mapping M4-256/128-7YC 88 23
PLD7 Sequencer & Sink M5-384/184-7HC 85 46
PLD8 ROD Busy M5-384/184-7HC 57 15
PLD9 TTC Interface M5-384/184-7HC 84 27
It can be seen that, apart from PLD-2, all devices use less
than 50% of their macrocell capacity, and thus are easily
reprogrammable. The PLD-2 circuit has been well tested on
CLOAC modules [ 16 ] and is not likely to require any
significant change.
As mentioned before, the TIM uses the TTC information
in the “Run” mode, or can operate stand-alone in the “SA”
( Stand Alone ) mode. Detailed flowcharts [ 17 ] show the
differences of the sources and of the flow of the fast
commands [ 18 ] and event ID information between the
NIMEX� TCLK
TCLK1
ECLEX�
TCLK2
ECLEX�
80
Z
XTAL
MH�
CLK� 0B
CLK� 0C
1�
1�
2�
CL� K0 INTC� LK2
4 x TRIGGER
WINDOW
DELAYS
INTC� LK1
TCLK
ENEX�
ENINTCLK
SYN� CH
TRIG D� ELAY
TIM - CLOCKS FLOW AND DELAYS
TRIG. W� INDOW
PLD3
PLD� 4B
PLD� 4A
PL� D6
PL� D5
PLD7
PLD8
PLD9
VME
Reg. 0A
DL� 8 DL7 DL� 6 DL� 5
DEL� SIZE AY
R� VME eg.
SW� 8 SW� 5
08
CLK3
4(A) CLK�
4(B) CLK�
K5 CL�
K6 CL�
7(B)
CLK� 7(A)
CLK�
K8 CL�
K9 CL�
Fig. 5 :
CLK� IN
CLK2� (A)
CLK2� (B)
SACLKLED
1�
TRIG� GER
2�
2�
2�
2�
2�
2�
3�
2�
2�
3�
CLKINB1
SACLKDELAY
various CPLDs on TIM, finally producing the same output to
the RODs via the backplane.
Another diagram ( Fig. 5 below ) shows the flow, the
distribution and the programmable delays of the clocks in both
the “Run” and the “SA” modes.
It is important to note that in the “Run” mode [ 19 ] the
priority is given to passing the BC clock and commands to the
RODs, in their correct timing relationship, with the absolute
minimum of delay to reduce the latency.
In the “SA” mode, both the clock and the commands can
arrive from a variety of sources [ 20 ]. The clock can be either
generated on-board using an 80.16 MHz crystal oscillator, or
arrive from external sources in either NIM or differential ECL
standards. Similarly, the fast commands can be generated on
the command of the local processor, or automatically by the
TIM under local processor control. The fast commands can
also be input from external sources in either NIM or
differential ECL [ 21 ]. Thus, any of these internally or
externally generated commands must be synchronised to
whichever clock is being used at the time, to provide the
correctly timed outputs.
In addition, a ‘sequencer’, using 8x32k RAM, is
provided to allow long sequences of commands and serial ID
data to be written in by the local processor and used for
KLED
BCCL�
SAMODE RUN
MODE
DL� 1
6� 5�
6�
DL� 2
DL3
DL� 4
3� DL4O� UT
5�
4� CLKINBC
4�
4�
4�
BCCL� K1B
K2B
BCCL�
PCL� KB
2 SW�
DL2OUT
6�
6�
6�
4�
4�
CLKINB3
SW� 3
SETUP
ROD�
DL2O� UTB TTCC� LKB
SAMODE
DL3O� UT
TTC
SETUP
RUNM� ODE
CLKINB4
MP/TJF UCL 2� 4 August 2001
4�
4�
4 SW� TIM
SETUP
Clocks Flow and Delays
CLOC� K40
0DES1
CLOCK4�
0DES2
CLOCK4�
TTC� rx
TTL - PECL PECL DRIVERS
x� 8
F / F
8 x
F / F
KOUT
NIMCL�
ECLCLKOUT1
ECLCLKOUT2
8� TTC(0-7)
8� TTC(0-7)B
9 x
CLOCK40
8 x
CLOCK40

testing the FE and off-detector electronics. A ‘sink’ ( receiver
RAM ) of the same size is also provided to facilitate off-line
checking of commands and ID data sent to the RODs [ 22 ].
All the backplane signals are also mirrored as differential
ECL outputs on the front panel to allow TIM interconnection.
Two prototype TIM-0 modules were designed and
manufactured during 1999 - 2000 and have been continuously
tested since then, in the stand-alone mode, first at UCL and
later also at Cambridge. During May and June 2001, a TIM-0
module was used in the first SCT ROD system test at
Cambridge. Meanwhile, the TTC interface has also been
tested at UCL using a TTC optical test system incorporating
TTCvi and TTCvx modules [ 1 ] .
III. SYSTEM TEST
The SCT off-detector electronics is based on 9U-sized
modules in a VME64x crate [ 23 ]. There will be one TIM,
one RCC ( Rod Crate Controller ) and up to 16 RODs and
BOC modules in each ROD crate. Samples of the purposedesigned
ROD crates have been manufactured by Wiener.
They have been equipped with the custom-designed J3
backplane [ 24 ] providing the complex inter-connection
between TIM and the RODs and BOCs [ 25 ].
The first ROD system test using prototype RCC,
ROD, BOC and TIM modules took place in Cambridge in
May and June 2001. This demonstrated successfully the
feasibility of the whole system design and showed that TIM
does correctly source and drive all the timing, trigger and
command information to the RODs and BOCs. The timing and
signal error rates have also been checked using the stand-alone
capabilities of the TIM.
Based on the results of this first system test, two
more updated TIM-1 modules have been built and are now
starting to be tested at UCL. Together, these four TIM
prototype modules will enable further ROD system tests to
take place later this year in Cambridge and in USA, to be
followed by the first system and beam tests at CERN in 2002.
Currently, the design of the final, production version of the
TIM is beginning at UCL with the aim of starting the
manufacture in the second half of 2002.
IV. ACKNOWLEDGEMENTS
We would like to thank Professor Tegid W. Jones for
his continuous support of our work in the ATLAS
collaboration. We also wish to thank Janet Fraser who helped
to produce the diagrams used in this paper.
V. REFERENCES
[ 1 ] TTC Home Page :
http://ttc.web.cern.ch/TTC/intro.html
[ 2 ] SCT Off-Detector Electronics Schematics :
http://www.hep.ucl.ac.uk/~jbl/SCT/archive/SCT_system_UCI.pdf
[ 3 ] TIM and CLOAC – LEB1999 Paper :
http://www.hep.ucl.ac.uk/~mp/TIM+CLOAC_paper1.pdf
[ 4 ] TIM Overview :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_overview.html
[ 5 ] TIM Functional Requirements :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_requirements.html
[ 6 ] TIM-BOC Interface Specification :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_interface_BOC.html
[ 7 ] TIM-ROD Interface Specification :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_interface_ROD.html
[ 8 ] TIM-RCC Interface Specification :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_interface_RCC.html
[ 9 ] TIM Registers :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_registers.html
[ 10 ] TIM Implementation Model :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_model.html
[ 11 ] J. Christiansen, A. Marchioro, P. Moreira, T.Toifl
“TTCrx Reference Manual : A Timing , Trigger and
Control Distribution Receiver ASIC for LHC
Detectors”, Version 3.2, February 2001
http:// http://ttc.web.cern.ch/TTC/TTCrx_manual3.2.pdf
[ 12 ] TTCrx Mezzanine Board Schematics :
http://ttc.web.cern.ch/TTC/TTCrxMezzanine2001.04.19.pdf
[ 13 ] TIM Backplane Interfaces :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_backplane.pdf
[ 14 ] SCT Latency Budget :
http://www.hep.ucl.ac.uk/~jbl/SCT/SCT_latency.html
[ 15 ] TIM CPLDs Block Diagrams :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_plds.pdf
[ 16 ] CLOAC Module Description :
http://www.hep.ucl.ac.uk/~jbl/SCT/CLOAC_welcome.html
[ 17 ] TIM Overall Block diagrams :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_flowcharts.pdf
[ 18 ] TIM Fast Commands Flow :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_fast-flow.pdf
[ 19 ] TIM Schematics -2- INTERFACES :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_schem-2.pdf
[ 20 ] TIM Schematics -1- STAND-ALONE :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_schem-1.pdf
[ 21 ] TIM Front Panel Interfaces :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_front-panel.pdf
[ 22 ] TIM Schematics -3- SEQUENCER
& STAND-ALONE ID & ROD BUSY :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_schem-3.pdf
[ 23 ] LHC Crates :
http://atlas.web.cern.ch/Atlas/GROUPS/FRONTEND/documents/
LHC_Crates_TS11.PDF
[ 24 ] ROD Crate J3 Backplane Design :
http://webnt.physics.ox.ac.uk/wastie/backplane.htm
[ 25 ] ROD Crate Backplane Interconnections :
http://www-wisconsin.cern.ch/~atlas/off-detector/ROD/doc/
2000-07-27-RODCrateBPSlot.doc
VI. FIGURES
Fig. 1 First TIM-0 Module :
http://www.hep.ucl.ac.uk/~mp/TIM-0_photo-4.jpg
Fig. 2 TIM Functional Model :
http://www.hep.ucl.ac.uk/~mp/TIM_Functional_model.eps.gz
Fig. 3 CPLDs versus Discrete Components :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_PLDs-vs-ICs.pdf
Fig. 4 CPLDs Arrangement on TIM-0 :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_func_pic.jpg
Fig. 5 Clocks Flow and Delays :
http://www.hep.ucl.ac.uk/atlas/sct/tim/TIM_clocks.pdf

Abstract
In this paper we describe the LHCb Timing and Fast
Control (TFC) system. It is different from that of the other
LHC experiments in that it has to support two levels of highrate
triggers. Furthermore, emphasis has been put on
partitioning and on locating the TFC mastership in one type of
module: the Readout Supervisor. The Readout Supervisor
handles all timing, trigger, and control command distribution.
It generates auto-triggers as well as controls the trigger rates.
Partitioning is handled by a programmable patch
panel/switch introduced in the TTC distribution network
between a pool of Readout Supervisors and the Front-End
electronics.
I. INTRODUCTION
LHCb has devised a Timing and Fast Control (TFC)
system[1] to distribute information that must arrive
synchronously at various places in the experiment. Examples
of this kind of information are:
• LHC clock
• Trigger decisions
• Reset and synchronization commands
• Bunch crossing number and event number
Although the backbone of the timing, trigger and control
distribution network is based on the CERN RD12 system
(TTC)[2], several components are specific to the LHCb
experiment due to the fact that the readout system is different
from that of the other experiments in several respects. Firstly,
the LHCb TFC system has to handle two levels of high-rate
triggers: a Level 0 (L0) trigger with an accept rate of
maximum 1.1 MHz and a Level 1 (L1) trigger with an accept
rate of maximum 40 - 100 kHz. This feature reflects itself in
the architecture of the Front-End electronics, which consists
of a L0 part and a L1 part (see Figure 1). The L0 Front-End
(FE) electronics samples the signals from the detector at a rate
of 40 MHz and stores them during the duration of the L0
trigger processing. The event data are subsequently de-
The LHCb Timing and Fast Control system
R. Jacobsson, B. Jost
CERN, 1211 Geneva 23, Switzerland
Richard.Jacobsson@cern.ch, Beat.Jost@cern.ch
A. Chlopik, Z. Guzik
Soltan Institute for Nuclear Studies, Swierk-Otwock, Poland
arek@ipj.gov.pl, zbig@ipj.gov.pl
randomized before being handed over to the L1 FE
electronics. The L1 FE electronics buffers the data during the
L1 trigger processing, de-randomizes the events before it
zero-suppresses the data, and finally feds the data into the
DAQ system for event building.
Secondly, the TFC architecture has been designed with
emphasis on partitioning[3]. A partition is in LHCb a generic
term, defined as a configurable ensemble of parts of a subdetector,
an entire sub-detector or a combination of subdetectors
that can be run in parallel, independently and with a
different timing, trigger and control configuration than any
other partition.
Furthermore, the aim has been to locate the entire TFC
mastership of a partition in a single module. The trigger
decision units are also considered as sub-detectors.
Level 0
Trigger
Level 1
Trigger
40 MHz
1 MHz
Timing
&
L0
40 kHz
Fast
L1
Control
1 MHz
Throttle
Variable latency
L2 ~10 ms
L3 ~200 ms Storage
LHC-B Detector
VDET TRACK ECAL HCAL MUON RICH
RU RU RU
CPU
CPU
CPU
CPU
Level-0
Front-End Electronics
Level-1
Front-End Multiplexers (FEM)
Front End Links
Read-out units (RU)
Read-out Network (RN)
SFC SFC Sub-Farm Controllers (SFC)
Trigge r Level 2 & 3
Event Filter
Figure 1: Overview of the LHCb readout system.
II. USE OF THE TTC SYSTEM
LAN
Data
rates
40 TB/s
1 TB/s
6-15 GB/s
6-15 GB/s
Control 50 MB/s
&
Monitoring
The TTC system has been found to suite well the LHCb
application. The LHC clock is transmitted to all destinations
using the TTC system and Channel A is used as it was
intended, i.e. to transmit the LHCb L0 trigger decisions to the
FE electronics in the form of a accept/reject signal at 40 MHz.

Channel B supports several functions:
• Transmission of the Bunch Counter and the
Event Counter Reset (BCR/ECR).
• Transmission of the L1 trigger decision (~1.1
MHz).
• Transmission of Front-End control commands,
e.g. electronics resets, calibration pulse triggering
etc.
Table 1: Encoding of the Channel B broadcasts. “R” stands for
reserve bit.
7 6 5 4 3 2 1 0
L1 Trigger 1 Trigger type EventID 0 0
Reset 0 1 R
L1
EvID
L1
FE
L0
FE
ECR BCR
Calibration 0 0 0 1 Pulse type 0 0
Command 0 0 R R R R R R
The information is transmitted in the form of the short
broadcast format[4], i.e. 16 bits out of which two bits are
dedicated to the BCR/ECR and six bits are user defined.
From the TTC bandwidth it follows that a maximum of
Local trigger
(optiona l)
L0
L1
Readout
Supervisor
L0 Throttle
switch
LHC clock
Clock fanout
BC and BCR
TTCrx TTCrx
L0 trigger L1 trigger
L0
Readout
Supervisor
~2.5 MHz of broadcasts can be transmitted. The eight bits are
encoded according to Table 1. A priority scheme determines
the order in which the different broadcasts are transmitted in
case they clash.
III. TFC COMPONENTS SPECIFIC TO LHCB
The TFC architecture is shown in Figure 2. It incorporates
a pool of TFC masters, Readout Supervisors[5], one of which
is interfaced to the central trigger decision units and that is
used for normal data taking. The other Readout Supervisors
are reserves and can be invoked for tests, calibrations and
debugging. The reserve Readout Supervisors also allow
connecting local trigger units.
The TFC Switch[6] distributes the TTC information to the
Front-End electronics and the Throttle Switches[6] feed back
hardware throttle signals from the L1 trigger system, the L1
de-randomizers and components in the data-driven part of the
DAQ system, to the appropriate Readout Supervisors.
The Throttle ORs[6] form a logical OR of the throttle
signals from sets of Front-End electronics.
A GPS system allows time-stamping the local event
information sampled in the Readout Supervisor.
L1
TFC switch
TTCrx
TTCrx
L0E L0E
ADC
TTCrx ADC
TTCrx
ADC ADC
Control
Contr ol
L1E
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FEchip
FEchip FEchip
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hip
r
ADC ADC DSP ADC DSP
L1 Throttle
switch
Readout
Sup er visor
SD1 TTCtx SD2 TTCtx SDn TTCtx L0 TTCtx L1 TTCtx
Optical couplers Optica l co uplers Optica l coup lers Optical couplers
TTCrx
TTCrx
L0E L0E
ADC
TTCrx ADC
TTCrx
ADC
ADC
Control
Contr ol
L1E
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L1 trig ger sy stem
FEc FEc
hip
FEchip
hip
FEc
hip
FEchip hip
FEchip
FEc
FEc
hip
L1 FEchip buffer hip
L1 FEchip buffer
ADC ADC DSP ADC DSP
Throttle OR
D AQ DAQ
Figure 2: Overview of the TFC architecture.
17
17
GPS receiver
Throttle OR
TTC system

IV. THE READOUT SUPERVISOR
The Readout Supervisor has been designed with emphasis
on versatility in order to support many different types of
running mode, and modifiability for functions to be added and
changed easily. Below is a summary of the most important
functions. A complete description can be found in Reference
[5].
The TTC encoder circuit incorporated in each Readout
Supervisor receives directly the LHC clock and the orbit
signal from the TTC machine interface (TTCmi). The clock is
distributed on the board in a star fashion and is transmitted to
all synchronous destinations via the TTC system.
The Readout Supervisor receives the L0 trigger decision
from the central L0 trigger Decision Unit (L0DU), or from an
optional local trigger unit, together with the Bunch Crossing
ID. In order to adjust the global latency of the entire L0
trigger path to a total of 160 cycles, the Readout Supervisor
has a pipeline of programmable length at the input of the L0
trigger. Provided no other changes are made to the system, the
depth of the pipeline is set once and for all during the
commissioning with the first timing alignment. The Bunch
Crossing ID received from the L0DU is compared to the
expected value from an internal counter in order to verify that
the L0DU is synchronized. For each L0 trigger accept, the
source of the trigger (3-bit encoded) together with a 2-bit
Bunch Crossing ID, a 12-bit L0 Event ID (number of L0
triggers accepted), and a “force bit” is stored in a FIFO. The
force bit indicates that the trigger has been forced and that
consequently the L1 trigger decision should be made positive,
irrespective of the decision of the central L1 trigger Decision
Unit (L1DU). The information in the FIFO is read out at the
arrival of the corresponding L1 trigger decisions from the
L1DU.
The RS receives the L1 trigger decision together with a 2bit
Bunch Crossing ID and a 12-bit L0 Event ID. The two
incoming IDs are compared with the IDs stored in the FIFO in
order to verify that the L1DU is synchronized. If the force bit
is set the decision is converted to positive. The 3-bit trigger
type and two bits of the L0 Event ID is subsequently
transmitted as a short broadcast according to the format in
Table 1. In order to space the L1 trigger decision broadcasts a
L1 de-randomizer buffer has been introduced.
The Readout Supervisor controls the trigger rates
according to the status of the buffers in the system in order to
prevent overflows. As the distance and the high trigger rate,
the L0 de-randomizer buffer occupancy cannot be controlled
in a direct way. However, as the buffer activity is completely
deterministic, the RS has a finite state machine to emulate the
occupancy. This is also the case for the L1 buffer. In case an
overflow is imminent the RS throttles the trigger, which in
reality is achieved by converting trigger accepts into rejects.
The slower buffers and the event-building components feed
back throttle signals via hardware to the RS. Data congestion
at the level of the L2/L3 farm is signalled via the Experiment
Control System (ECS) to the onboard ECS interface, which
can also throttle the triggers. “Stopping data taking” via the
ECS is carried out in the same way. For monitoring and
debugging, the RS has history buffers that log all changes on
the throttle lines.
The RS also provides several means for auto-triggering. It
incorporates two independent uniform pseudo-random
generators to generate L0 and L1 triggers according to a
Poisson distribution. The RS also has a unit running several
finite state machines synchronized to the orbit signal for
periodic triggering, periodic triggering of a given number of
consecutive bunch crossings (timing alignment), triggering at
a programmable time after sending a command to fire a
calibration pulse, triggering at a given time on command via
the ECS interface etc. The source of the trigger is encoded in
the 3-bit L1 trigger qualifier.
The RS also has the task of transmitting various reset
commands. For this purpose the RS has a unit running several
finite state machine, also synchronized to the orbit signal, for
transmitting Bunch Counter Resets, Event Counter Resets, L0
FE electronics reset, L1 + L0 electronics reset, L1 Event ID
resets etc. The RS can be programmed to send the commands
regularly or solely on command via the ECS interface. The
Bunch Counter and the Event Counter Reset have highest
priority. Any clashing broadcast is postponed until the first
broadcast is ready (L1 trigger broadcast) or until the next
LHC orbit (reset, calibration pulse, and all miscellanous
commands).
The RS keeps a large set of counters that record its
performance and the performance of the experiment (deadtime
etc.). In order to get a consistent picture of the status of
the system, all counters are samples simultaneously in
temporary buffers waiting to be read out via the onboard ECS
interface.
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Figure 3: Simplified logical diagram of the Readout Supervisor
showing the basic functions.
The RS also incorporates a series of buffers analogous to a
normal Front-End chain to record local event information and
provide the DAQ system with the data on an event-by-event
basis. The “RS data block” contains the “true” bunch crossing
ID and the Event Number, and is merged with the other event
data fragments during the event building.

The ECS interface is a Credit Card PC through which the
entire RS is programmed, configured, controlled, and
monitored. Note that in order to change the trigger and control
mode of the RS for testing, calibrating and debugging it is not
necessary to reprogram any of the FPGAs. All functionality is
set up and activated via parameters that can be written at any
time.
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Figure 4: The TFC architecture simplified to show an example of
partitioning.
A. The TFC Switch and Partitioning
A good partitioning scheme is essential in order to carry
out efficient commissioning, testing, debugging, and
calibrations. The LHCb TFC partitioning is shown by an
example in figure 4, in which the TFC architecture in Figure 2
has been simplified. The TFC Switch allows setting up a
partition by associating a number of partition elements (e.g.
sub-detectors) to a specific Readout Supervisor (Figure 5).
The Readout Supervisor can then be configured to control and
trigger the partition in whatever specific mode that is
required. In the example in figure 4, the partition elements 2 –
5 are running with the central RS, which is interfaced to the
central triggers. Partition element 1 is simultaneously running
a stand-alone run with a separate RS. The three other Readout
Supervisors are idle and can be reserved at any time for other
partitions. Note that the TFC Switch is located before the TTC
optical transmitters (TTCtx) and that it is handling the
encoded TTC signals electrically.
The configuring of the TFC Switch is done via the
standard LHCb ECS interface incorporated onboard: the
Credit Card PC.
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Figure 5: The principle of the TFC Switch.
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From the architecture of the system it follows that the FE
electronics that is fed by the same TTCtx is receiving the
same timing, trigger, and control information. Hence the
TTCtx define the partition elements. The TFC Switch has
been designed as a 16x16 switch and thus allows the LHCb
detector to be divided into 16 partition elements. To increase
the partition granularity an option exists whereby four TFC
Switches are deployed in order to divide the LHCb detector
into 32 partitions (Figure 6).
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Figure 6: Four TFC Switches put together to increase the partition
granularity to 32.
A crucial point concerning the TFC Switch is that all
internal paths from input to output must have equal
propagation delays. Otherwise, the partition elements will
suffer from timing alignment problems using different
Readout Supervisors. Measurements performed on the first
prototype of the TFC Switch shows that it will be necessary to
add adjustable delays at the outputs due to strongly varying
propagation delays in the 16:1 multiplexers used.
B. The Throttle Switches and the Throttle ORs
The function of the Throttle Switches is to feed back the
throttle information to the appropriate Readout Supervisor,
such that only the Readout Supervisor in control of a partition
is throttled by the components within that partition. Figure 4
shows an example of how they are associated. The logical
operation of the Throttle Switch is to perform a logical OR of
the inputs from the components belonging to the partition
(Figure 7). The system incorporates two Throttle Switches, a
L0 and a L1 Throttle Switch. The sources of L0 throttles are
essentially the components that feed the L1 trigger system.
The sources of L1 throttles are the L1 de-randomizers and the
event building components.
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Figure 7: The principle of the Throttle Switches.
For monitoring and debugging, the Throttle Switches keep
a log of the history of the throttles. A transition on any of the
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throttle lines trigger the state of all throttle lines together with
a time-stamp to be stored in a FIFO.
The configuring and the monitoring of the Throttle
Switches are done via the standard LHCb ECS interface.
The Throttle ORs group throttle lines belonging to the
same partition elements. They are identical to the Throttle
Switches in all aspects except that they OR all inputs and have
only one output.
VI. CONCLUSIONS
The LHCb Timing and Fast Control (TFC) system and the
use of the TTC system are well established. The Readout
Supervisor incorporates all mastership in a single module and
it provides a lot of flexibility and versatility. Partitioning is
well integrated through the TFC Switch and the Throttle
Switches.
The architecture and the components have been put
through two reviews and the system is now in the prototyping
phase.
V. REFERENCES
[1] R. Jacobsson and B. Jost, “The LHCb Timing and Fast
Control system”, LHCb 2001-016 DAQ.
[2] RD-12 Documentation on WWW
(http://www/cern.ch/TTC/intro.html) and references
therein.
[3] C. Gaspar, R. Jacobsson, B. Jost, “Partitioning in
LHCb”, LHCb 2001-116 DAQ.
[4] B. Jost, “The TTC Broadcast Format (proposal)”,
LHCb 2001-017 DAQ.
[5] R.Jacobsson, B. Jost, Z. Guzik, “Readout Supervisor
Design Specifications”, LHCb 2001-012 DAQ.
[6] Z. Guzik, Richard Jacobsson, and B. Jost, “The TFC
Switch specifications”, LHCb 2001-018 DAQ.

Implementation Issues of the LHCb Readout Supervisor
Z.Guzik, A.Chlopik
Soltan Institute for Nuclear Studies, 05-400 Swierk-Otwock, Poland
Zbig@ipj.gov.pl, Arek@ipj.gov.pl
Abstract
In this paper we describe the architecture of the most
crucial and sophisticated element of the LHCb Timing and
Fast Control (TFC) System - the Readout Supervisor (RS).
The multi-functionality, the complexity and the speed
demands dictate usage of the most advanced and performant
technological solutions. The logical part of the Readout
Supervisor is therefore based on the fastest PLDs on the
market i.e. the Altera MAX and FLEX devices working on
2.5V. There are 12 such units implemented where each unit
carry separate logical functions. The front-end logic of the
module is designed with positive ECLinPS Lite ICs. The
Experiment Control System (ECS) interface to the Readout
Supervisor is based on a commercial Credit Card PC from
Digital Logic AG.
I. INTRODUCTION
The Readout Supervisor is a central component in the
LHCb Timing and Fast Control (TFC) system. The functional
specifications and the detailed description of all the Readout
Supervisor tasks, features and nodes have been covered in
document [1].
The current implementations of the first minimal version
of the Readout Supervisor is covered in a separate document
[2]. There are a few minor differences between the actual
implementation described in [2] and the one proposed in the
Readout Supervisor Design Specification [1]. Therefore, the
final assignments and resource allocations are only valid as
presented in [2].
II. DESIGN CRITERIA
During designing and implementation process following
design criteria were obeyed:
• Modular approach to logical design - entire RS design
divided into logically consistent nodes (entities) which
are programmed on separate PLD’s. Logical connections
between modules have fully pipelined structure.
• The current prototype version of Readout Supervisor is
implemented with a FASTBUS board form factor; only
and
R.Jacobsson,
CERN, 1211 Geneva 23, Switzerland
Richard.Jacobsson@cern.ch
one external +5V power supply is used, either via the
FASTBUS connector or from an on-board special IBM-
PC type connector. The latter means that a FASTBUS
power–supply/crate is not necessary. On-board DC/DC
converters from DATEL provide the three additional
voltages: +3.3 V (7 A), +2.5 V (5A) and -5V (2A).
• Interfaces concerning external trigger data are based on
LVDS technology. The National DS90C402 chip was selected
as a dual receiver, while DS90C401 chip was
chosen as a dual LVDS driver.
• All discrete fast logic (clock regeneration and TTC
encoder) will be realized with MOTOROLA ECLinPS or
ECLinPS Lite integrated circuits from the 100E, 100EL
or 100ELT series.
• The TTC encoder (Channel A and Channel B time
division multiplexor for broadcasting L0, L1 triggers and
commands) is based - with slight modifications – on the
TTCvx module by Per Gällnö. Also TTCex design from
Bruce Taylor is taken into consideration as an alternate
mezzanine. TTC encoder together with clock PLL
regeneration is located on separate mezzanine board
• All Readout Supervisor functional logic will be
performed by Altera MAX 7000AE (for the most time
critical parts) and FLEX 10KE PLD devices. All of the
used PLDs (except PLD constituting IOBUS) have the
same 144-pin count. For easy debugging and to facilitate
connecting a Logic State Analyzer, all PLD’s will be
placed on separate Mezzanine sub-boards with 100 mils
pin spacing.
• All PLD's are working with 3.3 V power supply for
input-output (VCCINT). The in-core PLD logic
(VCCINT) for MAX devices is the +3.3 V and for FLEX
devises is the +2.5V. The speed grades of the selected
PLDs must not be worse than “5” for the MAX devices
and “1” for the FLEX devices. Configuration and
programming of all PLD’s is organized by means of
programmable JTAG chain.
• All the implemented FIFO’s are the CY7C4251 from
Cypress. They are 8Kx9 synchronous devices with 10 ns
access time and 3 ns setup time.

• MAX+plus II and AHDL were chosen as the PLD design
environment for all modules except for the random trigger
generator module. In the future the aim is to translate
all designs into VHDL. The PLD designs are simulated in
MAX+plus, as well as in Cadence using test benches in
VHDL.
• The schematics and the PCB layout are done with the
help of the Protel Design Explorer 99 SE software with
Service Pack 6.
• The Readout Supervisor is controlled by Commercial
Credit Card PC via Ethernet Link. Interfacing with its
Ext. L0 throttles
- L0 trigger inhibits (Q_T1B)
- Buffer emulators (Q_T1B)
Ext. JTAG
ECS JTAG
ECS PLX bus
- L0 random trigger (Q_RNDM)
- L1 random trigger (Q_RNDM
- State machine triggers (Q_CMD)
Count enables from RS logic
- Counters (Q_CNT)
- JTAG interface (Q_IOI)
- IOBUS interface (Q_IOI)
- General Configuration
Register (Q_IOI)
Local JTAG ro RS logic
IOBUS to RS logic
L0 Trigger decision unit
- L0 Pipeline (Q_PIPE)
- Strobe check (Q_PIPE)
- L0 trigger handling (Q_L0)
- Synchronization check (Q_L0)
- L0 counters (Q_L0)
PCI bus is organized with help of PLX PCI 9080
accelerator chip forming local bus.
• There is no single jumper on the Readout Supervisor
Board.
A schematic block diagram of the entire Readout Supervisor
is presented in Figure 1.
L0 Accept FIFO
(AFIFO)
- Command generator (Q_CMD)
- Reset (internal) generator (Q_CMD)
Resets to int. logic
TTC encoder
Channel A/B
- Generic Command Sender (Q_GCS)
- TTC Shifter (Q_GCS)
- General CSR (Q_GCS)
Figure 1: Block Diagram of the Readout Supervisor
L1 Trigger decision unit
- L1 trigger handling(Q_L1)
- Synchronization check (Q_L1)
- L1 counters (Q_L!)
L1 Trigger De-random.
(TFIFO)
Ext. L1 throttle
- L1 trigger inhibits (Q_T1B)
- Trigger brdcst generator (Q_T1B)

III. ECS INTERFACE
The Experiment Control System (ECS) interface to the
Readout Supervisor and its associated logic is presented in
Fig.2 below.
The ECS interface is based on a commercial Credit Card
PC (CC-PC) from Digital Logic AG. Its access to the onboard
logic is provided by means of smart480BUS consisting
of 480 pins. The smart480BUS resources include a PCI bus.
This is the basic medium to exchange information between
the CC-PC and the Readout Supervisor logic. In between the
CC-PC and the Readout Supervisor, there is an intermediate
interface, the so-called “Glue Board”, which contains a
PCI 9080 chip from PLX Technology. The PCI 9080is a PCIto-Local
Bus accelerator chip working in J-mode (multiplexed
a/d mode). The CC-PC is accessed externally via an
ETHERNET LAN and, optionally, via a serial RS-232 link.
CC-PC
Ethernet
Serial
Port
Parallel
Port
PCI Bus
USERo
USERi
LRESETi#
RST#
GLUE BOARD
PCI 9080
PLX chip
AMODE
BIGEND
MODE1
MODE0
BREQo
LHOLD
LHOLDA
WAITi
LAD[31..0]
The Glue Board also has JTAG interface incorporated that can
be used for indispensable PLD’s configuration and
programming. JTAG interface is composed from parallel
printer port.
All PLDs are accessed internally by means of an IOBUS
formed from PCI 9080 Local Bus
GND
VCC
GND
ADS#
BLAST#
LBE[3..0]
BTERMo#
READYo#
READYi#
LINTi
LINTo
LSERR#
S0
VCC
LRESETo#
LCLK
TCK
Local Bus
MAX 7256
Figure 2: Structure of the Experiment Control Interface
IV. PLD IN-SYSTEM PROGRAMMABILITY AND
CONFIGURATION
In the Readout Supervisor, two types of PLDs are used.
The programming mechanism is different for the two. While
the MAX 7K devices retain their configuration when power is
switched off, the FLEX 10KE must be re-configured after
each power-down. In the current design of the RS there are
six (+1 reserve) MAX 7K devices and four FLEX 10KE
devices. We have focused exclusively on JTAG for
programming, and the Altera native configuration system has
been skipped.
One PLD (MAX 7256-208) is used for interfacing
between CC-PC Glue Board PLX chip and rest of the Readout
Supervisor logic. Separate Byte Blaster driven externally via
on-board header should program this PLD. Remaining all
PLDs are programmed or configured by JTAG interface
located on PLX chip Glue
Board. This MAX 7256 PLD
contains JTAG distribution logic
/USR_LED
USR_SW
On Board
JTAG Chain
CS10-1
BDAT[31..0]
RADR[4..0]
WR
/SRES
Hardware Setup
External
ByteBlaster
RJ45
RS-232
IOBUS
for all other PLDs. The TCK
JTAG clock lines for
programmed PLDs are driven
directly from the „Glue Board”
JATG Interface. The remaining
three JTAG lines (TMS, TDI
and TDO) are passed through
the MAX 7256 and are
distributed to every other PLD
individually (see Figure 3).
Proposed approach allows
configuring and programming
any set of selected PLDs - from
one to all of them.
The selection of a specific
PLD to be configured is made
via programmable register
(CSR) contained in the MAX
7256 device (Q_IOI module).
When any " x " PLD is
unselected then its TMS_x and
TDO_x lines are driven
permanently HIGH and its
TDO_x/TDI_x pins doesn’t
participate in the closed JTAG
chain. When a given "x" PLD is
selected for programming or
configuration then its TMS_x is
controlled by the “Glue Board” JTAG Interface TMS. Its
TDO_x/TDI_x lines then constitute the JTAG closed chain
together with the other selected PLDs. The order of PLDs in a
global JTAG chain is given in Table 1. The device is selected
when the appropriate bit in CSR is set HIGH. In working
conditions all FLEX devices are selected and all MAX
devices should be deselected.

JTAG Interface
from Glue Board
TMS
TDI
TDO
MAX 7256
TMS_1
TDI_1
TDO_1
TMS_2
TDI_2
TDO_2
TMS_n
TDI_n
TDO_n
V. SYNCHRONIZATION
to PLD #1
to PLD #2
to PLD #n
Figure 4: Structure of the On-board JTAG Distribution
The Readout Supervisor receives the LHC bunch clock
and LHC orbit signal from the TTCmi. The bunch clock is
used without any phase adjustments but it is regenerated by a
Phase Locked Loop Frequency Multiplier (MPC991) to produce
the basic 40.08 MHz clock (BCLK), and the 80 and the
160 MHz clocks that are necessary for TTC encoding.
The external orbit signal is passed through a delay line to
be phase adjusted to the internal BCLK. The PDU54-1500
from Data Delay Devices is used as delay line. It has 16 steps
of 1.5 ns. It is also possible to work without external
synchronization signals. When selected the BCLK and the
ORBIT signals are produced internally.
Synchronizing the external L0 and L1 trigger data with the
internal clock is an important task. It is achieved by means of
clock edge selection as described below. The trigger data are
received according to the timing diagram presented in Figure
4. The data are accompanied by a strobe signal (every clock
cycle for the L0 trigger and every decision for the L1 trigger).
The received data are written into an internal buffer at the
rising edge of the strobe (First Pipeline). The external strobe
is subsequently delayed by approximately 5 ns and is or’ed
with original one. The presence of the strobe is tested by
sampling this or’ed signal with both the positive and the
negative edge of the internal clock. Selecting the good clock
edge is made by the H_0PHASE parameter (for L0) and the
H_1PHASE parameter (for L1) and is established during the
timing alignment of the experiment. If the negative edge of
the local clock was chosen as the proper one (as on the
picture), then the data are stored in a Second Pipeline at this
edge. After another half a clock period the data is transferred
into the Third Pipeline at the positive edge to form the final
data for this clock cell. Of course, if the positive edge was
chosen, then the Second Pipeline step is skipped. In addition,
for L1 triggers, a validation strobe is produced to be used as a
write enable to the L1 Trigger De-randomizer.
For proper on-board clock distribution, separate PECL
differential pairs of equal length are pulled to each PLD.
Translators from PECL to TTL are placed at the closest
distance to the clock pins of each PLD. A MC100E111 clock
driver distributes the PECL clock lines in star fashion.
EXTERNAL DATA
EXTERNAL STROBE
FIRST PIPELINE
DELAYED STROBE
TESTED STROBE (or)
LOCAL CLOCK (INVERTED)
LOCAL CLOCK
A B C
A B C
SECOND PIPELINE A B C
FINAL RECEIVED DATA A B C
VALIDATION STROBE (for L1)
Figure 3: Timing Diagram Showing the Synchronization
Principle
VI. TTC MEZZANINE
The TTC Mezzanine function is to multiplex and encode
A and B channel signals generated by appropriate PLD’s. The
another task of this sub-board is to regenerate Bunch Clock or
in case of its absence to generate internal 40 MHz clock.
Switching between internal and external clock is realized by
H_EXT level generated in Q_IOI module. The A and B
channels are time division multiplexed and bi-phase mark
encoded (see Figure 5). Phase locked loop frequency
synthesizer circuit handles clock multiplication necessary for
the encoding.
Basic Clock
A = "0"
B = "0"
A = "1"
B = "0"
A = "0"
B = "1"
A = "1"
B = "1"
Channel A Channel B
25 ns
Figure 5: Encoder Output Wave Forms

VII. PLD MODULES
For the first prototype design we have chosen solution
with a separate PLD for each logical entity (module). For the
most critical parts of the system the Altera MAX 7000AE
PLD is used – nowadays it is the fastest PLD on the market.
For the more complex entities, such as long multiple counters
or random generators, the Altera FLEX 10KE is sufficient.
There are 6 MAX devices and four FLEX devices used for the
entire project. One reserve MAX PLD will also be mounted
on the board.
A. I/O Interface & Resets
The main task of this module is to act as an interface
between the ECS Glue board and the Readout Supervisor
logic. It controls the internal IOBUS by providing dedicated
chip selects and common control signals to all the Readout
Supervisor PLDs. Another task of this module is to provide
system reset and to distribute programmable JTAG chain to
other PLDs. It is the only PLD programmed by external Byte
Blaster.
B. L0 External Trigger Phasing & Pipelining
The primary function of this module is to provide a 16stage
delay pipeline for L0 Trigger path, where the pipeline
depth is programmable. Besides that it phases the incoming
L0 trigger data to the internal clock and detects missing input
strobes.
C. L0 Trigger Handling
This module receives all the different types of Level-0
triggers (external and internal) and compiles a final trigger
qualifier according to the trigger priority, presence of the L0
inhibit and possible errors. It also performs the synchronization
check of the incoming external L0 triggers. The
accepted L0 triggers are written into the L0 Accept FIFO
(AFIFO) and the YES decisions are broadcasted over the TTC
Channel A. Additionally, this module contains the L0 gap
generator, which, if needed, can force gaps of programmable
length between L0 trigger accepts.
D. L1 Trigger Handling
This module receives the L1 external trigger data and
performs a synchronization check with the corresponding L0
triggers contained in the L0 Accept FIFO. It evaluates the L1
triggers and writes them into the L1 trigger de-randomizer
(TFIFO). It also ensures that internal triggers are maintained
when external L1 trigger path is blocked.
E. L1 Trigger Broadcasts & Inhibits
This module contains a rate controller for the L1 trigger
broadcasting (real broadcasting is performed by another module).
The second task of this module is to centralize the
evaluation of all the different L0 and L1 inhibits in order to
produce a single combined L0 inhibit and a single combined
L1 inhibit. It also runs a L0 front-end de-randomizer occupancy
controller and a L1 front-end buffer occupancy
controller.
F. Generic Command Sender & General Status
Register
The main task of this module is to resolve all of the
incoming requests for trigger and command broadcasting. The
module ensures that the command broadcasts get higher
priority than the pending trigger broadcasts. It also makes sure
that the Bunch Counter Resets and the Event Counter resets
are sent with highest priority at the appropriate times. If a
+command broadcast request is refused due to the Generic
Command Sender being busy, the command is postponed until
the same bunch crossing in the next LHC turn. In case a
trigger broadcast request is refused, it is delayed until the
Generic Command Sender is free.
Another important function of this module is to maintain
all the general status bits of the entire Readout Supervisor. Finally,
it also generates the internal orbit signal when internal
synchronization is selected by the user and detects presence of
external orbit signals.
G. Command Generator & Internal Triggers
This module runs a set of state machines that at the
appropriate times request sending the different type of
commands (resets, calibration pulsing, etc). It also generates
all the signals, which should accompany certain commands. It
also generates all the internal L0 triggers, except the random
triggers. Another important function of this module is to
maintain and generate dedicated resets to all logical nodes that
need to be cleared individually.
H. Random Generator
The Random Generator module produces random L0
triggers that are injected into the L0 trigger handling path. It
can also generate random L1 triggers by randomly forcing a
subset of the random L0 triggers at level one. Optionally, the
module can also be configured to force every or none of the
random L0 triggers. The triggers are generated according to a
Poisson distribution and the rate is fully programmable as will
be explained in the appendix concerning the Random
Generator.
I. Universal Counter Modules
Each of this module contains sixteen 32-bit counters every
of which increments when corresponding ”count enable” input
is produced by appropriate module. Optionally, each
counter may be pre-scaled by a common pre-scale factor. In
this minimal version of the RS, there are two such modules.
All counters are presented in table 1.

VIII. REFERENCES
[1] R.Jacobsson, B.Jost and Z.Guzik – Readout
Supervisor Design Specification, LHCb Technical
Note, LHCb 2001 – 012 DAQ, CERN, February
12, 2001.
Table 1: Implemented Readout Supervisor Counters
[2] Z.Guzik and R.Jacobsson – “ODIN” – LHCb
Readout Supervisor, Technical Reference,
Revision 1.4 – September 2001.
# Description
Proposed
prescaling
0 External L0 sync errors ungated -
1 External L0 sync errors gated -
2 External L0 accepts converted to NO by sync error -
3 Total L0 accept ungated 4
4 Total L0 accept gated 4
5 Total L0 forces ungated -
6 Total L0 forces gated -
7 External L0 accepts ungated 4
8 External L0 accepts gated 4
9 External L0 force ungated -
10 External L0 force gated -
11 Sequencer periodic L0 triggers ungated -
12 Sequencer periodic L0 triggers gated -
13 Random triggers L0 ungated 4
14 Random triggers L0 gated 4
15 reserved
16 Bunch Clock 2^10
17 Bunch Clock gated by L0 Inhibit 4
18 Bunch Clock gated by L1 Inhibit 4
19 L1 external sync errors -
20 External L1 Accepts (Triggers) -
21 reserved
22 L1 Random Force -
23 L1 Forces (from AFIFO) -
24 Total writes to TFIFO 4
25 Accepted writes to TFIFO -
26 Total broadcasts of L1 Trigger commands 4
27 Total number L1 positive trigger retrieved from TFIFO -
28 Total broadcast of L1 Positive Triggers commands -
29 Number of Turns -
30 Bunch Clock gated by L0 External Throttle -
31 Bunch Clock gated by L1 External Throttle -
...

Abstract
CMS REGIONAL CALORIMETER TRIGGER JET LOGIC
W. H. Smith, P. Chumney, S. Dasu, F. di Lodovico M. Jaworski, J. Lackey, P. Robl,
Physics Department, University of Wisconsin, Madison, WI 53706 USA
The CMS regional calorimeter trigger system detects
signatures of electrons/photons, taus, jets, and missing and
total transverse energy in a deadtimeless pipelined
architecture. This system contains 20 crates of custombuilt
electronics. Recent changes to the Calorimeter
Trigger have been made to improve the efficiency and
purity of jet and τ triggers. The revised algorithms, their
implementation in hardware, and their performance on
physics signals and backgrounds are discussed.
1. CMS CALORIMETER L1 TRIGGER
The CMS level 1 trigger decision is based in part upon
local information from the level 1 calorimeter trigger
about the presence of physics objects such as photons,
electrons, and jets, as well as global sums of E T and
missing ET (to find neutrinos) [1].
For most of the CMS ECAL, a 5 x 5 array of PbWO4
crystals is mapped into trigger towers. In the rest of the
ECAL there is somewhat lower granularity of crystals
within a trigger tower. There is a 1:1 correspondence
between the HCAL and ECAL trigger towers. The trigger
tower size is equivalent to the HCAL physical towers,
.087 x .087 in η x φ. The φ size remains constant in Δφ
and the η size remains constant in Δη out to an η of 2.1,
beyond which the η size increases.
Figure 1. Calorimeter Trigger Jet Algorithm
The jet trigger algorithm shown in Figure 1 uses the
transverse energy sums (ECAL + HCAL) computed in
calorimeter regions (4x4 trigger towers). Jets and τs are
characterized by the transverse energy ET in 3x3
calorimeter regions (12x12 trigger towers). For each
calorimeter region a τ-veto bit is set if there are more than
two active ECAL or HCAL towers in the 4x4 region. A jet
is defined as ’tau-like’ if none of the 9 calorimeter region
τ-veto bits are set.
2. CALORIMETER TRIGGER HARDWARE
The calorimeter level 1 trigger system, shown in Figure
2, receives digital trigger sums from the front-end
electronics system, which transmits energy on an eight bit
compressed scale. The data for two trigger towers is sent
on a single link with eight bits apiece, accompanied by
five bits of error detection code and a “fine- grain” bit for
each trigger tower characterizing the energies summed
into it, i.e. isolated energy for the ECAL or an energy
deposit consistent with a minimum ionizing particle for
the HCAL.
Figure 2. Overview of Level 1 Calorimeter Trigger

The calorimeter regional crate system uses 20 regional
processor crates covering the full detector. Eighteen crates
are dedicated to the barrel and two endcaps. These crates
cover the region |η|

The jets and τs are characterized by the transverse
energy E T in 3x3 calorimeter regions using a sliding
window technique that spans the complete (η,φ) coverage
of the CMS calorimeters seamlessly. The summation
spans 12x12 trigger towers in the barrel and endcap or
3x3 larger HF towers in the HF. The φ size of the jet
window is the same everywhere. The η binning gets
somewhat larger at high η due to the size of calorimeter
and trigger tower segmentation. The jet trigger central
region E T is required to be higher than the eight neighbor
region E T values.The jets are labeled by (η,φ) indexes of
the central calorimeter region.
For each calorimeter region a τ-veto bit is set ON if
there are more than two active ECAL or HCAL towers in
the 4x4 region. This assignment of a τ-veto bit is
performed by the input memory lookup tables on the
Receiver Card that assign the E T values to the appropriate
scales for downstream processing. Spare bits in these
memories are used as threshold ETs to determine the
number of active towers. These towers are counted by the
downstream logic to determine τ-like energy deposits. A
jet is defined as “τ-like” if none of the 9-calorimeter
region τ-veto bits are ON.
The Jet/Summary card receives 4x4 trigger tower 10-bit
4x4 E T sums, 1 overflow bit and active trigger tower
counts from all Receiver cards in the crate, including all
of the 14 regions 4x4 served by the crate. These data are
multiplexed for transmission at 80 MHz to the Cluster
crate for finding jets and τ candidates.
The Jet/Summary card processes the 2-bit ECAL and
HCAL activity counts for each of the 14 regions covered
by the crate. If the trigger tower activity counts from
ECAL or HCAL are greater than two, the 4x4 region τ
veto bit is set ON. There is enough room on the card to
implement this algorithm in discrete logic components.
The logic is used at least twice per crossing to determine
τ veto bits for all 14 regions handled by this card.
The eighteen regional trigger crates and the single HF
crate send 4x4 trigger tower E T sums to a single Cluster
crate where 12x12 overlapping ET sums are calculated to
form jet and τ candidates. As shown in Figure 4, the
Cluster crate consists of 9 Cluster Processor cards each
receiving data from two regional crates and one HF crate
on six 34-pair cables. The data from two regional crates,
covering |η|

The four highest energy central and forward jets, and
central τs in the calorimeter are selected. This choice of
the four highest energy central and forward jets and of the
four highest energy τs provides enough flexibility for the
definition of combined triggers.
In addition, counters of the number of jets above
programmable thresholds in various η regions are
provided to give the possibility of triggering on events
with a large number of low energy jets. Jets in the forward
and backward HF calorimeters are sorted and counted
separately. This separation is a safety measure to prevent
the more background-susceptible high-η region from
masking central jets. Although the central and forward jets
are sorted and tracked separately through the trigger
system, the global trigger can use them seamlessly as the
same algorithm and resolutions are used for the entire η−φ
plane.
Another possibility of performing the sliding window
jet cluster algorithm is to use the Global Calorimeter
Trigger hardware [4]. In this option, the GCT receives 14
subregion energies from the Jet/Summary Card in each
RCT barrel / endcap crate, along with the τ feature bits.
The subregion energy data from the HF is also input. A
clustering algorithm based on a 3 x 3-subregion sliding
window is employed to find jets over the full range. The
jets found by this procedure are then sorted as in the
baseline design in three streams: central jets, forward jets
and τ-jets.
In either realization, single, double, triple and quad jet
(τ) triggers are possible. The single jet (τ) trigger is
defined by the transverse energy threshold, the (η,φ)
region of validity and eventually by a prescaling factor.
Prescaling will be used for low energy jet (τ) triggers,
which are necessary for efficiency measurements.
The multi jet (τ) triggers are defined by the number of
jets (τs) and their transverse energy thresholds, by a
minimum separation in (η,φ), as well as by a prescaling
factor. The global trigger accepts the definition, in
parallel, of different multi jet (τ) triggers conditions.
4. JET AND t -TRIGGER PERFORMANCE
The jet trigger efficiency turn-on versus the generator
level jet pT for the location matched jets is shown in
Figure 5 for single, double, triple and quadruple jet
events. The plots are made from a full GEANT-based
detailed simulation of the CMS detector and trigger logic.
The jet trigger integrated rate is plotted versus the
corrected L1 jet E T for single, double, triple and
quadruple jet events in Figure 6. For the multi-jet triggers
all the trigger jets are required to be anywhere in |η|

Figure 6. Jet trigger rates for single, double, triple and
quadruple jet triggers.
Figure 7. Low Luminosity single and double jet and tau
trigger rates.
Figure 8. High Luminosity Single and double jet and
tau trigger rates.
6. REFERENCES
[1] CMS, The TRIDAS Project Technical Design Report,
Volume 1: The Trigger Systems, CERN/LHCC 2000-38,
CMS TDR 6.1.
[2] J. Lackey et al., CMS Calorimeter Level 1 Regional
Trigger Conceptual Design, CMS NOTE-1998/074
(1998).
[3] W.H. Smith et al., CMS Calorimeter Regional
Calorimeter Trigger High Speed ASICs, in Proceedings
of the Sixth Workshop on Electronics for LHC
Experiments, Cracow, Poland, September, 2000
[4] J. J. Brooke et al., An FPGA Implementation of the
CMS Global Calorimeter, in Proceedings of the Sixth
Workshop on Electronics for LHC Experiments, Cracow,
Poland, September, 2000

The Track-Finding Processor for the Level-1 Trigger of the CMS Endcap Muon System
D. Acosta, A. Madorsky (Madorsky@phys.ufl.edu), B. Scurlock, S.M. Wang
University of Florida
A. Atamanchuk, V. Golovtsov, B. Razmyslovich, L. Uvarov
Abstract
We report on the development and test of a prototype
track-finding processor for the Level-1 trigger of the CMS
endcap muon system. The processor links track segments
identified in the cathode strip chambers of the endcap muon
system into complete three-dimensional tracks, and measures
the transverse momentum of the best track candidates from
the sagitta induced by the magnetic bending. The algorithms
are implemented using SRAM and Xilinx Virtex FPGAs, and
the measured latency is 15 clocks. We also report on the
design of the pre-production prototype, which achieves
further latency and size reduction using state-of-the-art
technology.
I. INTRODUCTION
The endcap muon system of CMS consists of four stations
of cathode strip chambers (CSCs) on each end of the
experiment. The coverage in pseudo-rapidity (η) is from 0.9
to 2.4. A single station of the muon system is composed of
six layers of CSC chambers, where a single layer has cathode
strips aligned radially (from the beam axis) and anode wires
aligned in the orthogonal direction. The CSC chambers are
trapezoidal in shape with a 10° or 20° angular extent in
azimuth (ϕ). The CSC chambers are fast (60 ns drift-time)
and participate in the Level-1 trigger of CMS.
A “Local Charged Track” (LCT) forms the most primitive
trigger object of the Endcap muon system. Both cathode and
anode front-end LCT trigger cards search for valid patterns
from the six wire and strip planes of the CSC chamber. The
anode data provide precise timing information as well as η
information, and the cathode data provide precise ϕ
information. A motherboard on the chamber collects the LCT
information, associates the wire data to the cathode data, tags
the bunch crossing time, and selects the two best candidates
from each chamber. The end result is a three-dimensional
vector, encoded as a bit pattern, which corresponds to a track
segment in that muon station. It is transmitted via optical
links to the counting house of CMS. To reduce the number
St. Petersburg Nuclear Physics Institute
of optical connections, only the three best track segments are
sent from nine chambers (18 track segments).
The Track-Finder must reconstruct muons from track
segments received from the endcap muon system, measure
their momenta using the fringe field of the central 4 T
solenoid, and report the results to the first level of the trigger
system (Level-1). This objective is complicated by the nonuniform
magnetic field in the CMS endcap and by the high
background rates; consequently, the design must incorporate
full 3-dimensional information into the track-finding and
measurement procedures.
The experimental goal of the Track-Finder is to efficiently
identify muons with as low a threshold in transverse
momentum (PT) as possible in order to meet the rate
requirement of the Level-1 Trigger of CMS. This translates
into a single muon trigger rate which does not exceed about 1
kHz per unit rapidity at the full luminosity of the LHC. The
resolution on PT, therefore, should be less than about 30% at
least, which requires measurements of the ϕ and η
coordinates of the track from at least three stations.
II. TRACK-FINDER LOGIC
The reconstruction of complete tracks from individual
track segments is partitioned into several steps to minimize
the logic and memory size of the Track-Finder [1]. The steps
are pipelined and the trigger logic is deadtime-less.
First, nearly all possible pairwise combinations of track
segments are tested for consistency with a single track. That
is, each track segment is extrapolated to another station and
compared to other track segments in that station. Successful
extrapolations yield tracks composed of two segments, which
is the minimum necessary to form a trigger. The process is
not complete, however, since the Track-Finder must report
the number of distinct muons to the Level-1 trigger. A muon
that traverses all four muon stations and registers four track
segments would yield six track “doublets.” Thus, the next
step is to assemble complete tracks from the extrapolation
results and cancel redundant shorter tracks. Finally, the best
three muons are selected, and the track parameters are
measured.

A. Extrapolation
A single Extrapolation Unit forms the core of the Track-
Finder trigger logic. It takes the three-dimensional spatial
information from two track segments in different stations,
and tests if those two segments are compatible with a muon
originating from the nominal collision vertex with a curvature
consistent with the magnetic bending in that region.
All possible extrapolation pairs are tested in parallel to
minimize the trigger latency. This corresponds to 81
combinations for the 15 track segments of the endcap region.
However, we have excluded direct extrapolations from the
first to fourth muon station in order to reduce the number of
combinations to 63. This prohibits triggers involving hits in
only those stations, but saves logic and reduces some random
coincidences (since those chambers are expected to have the
highest rates). It also facilitates track assembly based on
“key stations,” which is explained in the next section.
B. Track Assembly
The track assembly stage of the Track-Finder logic
examines the results of the extrapolations and determines if
any track segment pairs belong to the same muon. If so,
those segments are combined and a code is assigned to denote
which muon stations are involved. The underlying feature of
the track-assembly is the concept of a “key station.” For this
design, the second and third muon stations are key stations. A
valid trigger in the endcap region must have a hit in one of
those two stations. The second station is actually used twice:
once for the endcap region and once for the region of overlap
with the barrel muon system, so there are a total of three data
streams. The track assembler units output a quality word for
the best track for each hit in the key stations.
C. Final Selection
The final selection logic combines the nine best
assembled tracks, cancels redundant tracks, and selects the
three best distinct tracks. For example, a muon which leaves
track segments in all four endcap stations will be identified in
both track assembler streams of the endcap since it has a
track segment in each key station. The Final Selection Unit
must interrogate the track segment labels from each
combination of tracks from the two streams to determine
whether one or more track segments are in common. If the
number of common segments exceeds a preset threshold, the
two tracks are considered identical and one is cancelled.
Thus, the Final Section Unit is a sorter with cancellation
logic.
D. Measurement
The final stage of processing in the Track-Finder is the
measurement of the track parameters, which includes the ϕ
and η coordinates of the muon, the magnitude of the
transverse momentum PT , the sign of the muon, and an
overall quality which we interpret as the uncertainty of the
momentum measurement. The most important quantity to
calculate accurately is the muon PT , as this quantity has a
direct impact on the trigger rate and on the efficiency.
Simulations have shown that the accuracy of the momentum
measurement in the endcap using the displacement in ϕ
measured between two stations is about 30% at low
momenta, when the first station is included. (It is worse than
70% without the first station.) We would like to improve this
so as to have better control on the overall muon trigger rate,
and the most promising technique is to use the ϕ information
from three stations when it is available. This should improve
the resolution to at least 20% at low momenta, which is
sufficient.
III. FIRST PROTOTYPE SYSTEM ARCHITECTURE
The Track-Finder is implemented as 12 “Sector
Processors” that identify up to the three best muons in 60°
azimuthal sectors. Each Processor is a 9U VME card housed
in a crate in the counting house of CMS. Three receiver
cards [3] collect the optical signals from the CSC chambers
of that sector and transmit data to the Sector Processor via a
custom point-to-point backplane. A maximum of six track
segments are sent from the first muon station in that sector,
and three each from the remaining three stations. In addition,
up to eight track segments from chambers at the ends of the
barrel muon system are propagated to a transition board in the
back of the crate and delivered to each Sector Processor as
well.
A total of nearly 600 bits of information are delivered to
each Sector Processor at the beam crossing frequency of 40
MHz (3 GB/s). To reduce the number of connections, LVDS
Channel Link transmitters/receivers from National
Semiconductor [2] were used to compress the data by about a
factor of three through serialization/de-serialization. A
custom point-to-point backplane operating at 280 MHz is
used for passing data to the Sector Processor.
Each Sector Processor measures the track parameters (PT,
ϕ, η, sign, and quality) of up to the three best muons and
transmits 60 bits through a connector on the front panel. A
sorting processor accepts the 36 muon candidates from the 12
Sector Processors and selects the best 4 for transmission to
the Global Level-1 Trigger.
A prototype Sector Processor was built using 15 large
Xilinx Virtex FPGAs, ranging from XCV50 to XCV400, to
implement the track-finding algorithm, one XCV50 as VME
interface and one XCV50 as an output FIFO (Fig. 1).
The configuration of the FPGAs, including the VME
interface, was done via a fast VME-to-JTAG module,
implemented on the same board. This module takes
advantage of the VME parallel data transmission, and reduces

the configuration time down to 6 seconds, instead of ~6
minutes if we use a standard Xilinx Parallel III cable.
The following software modules were written to support
testing and debugging:
• Standalone version of the C++ model for Windows
• Module for the comparison of the C++ model with the
board’s output
• JTAG configuration routine, controlling the fast VMEto-JTAG
module of the board
• Lookup configuration routine, used to write and check
the on-board lookup memory
• Board Configuration Database with a Graphical User
Interface (GUI), that keeps track of many configuration
variants and provides a one-click selection of any one of
them. Each variant contains the complete information for
FPGA and lookup memory configuration.
All software was written in portable C++ or C, to simplify
porting into another operating systems. The Board
Configuration Database is written in JAVA, since this is the
simplest way to write a portable GUI. All software can and
will be used for the second (pre-production) prototype
debugging and testing.
The first prototype was completely debugged and tested.
Simulated input data as well as random numbers were
transmitted over the custom backplane to this prototype, and
the results were read from the output FIFO. These results
were compared with a C++ model, and 100% matching was
demonstrated. The latency from the input of the Sector
Receivers [3] (not including the optical link latency) to the
output of the Sector Processor is 21 clocks, 15 of which are
used by Sector Processor logic.
Figure 2 shows the test stand used for testing and
debugging the first prototype.
IV. SECOND (PRE-PRODUCTION) PROTOTYPE
SYSTEM ARCHITECTURE
Recent dramatic improvements in the programmable logic
density [4] allow implementing all Sector Processor logic into
one FPGA. Additionally, the optical link components have
become smaller and faster. All this allows combining three
Sector Receivers and one Sector Processor of the first
prototype onto one board. This board will accept 15 optical
links from the Muon Port Cards [3]; each link carries the
information about one muon track segment. Additionally, the
board receives up to 8 muon track segments from the Barrel
Muon System via a custom backplane.
Since the track segment information arrives from 15
different optical links, it has to be synchronized to the
common clock phase. Also, because the optical link’s
deserialization time can vary from link to link, the input data
must be aligned to the proper bunch crossing number.
Next, the track segment information received from the
optical links is processed using lookup tables to convert the
Cathode LCT pattern number, sign, quality and wire-group
number into the angular values describing this track segment.
The angular information about all track segments is fed to a
large FPGA, which contains the entire 3-dimensional Sector
Processor algorithm. On the first prototype this algorithm
occupied 15 FPGAs.
The output of the Sector Processor FPGA is sent to the PT
assignment lookup tables, and the results of the PT
assignment for the three best muons are sent via the custom
backplane to the Muon Sorter.
In the second (pre-production) prototype Track-Finder
system we stopped using Channel Links for the backplane
transmission because of their long latency, and moved to the
GTLP backplane technology. This allows transmitting the
data point-to-point (from Sector Processor to Muon Sorter) at
80 MHz, with no time penalty for serialization since the most
relevant portions of data are sent in the first frame. The data
in the second frame are not needed for immediate calculation,
so they do not delay the Muon Sorter processing.
The entire second (pre-production) prototype Track-
Finder system will fit into one 9U VME crate (Fig. 3).
V. SECTOR PROCESSOR ALGORITHM AND C++
MODEL MODIFICATIONS
The Sector Processor algorithm was significantly
modified to fit into one chip and to reduce latency. The
comparison of the old and new algorithms is shown on Fig. 4.
In particular, the following modifications were made:
• The algorithms of the extrapolation and final selection
units are reworked, and now each of them is completed
in only one clock.
• The Track Assembler Units in the first prototype were
implemented as external lookup tables (static memory).
For the second prototype, they are implemented as FPGA
logic. This saved I/O pins on the FPGA and one clock of
the latency.
• The preliminary calculations for the PT assignment are
done in parallel with final selection for all 9 muons, so
when three best out of nine muons are selected, the precalculated
values are immediately sent to the external PT
assignment lookup tables.
All this allowed reducing the latency of the Sector
Processor algorithm (FPGA plus PT assignment memory)

down to 5 clocks (125 ns) from 15 clocks in the first
prototype.
The current version of the Sector Processor FPGA is
written entirely in Verilog HDL. The core code is portable; it
does not contain any architecture-specific library elements. It
is completely debugged with Xilinx simulator in timing
mode, and its functionality exactly matches the C++ model.
During the construction and debugging of the first
prototype, we have encountered many problems related to the
correspondence between hardware and C++ model. In
particular, sometimes it is very problematic to provide the
exact matching, especially if the model uses the C++ built-in
library modules, such as lists and list management routines,
etc.
To eliminate these problems in the future, the C++ model
was completely rewritten in strict line-by-line correspondence
to the Verilog HDL code. All future modifications will be
done simultaneously in the model and Verilog HDL code,
keeping the correspondence intact.
VI. SUMMARY
The conceptual design of a Track-Finder for the Level-1
trigger of the CMS endcap muon system is complete. The
design is implemented as 12 identical processors, which
cover the pseudo-rapidity interval 0.9 < η < 2.4. The trackfinding
algorithms are three-dimensional, which improves the
background suppression. The PT measurement uses data
from 3 endcap stations, when available, to improve the
resolution to 20%. The latency is expected to be 7 bunch
crossings (not including the optical link latency). The design
is implemented using Xilinx Virtex FPGAs and SRAM lookup
tables and is fully programmable. The first prototype was
successfully built and tested; the pre-production prototype is
under construction now.
VII. ACKNOWLEDGEMENTS
This work was supported by grants from the US
Department of Energy. We also would like to acknowledge
the efforts of R. Cousins, J. Hauser, J. Mumford, V. Sedov,
B. Tannenbaum, who developed the first Sector Receiver
prototype, and the efforts of M. Matveev and P. Padley, who
developed the Muon Port Card and Clock and Control Board,
which were used in the tests.
VIII. REFERENCES
[1]. D. Acosta et al. “The Track-Finding Processor for the
Level-1 Trigger of the CMS Endcap Muon System.”
Proceedings of the LEB 1999 Workshop, CERN 99-09,
p.318.
[2] National Semiconductor, DS90CR285/286 datasheet.
[3] CMS Level-1 Trigger Technical Design Report,
CERN/LHCC 2000-038
[4] Xilinx Inc., www.xilinx.com
Figure 1: The first prototype of Sector Processor
Figure 2: Prototype test crate.

Latency
1
1
4
2
3
2
3
3
2
Clock and Control
Board
Muon Sorter
From
Trigger Timing
Control
To
Global Trigger
BIT3 Controller
Optical receivers
Front FPGAs
Lookup tables
Channel link
transmitters
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
MS
CCB
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
Figure 3: Second Prototype Track-Finder Crate.
Sector Receiver st.1
Channel link receivers
Bunch crossing analyzer (not implemented)
Extrapolation units
Sector Receiver st.2,3
9 Track Assembler units (memory)
Final selection unit 3 best out of 9
Pt precalculation for best 3 muons
Pt assignment (memory)
Sector Receiver st.4
Figure 4: Comparison of the first and pre-production prototypes.
SR/SP Card
(3 Sector Receivers +
Sector Processor)
(60° sector)
From MPC
(chamber 4)
From MPC
(chamber 3)
From MPC
(chamber 2)
From MPC
(chamber 1B)
From MPC
(chamber 1A)
To DAQ
First prototype data flow Pre-production prototype data flow
From Muon Port Cards
Total: 21 Total: 7
To Muon Sorter
Sector Processor
Latency
1
1
0
1
1
1
1
1
SR/SP board
Optical receivers
Front FPGAs
Lookup tables
Bunch crossing analyzer (not implemented)
Sector Processor
FPGA
From Muon Port Cards
Extrapolation units
9 Track Assembler units
Pt precalculation for
9 muons
Output multiplexor
Pt assignment (memory)
To Muon Sorter
Final selection
unit 3 best out
of 9

The Sector Logic demonstrator
of the Level-1 Muon Barrel Trigger
of the ATLAS Experiment
V. Bocci, A. Di Mattia, E. Petrolo, A. Salamon, R. Vari, S. Veneziano
Abstract
The ATLAS Barrel Level-1 muon trigger processes
hit information from the RPC detector, identifying candidate
muon tracks and assigning them to a programmable pT range
and to a unique bunch crossing number.
The on-detector electronics reduces the information
from about 350k channels to about 400 32-bit data words sent
via optical fiber to the so-called Sector Logic boards.
The design and performance of the Sector Logic
demonstrator, based on commercial and custom modules and
firmware is presented, together with functionality and
integration tests.
I. THE ATLAS FIRST LEVEL MUON TRIGGER IN THE BARREL
The ATLAS first level muon trigger in the barrel is
based on fast geometric coincidences between three different
planes of RPC trigger stations in the muon spectrometer. The
trigger chambers are arranged in three different shells
concentric with the beam line, each chamber has four planes
of strips (two along η and two along φ) in order to reduce the
fake trigger rate due to the cavern background. For the same
reason the algorithm is performed both in η and in φ.
The trigger algorithm is executed for two separate pT thresholds.
• For the low-pT threshold, if a strip is hit in the pivot
plane (RPC2) the trigger processor searches for an hit in
the first trigger chamber plane (RPC1) looking inside a
window whose axis is on the line that connects the hit
point in RPC2 with the nominal interaction point, whose
vertex is on the RPC2 plane and whose opening gives the
cut on pΤ. A valid trigger is generated if RPC1 and RPC2
are hit in coincidence.
• For the high-pT threshold, if a valid trigger has been
generated by the low-pT algorithm, the processor searches
for an hit in the third plane RPC3, searching for a
coincidence between the trigger pattern given by the lowpT
algorithm and the hit on the RPC3 trigger station.
The schematic of the trigger principle is depicted in Figure 1.
The trigger processor is composed of various modules.
• The low-pT Coincidence Matrix ASICs (CMAs) are
mounted on the RPC2 trigger chambers and perform the
fast coincidence between the signals coming from RPC1
and RPC2. Each CM η board covers a region ∆η x ∆φ =
INFN RM1 and University of Rome “La Sapienza”, INFN RM2
andrea.salamon@roma2.infn.it
Figure 1: Trigger principle for the ATLAS first level muon trigger in
the barrel. The selection is performed using three dedicated trigger
chambers. For the low-p T trigger if an hit is found in RPC2, an hit is
searched for in the RPC1 trigger station inside a road defined by the
p T cut. The same algorithm is applied for the high p T threshold using
the low-p T trigger output and the RPC3 trigger station.
0.1 x 0.2, while the CM φ board covers a region ∆η x ∆φ
= 0.2 x 0.1.
• The low-p T Pad Logic Boards are mounted on RPC2
and collect the data from four coincidence matrices from
a region ∆η x ∆φ = 0.2 x 0.2. The low-p T Pad board
generates the low-p T trigger information and sends it to
the high-p T trigger boards.
• The high-p T Coincidence Matrix ASICs are mounted
on the RPC3 trigger chambers and perform the fast
coincidence between the signals coming from the low-p T
trigger and the RPC3 trigger station. The CM η board
covers a region ∆η x ∆φ = 0.1 x 0.2, while the CM φ
board covers a region ∆η x ∆φ = 0.2 x 0.1.
• The high-p T Pad Logic Boards are mounted on RPC3
and collect the data from the low-p T board and from four
high-p T coincidence matrix from a region ∆η x ∆φ = 0.2 x
0.2. The high-p T Pad board merges the bending (η) and
non bending (φ) views, selects the muon with the highest
threshold, associates the muon with a Region of Interest
∆η x ∆φ = 0.1 x 0.1 and with a unique bunch crossing
number. Trigger informations are sent to the Sector Logic
board.
• The Sector Logic boards are located in the
underground counting room. Each Sector Logic board
covers a region ∆η x ∆φ = 1.0 x 0.4, receives data from

up to 7 high-p T pad logic boards and from 32 Tile
Calorimeter trigger towers. The output of the Sector
Logic board is sent to the Muon Central Trigger
Processor Interface (MUCTPI).
• The MUCTPI elaborates the data from the Sector
Logic boards and sends its output to the Central Trigger
Processor.
In Figure 2 is reported a trigger slice from the RPC Front End
electronics to the Muon Central Trigger Processor Interface
and to the Read Out Buffer.
Figure 2: Trigger slice from the RPC Front End electronics to the
Muon Central Trigger Processor Interface and to the Read Out
Buffers.
II. SECTOR LOGIC FUNCTIONS
Each Sector Logic board collects information from
up to 7 high pT pad logic boards and form 32 Tile Calorimeter
trigger towers. 64 Sector Logic boards are foreseen in the first
level muon triggere in the barrel. Each Sector Logic board
performs various functions.
• Checks the correct timing of the input data. If some
problem is found a flag is sent to the MUCTPI.
• Performs the Tile Calorimeter coincidence. A muon
candidate is accepted only if an energy deposit is found in
a region of the Tile Calorimeter associated to the region
of the muon spectrometer in which the muon candidate
has been detected. This option will be used in case of
high background levels and is fully programmable.
• Performs the low-pT filter. For each low-pT muon
coming from one of the input Pads it checks if an hit is
found in the RPC3 trigger station. This check is
performed at the sector level. This option is also to be
used in case of high background levels and is fully
programmable.
• Solves η overlap between different Pads inside the
sector and flags all the muons crossing a region
overlapping with a neighbouring sector (this overlap is
solved by the MUCTPI).
• Selects the two muons with the two highest thresholds
in the sector and associates each muon with a Region of
Interest ∆η x ∆φ = 0.1 x 0.1 and with a unique bunch
crossing number. If more than two muon candidates are
found, the Sector Logic flags this condition to the Muon
Central Trigger Processor Interface.
III. SECTOR LOGIC HARDWARE IMPLEMENTATION
The Sector Logic is implemented with a pipeline
processor working synchronously with the 40 MHz LHC
clock.
Each Sector Logic chip receives the input from up to
8 Pad Logic boards (8 x 12 bit @ 40 MHz) and from 32 Tile
Calorimeter trigger towers (32 bit @ 40 MHz) and sends the
output synchronously to the Muon Central Trigger Processor
Interface (32 bit @ 40 MHz). A spare Pad input has been
added to the maximum number of 7 Pads input foreseen at the
current time. The low-pT filter and the Tile Calorimeter
coincidence are fully programmable depending on the content
of four configuration registers.
Sector Logic processing is perfomed in five pipeline
steps. Each pipeline block consists of an input D flip-flop
register (containing the data from up to 8 Pads and from 32
Tile Calorimeter trigger towers and the current result of the
trigger algorithm) followed by the combinatorial logic
implementing the desired functions on the current data. A
block dagram of the Sector Logic chip architecture is reported
in Figure 3.
Figure 3: Block diagram of the architecture of the Sector Logic chip.
The Sector Logic algorithm is implemented with a five steps
pipeline, each step of the pipeline implementing one task of the
algorithm.
We implemented the Sector Logic functionalities in
an FPGA. We used the EPF10K130E-2 of the ALTERA
FLEX 10KE family as target device.
A. Tile Calorimeter confirmation
The first step of the Sector Logic pipeline is the Tile
Calorimeter confirmation block. This block maps the input
coming from the pads to the input from the Tile Cal. A muon
candidate is accepted only if a corresponding track is found in
the expected region of the Tile Calorimeter. This option is
fully programmable for each threshold and thus can also be
disabled.
The Tile Calorimeter check can be programmed with
two arrays EnTCCh(0:7,1:6) and SetTCCh(0:7,1:6,0:31)
stored in the Sector Logic configuration registers. The Tile
Calorimeter coincidence is enabled for all the muons crossing
the i-th Pad with the j-th threshold if EnTCCh(i,j) is set to 1.

In the same way, for each muon passing in the i-th Pad with
the j-th threshold, an energy deposit is searched in the k-th
Tile Calorimeter trigger tower if SetTCCh(i,j,k) is set to1.
Figure 4: Tile Calorimeter coincidence implementation. For a given
Pad and a given threshold a muon candidate is accepted if one hit is
found in one of the corresponding Tile Calorimeter trigger towers.
The schematic of the Tile Calorimeter coincidence is
reported in Figure 4. This coincidence is executed in parallel
48 times, for each Pad and for each threshold.
B. Outer Plane (OPL) low-p filter T
The second step of the Sector Logic pipeline
performs a filter on low-pT muons. A muon with one of the
three low thresholds is confirmed only if an hit is found in the
outer plane of the spectrometer (RPC3 trigger chambers). This
coincidence is performed at the sector level. This option is
fully programmable for each threshold and can also be
disabled.
The OPL check can be programmed with two arrays
EnOPLCh(0:7,1:3) and SetOPLCh(0:7,1:3,0:7) stored in the
Sector Logic configuration registers. The OPL coincidence is
enabled for all the muons crossing the i-th Pad with the j-th
threshold if EnOPLCh(i,j) is set to 1. In the same way, for
each muon passing in the i-th Pad with the j-th threshold, an
hit is searched in the k-th Pad of the RPC3 trigger station if
SetOPLCh(i,j,k) is set to1.
Figure 5: Low-p T filter implementation. For a given Pad and a given
low-p T threshold a muon candidate is accepted if one hit is found in
one of the corresponding RPC3 Pads.
The schematic of the low-pT filter implementation is
reported in Figure 5. This coincidence is executed in parallel
24 times, for each Pad and for each low-pT threshold.
C. Solve η overlap
The η solving algorithm is aimed at avoiding to
double count a muon passing in a region of overlap between
two different chambers. The Sector Logic overlap solving
algorithm looks at the data from the various Pads and if it
finds two neighboring pads in which the same track has
passed, discards one of the two tracks.
The η overlap solving algorithm is performed in
various combinatorial steps:
• a check on all the overlap bits is performed; if a pad
with the overlap bit set to 1 and the threshold set to 0
(anomalous condition) is found, the overlap bit is reset;
• the overlap solving algorithm is performed first on
neighbouring Pads 0 and 1, 2 and 3, 4 and 5, 6 and 7
(even overlap solving);
• the same solving algorithm is performed next on
neighbouring Pads 1 and 2, 3 and 4, 5 and 6 (odd overlap
solving).
D. Find 1 st track
The fourth block of the pipeline selects the track with
the highest threshold and associates to the muon candidate
trigger informations. If there is more than one triggered track
with the same threshold the track with lower pad number
(lower η) is selected.
The 1 st
highest threshold selection algorithm is
performed in various steps:
• the highest threshold associated to each Pad is
compared with the highest threshold associated to all the
other pads. The output of these comparison are ANDed.
Eight bits indicating if the pad’s triggered threshold is
greater or equal than the thresholds associated to all the
other pads are produced at the output of this block.
A schematic of the highest threshold selection
algorithm is reported in Figure 6.
Figure 6: 1 st highest threshold search implementation. For each Pad
the muon candidate threshold is compared with the thresholds of all
the other Pads and the comparison output are ANDed for each Pad.

The output from the comparison block is sent in
parallel to two different blocks:
• the first block is composed of an encoder and a data
filter which transmit to the next step of the pipeline all
the Pads data except the data from the Pad corresponding
to the highest threshold (to avoid double counting of the
same highest threshold);
• the second block is composed of a priority encoder
and a selector which sends to the Sector Logic output
pipeline the data corresponding to the Pad with the
highest threshold.
E. Find 2 nd track
This step of the Sector Logic pipeline is identical to
the previous step, and is performed on the data from all the
Pads excepted the Pad with the highest threshold (which has
been reset to 0). The result of the search is synchronized with
the output from the previous step and is written in the part of
the SL output frame dedicated to the 2 nd
threshold. A flag is
written in the output data pattern if more than two tracks were
found in the sector.
IV. THE SECTOR LOGIC DEMONSTRATOR
F. The Multifunction Computing Core
In order to demonstrate the functionalities of our
implementation we used the Multi Function Computing Core
MFCC 8441 commercial board from CES. This commercial
hardware has been proven to be reliable and efficient solution
for the purposes of our tests.
The MFCC 8441 is a PCI Mezzanine Card which can
be plugged on a RIO2 VME board also from CES.
The MFCC board is composed of:
• a POWER PC CPU running the Sector Logic C test
control program;
• a PPC-PCI bridge implemented with an Altera FPGA
of the FLEX 10KE family;
• on board SDRAM which can be used for demanding
DAQ applications;
• a Front-End FPGA which is full user programmable;
the Sector Logic VHDL code is loaded in this FPGA, the
VHDL code needed to interface the Front-End FPGA
with the PPC bus, with the FE adaptor, with the SDRAM
and with the EPROM is produced by CES;
• a Front-End adaptor which must be designed for the
specific application;
• a flash EPROM storing the firmware for the PPC-PCI
bridge and for the FE FPGA; the EPROM can be
programmed with a dedicated download cable and from
the on-board PPC.
G. The test setup
In order to use the Sector Logic VHDL code with the
MFCC test board an interface with the CES VHDL code has
been created. The architecture of this interface is depicted in
Figure 7.
The Sector Logic Core is interfaced with an Input
Block constituted of 32-bit wide 32-bit deep RAMs, with a
Parameter Block in which are stored the Sector Logic
Initialization registers and the control registers and with the
Output Block constituted of a 32-bit FIFO.
Figure 7: High level Sector Logic schematics with the interface with
the test board. The Sector Logic core receives the input from the
Input Block, the configuration parameters from the the Parameters
Blobk and sends its output to the Output Blobk. All the registers in
the Input, Parameters and Output Bloks are accessible via the MFCC
Power PC bus.
A test session is performed in the following steps:
• the Sector Logic parameters are loaded in the
initialization registers;
• the inputs are loaded by the PPC in the 32-bit internal
FIFOs;
• a series of 40 MHz clock cycles is applied, it is also
possible to perform an infinite loop on the data loaded in
the input RAM (this feature has been used in the Sector
Logic MUCTPI integration tests);
• the data are elaborated by the FE FPGA which has
been programmed with the Sector Logic demonstrator
code;
• the output data are sent both to the FE Adaptor and to
the output FIFO; the data stored in the output FIFOs can
be read by the PPC and analized and checked off-line, the
data at the output of the FE Adaptor can be analized with
the scope or sent to the MUCTPI.
H. MFCC Front End adaptor card
The Frontend Adaptor card has been designed to
translate the 32 Sector Logic output bit from the FE FPGA to
suitable LVDS logic levels to be sent along a 10 meters 40
MHz parallel cable to the MUCTPI.
In Figure 8 is reported a photo of the MFCC with the
MUCTPI interface card.

Figure 8: Layout of the MFCC with the FE adaptor card translating
the MFCC Sector Logic output to LVDS logic levels used to
interface the Sector Logic demonstrator with the MUCTPI prototype.
V. SECTOR LOGIC TESTS
Two kind of thests were performed to validate and
test our design: off-line logic tests and integration tests with
the MUCTPI prototype.
I. Off-line logic tests
The input data from Pads and from Tile Calorimeter
trigger towers were loaded in the input RAM, elaborated and
read from the output FIFO. The output data were checked
with a C++ Sector Logic simulation program. This C++ code
will be inserted in the official first level muon trigger
simulation program.
J. Integration tests with the MUCTPI
The Sector Logic demonstrator and the MUCTPI
prototype were connected with a 10 meters 32 LVDS logic
levels transmission cable. The Sector Logic and the MUCTPI
run with the same 40 MHz LHC clock, but the two clock
signals are not required to be in phase. All the Sector Logic
output data are assumed to be in phase. The data are sampled
on the falling edge of the MUCTPI clock signal.
Theree kind of tests and measurements were
performed.
• Phase measurement. In order to allow a correct
sampling the phase spread of the changing edge of the
Sector Logic output data must be low. The phase spread
of a given bit at the output of the MUCTPI has been
measured with a TDC and a RMS less than 1 ns was
found.
• After the phase spread measurement has been
performed, a window sampling depth measurement were
performed. A fixed sequence of 27 input patterns were
loaded in the input RAMs and an infinite test loop on the
input data were started. The length of the pattern was
chosen in order to be a submultiple of the number of BCs
in an orbit. The data at the input of the MUCTPI are
sampled at a given BC in the orbit and so the MUCTPI
receives always the same known input data from the
Sector Logic. The phase of the sampling edge was moved
by 1 ns steps inside the 25 ns clock period corresponding
to the chosen BC and the sampled data are checked. The
width of the allowed sampling window was found to be
19 ns over 25 ns.
• Data integrity check. Correct data transmission was
checked over a one night run and no error was found.
VI. CONCLUSIONS
The Sector Logic demonstrator has been developed
using a commercial board, the PCI Mezzanine Card MFCC
8441 from CES with dedicated firmware running on FPGA.
A custom FE Adaptor Card has been designed to
connect the Sector Logic demonstrator with the Muon
Central Trigger Processor Interface.
The design has been checked with the official Sector
Loigc C++ simulation program.
Various kind of tests were performed to validate the
design. The performance of the Sector Logic demonstrator are
adequate for the 40 MHz operation and maximum latency of
125 ns.
This work has proven that the use of commercial
hardware is a valid solution during the first part of the
development of custom boards, because it reduces the
demonstrator development time and gives the designer good
support during the test phase.
The first Sector Logic VME board prototype is
currently been designed on the basis of the present
demonstrator.
VII. ACKNOWLEDGMENTS
We would like to thank F. Cidronelli and R. Lunadei
(INFN RM1) for designing the layout of the FE Adaptor card
and K. Nagano and R. Spiwoks (CERN) for the Sector Logic
MUCTPI integration tests.
VIII. REFERENCES
V. Bocci, E. Petrolo, A. Salamon, R. Vari, S.
Veneziano, Prototype Slice of the Level-1 Muon Trigger in
the Barrel Region of the ATLAS Experiment, Theese
Proceeedings
V. Bocci, G. Chiodi, E. Gennari, E. Petrolo, A.
Salamon, R. Vari, S. Veneziano, Radiation test and
application of FPGAs in the Atlas Level 1 Trigger, Theese
Proceeedings
P. Farthouat, Interfaces and overlaps in the LVL1
muon trigger system, Revision 4
http://www.ces.ch

Abstract
One Size Fits All: Multiple Uses of Common Modules in the ATLAS
Level-1 Calorimeter Trigger
G. Anagnostou, P. Bright-Thomas, J. Garvey, S. Hillier, G. Mahout, R. Staley,
W. Stokes, S. Talbot, P. Watkins, A. Watson
School of Physics and Astronomy, University of Birmingham, Birmingham B15 2TT, UK
R. Achenbach, P. Hanke, W. Hinderer, D. Kaiser, E.-E. Kluge, K. Meier,
U. Pfeiffer, K. Schmitt, C. Schumacher, B. Stelzer
Kirchoff-Institut für Physik, University of Heidelberg, D-69120 Heidelberg, Germany
B. Bauss, K. Jakobs, C. Nöding, U. Schäfer, J. Thomas
Institut für Physik, University of Mainz, D-55099 Mainz, Germany
E. Eisenhandler, M.P.J. Landon, D. Mills, E. Moyse
Physics Department, Queen Mary, University of London, London E1 4NS, UK
P. Apostologlou, B.M. Barnett, I.P. Brawn, J. Edwards, C.N.P. Gee, A.R. Gillman,
R. Hatley, K. Jayananda, V.J.O. Perera, A.A. Shah, T.P. Shah
Rutherford Appleton Laboratory, Chilton, Didcot OX11 0QX, UK
C. Bohm, S. Hellman, S.B. Silverstein
Fysikum, University of Stockholm, SE-106 91 Stockholm, Sweden
The architecture of the ATLAS Level-1 Calorimeter Trigger
has been improved and simplified by using a common module
to perform different functions that originally required three
separate modules. The key is the use of FPGAs with multiple
configurations, and the adoption by different subsystems of a
common high-density custom crate backplane that takes care
to make data paths equal widths and includes minimal
VMEbus. One module design can now be configured to count
electron/photon and tau/hadron clusters, or count jets, or form
missing and total transverse-energy sums and compare them to
thresholds. In addition, operations are carried out at both crate
and system levels by the same module design.
I. INTRODUCTION
The ATLAS Level-1 Calorimeter Trigger (figure 1) [1] uses
reduced-granularity data from ~7200 ‘trigger towers’, 0.1×0.1
in η–φ, covering all of the ATLAS electromagnetic and
hadronic calorimeters. After digitisation and assignment of
each pulse to the correct 25-ns bunch crossing in the
Preprocessor subsystem, the trigger algorithms (figure 2) are
Corresponding author: Ian Brawn (i.p.brawn@rl.ac.uk)
executed in two parallel subsystems. The Cluster Processor
(CP) finds and counts isolated electron/photon and tau/hadron
clusters, while the Jet/Energy-sum Processor (JEP) finds and
counts jets, as well as adding the total and missing transverse
energy (ET). The JEP also has logic to trigger on jets in the
forward calorimetry, and on approximate total ET in jets.
Cluster Processor Modules (CPMs), each covering an area of
∆φ=90˚ × ∆η~0.4, send the number of e/γ and tau/hadron
clusters they have found, up to a maximum of seven (three
bits), to two merger modules that sum cluster multiplicities.
One merger module handles 8 electron/photon threshold sets
(each set being a combination of cluster, e.m. isolation, and
hadronic isolation ET), and the other handles 8 threshold sets
that can each be programmed to be e/γ or tau/hadron. The
maximum multiplicity for each threshold set is also seven. The
multiplicity summing is in two stages: first for the 14 CPMs in
each CP crate, and then for the four-crate CP subsystem. In
the original design [2] these were Cluster Merger Modules,
fed by cables from the CPMs to a separate crate. The final
‘hit’ multiplicity results are sent to the Central Trigger
Processor (CTP).

On
Detector
In
Trigger
Cavern
LAr
(em)
~7000 analogue links
PPMs
9-bit jet elements
JEP
PPr
Calorimeters
Analogue Sum
Receiver
Preprocessor
10-bit FADC
FIFO, BCID
Look-up table
2x2 sum BC-mux
10-bit serial links:
400 Mbit/s (~10 m)
Figure 1: Overall architecture of the ATLAS Calorimeter Trigger.
Figure 2: Calorimeter trigger algorithms.
Tile/LAr
(had)
twisted pair,

performance, either on the individual JEM sums in each crate
or on the inter-crate sums. The optimal scaling was to use the
two scale bits to multiply by 1, 4, 16 or 64. At the same time,
it was shown that FPGA code for summing the hit
multiplicities, or for computing total and missing transverse
energy, could be run in the same type of FPGAs. The
multiplication needed for the energy scaling can be done by
bit-shifting to keep the latency low. The JEP then has two
CMMs in each crate: one for counting jet multiplicities, and
one for summing transverse energy.
We thus end up with just one type of merger module, for both
CP and JEP subsystems, and for both hit-counting and
transverse-energy summing. Furthermore, this one module
design contains both the crate-level and system-level logic.
Which operations they carry out will be determined
automatically by the crate and slot that they occupy.
III. COMMON MERGER MODULE DESIGN
A block diagram of the CMM is shown in figure 3. At the core
of the design are the two blocks labeled Crate Merging Logic
and System Merging Logic. These blocks contain all of the
logic that is specific to one or more versions of the CMM. All
of the other logic shown is common to all versions. The data
widths shown are the maximum needed to implement all of the
required versions of CMM.
Each CMM receives data from the local crate via a maximum
of 400 backplane links. These data are re-timed to the system
clock and sent to the Crate Merging Logic. The data output
from the Crate Merging Logic are sent to System Merging
Logic, either on the same CMM (in the case of system-level
CMMs) or on a remote CMM (in the case of crate-level
CMMs). The transmission of these data between CMMs is
performed using parallel LVDS cable links.
On system-level CMMs, the System Merging Logic receives a
maximum of 50 bits of data from the local Crate Merging
Logic, and up to 75 bits of data from up to three remote cratelevel
CMMs. Data received from remote CMMs are re-timed
to the board clock and data from the local crate merging logic
are fed through a pipeline delay to compensate for any
difference in the latency of the local and remote data paths.
The results from the System Merging Logic are fed to the CTP
via LVDS cable links. The System Merging logic on cratelevel
CMMs is redundant.
The core of the CMM logic is implemented in two large
FPGAs, labeled Crate FPGA and System FPGA. These
implement the following logic:
• Crate FPGA: Crate Merging Logic, Backplane Receiving
Logic, Event Data Readout, Readout Control.
• System FPGA: System Merging Logic, Cable Receiving
Logic, Event Data Readout, RoI Data Readout.
The main motivation for using FPGAs on the CMM is the
flexibility they introduce into the design. By choosing two
large devices rather than several smaller ones this flexibility is
increased, as the number of hard-wired interconnections at
board level is reduced. Both the Crate and System FPGAs are
implemented with Xilinx XCV1000E devices. This device
was chosen to meet the I/O requirement of the Crate FPGA
and the RAM requirement of the System FPGA. It contains
approximately 1.5 million gates including 96 blocks of 4kbit
RAM. It is a fine-pitch ball-grid array package, with 660 pins
of user-I/O.
From Crate
CMM
From CPMs
or JEMs
Figure 3: A block diagram of the Common Merger Module.
from
Cable from
Receivers Cable
Receivers
from
Cable from
Cable
Receivers
Receivers
from
Cable from
Receivers Cable
Receivers
Figure 4: The system-merging logic of the e/γ System-level CMM.
from
Cable
Receivers
from
Local Crate
Merging
from
Local Crate
Merging
from
Local Crate
Merging
25
25
from
24
local from Crate
Local Merging Crate
Merging
75 bit
Cable
Receive
and Re-time
400 bit
CMOS
backplane
Receive
and Re-time
TCM
Interface
VME
Interface
25
50
400
Parity
Check
(CMM 1)
Parity
Check
(CMM 2)
Parity
Check
(CMM 3)
16
15
17
16
16
8x3
Crate
Merging
Logic
Event Data Readout
Dual-port RAMs
Playback
FIFO
75
Shift Register
Parity
Check
Parity
Check
Parity
Check
3-bit add
8x3
with
3-bit
over-
add
with
3-bit
flowover-
add
with
3-bit
flowover-
add
with
3-bit
flowover-
add
with
3-bit
flowover-
add
with
3-bit 4-input
flowover-
add
with
flow3-bit
over-
saturating flow
adder
15
16
16
Pipeline
Delay
ET
sum &
Theshold
Ex
sum
Ey
sum
ET to RoI
Ex to RoI
Parity
Error
Counter
&Map
Ey to RoI
System
Merging
Logic
Vector
Add &
Threshold
(LUT)
Parity
Generator
Parity
Error
Counter
& Map
Figure5: The system-merging logic of the Energy System-level
CMM.
50
RoI Readout
Dual-port RAM
FIFO
Shift Register
Readout Controller
24
46
Parity
Generation
ClusHitSys22Nov00.cnv
3
3
Parity
Check
Results
50 bit
Cable
Transmit
46 bit
CTP
Interface
Glink
Glink
Serial Link
to R-ROD
Serial Link
to D-ROD
Overview07Dec00.cvs
25
7
To System
CMM
To CTP
To CTP
Interface
To CTP
Interface

The ATLAS level-1 calorimeter trigger requires the CMM to
perform a number of different functions (see table 1). For a
CMM to implement a function the specific configuration files
for that function must be loaded into the Crate and System
FPGAs. On board every CMM are flash memories that house
all configuration files, so that every CMM has the potential to
perform any of the functions listed in table 1. On power up,
the CMM automatically configures itself to perform one of
these functions, determined by the geographical address of the
module.
CMM Module Types
e/γ Crate-level CMM
e/γ System-level CMM
τ/hadron Crate-level CMM
τ/hadron System-level CMM
Jet Crate-level CMM
Jet System-level CMM
Energy Crate-level CMM
Energy System-level CMM
Table 1: CMM module types.
Figures 4 and 5 show two examples of different logic designs
that can be implemented in the System FPGA. Figure 4 shows
the System Merging Logic required by the e/γ subsystem. This
consists mainly of 7-bit adder trees which sum the e/γ
multiplicities over all crates for each of 8 thresholds. Figure 5,
on the other hand, shows the system-merging logic required to
perform energy summation. Here the total ET, Ex and Ey
values are formed by summation. A bank of look-up tables
(LUTs) is then used to apply thresholds to these values to
produce the number of total-ET and missing-ET hits. In all
cases, the output from the System Merging logic is sent to the
CTP.
IV. COMMON BACKPLANE
The use of the CMM in both the CP and JEP subsystems
means that these subsystems require very similar backplanes.
It can be seen from table 2 that, with the exception of speed,
the requirements of the CP subsystem are a subset of those of
the JEP subsystem. A backplane capable of hosting the JEP
subsystem can therefore also be used to host the CP
subsystem, provided the fan-in/out links between modules are
capable of operating at 160 MHz. To take advantage of this,
and rationalise the design of the Level-1 Calorimeter Trigger
further, a common backplane has been designed for these two
subsystems.
The common backplane is 9U high (400.05 mm) and 84 HP
wide (426.72 mm). It can accommodate up to 21 modules,
comprised of the following: 16 JEMs or 14 CPMs, 2 CMMs,
1 Timing Control Module (TCM) and 2 VME controllers.
Most of the tracks on the backplane carry data fanned between
neighbouring CPMs/JEMs, or data transferred from these
modules to CMMs. There are also timing signals and a
CANbus that is used to monitor temperatures and voltages
within the crate.
Due to the large number of signal tracks on the backplane it is
not possible to accommodate a full VMEbus. Instead a custom
VME bus is used, called VME – –. This allows only A24 D16
VME cycles using a minimal set of VME lines: SYSRESET,
A[23:1], D[15:0], DS0*, WRITE* and DTACK*. A custom
adapter card is needed to provide the interface between the
crate and a standard VME64 controller.
CP subsystem crate JEP subsystem crate
14 CPMs 16 JEMs
CPM input from pre-processor JEM input from pre-processor
= 80 serial links via 20 cable = 88 serial links via 24 cable
assemblies
assemblies
CPM–CPM fan-in/out = 320 JEM–JEM fan-in/out = 330
single-ended point-to-point single-ended point-to-point
links @ 160 MHz
links @ 80 MHz
Data input to each CMM from Data input to each CMM from
CPMs = 350 single-ended JEMs = 400 single-ended
point-to-point links @ 40 MHz point-to-point links @ 40 MHz
TTC, CPU, DCS (CANbus) TTC, CPU, DCS (CANbus)
required
required
Table 2: Comparison of the JEP and CP subsystem crate backplane
requirements.
In addition to the signal tracks across the backplane, the
backplane must also accommodate the serial links that bring
data from the Preprocessor system to the CPMs/JEMs. These
are brought to the back side of the backplane via untwisted
shielded pair cable assemblies. These assemblies are mated to
long through-pins on the rear of the backplane, and passed
directly through the backplane to the processor modules on
the other side. The same system of through pins is used on the
CMM connectors to receive 84 twisted-pair cables carrying
data from CMMs in remote crates.
The connections between the backplane and the modules are
implemented using AMP Z-pack (Compact PCI) connectors.
These feature 5 rows of pins at a 2 mm pitch, allowing a total
of 820 pins to be connected to each module. A signal to
ground ratio of 4:3 is used on these pins to minimise
interference between the signals.
V. EXAMPLE OF FLEXIBILITY: NEW ALGORITHMS
This backplane just described, combined with the use of
FPGAs in both the CMM and JEM designs, allows us to add
some new trigger algorithms that have been requested by
ATLAS but were not foreseen in the original design. No doubt
other variations will appear in the future.
• The forward calorimetry, covering rapidities from 3.2 to
4.9, was originally included in the trigger only because it
was needed to improve the missing-ET resolution.
However, in addition to allowing extension of the normal
jet trigger into this range, it has recently been proposed
that certain Higgs decays via Ws (i.e., the ‘invisible Higgs’
channel) might be picked up by a trigger on jets in the
FCAL in conjunction with missing-ET. The flexibility of
the FPGA logic in the JEMs allows forward jets to be
found on their own, and the logic in the CMM can be
altered to count them separately.
• A trigger on approximate total ET in jets was going to be
done in the CTP. This multiplies the number of jets
exceeding each jet threshold by the value of the threshold,
and compares the estimated total jet ET obtained with some

total jet-ET thresholds. This can now be done in the final
subsystem-level jet-counting FPGA, which is more logical
and appropriate.
• Triggers on total ET can be spoiled by noise, particularly if
it is coherent. Simulation indicates that matters might be
improved by requiring local regions to exceed a low
threshold value if they are to be added to the total. This
could, of course, be done in the JEMs and simply replace
the normal total-ET trigger. However, if it is desired to use
this trigger in parallel with the normal total-ET trigger, the
use of FPGA logic in both the JEMs and CMMs allows
this to be done by using some of the jet logic.
VI. OTHER COMMON MODULES: TCM AND ROD
In addition to the hardware described above, two other
modules in the ATLAS Level-1 Calorimeter Trigger perform
multiple roles. A common Readout Driver handles both
readout data and level-1 trigger regions-of-interest in both CP
and JEP. This module is described in an accompanying
paper.
A common Timing Control Module has also been designed for
use in the CP, JEP, and Preprocessor subsystems. It provides
the interface between the crates in these subsystems and the
ATLAS TTC and DCS networks. One difficulty in the design
of the TCM is that the Preprocessor and CP/JEP crates use
different formats and connectors to implement their VME
buses. To overcome this problem the TCM uses and an
Adapter Link Card (ALC) to house the VME interface. The
ALC is essentially a daughter card for the TCM. It differs
from normal daughter cards, however, in that it fits into a cutout
section at the rear of the TCM and lies flush with that
card. Two ALCs have been designed, to implement the VME
interfaces for the Preprocessor and CP/JEP systems.
VII. STATUS AND TESTING
Prototype versions of the CMM and the common backplane
have been designed, and will shortly be sent out for
manufacture. A prototype TCM has been manufactured and is
currently undergoing stand-alone tests, and a prototype
common ROD module exists and its interfaces with other
ATLAS subsystems have been tested at CERN.
In March 2002, a complete vertical ‘slice’ of the ATLAS
Level-1 Calorimeter Trigger will be built and tested. This will
include prototype versions of all of the hardware elements in
the system, including all of the common hardware described
above.
VIII. CONCLUSIONS
We have shown how the use of programmable FPGA logic
has allowed us to implement what were originally three
separate kinds of merger modules as a single design. Although
two of the three were fairly similar, the energy summation is
quite a different task from hit counting, but by making the
number of input and output signals the same and by using
versatile and powerful FPGAs it could still be accommodated.
This reduction in the number of different module types saves
on design effort and on non-recurrent engineering costs, and
reduces the number of spare modules required.
Although the use of a common custom backplane in the CP
and JEP subsystems was mandated by the use of the Common
Merger Module, the gains just mentioned make it too a useful
simplification to the trigger system.
The use of a common Readout Driver Module for the two
subsystems, again made possible by the use of programmable
logic, and the use of a common Timing Control Module
throughout all three calorimeter trigger subsystems, also
carries the same advantages.
REFERENCES
[1] ATLAS Level-1 Calorimeter Trigger home page:
http://hepwww.pp.rl.ac.uk/Atlas-L1
[2] ATLAS Level-1 Trigger Technical Design Report:
http://atlasinfo.cern.ch/Atlas/GROUPS/DAQTRIG/TDR/tdr.ht
ml
[3] M. K. Jayananda, ATLAS Level-1 Calorimeter
Trigger — Simulation of the backplane for Common Merger
Module, ATL-DAQ-2000-004.
[4] R. Dubitzky and K. Jakobs, Study of the performance
of the Level-1 Pt miss Trigger, ATL-DAQ-99-010

The Final Multi-Chip Module
of the ATLAS Level-1 Calorimeter Trigger Pre-Processor
G. Anagnostou, P. Bright-Thomas, J. Garvey, S. Hillier, G. Mahout, R. Staley, W. Stokes, S. Talbot,
P. Watkins, A. Watson
School of Physics and Astronomy, University of Birmingham, Birmingham B15 2TT, UK
R. Achenbach, P. Hanke, W. Hinderer, D. Kaiser, E.-E. Kluge, K. Meier, U. Pfeiffer, K. Schmitt,
C. Schumacher, B. Stelzer
Kirchoff-Institut für Physik, University of Heidelberg, D-69120 Heidelberg, Germany
B. Bauss, K. Jakobs, C. Nöding, U. Schäfer, J. Thomas
Institut für Physik, University of Mainz, D-55099 Mainz, Germany
E. Eisenhandler, M.P.J. Landon, D. Mills, E. Moyse
Physics Department, Queen Mary, University of London, London E1 4NS, UK
P. Apostologlou, B.M. Barnett, I.P. Brawn, J. Edwards, C.N.P. Gee, A.R. Gillman, R. Hatley, K. Jayananda,
V.J.O. Perera, A.A. Shah, T.P. Shah
Rutherford Appleton Laboratory, Chilton, Didcot OX11 0QX, UK
C. Bohm, S. Hellman, S.B. Silverstein
Fysikum, University of Stockholm, SE-106 91 Stockholm, Sweden
Corresponding author: Werner Hinderer (hinderer@kip.uni-heidelberg.de)
Abstract
The final Pre-Precessor Multi-Chip Module (PPrMCM)
of the ATLAS Level-1 Calorimeter Trigger is presented. It
consists of a four-layer substrate with plasma-etched vias
carrying nine dies from different manufacturers. The task of
the system is to receive and digitize analog input signals from
individual trigger towers, to perform complex digital signal
processing in terms of time and amplitude and to produce
two independent output data streams. A real-time stream
feeds the subsequent trigger processors for recognizing trigger
objects, and the other provides deadtime-free readout of the
Pre-Processor information for the events accepted by the
entire ATLAS trigger system. The PPrMCM development has
recently been finalized after including substantial experience
gained with a demonstrator MCM.
I. INTRODUCTION
The event selection at the ATLAS experiment requires a fast
three level Trigger system for the selection of physics processes
of interest. The first trigger level (Level-1 Trigger) is designed
to reach an event rate reduction from the 40 MHz LHC bunch-
crossing rate down to the first level accept rate of 75 kHz -
100 kHz [1]. The Level-1 Trigger is composed of a number
of building blocks - the Calorimeter Trigger, the Muon Trigger
and the Central Trigger Processor. The input to the Level-1
Trigger for the calorimeter part is based on reduced granularity.
Analog calorimeter signals are summed to ’trigger towers’ on a
basis of a two dimensional grid with steps of 0.1 in the � and �
direction. This is done separately for the Electromagnetic and
the Hadronic Calorimeter. It amounts to about 7200 signals
which are then transmitted electrically via twisted pair cables
to the Level-1 Trigger.
Figure 1 shows a block diagramm of the Calorimeter
Trigger. The Pre-Processor at the front-end of the Calorimeter
Trigger links the ATLAS calorimeters with the subsequent
object finding processors - the Cluster Processor and the
Jet/Energy-Sum Processor.
The maximum latency to find a Level-1 trigger decision
is 2.0 �s including cable delays. This and the large number
of trigger tower signals requires a compact system with fast
hard-wired algorithms implemented in application-specific

Calorimeter
~7200
anal. summed
trigger towers
0.1 x 0.1
~7200 anal.
electr. signals
em. & had.
Pre−Processor (PPr)
digitization, 10bit
BCID
energy cal. (LUT)
data transmission
pre−sums of
Jet−elements
BC−mux
readout
Phi duplication
0.2 x 0.2 jet−elem.
em. and had.
Cluster Processor (CP)
|Eta|

Analog In
¯ one four-channel PPrASIC, providing readout and
preprocessing;
¯ one timer chip (Phos4) for the phase adjustment of the
FADC strobes with respect to the analog input signals;
¯ three Bus LVDS Serializers, 10-bits at 40 MHz
(400 Mbit/s user data rate, 480 MBd including start- and
stop bit);
Digitization
ADC FIFO
10−bit delay
# BC
fine
sync.
0−25ns
Digital signal processing Transmission
(ADC) (PPrASIC)
(LVDS Serializer)
(Phos4)
real−time data path (40 MHz)
BCID: LUT BC− par. to
FIR +
mux ser.
Peak,
sat.,
ext.
10−bit
40MHz
readout data path (100 kHz)
Playback & Monitoring
Figure 3: Block diagram of the final MCM
+
par. to
ser.
10−bit
40MHz
480 MBit/s
to CP
480 MBit/s
to JEP
Figure 3 shows the preprocessing of one trigger tower
signal. Four such channels are combined on one MCM. The
real-time signal processing flows from the left to the right.
First, the FADCs digitizes the analog trigger tower signals at
40 MHz with 12-bit resolution (only 10-bits are used, the two
lowest significant bits are not connected) in a range of 1 V
peak-to-peak around the internal generated 2.4 V reference
voltage. Each FADC die generates its own reference voltage.
The offset adjustment and scaling from the 2.5 V input signal
range to this 1 V range is done by the Analog Input board
shown in figure 2. Next, the four 10-bit data buses emanating
from the four FADCs are each digitally preprocessed inside
the PPrASIC. The PPrASIC output is interfaced to three
LVDS Serializer chips. In the case of the data transmission
to the Cluster Processor (CP), a bunch-crossing multiplexing
scheme (BC-mux) is applied, so that one LVDS Serializer
transmits the data from two FADCs. Due to the coarser
jet-elements the LVDS Serializer used for data transmission to
the Jet/Energy-Sum Processor (JEP) transmits the data from
four channels. Figure 3 also shows the second independent
output data stream produced by the MCM. This second stream
allows pipelined readout of raw trigger input data as well as
� Ì values after the lookup table (LUT) in order to tell what
has caused a trigger and to provide diagnostic information.
It allows the monitoring of the performance of the trigger
system and the injection of test data for trigger system tests.
The function of the readout pipelines in the Pre-Processor is
equivalent, but independent of those of the detector readout.
The Level-1 Trigger captures its own event data as soon as it
has triggered. Two sets of pipeline memories capture the event
data in the Pre-Processor. One records the raw FADC data
at the Pre-Processor input and one records after the lookup
table. Without introducing deadtime to the readout, the readout
data path can record data from the pipeline memories up to a
Level-1 accept rate of 100 kHz for five time-slices including
the BCID result.
A. Design Experience
Considerable design experience has been gained from
a demonstrator MCM which has been built, simulated and
successfully operated (see [3] for details). This demonstrator
MCM was designed with the same feature size (100 �m) as
the final MCM and it was fabricated in the same laminated
MCM-L process described in the following subsection.
B. MCM production technique
The MCM technology can be classified by its substrate
type. It is refered to as an MCM-L (laminated) technology.
This technique was chosen to combine small feature sizes
with low prices. The design process of the laminated
multi-layer structure is based on an industrially-available
production technique for high-density printed circuit boards.
The process, which is offered by Würth Elektronik [5] is
called TWINflexÖ . It is characterized by its use of plasma
etched micro-vias, where plasma is used for ‘dry’ etching
of insulating material (Polyimide). Plasma etching enables
precise via contacts between layers with a diameter of 100 �m
down to 50 �m.
The body of the MCM is a combination of three flexible
Polyimide foils laminated on a rigid copper substrate to form
four routing layers. The layer cross-section consists of a core
foil of 50 �m thickness, which carries 18 �m copper plates on
either side. Plasma etching is used for ‘buried’ via connections
to adjacent layers and routing structures are formed in copper
using conventional etching techniques. The core foil is
surrounded by outer foils of 25 �m Polyimide, which are
copper plated only on one side. The actual contact through
the core foil is accomplished with electroplated copper and
after that, the routing structures are formed. The electroplating
process increases the track thickness from 18 �m to25�m.
The application of adhesive accomplishes laminating.
Routing
structures
Staggered
via
Figure 4: Cross-section of the flexible MCM part after laminating.
Staggered vias are used for the connection through all layers.
Figure 4 shows the final laminated and flexible part of the
MCM. A combination of three vias (staggered vias) is needed
to accomplish a contact from the top to the bottom layer.
Finally the flexible part is glued onto a copper substrate of
800 �m thickness.
Due to the high power dissipation of the FADCs (0.6 W for
each), for all four FADCs staggered vias were grouped as close
as possible to form thermal vias which provide good thermal
conductance to the substrate.
Figure 5 shows the final MCM cross-section. Components
such as capacitors and resistors are connected to the multi-layer
structure using surface-mount technology (SMD). On each
end a 60 pin SMD connector from SAMTEC (BTH030)
connects the MCM to the Pre-Processor Module. The chips are

2.0 cm
Figure 6: Partly assembled MCM substrate.
Phos4
SMD connector Silicone gel Chip attach SMD component Metal lid
FADCs
four-layer
Cu-polyimide
Cu substrate
Figure 5: Side view of the hermetically sealed MCM. High-density
SMD connectors were used to allow quick replacement upon
component failure.
encapsulated with a lid in between the two SMD connectors.
The lid will be glued with electrically conducting epoxy to
the layer compound. It will act as an EMI-shielding device
and it will be filled with a silicone gel to remove atmosphere
and to protect the dies from moisture. On the backside of the
substrate an 8 mm Al heatsink is glued to it.
C. MCM layout
This section describes the physical layout of the MCM.
The following points were considered in the design of the final
MCM:
¯ Analog and digital parts were separated: this applies to
power and ground, the signal routing and the placement
of the dies.
¯ Broad power traces (� � �m) were used to limit the
voltage drop, the width of the other traces are usually
only �m.
¯ For each die at least two decoupling capacitors were
used.
¯ The clock distribution was done for each die individually
using short traces, this ensures a uniform propagation
delay for all clock signals.
¯ A bond pad size of 150 �m ¢ 300 �m was used. This
size is large enough for wire-bonding, even if one needs
to probe at bonding pads during the MCM test or to place
a second bond.
¯ Copper shapes beneath each die are required to connect
the die substrate with its voltage potential.
7.0 cm
footprint of
the PPrASIC
LVDS Serializers
¯ A solder mask is used to prevent short circuits during
soldering of SMD components.
¯ On the top layer, a cross-hatched ground shape
surrounds bonding and SMD pads. This reduces the
electromagnetic influence of signals to each other and it
stabilizes the ground potential. A cross-hatched shape
is needed because drying moisture coming out of the
cross-section can destroy the MCM.
A partly assembled MCM is shown in Figure 6 prior to
final hermetic encapsulation. The PPrASIC is missing on the
picture. The layout has a form factor of 2.0 cm ¢ 7.0 cm. The
total power consumption is 5.2 W. 932 vias were used, the total
line length is about 2.5 m.
IV. FUNCTIONAL TEST OF THE MCM
As more than 3200 MCMs have to be tested, an automated
test able to say ’well working’ or ’defective’ within minutes is
required. Figure 7 shows the necessary hardware for such a
test.
sync.
PC with dual head
video card
Video
RAM
R
G
B
R
G
B
set−up
PC with:
analog
input
board
Figure 7: MCM test-setup.
MCM test board
PPrMCM
HDMC=
Hardware Diagnostics, Monitoring
and Control software
compare with vectors
VME Motherboard with
Common Mezzanine Cards
(CMC)
LVDS receiver CMC
real−time data path
CMC card
readout data path
configure
readout
First of all, a dual head video card is used as a signal
generator. The advantages of using a video card as a signal
generator are that a video card is very cheap, very fast and
arbitrary analog output signals can be programmed. A dual
head video card has six analog outputs. Out of these six
outputs four are chosen to provide the analog stimilus signals
VME

for the test. The signals are conditioned by the Analog Input
board, the same board which is used on the Pre-Processor
Module. The conditioned signals are received by the MCM
to be tested. Both, the MCM and the Analog Input board are
plugged on a test board. The output of the real-time data path
is received by a LVDS receiver CMC card. The data of the
readout path are received by a Xilinx FPGA, located on a
second CMC card. This CMC card also hosts a large SRAM
which buffers the data of the readout path as well as the data of
the real-time path which is transmitted from the LVDS receiver
CMC card to this CMC card. The memory can be read out by
VME and thus data can be transmitted to a PC.
The test will be set-up and analysed by the Hardware
Diagnostics, Monitoring and Control software (HDMC) which
was developed by the ATLAS group of Heidelberg. The
output of the MCM can now be compared with expected
results gained from a mixed signal simulation of the full MCM
including the chip logic. Because of the analog part of the
MCM the check will have boundaries within which the result
can be seen as correct.
V. MASS PRODUCTION AND QUALITY
ASSURANCE
The development and design of the MCM was done by
the University of Heidelberg, whereas the final production of
3200 MCMs needs to be done in cooperation with external
companies. The four-layer MCM substrate including the
800 �m copper carrier is done by Würth Elektronik [5]. The
mounting of dies and SMD components, wire-bonding and
encapsulation will be done by Hasec [4].
The following list provides the sequence for mass
production and quality assurance:
1 Production: Substrate layer compound
2 Test : Electrical test
3 Test : Test bonding
4 Assembly : Silk-screen printing of solder paste
5 Assembly : Placement of SMD components
6 Assembly : SMD reflow soldering
7 Assembly : Chip mounting
8 Assembly : Ultrasonic wire-bonding
9 Test : MCM test with the test system shown in section IV
10 Assembly : Repair of defective MCMs
11 Assembly : Encapsulation, lid and silicone gel
12 Test : Performance test on the Pre-Processor Module
VI. CONCLUSIONS
The design of the final MCM benefited from the design
experience gained by a demonstrator MCM. Compared to
this demonstrator MCM the final MCM presented here is less
demanding in terms of power, temperature and link speed and
hence it can achieve an improved reliability. An extensive
test will be done in the near future when the so called ’slice
test’ starts. It is planned to assemble the whole preprocessing
chain with the subsequent object-finding processors for several
hundred analog trigger tower signals. This test will show if the
final MCM meets all the requirements.
VII. REFERENCES
[1] ATLAS Level-1 Trigger Group
ATLAS First-Level Trigger Technical Design Report
ATLAS TDR-12, CERN/LHCC/98-14, CERN, Geneva 24
June 1998
http://atlasinfo.cern.ch/Atlas/GROUPS/DAQTRIG/TDR/tdr.html
[2] Pre-Processor Module
Specification of the Pre-Processor Module (PPM) for the ATLAS
Level-1 Calorimeter Trigger
The ATLAS Heidelberg Group
http://wwwasic.kip.uni-heidelberg.de/atlas/docs/modules.html
[3] Pfeiffer, U.
A Compact Pre-Processor System for the ATLAS Level-1
Calorimeter Trigger
PhD Thesis, Institut für Hochenergiephysik der Universität
Heidelberg, Germany 19 October 1999
http://wwwasic.kip.uni-heidelberg.de/atlas/docs.html
[4] HASEC-Elektronik.
http://www.hasec.de
[5] Würth Elektronik
http://www.wuerth-elektronik.de

Prototype Readout Module for the ATLAS Level-1 Calorimeter Trigger Processors
G. Anagnostou, P. Bright-Thomas, J. Garvey, S. Hillier, G. Mahout,
R. Staley, W. Stokes, S. Talbot, P. Watkins, A. Watson
School of Physics and Astronomy, University of Birmingham, Birmingham B15 2TT, UK
R. Achenbach, P. Hanke, W. Hinderer, D. Kaiser, E.-E. Kluge, K. Meier,
U. Pfeiffer, K. Schmitt, C. Schumacher, B. Stelzer
Kirchhoff Institut für Physik, University of Heidelberg, D-69120 Heidelberg, Germany
B. Bauss, K. Jakobs, C. Nöding, U. Schäfer, J. Thomas
Institut für Physik, Universität Mainz, D-55099 Mainz, Germany
E. Eisenhandler, M.P.J. Landon, D. Mills, E. Moyse
Physics Department, Queen Mary, University of London, London E1 4NS, UK
P. Apostologlou, B.M. Barnett, I.P. Brawn, J. Edwards, C.N.P. Gee,
A.R. Gillman,R. Hatley, V. Perera, A.A. Shah, T.P. Shah
Rutherford Appleton Laboratory, Chilton, Didcot OX11 0QX, UK
C. Bohm, S. Hellman, S.B. Silverstein
Fysikum, University of Stockholm, SE-106 91 Stockholm, Sweden
Corresponding author: Gilles Mahout (gm@hep.ph.bham.ac.uk)
Abstract
The level-1 calorimeter trigger consists of three
subsystems, namely the Preprocessor, electron/photon and
tau/hadron Cluster Processor (CP), and Jet/Energy-sum
Processor (JEP). The CP and JEP will receive digitised
calorimeter trigger-tower data from the Preprocessor and will
provide trigger multiplicity information to the Central Trigger
Processor and region-of-interest (RoI) information for the
level-2 trigger. It will also provide intermediate results to the
data acquisition (DAQ) system for monitoring and diagnostic
purposes. This paper will outline a readout system based on
FPGA technology, providing a common solution for both
DAQ readout and RoI readout for the CP and the JEP. Results
of building a prototype readout driver (ROD) module will be
presented, together with results of tests on its integration with
level-2 and DAQ modules.
I. INTRODUCTION
The ATLAS Level-1 Calorimeter Trigger is described in
[1]. It consists of three subsystems: the Preprocessor (see
accompanying paper on MCM), the electron/photon and
tau/hadron Cluster Processor (CP), and Jet/Energy-sum
Processor (JEP). The CP and JEP will receive digitised
calorimeter trigger-tower data from the Preprocessor, and will
provide multiplicity information on trigger objects to the
Central Trigger Processor via Common Merger Modules
(CMMs). For a more detailed overview of the trigger, see the
accompanying talk on “One Size Fits All”. Using Readout
Driver (ROD) modules (fig. 1), the CP and JEP must also
provide region-of-interest (RoI) information for the level-2
trigger, and readout data to the data acquisition (DAQ) system
for monitoring and diagnostic purposes.
The ROD modules used for the Cluster Processor and the
Jet/Energy-sum Processor are based on FPGA technology. We
will use one common design for both subsystems, using
appropriate firmware to handle the several different types of
RoI and trigger readout data.
In order to see if such a design is feasible, a prototype
ROD module has been built. We will first summarise the
requirements and functionality of this prototype. The readout
process and hardware implementation are then described,
followed by first test results from both standalone tests and
integration with ATLAS level-2 trigger and DAQ modules.

Cluster Processor Jet/Energy Jet Energy Processor
x4 ◊4 x2 ◊2
C C C
M P P
M M M
14
C T
M C
M M
G-link
T T R R R R R
T T O O O O O
C C D D D D D
v v
x i
S-link
DAQ
JC
J J
M E E
M M M
16
◊2 x2
Level-2
SC
T
M C
M M
Figure 1: Readout path of the Cluster and Jet/Energy Processors.
II. TRIGGER REQUIREMENTS
The CP and JEP find trigger objects of various types for
each bunch crossing, and send the multiplicity for each type to
the Central Trigger Processor. The CP identifies isolated
electron/photon showers (between 8 and 16 sets of thresholds
in ET) and isolated single-hadron/tau candidates (up to 8
threshold sets in ET for a grand total of 16 threshold sets). The
JEP identifies jets above 8 ET thresholds, as well as triggering
on missing-ET, total-ET, forward jets, and total jet ET. Coordinates of all the objects found, as well as the total
value and components of ET, must be sent to the level-2
trigger as RoI information for all bunch crossings which
generate a level-1 trigger in the CTP.
III. READOUT DRIVER REQUIREMENTS
The Readout Driver module collects data from CP
Modules (CPMs and CMMs) and JEP Modules (JEMs and
CMMs). It formats the data and sends it on to the DAQ and to
level-2 (RoIs). The ROD requirements are as follows:
• Collect data from several trigger processing modules
• Read out data from more than one consecutive bunchcrossing
(‘slice’) if required
• Perform error detection on received data
• Process data, including zero suppression when needed
• Format DAQ and RoI data
• Interface to the readout S-link [2]
• Monitor the data sent on the S-link via a spy
• Receive TTC signals and commands [3]
• Interface to CTP (ROD busy signal)
• Operate at level-1 event rate of up to 100 kHz
IV. READOUT PROCESS
Readout data for monitoring trigger operation and
performance comprise the input data and results of the CPMs,
JEMs and CMMs. RoI data for discrete trigger objects comes
from the CPMs and JEMs, and energy-sum results from
CMMs in the JEP. Because level-1 triggers are asynchronous,
we have chosen to use 20-bit G-links [4] to transmit the data
to the RODs, with two links per trigger module — one for
DAQ data and one for RoIs. The RODs receive and buffer the
serialised 20-bit data using a G-link receiver mezzanine board
On receipt of the level-1 accept signal (L1A), the ROD’S
control logic places the event number and the bunch-crossing
number (BCID) generated by the TTC [3] into the event and
the BCID buffer. It also checks how many ‘slices’ (1–5) of
trigger-tower data to read out. When the ROD receives the Glink
Data AVailable (DAV) signal, the controller takes the
event number and the BCID number from these buffers and
places them in the header buffer FIFO and then initiates the
zero-suppression logic. The control logic also checks the
received BCID number against the TTC-generated number
and flags an error if they are not in agreement.
The controller also monitors the Xoff signal from the
DAQ Readout Subsystem (ROS) to stop any data transfer in
case it is getting full. Since the Xoff prevents the data transfer
out of the ROD module, the incoming data may fill the ROD
buffers. In this situation, before the ROD buffers are
completely full the ROD must indicate to the Central Trigger
Processor via the BUSY signal to stop sending data.
The principle of data transfer for the RoIs is the same
except for the bit-field definitions, and the additional
requirement for terminating RoI transmission to level-2 if
there are too many RoIs in the event.
V. IMPLEMENTATION OF THE PROTOTYPE
A ROD prototype has been built in order to demonstrate
the data transfer from multiple data sources to a data sink. The
prototype has four input channels, whereas the final ROD will
probably have 18 channels. Fig. 2 shows its block diagram
and fig. 3 a photograph. Its functionality is as follows:
• Input on 800 Mbit/s G-link Rx daughter cards
• Compare transmitted bunch-crossing numbers with onboard
TTCrx-generated numbers, and set error flag in
readout data if they do not match
• Perform parity check on the incoming data
• Perform zero suppression on trigger-tower data for each
channel, if needed
• Write formatted data to FIFO buffers
• Transmit data to the RoIB and the DAQ Readout
Subsystem using S-link
• Provide an event buffer, accessible via VME, to spy on
the S-link data
• Provide a PCI interface for processing the spy-buffer data
using an FPGA or PCI DCP mezzanine card

The implementation has the following features:
• Triple-width 6U VME module
• Four Common Mezzanine Card positions:
o One G-link (HDMP-1024) 4-channel daughter card
o Two S-link daughter cards
o One position for a commercial PMC co-processor card
• All processing and data-handling carried out by FPGAs
• The same module with different firmware will handle
CPMs, JEMs or CMMs, and DAQ and/or RoI data
• Off-the-shelf S-link card to transfer data out
• Spy on events for monitoring using 32 kbyte buffer
• TTCdec decoder card [5] to interface to TTC system
Note that for testing purposes the ROD can send duplicate
copies of the same fragments in parallel over both S-links.
VME Interface
CH 1
CH 4
XOFF
TCM
Receiver
CMC
G-Link
Rx
D0
D19
G-Link
Rx
TTCrx
DAV
D0
D19
DAV
VME
registers
DAV 1-4
LHC clock
L1A
BCnt[11:0]
BCntStr
BCntRes
Shift register output from the FIFO
Controller
DATA FPGA
Shift register output from the FIFO
Shift register output from the FIFO
DATA FPGA
Shift register output from the FIFO
Dout [7:0]
DQ[3:0]
DoutStr
SubAddr [7:0]
Brcst[7:2]
BrcstStr1
BrcstStr2
Rd-En [0:3]
FPGA
Trigger Type
FIFO
BCID Number n
BCID Number 1
BCID FIFO
Event Number n
Event Number 1
Parity Check
&
Zero
Suppression
Logic
Parity Check
&
Zero
Suppression
Logic
En-Zero suppression
start and end marker
start and end marker
Interrupt to the SBC
ROD Busy
To Header + controller
To Header + controller
Data
Wr-En
Rd-En[0]
Data
Wr-En
Rd-En[3]
Sub-header
Data Buffer
Data Buffer
S-Link (CMC)
Spy Event Buffer
(Selected
Sample for
Local
Monitoring)
FPGA(DSP)
Header
Data
Sub-header
Status Register
Status Count
Data Count
Trailer
S-Link (CMC)
S-Link interface
PCI interface
Spy buffer manager
Interface to Single
Board Computer (SBC)
PCI Interface
Figure 2: Block diagram of prototype ROD module.
A. Standalone test
VI. TEST RESULTS
A Data Source/Sink module (DSS) [5] has been designed
and built, to allow a variety of tests on different modules. The
use of daughter cards allows several different types of data
(1)
(2)
32
ROD Busy
To the SBC via VME
DAQ
RoI
transmitters and receivers to be used. FPGAs on the DSS can
be used to generate pseudo-random data for transmission, and
the data received can be compared automatically with what
was transmitted in order to search for errors at very high
speeds, thus permitting detection of bit errors with very high
sensitivity. Data memories on the DSS are also accessible via
VME for various other types of monitoring.
TTC
TTC
Module
Figure 3: The 6U prototype ROD module.
DSS Module ROD Module
G-Link Tx
(Emulate CPM)
S-Link (D)
(Emulate ROB)
Data
Data/Control Signal
XOFF
G-Link Rx
S-Link (S)
Figure 4: The standalone test setup.
TTC
TTC
Module
For the ROD prototype test, a 4-channel G-link transmitter
card emulated the readout logic for DAQ and RoI data on the
CPMs to feed input data to the ROD, and an S-link receiver
card was used as the destination for output data transmitted by
the ROD. This arrangement is shown in fig. 4.
The DSS firmware was configured to generate a packet of
serial data on the G-links following each level-1 accept
received from the TTC. The packet content was obtained from

an internal DSS memory which was pre-loaded with data
corresponding to a range of RoI content at different stages
during the tests. Data arriving over the S-link was captured in
a 32 kbyte memory and could later be read from VME.
For much of the testing a sequence of closely spaced L1A
signals was generated by a burst-mode pulse generator and
distributed by the TTC system. On each L1A, RoI data were
generated and transmitted by the DSS, received and
reformatted by the ROD, transmitted over S-link, received by
the second DSS daughter card, and captured in DSS memory.
The number of L1As per burst was chosen so that all S-link
RoI packets generated in one burst by the ROD could be
recorded in the DSS memory without overwriting.
For each burst, the recorded S-link data were read out by
the online computer and compared with what was expected.
All events in the burst were different, with a cyclical pattern
used to check correct ROD processing of a variety of RoI
data. The test program could not check the bunch-crossing
number copied into each event from the TTC by the ROD, but
it did check that the event number increased monotonically
through the run.
It was found that this test could routinely be run overnight
without any errors at L1A burst frequencies beyond 800 kHz,
exceeding the required 100 kHz by a large factor. It should be
noted that the DSS could sustain incoming S-link data at the
full speed of the S-link, so did not normally use the S-link’s
flow control features.
B. Integration tests
The primary purpose of the tests was to check that data
could be transferred completely and correctly from the ROD
to both the level-2 RoI Builder (RoIB) [6] module and the
DAQ Readout Subsystem (ROS).
1) Test setup
A diagram of the integration test setup is shown in fig. 5.
At different times, both the RoIB and the ROS received the
data from the ROD prototype. The RoIB consisted of an input
card and the main RoIB card. The input card received S-link
data from the ROD, and then prepared and sent two identical
copies to the RoIB card, which required at least two input
fragments to assemble composite RoI S-link output packets.
The ROS consisted of the interface layer to the complete ROS
subsystem, running on a conventional Pentium-based PC.
Three different physical implementations of the S-link
were available for use in the tests. All tests with the RoIB
used an electrical cable link developed at Argonne National
Laboratory (ANL). The links from ROD to DSS were the
CERN electrical S-link, and the link to the ROS used the
ODIN optical S-link [2].
2) Results of low-rate tests with RoI Builder
For tests with the RoIB, events were transferred in bursts,
and the L1A frequency gradually raised until errors occurred,
which on investigation proved to be related to incomplete
implementation of the S-link flow control protocol.
DSS ROD
Glink Tx
CMC
Slink Rx
CMC
TTC
GlinkRx
CMC
SlinkTx
CMC
SlinkTx
CMC
PC PC ROS
ROS
Slink/PC
Slink I Rx
CMC
RoIB:
Input RoI Boar Board
B d B d
Slink Rx
CMC
Figure 5: Schematic view of the integrated test installation.
Testing then continued at lower frequencies, where the
protocol errors did not appear. An overnight run with 124byte
events containing 16 RoIs was successfully completed
without error. The events were generated in bursts of 1024,
2 ms apart in a 3 s cycle, which averaged 418 Hz. In total,
2.1×10 7 events, corresponding to 2.1×10 10 bits, were sent and
received without error. The 1024 events in each burst were all
different in their RoI content. No events were lost and none
was duplicated.
3) ROD BUSY performance
Data entering the ROD from the four serial G-links were
processed and placed into four FIFOs to await readout. A
BUSY threshold inside the ROD was constantly compared
with the occupied depth of each FIFO, leading to assertion of
the front-panel BUSY signal whenever one or more of the
FIFOs was filled up to or beyond the threshold level. The
normal operation of the BUSY signal provided a useful tool to
monitor the ROD performance.
Figure 6: Timing relationship between L1A (upper trace) and BUSY
signal (lower trace), for 16 RoIs. The busy threshold is set at 3.
Fig. 6 shows the behaviour of the BUSY signal when the
threshold was set to the artificially low value of 3. This
threshold was reached as soon as 3 RoIs had entered the

FIFOs, and remained asserted until the depth of the last FIFO
to be emptied fell below 3 again. For events with 16 RoIs, the
theoretical minimum busy time (to transfer 13 RoIs over the
S-link) is 325 ns. This is in good agreement with the measured
time of approximately 400 ns.
4) Latency measurements
The latency of the system was measured using the above
configuration and monitoring various test points using a
digital oscilloscope. The test points included the L1A, DAV,
ROD BUSY and S-link control bit (LFF). The readout
sequence is illustrated in fig. 7, for events with 8 RoIs.
Transmission on the S-link started 2100 ns after the original
L1A. The complete sequence of timing is shown in fig. 8. The
total time to the input of the RoIB is less than 3 µs. The ROD
itself has a latency of less than 1 µs.
LVL1A
S-link
LFF
Busy
Figure 7: Readout latency in the DSS/ROD system for 8 RoIs.
L1A to TTC L1A from TTC DAV BOF LFF on LFF off
TTC
DSS
G-Link
CPROD
S-Link
RoIB
150 450 550 950 525 1750
>4 x 25 =100 22 x25=550 23 x25=525 >23 x 66.6 = 1533
2625
Figure 8: Overall timing from L1A to end of RoIB
input card readout.
ns Measured
Expected
5) Tests with the Readout Subsystem
For testing with the ROS, the S-link interfaces used the
ODIN optical S-link. It was found that event frequencies of up
to 20 kHz could be sustained into the ROS with full event
checking, and that instantaneous L1A frequencies of up to
660 kHz could be sustained, in bursts of 127 events.
Very careful control of the ROD was necessary. The DSS
module needed to be reset after each burst of events, and the
checking software required an exact repeating sequence of
127 events. It was therefore not possible to use the BUSY
signal to suppress L1As if the ROD memories became full, so
it was essential to wait for the ROD FIFOs to empty
completely before triggering the next event burst. This
constraint had not been fully appreciated before the test, and
has implications for future development of the DSS firmware
and other supporting test hardware.
6) Combined tests with the RoIB and ROS
A series of short tests were made with data transmitted
over S-link both to the RoIB and to the ROS. This represented
exactly the connectivity to be used in the production trigger,
where the RoI fragments will be sent both to the RoIB and to
the main DAQ readout system.
Running with bursts of 127 different events spaced 1 ms
apart, several runs of about 2M events were performed, after
which the first data error typically appeared. The same errors
were detected by software in the RoIB and ROS. Investigation
revealed a firmware problem related to the emptying of the
ROD FIFOs. This was understood, but it was not possible to
obtain a new firmware version before the end of the tests. This
test nevertheless established that the ROD could transfer Slink
data concurrently to two downstream modules.
VII. CONCLUSIONS
The prototype ROD is one of the first ATLAS trigger
modules to show the feasibility of flexible design using FPGA
technology. Firmware can be dedicated to either DAQ or RoI
readout. Test results have shown that data could be passed at
rates higher that the required level-1 rate with no errors
detected over long runs. No hardware design fault was found
and the problems occurred in the firmware, which can be
easily corrected.
The integration test with downstream modules was
essential to the understanding of the interfaces between level-
1 and the level-2 and dataflow (ROS) systems. Tests were not
complete and further work still needs to be done, but good
experience has been gained and first results are very
encouraging.
REFERENCES
[1] ATLAS First-Level Trigger Technical Design Report,
CERN/LHCC/98-14 and ATLAS TDR-12, 30 June 1998:
http://atlasinfo.cern.ch/Atlas/GROUPS/DAQTRIG/TDR/t
dr.html
[2] CERN S-link Specification:
http://www.cern.ch/HIS/s-link
[3] Timing, trigger and control system (TTC):
http://www.cern.ch/TTC/inro.html
[4] Agilent G-link information:
http://www.semiconductor.agilent.com:80/cgibin/morpheus/home/home.jsp
[5] Calorimeter trigger modules:
http://hepwww.rl.ac.uk/atlas-l1/Modules/Modules.html
[6] R.E. Blair et al., A Prototype RoI Builder for the Second
Level Trigger of ATLAS Implemented in FPGAs,
ATLAS note ATL-DAQ-99-016, December 1999.

Prototype Slice of the Level-1 Muon Trigger in the Barrel Region of the
ATLAS Experiment
V.Bocci, G.Chiodi, S.Di Marco, E.Gennari, E.Petrolo, A.Salamon, R.Vari, S.Veneziano
Abstract
The ATLAS barrel level-1 muon trigger system makes use
of the Resistive Plate Chamber detectors mounted in three
concentric stations. Signals coming from the first two RPC
stations are sent to dedicated on detector ASICs in the low-pT
PAD boards, that select muon candidates compatible with a
programmable pT cut of around 6 GeV, and produce an output
pattern containing the low-pT trigger results. This information
is transferred to the corresponding high-pT PAD boards, that
collect the overall result for low-pT and perform the high-pT
algorithm using the outer RPC station, selecting candidates
above a threshold around 20 GeV. The combined information
is sent via optical fibre to the off-detector optical receiver
boards and then to the Sector Logic boards, that count the
muon candidates in a region of ∆η×∆φ=1.0×0.1, and encode
the trigger results. The elaborated trigger data is sent to the
Central Trigger Processor Muon Interface on dedicated
copper link. The read-out data for events accepted by the
level-1 trigger are stored on-detector and then sent to the offdetector
Read-Out Drivers via the same receiver boards used
for trigger data, sharing the bandwidth.
A trigger slice is made of the following components: a
splitter, a low-pT PAD board, containing four Coincidence
Matrix boards; a high-pT PAD board, containing 4 CM boards
and the optical link transmitter; an optical link receiver; a
Sector Logic board; a Read-Out Driver board.
I. THE ATLAS BARREL LEVEL-1 MUON TRIGGER
The ATLAS muon spectrometer in the barrel, which
covers a pseudorapidity region equal to |η| < 1.05, makes use
of the Multi Drift Tube detectors for particle track precise
measurement, and the Resistive Plate Chamber detectors for
triggering.
The barrel first level muon trigger has to process the full
granularity data (about 350.000 channels) of the trigger
chambers [1]. The latency time is fixed and less then 2.5 µs.
The maximum data output frequency to the higher-level
triggers is 100 kHz.
A. Trigger Algorithm
Level-1 trigger main functions are:
− identification of the bunch crossing corresponding to
the event of interest;
− discrimination of the muon transverse momentum pT;
INFN Sezione di Roma, P.le Aldo Moro 2, 00185 Rome, Italy
Riccardo.Vari@roma1.infn.it
− fast and coarse muon tracking, used for higher-level
trigger processors;
− second coordinate measurement in the non-bending
projection with a resolution of ~1 cm.
The level-1 trigger is able to operate with two different
transverse momentum selections, providing a low-pt trigger
(pT ~ 5.5 GeV), and a high-pT trigger (pT ~20GeV).To
reduce the rate of accidental triggers, due to the low energy
background particles in the ATLAS cavern, the algorithm is
performed in both η and φ, for both low-pT and high-pT
triggers. Barrel precision MDT chambers can only measure
the bending coordinate, thus the φ projection is used to give to
the experiment the non-bending muon coordinate with a
resolution of ~1 cm. The measured non-bending coordinate is
used in addition with the data coming from MDT detectors for
precise particle track reconstruction.
A section view of the trigger system is represented in
Figure 1, showing where the three RPC stations are located
inside the ATLAS Muon Spectrometer. The ATLAS muon
trigger system is composed by three RPC stations. The RPC
detectors are mounted on the MDT chambers.
Figure 1: The ATLAS Muon Spectrometer Layout
Each RPC chamber is readout by two planes of orthogonal
strips. The η strips give the bending projection, while the φ
strips give the non-bending one.
Muon pT selection is performed by a fast coincidence
between strips of different RPC planes. The number of planes
in the whole trigger system has been chosen in order to
minimise accidental coincidences and to optimise efficiency.
For accidental counting reduction, the trigger operates in both
bending and non-bending projection.

Figure 2 shows the trigger scheme. The low-pT algorithm
makes use of information generated from the two Barrel
Middle stations RPC1 and RPC2. The first stage of the
algorithm is performed separately and independently in the
two η and φ projections. If a track hit is generated in the
RPC2 doublet (pivot plane), a search for the same track is
made in the RPC1 doublet, within a window whose centre is
defined by an infinite momentum track coming from the
interaction point. The width of the window is programmable
and selects the desired cut on pT (the smaller the window, the
higher the cut on pT). Three programmable pT thresholds in
each projection can be applied simultaneously. To cope with
the background from low energy particles in the cavern, a
majority coincidence of the four hits of the two doublets in
each projection is required.
The high-pT algorithm makes use of the result of the lowpT
trigger system and the hits available in the RPC3 station. A
coincidence between the 1/2 majority of the RPC3 doublet
and the low-pT trigger pattern is required.
Figure 2: The ATLAS Barrel Level-1 Muon Trigger
B. Trigger Segmentation
The ATLAS barrel trigger system is composed of two
independent trigger subsystems, the first in the region of
positive η values, called barrel system 0, the second, the
barrel system 1, in the negative η region [2]. Each barrel
subsystem(6.7m

Four low-pT CMAs, covering a total region of ∆η×∆φ ~
0.2×0.2, are mounted on a low-pT PAD board, the four highpT
CMAs are mounted on a high-pT PAD board. The low-pT
PAD board collects data coming from the four low-pT CMAs,
and sends trigger data to the high-pT PAD board, which
collects low-pT and high-pT data and serially sends data offdetector
via an optical fibre. The optical receiver, located in
the counting room, receives serial data from the optical fibre,
and sends them to the Sector Logic board and to the Read-Out
Driver.
The on-detector electronics will be mounted on top on the
RPC detectors as shown in Figure 6. A Splitter Box contains
two or three splitter boards, depending on the required fanout.
In order to reduce the number of interconnections, each
couple of φ strips in one RPC detector belonging to two
adjacent RPC chambers is wire or-ed on detector.
Figure 6: Schematic view of a Barrel Middle RPC station
A. Coincidence Matrix ASIC
The CMA is the core of the level-1 trigger logic, its main
functions are:
− incoming signal timing alignment;
− input and output signal masking;
− de-clustering algorithm execution;
− majority logic;
− trigger algorithm execution;
− level-1 latency memory data storing;
− readout data formatting, storing and serial
transmitting.
A schematic view of the chip internal architecture and its
main block division is represented in Figure 7.
The CMA can be programmed to perform either the lowpT
or the high-pT trigger algorithm. The chip can be used as a
η CMA, covering a region ∆η×∆φ ~0.2×0.1, or as a φ CMA,
covering a region of ∆η×∆φ ~0.1×0.2.
The chip has 2×32 + 2×64 inputs for the front-end signals
[4]. In the low-pT CMAs the 2×32 inputs are connected to the
front-end signals, either η strips or φ strips, coming from a
doublet of the RPC2 pivot plane, while the 2×64 inputs are
connected to the signals coming from the RPC1 doublet. For
the high-pT CMAs the first 32 inputs are connected to the
output trigger signals coming from the low-pT PAD board, the
second 32 inputs are not used, while the 2×64 inputs are
connected to the signals coming from the RPC3 doublet.
The CMA aligns in time the input signals in step of oneeight
of a bunch crossing period. For this reason the chip
internal working frequency is 320 MHz, eight times the 40
MHz bunch crossing frequency. Input signals can be masked
to the zero logic in order to be able to suppress noisy channels
and to handle unconnected input signals.
RPC average cluster size is ~1.4, hence input signals are
pre-processed and de-clustered in order to sharpen the pT cut.
Themaximumclustersizetobeprocessedinthede-clustering
logic is programmable.
Processed input signals are sent to the coincidence logic,
which performs the coincidence algorithm. The logic is
repeated three times, so that three different coincidence
windows can be simultaneously applied inside the chip. The
three coincidence windows can be independently
programmed, thus providing three different muon pT cuts.
Coincidence logic inputs can be masked to “one” logic, to
simulate unconnected inputs. A programmable majority logic
can be applied to the coincidence algorithm, choosing a 1/4,
2/4, 3/4 or 4/4 plane confirmation. The 32-bit trigger output
pattern is then sent to the chip outputs.
Figure 7: CMA block scheme
The CMA readout logic collects chip input data and
trigger output data in a latency memory, used to store events
during level-1 latency period [5]. Data corresponding to one
event are accepted according to the Level-1 Accept signal
arrival time and to the programmed acceptance window time.
All other hits are discarded, while level-1 validated data are
formatted and sent to de-randomising buffers for the serial
readout.
The CMA chip has ~ 300 internal registers programmable
via I 2 C bus. Single Event Upset detection logic has been
implemented for all registers, redundancy logic has been
implemented for critical control registers.
CMA design has been realized with a 0.18 µm CMOS
technology. The external clock frequency is 40 MHz, the
internal working frequency is 40 MHz for register
initialisation, 320 MHz for the pipeline and trigger logic, 160
MHz for the readout logic. An internal PLL has been used for
clock frequency multiplication. JTAG boundary and scan
chain logic has been implemented for test purposes. The
CMA has ~ 500.000 basic cells, including ~ 80 kbit of
internal memory. Chip area is ~ 20 mm 2 , power dissipation is

B. PAD Logic boxes
The first step of the trigger algorithm is performed
separately in the η andintheφ projections. Four CM boards,
each one mounting one CMA, are plugged on one PAD board,
which is responsible to collect data coming from two η CMAs
and two φ CMAs, to elaborate incoming data and to associate
muon candidates in the Region-Of-Interest ∆η×∆φ ~0.1×0.1.
Globally the PAD logic board covers a region ∆η×∆φ ~
0.2×0.2. A dedicated FPGA chip performs the PAD logic. It
combines η and φ information, selects the higher triggered
track in one RoI and solves overlaps inside the PAD.
Timing, trigger and control signals are distributed in the
PAD boards from the TTCrx ASIC, which will be mounted on
a dedicated plug-in board.
In the low-pT PAD board, which is mounted on the RPC2
detector, low-pT trigger result and the associated RoI
information is transferred, synchronously at 40 MHz, to the
corresponding high-p T PAD board via copper cables, using
LVDS signals. LVDS driver and receiver chips are mounted
on the PAD board. The high-pT PAD board, which is mounted
on the RPC3 detector, is similar to the low-pT one. It performs
the high-pT algorithm, collects the overall result for both the
low-p T and the high-p T trigger and sends the readout data to
the Read Out Driver via optical link. The custom built optical
link is mounted on a dedicated board to be plugged on the
high-pT PAD board.
The Embedded Local Monitor Board, a general-purpose
CANBUS plug-in board (CERN & Nikhef project) is used in
both the PAD boards for JTAG and I 2 C chip initialisation and
for local control and monitoring.
Each PAD board is enclosed in a liquid cooled PAD Box
that will be mounted on the RPC detector.
C. Off-detector electronics
The optical link board in the high-pT PAD box transmits
the trigger and readout data to the receiver board located in
the USA 15 counting room. One Receiver board receives the
inputs from four optical links and sends the output to the
Sector Logic board and to the Read Out Driver board.
Proposed crate for containing Receiver boards, ROD
boards and Sector Logic boards is 6U VME 64X format. A
single crate contains 8 Receiver boards, 4 Sector Logic
boards, 2 ROD boards and a ROD controller, as shown in
Figure 8.
The Sector Logic covers a region ∆η×∆φ =1.0×0.2, each
SL board receives data from 7 high-pT PAD logic boards in
the small sectors and 6 high-pT PAD logic boards in the large
sectors [6]. It maps the signals coming from the Tile
Calorimeter trigger towers to the triggered muons, it performs
outer plane confirmation for all the three low-pT thresholds, it
solves the η overlap inside the sector, it selects the two higher
thresholds triggered in the sector, associating with each muon
a region of interest ∆η×∆φ ~1.0×0.1.
The outputs from the Sector Logic boards are sent to the
Muon Central Trigger Processor Interface via parallel
differential LVDS links.
LAN
CPU (DAQ/DCS)
MUCTPI
FE link
Sector logic
Data/Trigger RX
Data/Trigger RX
ROD
Data/Trigger RX
Data/Trigger RX
Sector logic
RO link
TTC RX
Sector logic
Data/Trigger RX
Data/Trigger RX
ROD
Data/Trigger RX
Data/Trigger RX
Sector logic
ROD_BUSY
Figure 8: Off-detector crate with the contained VME cards
III. RADIATION ASSURANCE
Radiation effects for the level-1 muon trigger electronics
have to be taken into account, since on-detector electronics
will be mounted on the RPC detectors. Radiation levels for
the RPCs have been simulated, Figure 9 and Figure 10 show
the simulated total dose and the > 20 MeV neutron
distribution inside the experiment.
Pre-selection and qualification of electronic components
have to be made following the ATLAS Standard Test
Methods [7]. Components have to be qualified for Single
Event Effects and for Total Ionising Dose.
The ATLAS Radiation Tolerance Criteria for TID is:
RTCtid =SRLtid ·SFsim ·SFldr ·SFlot ·10y,wheretheSafety
Factors depend on simulation accuracy, low dose rate effects
and components lot differences. The Simulated Radiation
Levels for the RPC are shown in Table 1. The resulting RTCtid
is of the order of 1 krad, depending on the electronics
component type.
For Single Event Upsets the foreseen soft SEU rate is:
SEUf =(softSEUm /ARL)·(SRLsee /10y)·SFsim, where
SEUm is the number of measured soft SEU during test, and
the Applied Radiation Level is the integrated hadrons flux
received by the tested component.
SEE and TID pre-selection test have been completed for
almost all the electronics components that will be mounted on
the RPCs. All tested components successfully passed the
radiation tolerance criteria. No Single Event Latchup was
observed, and the foreseen soft SEU frequency for the
components that had SEU is low enough for not
compromising trigger functionality. All tested components
functionality was not altered after the maximum foreseen total
dose.
A few components have still to be tested. Final component
pre-selection is supposed to be completed during 2002.

Figure 9: ATLAS Simulated Total Ionisation Dose
Figure 10: ATLAS Simulated Hadrons Distribution
Table 1: ATLAS Barrel RPC Radiation Levels
SIMULATED RADIATION LEVEL
SRLtid [Gy·10y -1 ]
SRLniel [1 MeV n·cm -2 ·10y -1 ]
BMF 3.02 2.49·10 10
BML 3.04 2.82·10 10
BMS 3.03 2.50·10 10
BOF 1.19 2.14·10 10
BOL 1.33 2.20·10 10
BOS 1.26 2.10·10 10
SRLsee [> 20 MeV h·cm -2 ·10y -1 ]
4.69·10 9
5.65·10 9
4.73·10 9
4.08·10 9
4.21·10 9
4.10·10 9
IV. CONCLUSIONS
All prototype components produced up to now
successfully passed lab tests. Coincidence Matrix ASIC is
missing to complete the Trigger Slice, and is planned to be
available by the end of 2001. Further test on RPC chambers
on cosmic ray is planned before having the CMA.
A C++ high-level simulation code for the level-1
electronics is being developed for trigger functionality
confirmation. CMA VHDL simulation has been compared
with C++ simulation, giving good crosscheck results.
Irradiation test for components pre-selection and
qualification are planned to be finished before the end of
2002. First slice test will be performed during year.� next
V. REFERENCES
[1] ATLAS Level-1 Trigger TDR
[2] E. Gennari, S. Di Marco, A. Nisati, E. Petrolo,
A. Salamon, R. Vari, S. Veneziano
Barrel Large RPC Chamber Sectors Readout and
Trigger Architecture
[3] E. Petrolo, A. Salamon, R. Vari, S. Veneziano
Barrel LVL1 Muon Trigger Coincidence Matrix ASIC
User Requirement Document (ATL-COM-DAQ-2000-
050)
[4] E. Petrolo, A. Salamon, R. Vari, S. Veneziano
CMA ASIC Hardware Requirement document (ATL-
COM-DAQ-2001-005)
[5] E. Petrolo, A. Salamon, R. Vari, S. Veneziano
Readout Requirements in the Level-1 Muon Trigger
Coincidence Matrix ASIC (ATL-COM-DAQ-2000-052)
[6] V. Bocci, A. Di Mattia, E. Petrolo, A. Salamon, R. Vari,
S.Veneziano
The ATLAS LVL1 Muon Barrel Sector Logic
demonstrator simulation and implementation (ATL-
COM-DAQ-2000-051)
[7] ATLAS Policy in Radiation Tolerant Electronics
http://atlas.web.cern.ch/Atlas/GROUPS/FRONTEND/ra
dhard.htm

Fast Pre-Trigger Electronics of T0/Centrality MCP-Based Start Detector for
ALICE
L.Efimov 1 ,G.Feofilov 2 , V.Kondratiev 2 ,V.Lenti 3 ,V.Lyapin 4 , O.Stolyarov 2 , W.H.Trzaska 4 ,
F.Tsimbal 2 , T.Tulina 2 , F.Valiev 2 , O.Villalobos Baillie 5 , L.Vinogradov 2
1 JINR, Dubna, Russia, Joint Institute for Nuclear Research
2 St.Petersburg, Russia, Institute for Physics of St.Petersburg State University
Ulyanovskaya,1, 198904, Petrodvorets, St.Petersburg, Russia, e-mail: feofilov@hiex.niif.spb.su
3 Bari, Italy, Dipartamento di Fisica dell’Universi ta and Sezione INFN
4 Jyvaskyla University,Finland
5 Birmingham, United Kingdom, University of Birmingham, School of Physics and Astronomy
Abstract
This work describes an alternative to the current AL-
ICE baseline solution for a TO detector, still under development.
The proposed system consists of two MCPbased
T0/Centrality Start Detectors (backward-forward
isochronous disks) equipped with programmable, TTC
synchronized front-end electronic cards (FEECs) which
would be positioned along the LHC colliding beam line
on both sides of the ALICE interaction region. The purpose
of this arrangement, providing both precise timing
and fast multiplicity selection, is to give a pre-trigger signal
at the earliest possible time after a central event. This
pre-trigger can be produced within 25 ns. It can be delivered
within 100 ns directly to the Transition Radiation
Detector and would be the earliest L0input coming to the
ALICE Central Trigger Processor. A noise-free passive
multichannel summator of 2ns signals is used to provide a
determination of the collision time with a potential accuracy
better than 10ps in the case of Pb-Pb collisions, the
limit coming from the electronics. Results from in-beam
tests confirm the functionality of the main elements. Further
development plans are presented.
I. INTRODUCTION
A fast pre-trigger decision (which can be made within
one 25 ns bunch crossing) for the ALICE experiment at
the LHC should handle the following functions([1]):
(i) precise T0 determination (better than 50-100 ps
resolution);
(ii) centrality of the collision determination;
(iii) min-bias pre-trigger production within 100 ns after
the collision for the Transition Radiation Detector;
(iv) coordinate of primary vertex (indication of collision
with the interaction diamond);
(v) beam-gas interaction signal;
vi) indication of the pile-up signal.
These functions could be combined into one logic signal
or a set of signals forwarded to the Central Trigger
(For the ALICE collaboration)
Processor (CTP).
This work is a continuation of [2] and [3], combining
both the upgrade of the functional pre-trigger scheme, new
developments and the in-beam test results of the fast detector
and electronics.
II. FUNCTIONAL SCHEME
The fastest pre-trigger decision in the ALICE detector
could be made using the information from two
T0/Centrality disks covering 2.5-3.5 regions of pseudorapidity
on both sides of interaction region. The system is
based on the application of Microchannel Plates (MCPs).
The signals from these MCP detectors are very short (less
than 2 ns at the base), they allow very precise timing and
their pulse height is proportional to the multiplicity. It is
possible to use these features for the fastest preliminary
decision making done by the ALICE pre-Trigger. The extremely
good timing resolution and counting rate properties
of the MCP-based detector implies the possibility to
obtain the first fast indication of a central event within two
neighbouring 25 ns bunch crossings in case of pp collisions.
A. Detector
Detectors are placed symmetrically on both sides of
the interaction region [4]. They are hermetically sealed inside
thin-wall disk vacuum chambers. A multianode MCP
isochronous readout system provides the needed high accuracy
in timing measurements. Passive summation of
signals from the anode of the segmented MCP disk gives
a multiplicity signal with very precise timing properties.
The pre-trigger decision is based on the information obtained
for each bunch crossing on the total multiplicity for
the event in a given rapidity range (2.6-3.6), primary vertex
Z-location within the interaction region , while permitting
the rejection of beam gas events. A general functional
scheme of a fast trigger is shown in Figure 1.

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Figure 1: Functional scheme of ALICE pre-trigger T0/Centrality detectors and electronics. Two MCP based disks are situated on
both sides (”backward-forward”) of the interaction region. The ALICE’s Inner Tracking System (ITS), Time Projection Chamber
(TPC) and Transition Radiation Detector (TRD) are shown schematically (not to scale). SUM - passive multichannel summator
of short 2ns pulses; FA - fast amplifiers; FFO - fast fan-out; DTD - Double Threshold TimingDiscriminator; TDC,QDC - time
and charge digital converters; MD - fast multiplicity discriminator; L0*T0 -Fast Programmable Logic Unit.
B. General Scheme
The new scheme of the fast front-end electronics (AL-
ICE L0trigger electronics or ALICE pre-trigger) integrated
for each half of two MCP T0/Centrality disks into
one Front-End Electronics Card (FEEC) is represented
here in Fig. 1. The scheme is based on the passive multichannel
summator application which is integrated into the
detector design providing the noiseless precise summation
and isochronous timing for a large area MCP disk while
preserving the charge information.
As previously mentioned [1], precise timing from a
large area detector implies a high granularity of the detector
elements (cells) This is because individual elements
must be small in order to minimize the signal propagation
spread within a given cell. Using the most straightforward
approach, one would have to develop about 300 fast electronics
channels with very high precision timing properties
matching the total number of pads in a MCP disk that
covers 1 unit of pseudorapidity. In order to simplify the
task, we propose to use the isochronous summation of signals
from many pads belonging to one disk, preserving the
timing precision and good linearity of the pulse heights.
The proposed use of noise-free passive isochronous summators
has the advantage of a strong decrease in the number
of electronic channels and simplifies considerably the
fast logic for multiplicity and timing. The analogue signal
from the passive UHF summator output is used for the
LO trigger applications (see splitter FFO on the Fig. 1).
In general the duration of a signal from the MCP detector
is about 2 ns with 200-300 ps peaking time. This implies
a UHF requirement for the design and development of the
fast electronics (1GHz frequency range).
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C. Fast Front-End Electronics Cards
Each FEEC integrates preamplifiers , QDC chips, pipeline
FIFO and new type fast TDC chip (we supposed to
apply the developments started in[5]). FEEC contains also
the interface between the L0-Trigger electronics and DAQ
system.
The FEECs are situated close to the T0/Centrality
MCP disks providing service to one half of the disk or for
the whole disk ( a baseline option). The FEEC contain
the following (programmable) units:
(i) fast input signal splitters (FFO) matched in
impedance with transmission lines coming from the fast
pre-amplifiers (50Ohm) and the inputs to discriminators;
(ii) a fast analogue single threshold discriminator for
multiplicity analysis (MD);
(iii) a fast timing discriminator (TD) which provides
precise time mark of the incoming analogue sum signal for
agivenMCPhalf-disk;
(iv) a fast TDC for precise timing of the incoming signal;
(v) a fast 8 bit QDC for charge digitization of the signal
for a given disk.
(vi) a pipe-line for storing the MCP disk data during
the L0decision making. Only about 240bytes per card are
required for storage of data from all 40MHz bunch crossings
during 3mks time.(Here we apply some extra margins).
(vii) The FEEC also provides the place for the TTC
adaptors (TTCrx chip) and elements for the connection to
the DDL. (This should be developed in the future using
the standard approach for ALICE.)

D. Functions
Centrality of collisions:
We use the pulse height analogue sum from the MCP disk
to make selections based on multiplicity. This is done
by a fast Multiplicity Discriminator [6] which gives the
logic signal as an indication of high multiplicity event. A
minimum-bias pre-trigger signal could be delivered within
100 ns directly to the ALICE Transition Radiation Detector
(the TRD start). Selection on multiplicity, which is
done by the fast Multiplicity Discriminator(MD), would
provide the earliest L0input signal coming to the Central
Trigger Processor [8].
Event vertex location:
The fast vertex determination is done by time of flight
difference measurements (50ps timing resolution is to provide
about 1.5 cm accuracy).
Precise T0 signal for TOF system:
The general LHC TTC distribution (“the LHC clock”)
is included as the most efficient and independent “start”
signal in TOF measurements for each of MCP disk detectors.
Any possible TTC jitter would not affect these timing
measurements results because the present design implements
isochronous measurements done using two disks.
Proposals for a TOF measuring system using very fast
time-to-digital precise converters (TDC) were suggested
earlier [3]
A precise T0signal could be supplied in two ways:
1) By the hardware electronics (”meantimer” device)
that is supposed to provide the T0relevant to the collision
vertex coordinate Z.
2) By software TOF off-line data treatment using precise
“left” and “right” T0data obtained by the relevant
TDCs. This is considered as the most suitable option.
Pre-trigger signal:
Logic signals L0*T0*Centrality from the TDC and from
the multiplicity discriminator are the result of two criteria
(multiplicity and vertex location)being satisfied for each
MCP disk. The Programmable Fast Coincidence Logic
(PL) provides the necessary logic decisions concerning
the location within the interaction diamond, pile up and
beam-gas interaction logical signals. A pipe-line of about
120cells depth is proposed to store the 8 bit multiplicity
information from individual disk Thus the reliability of
the fast L0decisions can be monitored and the multiplicity
data for a given selected event fed to the DAQ.
“Wake-up” signal for TRD
Two Programmable Logic (PL) units (left and right)
placed near the MCP disks are connected by 1.5m cable
passing outside the ITS cylinder surface. This thin
signal cable is used for the transfer of the minimum bias
MD logical signals. Another two signal cables (left and
right) transfer the TDR pre-trigger signals to the left
and right parts of the TRD pre-trigger signal distribution
system (SDS). We suppose that 10m cable length is a
reasonable estimate to get a signal from the T0/centrality
PL card to the input of the TDR SDS providing 60-80ns
delay after the collision.
T0/Centrality MCP Detector Data Link
The simplest evaluations of the T0/Centrality MCP Detector
Data Link (DDL) feasible distribution have been
made taking into account total amounts of data from the
detector (240bytes/event), a limitation for a total readout
time (< 140 µsec) and a suggested DDL transfer rate (100
MBytes/sec). Only one DDL is sufficient for the start
detector.
Central Trigger Processor(CTP) User Requirements
The L0decision, - as formulated in [8] - is to be done
by the CTP within 1.2 µs which is limited by the signal
propagation time from the detector to the trigger crate.
This means that (i) the minimal depth of the FEEC pipeline
should provide at least 1.2µs storage time and that
(ii) the “wake-up”signal for the TRD should be generated
by the FEEC logic and submitted by the shortest way to
the TRD Signal Distribution System within the required
100ns limit after the collision.
III. SIMULATION
Numerical estimates of the ALICE MCP-disks pretrigger
efficiency were obtained for various colliding relativistic
nuclei at LHC energies. The existing detector
response functions and signal shapes, experimental noise
levels of the electronics, measured values of efficiency for
MIPs, gamma and neutral particle detection were taken
into account. Results are shown in Fig. as a function of
start detector general efficiency. One can see that in case
of O–O,Ar–Ar,Kr–Kr,Sn–Sn and Pb–Pb collisions the pretrigger
efficiency will be 100% even for small acceptance
detectors. However, in case of pp collisions HIJING and
PYTHIA event generators produce considerably different
predictions in terms of multiplicity and trigger efficiency.
This brings the requirement of 100 % geometrical efficiency
for any detector applied as ALICE start counter in
case of possible low multiplicity events studies. Estimates
for high multiplicity events show that with suitable electronics
a limiting time resolution better than 10ps could
be achieved (see Fig. 3). These very promising estimates
confirm the use of a noise-free summation concept.

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Results of in-beam tests at CERN of the main system
elements, including the fast summators, preamplifiers, MD
and the DTD, confirmed their functionality. A measured
value of 75 ps timing resolution was achieved for MIPs during
our in-beam tests at CERN PS, close to the predicted
result for a single particle.
The same electronics was used in the first in-beam
studies of multiplicity events done with MCP detector.
The measurements were performed at the SPS with proton
40GeV/c beams using a 5cm Pb target positioned
in front of the detector. QDC spectra are shown at the
Fig.5. The low curve is obtained without any target and
demonstrates a single particle detector response function.
The high multiplicity events were obtained with Pb target
positioned in the beam 13cm from the detector (the upper
curve). This spectrum is in line with the first simulations
showed wide distribution expected in this case (multiplicities
up to 20are predicted for the given dynamic range).
VI. PLANS
Further developments of the electronics are foreseen:
A). Development of the electronic card (FEEC) including
the following fast analog devices : MD,DTD,
preamplifier-shaper for 2ns signals timing preamplifier,
FFO and gain variation unit.
b). Investigation of different ASIC -Application Specific
Integrated Circuits) with embedded PL - (Programmable
Logic) based configurations for making high
speed (40MHz clock) pre-triggers and precise (50ps resolution)
pipe-lined TOF measurements;
c). The search and study of a suitable schematic approach
to charge-to-digital conversion arrangement for the
40MHz pipe-lined measurement of the charge accumulated
by MCP disk ;
B. Concept investigation, design and layout of Detector
Data Link/Source Interface Unit protocol and schematic
drawings (DDL/SIU) for its arrangement in the MCP
front-end electronics :
a). Data readout algorithms and circuitry implementation
in FEE.
b). Control algorithms and circuitry implementation
in FEE.
C. The investigation and adaptation to the MCP
FEEC of the LHC Synchronizing Clock System interface.
D. The concept and initial schematic design of the standard
bus-based Fast Programmable Modular Units (PL)
for integrated pre-triggers assembling aimed at making
ALICE Pre-trigger and Veto signals.
VII. CONCLUSIONS
1) New functional scheme of the pre-trigger electronics
with very promising features has been developed.
2) The upgraded technology of the microelectronic passive
summator integrated with the fast MCP based detector
is successfully tested.
3) Results of the in-beam tests of multichannel passive
summator and standard available fast electronics modules
(timing discriminators, QDC,TDC) developed for other
applications confirm the expectations coming from simulations
of timing resolution and multiplicity signal measurement(75ps
timing resolution is obtained for MIP registration,
the 1st multiplicity spectra with Pb target were
obtained).
4) Further plans involve the development of the FEEC
and continuation of the in-beam studies at high multiplicity
environment.
Acknowledgements: Authors are indebted to NA57
Collaboration for the support of these studies, to L.Ulrice
and L.Dimovasili for their help with targets during the
in-beam tests at CERN, to J.Stachel, G.Valenti and
C.Williams for their interest and useful discussions. This
job is partially supported by the International Science
and Technology Center, Grant No.1666 and by grant from
Higher Education Ministry of Russian Federation No.520.
References
[1] ALICE Technical Proposal, CERN/LHCC 95-71,
LHCC/P3, Chapters 7,9,10, 15 December 1995
[2] L.G.Efimov et al., Proceedings of the 2nd Workshop
on Electronics for LHC Experiments, Balatonfured,
September 23-27, p.166-169, 1996; CERN/LHCC/96-
39
[3] L.G.Efimov et al., Proceedings of the 3rd Workshop
on Electronics for LHC Experiments, London,
Sept.1997, p.359-363, 1997; CERN/LHCC/97-60
[4] M.A.Braun et.al., ALICE Technical Design Report
for T0/Centrality MCP-Based Start Detector,
ISTC#Technical 1666 Report, St.Petersburg, June
2001
[5] M.Mota, J.Christiansen, see Abstr./Summaries of the
3-rd Workshop on Electronics , 1997 London
[6] L.Efimov et al., ”Fast Multiplicity Discriminator”,
7th Workshop, LEEC-2001,
[7] C.Neyer, Proceedings of the 3rd Workshop on
Electronics for LHC Experiments, London, 22-26
Sept.1997, p.238-241, 1997; CERN/LHCC/97-60, 21
Oct.1997
[8] ALICE Central Trigger Processor USER REQUIRE-
MENTS DOCUMENT (1 June 2000, Draft 01, AL-
ICE Internal Note)

Design and Test of the Track-Sorter-Slave ASIC
for the CMS Drift Tube Chambers
F. Odorici and G.M. Dallavalle, A. Montanari, R. Travaglini
I.N.F.N. and University of Bologna, V. B. Pichat 6/2, 40127 - Italy
Fabrizio.Odorici@bo.infn.it
Abstract
Drift Tubes Chambers (DTCs) are used to detect muons in
the CMS barrel. Several electronic devices installed on the
DTCs will analyse data at every bunch crossing, in order to
produce a level-1 trigger decision. In particular, the Trigger
Server system has to examine data from smaller sections of a
DTC, in order to reduce the chamber trigger output by a factor
of 24. The basic elements of the Trigger Server system are the
Track-Sorter-Slave (TSS) units, implemented in a 0.5 micron
CMOS ASIC. This paper describes the way the project of the
TSS ASIC has been carried on, with emphasis on the
methodology used for design verification with IC simulation
and prototypes test.
I. THE TRACK SORTER SLAVE
In the CMS muon barrel, the DTCs represent an important
detector to produce a level-1 trigger decision [1]. The DTC
trigger system is made of a chain of several devices that are
placed on the chambers and arranged on 1080 trigger boards.
Each chamber can have up to seven trigger boards. Each
trigger board allocates a TSS unit. The full functionality of the
TSS is described in [2]. Essentially, it works as a processor
with the following main tasks:
• Track quality sorter. It selects two out of 8 tracks,
based on their quality (transverse momentum, number
of hits, correlation, etc.).
• Background filter. It rejects ghost tracks that can be
erroneously
windows.
reconstructed within small angular
• Data watcher. It allows on-line monitoring of the
trigger data, permitting, for example, to exclude noisy
channels from the trigger decision.
• Tx/Rx unit. The TSS is mounted on a trigger board,
which covers about (at least) a seventh of a chamber.
The TSS controls the link between the trigger board
and the chamber’s Control-Board.
In order to decide which technology is more convenient to use
for the device implementation, the following boundary
conditions were taken into account:
1. 1200 TSS needed for the whole detector;
2. A device needs 90 I/O pads, among which 40 pads are bidirectional;
3. Reduced power dissipation. The device has to be
allocated on the chamber itself and cooling will not be
very effective and powerful.
4. Event processing has to complete within 25 ns, i.e. the
TSS latency has to be 1 BX;
5. The whole functionality is quite complex. In addition to
many base functionalities it has to account for remote
programmability and on/off-line monitoring. It has to
include a built-in self-test and a connectivity test
(Boundary Scan).
6. Radiation tolerant. The total dose expected for the TSS in
10 LHC years is not very big, around 0.01 krad (with a
factor 10 as uncertainty). Instead, Single Event Effects
(SEE) could cause serious problems to the whole system,
for example a bus direction flip.
Based on the previous conditions (especially 4-6) we
considered appropriate to implement the device as an ASIC.
In the IC design particular effort has been devoted to speed
optimisation, remote programmability and monitoring.
Programmability allows choosing among different processing
options, depending on the local trigger demands of each DTC
section, and permits to partially cover for malfunctioning
trigger channels. Since TSS units will be hosted onto the DT
chambers and their access will not be easy or frequent, much
effort has been dedicated to redundancy of remote
programming and monitoring logic. In particular, two
independent access protocols, via serial JTAG and/or via an
ad-hoc 8-bit parallel interface, allow programming and
exhaustive monitoring of each device. In Figure 1 a block
diagram is shown to summarize the TSS functionalities.

4 x 9 bit
TRACO
previews
I/O
pads
TEST
regs
SNAP
regs
R E
G
Configuration
Registers
Input
mask
Parallel
Interface
Program
mode
Quality
Filter
Priority
Encoder
JTAG
controller
JTAG
serial line
Figure 1: Block diagram of TSS functionalities.
II. THE EXECUTIVE PLAN
The TSS project has been carried on by following a
three-step plan:
• Working Rules. Firstly, define rules that fully
describe the TSS functionality. Some of these Rules
are the outcome of the Trigger simulation.
• Design Joined Approach. Design a “machine” which
satisfy the Rules using two independent formalisms:
– A logic description (VHDL);
– A software Device Emulator (C language).
• Software Tools Common Base. In order to master and
verify the considerable design complexity, we
developed a common base of software tools for IC
simulation and prototype (also production) testing
phases. The common base consists of an event
generator, a device emulator and an output comparator.
The above approach gives several advantages. For
example, the two independent formalisms allow to perform
a reciprocal verification of the design and to correct for
“wrong” or “missing” Rules. The Device Emulator allows
to produce an exhaustive test vector set and becomes a
certified “bug-free” software for prototype verification.
More generally, a common base of software tools gives
advantages in terms of development time and code
correctness.
In Figure 2 the methodology adopted during the
development of the project is shown as a flow diagram. The
test software tools are shared between IC simulation and
prototype test phases.
4 x 9 bit
Ghost2
Buster
Ghost1
Buster
Carry
9 bit
2 word
comp
x 10
FBT
SBT
R E
G
R E
G
R E
G
FBT = First Best Track
SBT = Second Best Track
I/O
pads
5 bit
TRACO
select
11 bit
I/O
pads
TSM
preview
8
Figure 2: Methodology used to develop the TSS device.
III. WORKING TOOLS
The basic tools we adopted during the project life were:
• ASIC development system (Synopsys). To implement
the VHDL design and IC Simulation at various levels
(VHDL, Gate, Post Layout).
• Layout & Prototypes were made via Europractice
(IMEC), which offers low rates for no-profit institutes.
For the same reason also the mask and the small
volume (less than 10 kpcs) production is made via
Europractice.
• Custom Test-Software (programs and libraries) was
implemented in C language.
• Custom Test-Hardware was based on a programmable
I/O Pattern Unit VME module, able to operate well

eyond the LHC bunch crossing frequency, i.e. up to
100 MHz. The Pattern Unit is a very flexible
instrument; in fact, we designed it as a general testing
tool for digital electronic devices. The device controls
up to 128 I/O channels and has many features and
programmable options that make it a suitable tool for
both a prototype test bench and for a test-beam set up.
In Figure 3 a Pattern Unit is shown and a complete
description of its functionality can be found in [3]. The
device under test (DUT) is connected to the Pattern Unit
through a piggy board, inserted on appropriate socket
strips.
Figure 3: Pattern Unit hosting the DUT interface board.
The DUT interface board can also be used with a remote
connection to the Pattern Unit. For example, we used the
remote connection in the radiation test set up (see Figure
4). In that case, data were injected and monitored via
JTAG. In correspondence of the chip die (4.5x4.5 cm 2 ) the
interface board has a 16 mm diameter hole in order to
minimize attenuation effects due to extra material.
Figure 4: Radiation Test set up on 60 MeV protons beam.
The test was made at the Cyclotron facility (CRC) in
Louvain la Neuve (Belgium).
IV. PERFORMANCES AND RESULTS
The adopted technology for the TSS is the Alcatel-Mietec
0.5 µm CMOS. A picture of the TSS layout is shown in
Figure 5.
Figure 5: layout of the final TSS device.
An important aspect of the device implementation is the
completeness of the IC simulation and prototype test. For
many digital processors, as well for the TSS, the number of
possible I/O patterns and internal device configurations is
so large that an exhaustive test pattern set can easily get
over millions of events. Moreover, hardware tests usually
require long term (hours) observations in order to verify
temperature stability and noise immunity. For those reasons
it is useful to dispose of fast simulation system and fast test
chains. For the TSS the IC simulation was performed
within the Synopsys CAD, running on a Sun Ultra 10
workstation. The prototype test was controlled by our
custom software, running on a PC (Pentium-II, 333 MHz),
embedded on the same VME crate that houses the Pattern
Unit. The performances of our systems are reported in
Table 1.
Table 1: performances of the simulation and test systems.
Performances IC simulation Prototype Test
Event generation negligible negligible
10 Mevt/h
Event injection negligible (VME limited)
10 Kevt/h negligible
Event processing (CPU limited) (40 Mevt/s)
Output analysis negligible negligible
Full test ∼ 1 Mevt > 100 Mevt

The behaviour of the TSS under radiations has been
verified using a 60 MeV proton beam at the Cyclotron
facility (CRC) in Louvain la Neuve (Belgium). We find the
IC to be fully tolerant (the drawn current is stable) up to 30
krad, while the rate of single event effects (SEEs) was
observed to be:
σ = 8.4 x 10 SEE -15 cm2 /bit .
For the TSS, which is placed on the muon drift tube
chambers, the expected integrated flux is moderate (0.01-
0.1 krad/10 LHC years). Since also the number of SEEs
expected for about 1000 TSS is negligible (less than 1 in 10
LHC years), we can exclude problems related to radiations
for the TSS.
The TSS project, during his development, required the
implementation of two prototypes, the first one with
reduced functionality. Each step of the project required a
variable amount of manpower, with different distributions
for the two prototypes. The manpower, expressed in terms
of “full time work”, is reported in Table 2. The total R&D
full time work corresponds to more than 4 years, excluding
the time invested for trigger simulation. Most of the
manpower has been devoted to implement the Test System
and the Test Software.
Table 2: manpower dedicated to each project step, for the
two prototypes, expressed in terms of "full time work".
ASIC v. 1 ASIC v. 2
Project steps (f.t.w.)
(f.t.w.)
Rules definition 0.1 y 0.1 y
VHDL design 0.4 y 0.3 y
Device Emulator 0.3 y 0.1 y
IC Simulation 0.2 y 0.3 y
Test System 1.2 y 0.1 y
Test SW 0.5 y 0.1 y
Interface board 0.1 y 0.1 y
Prototype tests 0.1 y 0.1 y (undergoing)
Total R&D 2.9 y 1.2 y
V. CONCLUSIONS
The Track-Sorter-Slave, the basic element of the Trigger
Server system for the trigger chain of the CMS Drift Tube
Chambers, has been implemented in a 0.5 micron CMOS
ASIC. The project has been organized on a long term
perspective, because different steps of the realization
(milestones) have been affronted: two prototypes with
increased complexity, radiation tests, test-beams and
integration tests. The R&D work dedicated to the project
involved about 4 years of manpower. Most of the job was
dedicated in developing software and hardware test tools,
which were not, as usual, commercially available.
REFERENCES
[1.] CERN LHCC-2000/038, CMS Collaboration, “The
Level-1 Trigger, Technical Design Report”;
[2.] CMS TN 1996/078, G. M. Dallavalle et al., “Track
Segment Sorting in the Trigger Server of a Barrel
Muon Station in CMS”;
CMS IN 2001/xxx (in preparation), A. Montanari et
al., “Track Sorter Slave reference manual”.
[3.] CERN LHCC 1998/036 291, G. M. Dallavalle et al.
“Pattern unit for high throughput device testing”;
CMS IN 2001/xxx (in preparation), F. Odorici et al.,
“A high throughput Pattern unit as a testing tool for
digital Integrated Circuits”.

Use of Network Processors in the LHCb Trigger/DAQ System
Abstract
Network Processors are a recent development targeted at
the high-end network switch/router market. They usually
consist of a large number of processing cores, multi-threaded
in hardware, that are specialized in analysing and altering
frames arriving from the network. For this purpose there are
hardware co-processors to speed-up e.g. tree-lookups,
checksum calculations etc. The usual application is in the
input stage of switches/routers to support de-centralized
packet or frame routing and hence obtain a better scaling
behaviour.
In this paper we will present the use of Network
Processors for data merging in the LHCb dataflow system.
The architecture of a generic module will be presented that
has the potential to be used also as a building block of the
event-building network for the LHCb software trigger.
I. INTRODUCTION
Network processors are a relatively new development. The
first one was introduced by C-Port (now Motorola) in 1999.
Nowadays every major and a lot of smaller chip-manufacturer
has one in their product line.
A network processor is a dedicated processor for network
packet (=frame) handling. It provides fast memory and
dedicated hardware support for frame analysis, address lookup,
frame manipulation, check summing, frame classification,
multi-casting and much more. All these operations are driven
by software, which runs in the network processor (NP) core.
These processors are usually multi-threaded in hardware,
multiple threads are running at the same time with zerooverhead
context switching. They were primarily designed as
powerful and flexible front-ends for high-end network
switches and switching routers. Because they are software
driven they can easily be customised to various network
protocols, requirements or new developments. They allow to
create really big switching frameworks, because the
decentralise the address resolution and forwarding functions
traditionally performed by a single, powerful control
processor. Thus they enable switch manufactures to construct
large switches (up to 256 Gigabit ports and more), with
dedicated software in a short time. Currently the “Gigabit”
generation of network processors is on the market, while the
next one will be able to handle 10 Gigabit speeds (either as
10-Gigabit Ethernet or OC-192). These processors will be
available in the course of 2002. More information can be
found in [1].
J-P. Dufey, R. Jacobsson, B. Jost and N. Neufeld
CERN, CH-1211 Geneva 23, Switzerland
beat.jost@cern.ch, niko.neufeld@cern.ch
We present the use of a specific network processor, the
IBM NP4GS3 to implement a versatile module for LHCb.
The NP4GS3 can be operated either together with a switching
fabric or in back-to-back with a second NP4GS3. In this note
we will summarise our experiences so far, and will
demonstrate how a NP-based module can fulfil many uses in
the LHCb data acquisition system, but also potentially in the
Level 1 trigger system.
II. THE IBM NP4GS3
The IBM NP4GS3 is a network processor, which
comprises 8 dual processor units (DPPU), each being able to
run 2 out of 4 total threads at the same time. Each DPPU
shares a set of coprocessors, which regulate the efficient
access to external resources, such as port queues, memory,
tree look-up, check-summing and policy. The chip includes
also 4 media access controllers, to which Gigabit Ethernet
Physical Layer Interfaces (PHYs) can be directly attached
either using the GMII or the 8/10 bit encoding. The processor
has a 128 kB fast, on-chip input buffer, and a 64 MB output
buffer, made from DDR RAM chips. The access to the
memory is via a 128-bit wide data-path. The chip also
includes a PPC 405 core for control and monitoring and
exception handling. This PPC can run an operating system, if
desired Also attached are various memory interfaces for very
fast and fast address look-up memory, in total up to 64 MB.
For more details the datasheet can be consulted [2].
The data-flow through the NP4GS3 is shown in Figure 1.
Data is coming in from the ports, are stored in the ingress
memory, can be accessed here and are then transferred to the
Switch Interface Link (the DASL). From here they can either
reach their own blade or a twin processor connected back to
back to the first one. They will arrive in any case in the output
buffer or egress memory, where they can be accessed a
second time, before they are finally put on to one of several
output queues for transfer over the network.
III. A VERSATILE 8 GIGABIT PORT MODULE
The IBM NP4GS3 has a high-speed interface to connect to
a switching engine, the Data Aligned Synchronous Link
(DASL). In fact it has 2 such interfaces. When there is no
switching engine to connect to, one of these interfaces can
used to connect to another NP4GS3, thus creating effectively
an 8-port switch. The other DASL will be usually wrapped to
itself to ensure full connectivity.
In addition to the DASL the NP4GS3s (can) share the
following resources: power and clock distribution and access
to a PCI interface for configuration and monitoring. Each

NP4GS3 requires its own memories and physical layer
interfaces. The Media Access Controller (MAC) is already
incorporated on-chip.
DASL DASL
Access to frame data Access to frame data
Ingress Event Building Egress Event Building
Figure 1: Main components of the NP4GS3 together with an
indication of the standard data-flow paths. Data can be accessed and
modified at the input/ingress and output/egress stage, leading to two
different event building algorithms. One of the two DASL interfaces
is always wrapped, so that each NP can send to itself. Also indicated
are the various external memories.
Since the network processor and memory carrying part of
the module is by far the more complex and deep (in terms of
layers), it is very attractive separate this module of as a
daughter/piggy-pack board, which carries everything
belonging to one NP4GS3 alone (except the physical layers
interfaces), and feeding out the connections for PCI, DASL
(to the other Processor if present) and PHYs.
The common, “simpler” functionality and the control
processor (Credit Card PC) would be housed on a
motherboard. The two boards will be described in more detail
in the following:
A. Motherboard
The mother board will provide all common “infrastructure”
needed for the operation of the NP4GS3’s. This
includes power generation, clock generation and the physical
layer interfaces. It will also include a Credit-Card PC (CC-
PC) , the standard LHCb interface to the Experimental
Control System (ECS). It provides the connectors for the two
carrier cards with the Network Processors. These connectors
carry the following lines and interfaces: DASL, PCI, JTAG,
DMU. PCI is used by the CC-PC to configure and monitor the
NPs and also to communicate with the embedded PowerPC.
JTAG is needed for the boundary scan and for the hardware
debugging using RISCWatch [3]. The DASL is used to
connect two NPs, as has been said already. The DMU (Data
Mover Unit) interfaces connect the Media Access Controllers
integrated on the NP4GS3 to the physical interfaces. These
could be hot-plugable, thus allowing more flexibility in
configuring them either as 1000BaseT (CAT 5 copper) or
1000BaseSX (multi-mode fibre).
Except for some length requirements on the DMU and
DASL lines and some necessary screening for the high
frequency signals this mother-board will not be particularly
complex. A simple layout is shown in Figure 2.
Figure 2: Mother-board for the NP4GS3 carriers. It provides power,
clock and PCI to both NPs. Also shown are the 9 physical connectors
(8 for the NPs, one for the CC-PC).
B. Piggy-back Board
This board will be comparatively complex, with ~ 12 layers
and has rather stringent requirements on timing and distances.
To have it on a small carrier board has therefore quite some
advantages: the multi-layer board can be kept small, which
eases production, and the flexibility to connect different
physical layers is kept. An simplified block-diagram is shown
in Figure 3:.
8Mx16
DDR
D3
DRAM DRAM Control
Control
2x
32Mx4
DDR
PARITY
D6
8Mx16
DDR
D2
DRAM DRAM Data
Data
2x
32Mx4
DDR
DATA
D6
8Mx16
DDR
D1
2x
32Mx4
DDR
DATA
D6
2x
8Mx16
DDR
D0
PCI
DASL A
NP4GS3
DMUs
A A B B C C D
D
2x
512kx18
SRAM
LU
2x
8Mx16
DDR
PARITY
D4
Throttle
2x
8Mx16
DDR
DATA
DS0
DRAM DRAM Data
Data
512kx18
SRAM
SCH
DRAM DRAM Control
Control
2x
8Mx16
DDR
DATA
DS1
Figure 3: The piggy-back or carrier board will house the NP4GS3
processor and its associated memory-chips.
IV. APPLICATIONS IN LHCB
The flexibility of the module allows for a range of
applications in the LHCb Data Acquisition system. They are

shortly discussed here. For details about the LHCb DAQ
system see for example [4].
1) Readout Unit
The most obvious application is as a Readout Unit, which
is interfacing/multiplexing front-end links to the Readout
Network. The network processor is in this context as a fast
sub-event merger, to assign destinations and function as a
front-end to the event building switching network. The
Readout Unit always has one (and only one) output to the
Readout Network (RN), it can have several inputs (usually
either 2 or 4). The NP-based Readout Unit will merge the subfragments
and send them out to the network, using addresses
determined by a pre-loaded address table. It will respect flowcontrol
messages (“X-On/X-Off”) from the network, to cope
with local congestion, and it will itself have the possibility to
throttle the trigger, when its buffers are about to overspill.
2) Front-end Multiplexer
The Front-end Multiplexer (FEM) application is basically
the same as the Readout Unit. The multiplexing factor will be
anywhere, between 7 and 2. For multiplexing factors smaller
then 4, 2 FEMs can be implemented using a single, fully
equipped module.
3) Main Event builder
The main event builders task is to collect all the fragments
belonging to a specific event, originating from the RUs. This
will be some 100 fragments, which have to be assembled into
one contiguous event and sent to the Sub farm Controller
(SFC). The fragments will arrive out of the order from the
network, because the LHCb data acquisition does not have
(nor does it want or need) any synchronisation after the
Level 1 derandomisers. They have to be re-arranged into
correct order and the possibly empty data and error blocks
have to be merged.. Since the rates are low at this stage, one
module could drive 4 event building streams, that is it can
feed 4 SFCs.
4) Elementary Switching Module
The 8-port module can also be used as the building
network for the switching network itself. Performance-wise
this is definitely no problem, because this is the original
domain of the network processors from their conception. The
question is then more if such a switching network can be costeffective
on a price/port basis. Obviously one needs quite a lot
of them, because one has to provide interconnections, which
serve the purpose of the backplane in a conventional
monolithic switch. There are however studies on how to
reduce the number of modules, by making intelligent use of
the traffic patterns in a data acquisition system see for
example [4]. Additional advantages would be, that such a
module would allow full control over switching process and
functionality. Flow control, traffic shaping, check-summing
could be implemented at will and customised for maximum
performance in the DAQ. Furthermore such a switching
network could do the final, main event building in its last
stage.
V. EXAMPLES OF SOFTWARE FOR APPLICATIONS
A. Sub-event merging in a Readout Unit
The task here is to collect up to 7 fragments arriving at a
rate of at most 100 kHz. The fragments have an average size
of a few 100 Bytes, which increases after successive levels of
multiplexing. Sub-event building proceeds by analysing the
fragment headers and waiting until all fragments belonging to
an event have been received or a time-out condition has
occurred. In any case event-building will start, in the latter
case an error will be flagged in the error block. The frames
will then be connected by adapting the link-pointers, moving
as little data as possible. At the boundaries of original frames,
it sometimes becomes necessary to actually copy some data to
fill from the bottom. New frames are being built until a predefined
maximum transfer unit has been reached. The frame
is then dispatched, and the procedure is iterated until all data
have been used up.
Care has to be taken to avoid corruption of the static data,
due to multiple threads wanting to access them at the same
time. The NP4GS3 provides a powerful semaphore
mechanism to handle these situations.
Performance of egress event building according to
simulation is shown in Figure 4:, only 16 out of 32 threads
have been enabled, an improvement of at least 50% can still
be expected.
Maximum Allowed Fragment Rate [kHz]
350
300
250
200
150
100
50
Limit imposed by NP Processing Power
Limit imposed by single Gb Output Link
Range of possible Level-1 trigger rates
0
0 100 200 300 400 500 600
Average Fragment Size [Bytes]
Figure 4: Performance of the Egress Event Building as a function of
the average input fragment size. The green area shows the range of
possible L1 trigger rates.
B. High rate event-building
Another application which could be of interest for the
LHCb Level 1 trigger is sub-event merging at high rates of
incoming fragments. Here very small fragments of some 30 to
50 Bytes are coming on 2 to 3 links at rates above 1 MHz.

The very high speed of the ingress memory, makes it ideal
to perform event-building at high data rates and high trigger
rates. The main idea is to store the data fragments waiting for
all belonging to the same event having arrived and then copy
the payload to form a new fragment to be sent towards the
output ports. After stripping of the transport headers only part
of the incoming data is transferred to the egress side after the
event-building process, including the new transport structure
for the outgoing event fragment. It has been shown that this
strategy allows for event-building performances far beyond
the capabilities of the output port. The performance is shown
in Figure 5:.
Maximum Acceptable L0 Trigger Rate [MHz]
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0 10 20 30 40 50 60 70 80 90 100 110 120
Average Input Fragment Payload [Bytes]
Limit imposed by NP Perfomance
Limit imposed by single Gb Output Link
Max. Level-0 Trigger Rate
Figure 5: Performance of Ingress event-building from simulation as
a function of the average incoming packet size. The straight line
shows the fixed level 1 trigger rate of 1.1 MHz. The limitation on
performance comes from the output link bandwidth only.
VI. MEASUREMENTS WITH THE IBM POWERNP
REFERENCE PLATFORM
The results presented so far have been obtained using
simulation. It is therefore interesting to assess how reliable the
timing information of the simulation is. Since the latest
version of the processor (revision 2.0) is not yet available on a
reference platform, some parts of the sub-event building code
cannot run un-modified on the reference design hardware.
However, it has been possible to compare a representative set
of algorithms on simulation and real hardware. The results
agree well. They will be described in the following:
A. The IBM N4GS3 Reference Platform
The IBM NP4GS3 Reference Kit [6] aims at providing
users with an implementation, which allows exploring most of
the functions of the processor. The chassis with the important
cards is shown in Figure 6. The configuration used for our
measurements consisted of a chassis, a control processor (a
PPC 705 based cPCI computer), two carrier boards with a
NP4GS3 and 4 daughter cards, each with 2 Gigabit Ethernet
SX optical ports. Furthermore we had a RiscWATCH ([3])
probe attached to the JTAG interface of one of the blades,
which allows to access the network processor’s internal
registers directly from the NPSCOPE debugger (via Ethernet).
Figure 6: Main components of the NP4GS3 reference platform. The
packet routing switch board is not included in our set-up.
B. Test set-up
The test set-up shown in Figure 7: consisted of 4 Netgear
Gigabit Ethernet NICs, running a dedicated firmware, which
made them traffic generators and sinks. The internal clock of
the NICs allowed to measure latencies with approximately
1 µs precision. More information about these “smart NICs”
can be found in [7].
.
Figure 7: Test-setup for the NP4GS3 reference kit. The data are fed
and read back using four Tigon 2 based Gigabit Ethernet NICs,
shown at the top of the figure. Download of NP software and
monitoring of the NP is done via JTAG using the RISCWatch probe

The network processor is accessed remotely via the
RiscWATCH. This configuration allowed to test 3 to 1 eventbuilding.
Each NIC has an internal clock which has been used
to measure the latencies imposed by the event building code.
This clock has an intrinsic resolution of 1 micro-second. The
generation of frames and the evaluation of the timedifferences
in the receiving NICs, which are the same as the
senders.To synchronise the NIC (the sources), which is
necessary for the reasons outlined above, a special frame is
send by one of the NICs to the NP, which then multi-casts it
to all NICs. This triggers the collective sending of the packets,
within 0.5 microseconds.
C. Results
The main aim of all measurements was to understand the
accuracy of the simulation. The simulation is claimed to be
cycle precise. It takes into account the contention between
threads. However, it does not accurately simulate all external
resources with their associated latencies. It was therefore
especially interesting to see to what extend simulation results
can be trusted. One problem with these measurements is that
the version of the NP on these boards is not the latest. It lacks
the semaphore coprocessor, a unit specifically designed for
efficient resource protection to avoid race conditions in a
multi-threaded application. Since our code heavily relies on
this feature, it was necessary to tune the test conditions
somewhat. This has been done by doing either a single thread
measurement or by reducing the spread in the arrival time of
the fragments by careful synchronisation. This does not
change the run-time of the code, the simulations for both
versions agree on that. It allows, however to avoid the
occurrence of synchronisation problems which would
otherwise be avoided by the semaphore coprocessor. We are
confident that these measurements give a realistic impression
of the performance of our sub-event building codes.
Measurements have been done only in the “high rate“
environment, which means short frames at high rates, since
this is the more demanding and critical application.
Table 1: Comparison of measurements with simulation results. The
handling time per fragment is shown in microseconds. The
measurement times are shown once raw as measured, and second
corrected, with the round-trip and handling time in the NICs
subtracted.
1 source
1 thread
4 sources
1 thread
1 source
16 threads
Measurement
[µs/fragment]
Simulation
[µs/fragment]
6.6(4.9) 4.9
4.5(2.8) 3.2
1.7 (0.0) 0.5
First the round-trip time of a packet has been measured.
This is necessary to subtract any overheads coming from the
transport over the DASL, the cables and especially the
creation and time-stamping in the NICs, which are not
included in the simulation. This time has been found to be
1.7 µs. It can be seen as an intrinsic resolution of the
measurements. Since the whole system is pipe-lined (many
threads working) time-intervals smaller than this intrinsic time
cannot be accurately measured. This is the reason for the
apparently strange value 0.0 in the last row of the following
table.
Several scenarios have been tried, varying the number of
active threads and active sources. The results are summarized
in Table 1:.
VII. CONCLUSIONS
In this paper we have presented the use of a Network
Processor for several applications in the LHCb Data
Acquisition System. An integrated module has been
described, whose function would be determined only by the
software driving it, providing maximum flexibility and
excellent debugging capabilities.
Two such sample software codes have been developed and
benchmarked using a cycle-precise simulation .
The simulation results have been compared with
measurements obtained with the reference platform of the
IBM PowerNP. The results are in very good agreement,
making us confident that we will have one, and only one,
powerful, versatile module for the LHCb Data Acquisition.
VIII. REFERENCES
[1] Network Processor Central, [online]
http://www.linleygroup.com/npu
[2] IBM PowerNP NP4GS3 Datasheet, [online]
http://www3.ibm.com/chips/techlib/techlib.nsf/techd
ocs/852569B20050FF7785256983006A3809
[3] RISC Watch Debugger, [online]
http://www3.ibm.com/chips/techlib/techlib.nsf/produ
cts/RISCWatch_Debugger
[4] B. Jost, “The LHCb DAQ system”, Presentation at
the DAQ 2000 Workshop, Lyon
[5] J. P. Dufey et al., “Results from Readout Network
Simulation” LHCb Note in preparation
[6] IBM PowerNP NP4GS3 Reference Platform,
[online]
http://www3.ibm.com/chips/techlib/techlib.nsf/techd
ocs/546B9AC56334EA0F872569F9005F7DA5
[7] LHCb Event-Building, [online]
http://lhcb-comp.web.cern.ch/lhcb-comp/daq/Event-
Building/default.htm

Abstract
STATUS OF ATLAS LAr DMILL CHIPS
C. de La Taille, LAL, Orsay, France (email: taille@lal.in2p3.fr)
This document reviews the status and performance of
the ten DMILL chips developed in 2000-2001 by the
ATLAS liq uid argon (LAr) community in order to ensure
the radiation tolerance of its front-end electronics.
1. INTRODUCTION
The LAr front-end electronics is located right on the
cryostat in dedicated front-end crates [1]. These house
four different species of boards :
• Front-end boards (FEB) which bear
preamplifiers, shapers, analog memories, ADCs and
optical outputs.
• Calibration boards to generate 0.2% accuracy
calibration pulses
• Tower builder boards (TBB) which perform
analog summation and re-shaping for LVL1 trig ger
• Controller boards which handle TTC and serial
link (SPAC) control signals
.All these boards have been produced in several
exemplars in order to equip module 0 calorimeter and
extensively used in the testbeam for the last three years.
Their performance has met the requirements in terms of
signal, noise, density at the system level on several
thousands of channels [2]. However, they make use of
many COTS, in particular FPGAs which are not radiation
tolerant.
Since then, several developments have been realised in
order to design the “final” ATLAS boards, based on the
same architecture but completely radiation tolerant, by
migrating most of the COTS into DMILL ASICs [3]. A
milestone has been set to get the first boards by end-2001
and a full crate by the end of 2002.
The radiation levels anticipated at the LAr crate
location is 50 Gy in 10 years and 1.6 10 12 N/cm 2 . Taking
into account the safety factors required by the rad-tol
policy [4] , they must be qualified up to 0.2-3 Gy (20-300
krad) and 1-5 10 13 N/cm 2 , depending on the process as
explained in ref. [5]. For DMILL chips, the radiation
tolerance criteria (RTC) are
• RTCTID = 3.5*1.5*2*50 = 5 kGy
• RTCNIEL = 5*1*2*1.610 12 = 1.6 10 13 N/cm 2
• RTCSEE = 5*1*2*0.710 11 = 7.7 10 12 h>20MeV/cm 2
The performance of all these DMILL chips and in
particular the yield and results of irradiation and SEE tests
are presented below.
On behalf of the LArG collaboration
2. CALIBRATION BOARDS [6]
The calibration board houses 128 pulsers which
generate accurate pulses to simulate the detector signal
over the full 16bit dynamic range. It is based upon 128
0.1% precision DC current sources and HF switches which
transform the DC current into fast pulses with a 400 ns
exponential decay. The calibration board is used to intercalibrate
the 160 000 readout channels and measure their
three gains.
2.1 16bit DAC
A 16bit DAC with 10 bit accuracy is necessary to cover
the full dynamic range of ATLAS and COTS did not
provide adequate radiation tolerance. Therefore, a 16 bit
R/2R ladder DAC has been made with 16 switched
identical current mirrors. As there is only one DAC per
board, external precision resistors (0.1%) can be
accomodated. To reduce the sensitivity to VBE mismatch
and variations with temperature the emitters of the current
sources are strongly degenerated. This ladder DAC has
been developed and tested successfully in AMS 0.8 μm
BiCMOS and submitted to DMILL in may 2000, with
improved temperature stability (1 μV/K).
Figure 1 : Schema tic diagram of the 16bit ladder DAC
19 chips have been received in march 2001 among 18
were fully functional, giving a yield of 94% for a chip area
of 6.3mm 2 .
The performance measured is 0.01% integral non
linearity over the 3 gains as shown in Fig. 2. The
temperature stability has been measured on 10 chips
between 20 and 65C to be of +0.01%/K.

Figure 2 : residuals of a linear fit on the DAC output
over the three shaper ranges (10 mV, 100mV, 1V)
10 chips have been irradiated up to 9. 10 13 N/cm 2 at
CERI (20 MeV) and to 2 kGy 60 Co at Saclay and measured
on line. The result, shown in Fig. 3 and 4, indicate good
tolerance to Neutrons (0.1% variation up to RTC) but also
a visible drift with gammas (-0.5% after 2 kGy). As the bits
ratio turned out to be very stable, the decay has been
traced down to a change in the reference current : in effect
a one-mV VT shift in he current mirror is enough to cause
the effect.
RTCNIEL 0.2%
Figure 3 DAC output voltage under Neutron
irradiation
Although acceptable as such, enough time was available
for an iteration with an improved reference source : a band
gap reference incorporated and the current mirror
has been replaced by a reference source built around a
low-offset opamp as described below.
2.2 Low offset opamp
RTCTID
0.1%
Figure 4 : DAC output voltage under gamma irradiation
The DAC voltage is distributed throughout the board
to 128 channels in order to produce the 2 μA – 200 mA
precision current. The voltage to current conversion is
based upon a low-offset opamp and a 0.1% 5Ω resistor.
The opamp offset should not be larger than the DAC
LSB=16μV. Again COTS did not provide adequate
radiation tolerance and ASICs were developed along two
paths : static and auto-zero. After prototyping in AMS,
the static configuration was chosen and translated into
DMILL.
As shown in Fig. 5, the circuit is built around a bipolar
differential pair and external precision collector resistors
(150kΩ 0.1%). The transistors are 10*1.2 NPN, mounted in
centroid configuration ; a larger transistor size would in
principle further reduce the offset, but would decrease the
radiation hardness due to a too low current density. This
input stage provides a gain of 127, enough to disregard
the second stage offset. The chips are sorted to be within
± 100μV.
Figure 5 : Schematic diagram of the low-offset opamp

The second stage is built around a cascoded PMOS
differential pair, again in a centroid configuration. A bank
of 5 binary scaled current sources allows to add or remove
up to 20% of the static current and allow further trimming
down to ± 10μV. The total open loop gain is 80 000, in
good agreement with measureme nts. The output stage is a
large (20,000/0.8) PMOS in order to drive the large
maximum output current (200 mA).
40 chips have been received in march 2001 among
which 37 were fully functional, giving a functional yield of
94% for a chip area of 2 mm 2 . The circuits have then been
tested for the offset performance. As anticipated, the
offset is dominated by the input pair and 27 chips were
found between ± 100μV, giving a total yield of 70%, similar
to what was obtained with the AMS prototype.
Figure 6 : Offset distribution of the input bipolar pair.
Concomitantly to the DAC, ten opamps have been
irradiated to photons and neutrons. As can be seen in
Fig.7, the offset has remained stable inside 15 μV up to 2
kGy. Incidentally, an AMS version which was left there
died immediately after RTC (yellow curve).
ID
±100 μV
The test to Neutrons was also performed far in excess
of the requirements. After 2.5 10 12 N/cm 2 , the circuits could
no longer be measured on line because of the failure of a
discrete NPN transistor commanding the multiplexing
relays. Notwithstanding, the circuits were measured again
after the irradiation and had remained stable.
2.3 Calibration logic
RTCNIEL
Death of
mux
readout
25 μV
Figure 7 : Neutron irradiation of the low offset opamp
The calibration boards used on module 0 were
controlled by an elaborate digital circuitry which allowed
to load on board a full calibration sequence (ramping the
DAC, changing patterns…)[7]. Although practical and
very time efficient this circuitry was based on memories
and numerous FPGAs which would not operate reliably in
the high radiation environment. It has thus been decided
to simplify the control logic and load through the SPAC
serial bus the run parameters (DAC value, delays, pulsing
patterns). These parameters are decoded from I 2 C local
bus and stored in registers which have again been
designed in DMILL. No particular SEU mitigation has
been included as the calibration board is idle 99% of the
time and SEU results only in a wrong calibration pulse,
which can be discarded in the RODS.
The chip covers an area of 16 mm 2 and has been
submitted in may 2000. 20 chips have been received in
march 2001, among which 17 were functional, giving a
yield of 70%.
Two chips have been subsequently tested for SEU at
Louvain with 70 MeV protons. No SEE have been
observed up to a fluence of 3 10 12 p + /cm 2 . Extrapolating
this cross-section to ATLAS yields one SEE/2 days,
assuming the calibration is used 1% of the time.

3. FRONT-END BOARDS [8]
The Front-end board has necessitated the development
of 6 chips in DMILL in order to ensure the integration of
all the elaborate digital electronics necessary to operate
the board. Except the preamplifier (bipolar hybrid) and the
shaper (BiCMOS AMS), almost all the front-end board is
built around DMILL chips. The analog pipelines (SCA)
which follow the shapers have been designed from the
start in DMILL. They make use only of the CMOS
components and of full custom logic running at 40 MHz.
The read and write addresses necessary to operate the
SCA with no dead time are generated by a SCA controller.
The gain selection at the SCA output are also handled by
a dedicated ASIC : the gain selector. Then the data are
multiplexed to 16bit 80 MHz (MUX chip), to be fed into the
Glink serializer and output optically. Furthermore, the
parameters necessary to operate the board are loaded by a
serial lin k (SPAC). A serial link decoder (SPAC slave) is
necessary as well as a configuration controller.
3.1 Switched Capacitor Arrays (SCA)
The analog pipeline is a key element of the front-end
board, as it stores the analog signal until the reception of
LVL1 trigger in a bank of 144 capacitors with a 13 bit
dynamic range. Several prototypes have been realized in
DMILL in the last 3 years, as well as in radiation soft
technologies (AMS 0.8 μm, HP 0.6 μm) with similar
electrical performance [9].
As more than 50 000 good chips will be necessary,
corresponding to more than 200 wafers, the yield is of
particular concern. Most of the various batches received
so far have exhibited satisfactory yield above 65%, except
a recent one as low as 10% due to a few randomly
distributed leaky switches. This process defect has
subsequently been understood and fixed in a later batch.
Before undergoing mass-production in 2002, the final
engineering run has been submitted at the end of 2000 and
received in march 2001. More than 2500 circuits have been
measured with the automated testing setup [10].
batch date # chips yield
V 1.1 6/98 30 90%
V 1.2 8/98 30 80%
V 2 wafer 12 8/99 68 50%
V 2 wafer 4 8/99 49 84%
V 3.1 12/99 18 10%
V 3.2 7/00 35 65%
V 3.2 eng. run 3/01 2534 65%
An important parameter on the acceptance cuts is the
leakage current. Although most of the cells exhibit very
low leakage (2 fA in average), the requirement of having
all cells on the sixteen channels (16*144) below 5 pA is
enough to induce a 4% yield loss.
Figure 9 : leakage current of all the SCA cells
3.2 SCA controller (SCAC)
In module 0 FEB, the SCA controller was implemented
in a XC4036 Xilinx, based on 0.35 μm technology. This
component has been extensively tested for radiation
tolerance and has shown a significant supply current
increase after 400 Gy. Moreover, SEU tests have been
carried out and have shown a cross section for SEU of
σ SEU = 2.7 10 -9 cm 2 , a LET for the configuration switches of
22 MeV and worse of all, one latch-up event [11].
It has then been decided to migrate this element into
DMILL. However, the chip complexity and critical timings
have turned out to be marginally achieved and resulted in
a very large chip area (80mm 2 ) for which the yield was
likely to be rather small (20%). Besides, due to the large
area, it has not been possible to include any error
correction mechanism, leaving the SEU problem open. For
such chip, the SEU effects are rather serious as read or
write pointers could get systematically wrong. A fallback
in 0.25 μm technology has thus also been designed,
including SEU error correction logic, and submitted in
march 2001.
40 DMILL SCA controllers have been received in june
01, among which 28 have passed all the digital tests,
giving an unexpectedly high yield of 70%. Nine chips
have been tested for maximum clock frequency and all ran
up to 50 MHz. The chips also passed successfully a burn -
in test.
Four chips have then been tested for SEU at Triumf
with 74 MeV protons. The associated TID was around 40-
70 krad. After 4.6 10 10 p+, all chips needed a power-on
cycling to reset. It has been traced to a fault in the
(analog) power-on reset, which has been subsequently
removed. Extrapolated to ATLAS, each SCAC would need
a reset every 70 days, amounting to a reset every hour
over the whole experiment.

3.3 Gain selector
The SCA is followed by a 12 bit 5 MHz ADC (AD9042)
which has been qualified by CMS [12]. Two ADCs feed a
gain selector chip which chooses the correct gain and
formats the data for the subsequent RODs. As the chip
stores two thresholds per channel for the gain selection,
SEU have been mitigated with a Hamming correction code.
It results in a 21 mm 2 ASIC, submitted to DMILL in
september 2000. The same chip has also been submitted in
0.25 μm alongside with the SCA controller.
29 DMILL chips have been received in may 2001 and 27
were functional, giving a yield of 93%. Five chips have
been tested for SEU at Harvard facility with 50, 100 and
158 MeV protons. The single event upset can be sorted in
two categories : single bit errors (SBE) corresponding to
one bit flip in the registers which is corrected by the error
correction algorithm and single event upsets
corresponding to a wrong bit in the output data which
leads to a rejected event in the RODs. The measurements
are shown in the table below. Coarsely extrapolated to
ATLAS by multiplying the cross section by the hadron
flux RTC (supposed flat) leads to 1 SBE/30mn and 1
SEU/168 mn for the full calorimeter (13 000 chips).
Energy Fluence #SBE σ SBE #SEU σSEU
MeV 10 13 /cm 2 10 -13 10 -13
50 2.4 0 - 0 -
100 4.0 14 3.5 4 1.0
158 20.8 212 10.2 38 1.8
3.4 Optical output
The formatted digital data are sent out after LVL1
trigger through an optical fiber. Five samples of each 128
channels are multiplexed at 40 MHz, resulting in 2.6 Gbit/s
output rate. The baseline option was using HP Glink, but
extensive irradiation studies [13] have shown that
although the link exhibited very good total dose tolerance
up to 43 kGy and 10 13 N, it was sensitive to SEU, 0.05
error/link/hour with ATLAS spectrum. In particular,
energetic neutrons could induce synchronization errors,
bringing the link down up to 10 ms [14].
A multiplexing chip (MUX) is necessary to turn the
32bit 40 MHz data into 16bit 80 MHz Glink input format.
Initially, the design was done for a dual Glink option to
improve redundancy [14]. This DMUX chip has been
submitted in DMILL in may 2000 [15].
18 chips have been received in march 01, with a
functional yield of 88% for a chip area of 16 mm 2 . Four of
them have been irradiated at CERI for SEE tests alongside
with the Glink. Its contribution to SEU rate is negligible
compared to the Glink. Furthermore, no parameters are
stored in the chip, which renders SEU effects very minor.
3.5 Configuration chips (SPAC,FEBconfig)
All the parameters necessary to operate the FEB are
loaded via a serial bus on the front-end crate (SPAC),
inspired from I 2 C [16]. This bus is decoded by an ASIC
called SPAC slave, which provides regular I 2 C and parallel
outputs. This chips has also required the development of
a special RAM and is common to all the boards.
Submitted in September 00, 18 chips have been received
in march 01. The functional yield is 94
%, for a chip area of 27 mm 2 . It has been iterated in sept 01
to mitigate possible SEU effects, in particular on the subaddress,
with error correction logic.
Some additional functions which are specific to the FEB
have been grouped in another DMILL chip called
configuration controller. The design has also been
submitted in September 2000 and 40 chips have been
tested in july 2001. The functional yield is 93
%, for a chip area of 20 mm 2 . The chip is final and has been
tested successfully in relation with the other chips on a
“quarter digital FEB”, shown below.
Optical
transceive
HP
Glink
DMILL
MUX
DMILL
or DSM
Gain
selector
Figure 10 : Picture of the "quarter digital FEB"
used to test the FEB DMILL chips.
4 chips have also been tested for SEE at Harvard with
158 MeV protons. The associated TID was 2-15 Mrad.
After a fluence of 7 to 22 10 13 p + /cm 2 , 69 SEU have been
observed, giving a cross section of σ SEU = 1.5 10 -13 cm 2 .
Extrapolating this rate to ATLAS gives a rate of 1
SEU/26.8 hr.
DMILL
TTCRx
DMILL
SPAC
DMILL
Config
controller
DSM SCA
controller

4. PRODUCTION STRATEGY
Except the SCA, the SCA controller and the gain
selector, most of the DMILL chips are needed in
quantities which are too small to justify dedicated wafers.
It has thus been decided to group them on shared wafers
to reduce the price of the masks. Two shared wafers will
thus be produced :
• An analog wafer grouping 52 low offset
opamps, 1 DAC and 26 BiMUX
• A digital wafer with the 4 SPAC, 2 calogic, 3
FEB config and 3 MUX.
13 analog wafers and 20 digital wafers will be needed for
a total cost of 350 k$. It should be noted that this cost is
similar to the cost which was allocated for COTS.
Figure 11: layout of the analog and digital shared
DMILL wafers
5. CONCLUSION
Ten new DMILL chips have been designed and tested
in 2000-2001. All of them are now final and ready for
production in 2002. Shared wafers will be used to reduce
the production costs.
Seven of these chips are purely digital and exhibit a
yield above 70% for an area between 20 and 80 mm 2 . Two
of these chips have a DSM alternative (SCAC and gain
selector) which are also ready and working satisfactorily.
The choice will be made in October 2001.
Three chips are analog. Their yield is also larger than
70% and their electrical performance is very good, similar
to what was prototyped in AMS 0.8 μm BiCMOS.
The engineering run of the analog pipeline (SCA) has
been produced and tested successfully with a yield of
65%. The full production (200 wafers) will be launched at
the end of 2001.
6. ACKNOWLEDGEMENTS
This paper reviews the work of several institutes from
the LArG collaboration : Alberta, Annecy, BNL, Grenoble,
Nevis, Orsay, Paris VI -VII, Saclay. The author expresses
his gratitude to N. Dumont-Dayau, D. Gingrich, J. Parsons,
JP Richer, N. Seguin -Moreau and D. Zerwas for their help
in preparing this work.
Chip
Area
(mm 2 )
SCA 30
Number
needed
OK/tested Yield
(%)
54 400 1643/2500 65
SCA contr. 80 3 300 28/40 70
Gain select 21 13 300 27/29 9 3
FEB config 20 3 300 37/40 93
MUX 18 1 650 15/17 88
SPAC slave 27 2 500 17/18 94
Opamp 3 17 000 26/37 70
DAC 6.3 130 18/19 94
Calib logic 16 700 8/10 80
BiMUX 4.6 8 320 65/80 81
7. REFERENCES
The transparencies can be found on :
http://www.lal.in2p3.fr/recherche/atlas
[1] LAr technical design report. CERN/LHCC/98-016
[2] J. Colas : overview of the ATLAS LArG electronics.
CERN/LHCC/99-33 LEB5 (Snowmass) p 217-221
[3] C. de La Taille : overview of ATLAS LAr radiation
tolerance. LEB6 (Krakow) p 265-269
[4] ATLAS policy for radiation hardness.
http://atlas.web.cern.ch/Atlas/GROUPS/FRONTEND/
radhard.html
[5] M. Dentan : overview of ATLAS radiation policy. On
radiation tolerant electronics. LEB6 (Krakow) p 270
[6] J. Colas et al.. : The LArG calibration board ATLAS
internal note : LarG-99-026
[7] G. Perrot et al. : .the ATLAS calorimeter calibration
board. LEB5 (Snowmass) p 265-269
[8] D. Breton et al. : the front-end board for the ATLAS
liquid Argon calorimeter. CERN/LHCC/98-36 LEB4
(Rome) p 207-212
[9] D. Breton et al. : HAMAC a rad-hard high dynamic
range analog memory for Atlas calorimetry LEB6
(Krakow) p 203-207
[10] G. Perrot et al. : the ATLAS calorimeter calibration
board. LEB5 (Snowmass) p 265-269
[11] D. Gingrich et al. : Proton induced radiation effects
on a Xilinx FPGA... ATLAS LArG 2001-011
[12] P. Denes : digitization and data transmission for the
CMS electromagnetic calorimeter. LEB4 (Roma) p 223-
228
[13] M.L. Andrieux et al.. ATLAS LArG No -00-006
[14] B. Dinkespieler : Redundancy or GaAs ? two different
approaches to solve the problem of SEU in digital
optical links. LEB6 (Krakow) p 250-254
[15] D. Dzahini : A DMILL multiplexer for glink. LEB7
(Stockholm)
[16] B. Laforge : implementation of a Serial Protocol for the
liquid argon Atlas calorimeter (SPAC). LEB6 (Krakow)
p 454-458

DeltaStream : A 36 channel low noise, large dynamic range silicon detector readout ASIC
optimised for large detector capacitance.
P.Aspell * 1 , D.Barney 1 , A.Elliot-Peisert 1 , P.Bloch 1 , A.Go 2 , K.Kloukinas 1 , B.Lofstedt 1 , C.Palomares 1 ,
S.Reynaud 1 , N.Tzoulis 3
* Corresponding author … Paul.Aspell@cern.ch
1 CERN, 1211 Geneva 23, Switzerland, 2 NCU, Chung-Li, Taiwan, 3 University of Ioannina, GR-45110 Ioannina, Greece
Abstract
DeltaStream is a 36 channel pre-amplifier and shaper
ASIC that provides low noise, charge to voltage readout for
capacitive sensors over a large dynamic range. The chip has
been designed in the DMILL BiCMOS radiation tolerant
technology for the CMS Preshower project. Two gain settings
are possible. High gain (HG), has gain ~30 mV/MIP (7.5
mV/fC) for a dynamic range of 0.1 to 50 MIPS (0.4 fC – 200
fC) and low gain (LG), has gain ~4 mV/MIP (1 mV/fC) for a
dynamic range of 1 to 400 MIPS (4 fC – 1600 fC). The
peaking time is ~25 ns and the noise has been measured at
~ENC = 680 e + 28 e/pF. Each channel contains a track &
hold circuit to sample the peak voltage followed by an analog
multiplexer operating up to 20 MHz. The response of the
signal is linear throughout the system. The design and
measured results for an input capacitance < 52 pF are
presented.
I. INTRODUCTION
DeltaStream has been developed within the framework of
the CMS Preshower development [ 1 ]. It provides a simple
analog signal processor, which can be used for the multichannel
readout of silicon sensors with strip/pad capacitances
up to 55 pF per channel. The prime motivation for the
development was to provide the signal processing necessary
for the production testing of the CMS Preshower silicon
Idet
LCC
Delta Preamplifier
Switched gain shaper
DeltaStream
HG
sensors. DeltaStream incorporates the same analog design
specifications as needed for the CMS Preshower front-end
electronics foreseen for LHC (PACE) but avoids its
complexity.
The main features of DeltaStream are dc coupling to the
sensors, sensor leakage current compensation, two dynamic
range settings with linear response over the ranges 0.1-50
MIPs and 1-400 MIPs, S/N > 10 (for 1 MIP in the 0.1-50 MIP
range), single channel or multiplexed analog readout with
multiplexing frequency up to 20 MHz, radiation tolerance up
to 10 Mrads(Si) of ionising radiation and 4x10 13 ncm -2 .
II. DELTASTREAM DESIGN
The DeltaStream channel architecture is shown in Figure 1.
The architecture is similar to that of the AMPLEX family of
ASICs [ 2 ] but differs in its analog properties and speed of
multiplexed readout.
Each of 36 identical channels include a charge sensitive
pre-amplifier (Delta) with leakage current compensation
(LCC) [ 3 ] followed by a CR-RC 2 shaper and a track & hold
circuit. The outputs from the 36 channels feed into an analog
multiplexer. The multiplexer serialises the sampled analog
voltage from each channel into a stream of analog values. The
analog stream is the then buffered to the outside world
through a single analog output.
(Low Gain = 4mV/Mip)
(High Gain = 30mV/Mip)
T/H
Vo
Track & Hold
Figure 1 : The DeltaStream channel architecture.
36:1
20MHz
Analog
Multiplexer
q
s
Analog
Output
Buffer
Clk

The Delta pre-amplifier provides charge to voltage
conversion producing a “step like” function with a fast initial
response and a slow tail back to the operating point. Delta has
a bipolar input device with optimised emitter area with respect
to noise for highly capacitive sensors (~55 pF) and expected
radiation levels of 10 Mrads(Si) of ionising radiation and
4x10 13 ncm -2 .
The LCC enables dc coupling to the sensor and virtual
insensitivity to sensor leakage current up to 150 µA (well
beyond the requirements of most modern day silicon sensors).
A switched gain shaper provides noise filtering and offers
the possibility of two gain settings and hence two dynamic
ranges. These are:
• High gain (HG) ~30 mV/MIP, dynamic range 0.1-
50 MIPs
• Low gain (LG) ~4 mV/MIP, dynamic range 1-400
MIPs
The peaking times in the two gains have been matched to
25 ns.
The Delta pre-amplifier, LCC circuit and switched gain
shaper were first developed on a demonstrator chip. Details of
the design, optimisation for noise with respect to input
capacitance and irradiation and the demonstrator chip results
before and after irradiation can be found in [ 3 ].
In DeltaStream a track & hold circuit (shown in Figure 2)
is implemented after the shaper which comprises a switch,
storage capacitor (Ch) and an amplifier implemented as a
unity gain buffer. The switch has been designed as a
complementary CMOS switch with W/L values chosen to
have an almost constant “on” resistance with respect to signal
value in order to maintain dynamic range and linearity. The
time constant of the switch plus Ch is 620 ps allowing the
voltage on Ch to track effectively the output from the shaper.
Also shown in Figure 2 is the multiplexer which is
designed to run a 20 MHz. A static shift register is used to
sequentially turn on and off switches connecting each channel
output to the output buffer. The same complementary switch
design as used in the track and hold circuit is used to maintain
linearity.
Output from
shaper
Analog switch
Track & Hold
Ch
p=20/0.8
n=10/0.8
Ch2
Multiplexer
Output Buffer
Cp(mux)
Figure 2 : The track & hold plus multiplexer circuit.
Cl
The drain capacitance of one analog switch is 42fF. The
output node of the multiplexer is connected to each channel
by a metal line, which has a calculated capacitance of 462 fF.
The total parasitic capacitance of the multiplexer output node
including the metal interconnect (462 fF) and drain
capacitance of each analog switch (42 fF each) is ~ 2 pF . This
is represented in Figure 2 by Cp(mux) and is naturally much
larger than the parasitic capacitance associated with each
multiplexer input. Since the signal voltage difference from
one channel to the next may be as large as 1.6V, it is possible
that charge stored on Ch couples back to the multiplexer input
of the next selected channel causing distortion when
multiplexing at high speed. This problem can be reduced by
increasing the drive capability of the track & hold unity gain
buffer but this increases power consumption. Another option
(used in this design) is to deliberately load the track & hold
output with a capacitance matched with Cp(mux) therefore
eliminating the capacitive imbalance. Ch2 in Figure 2
represents the additional capacitor.
Figure 3 shows a photograph of a bonded DeltaStream
chip. The 36 channel inputs are located on the left and the
analog readout buffer is the central block on the right. The
power supply is delivered to the top and bottom as well as
bias currents and voltages. Digital signals for the control of
the multiplexer enter DeltaStream in the lower right hand
section. The digital circuits have their own power supply and
guard-ring. The overall dimensions of the chip are 3.115 mm
x 5.106 mm = 15.9 mm 2 .
Figure 3 : Photograph of DeltaStream.

e
clk
s
Track/Hold
Q pulse on input
Analog output
Single channel mode
re
clk
s
Track/Hold
Q pulse on input
Shaper Output
Analog output
x
Multiplex mode
multiplexed output from 36 channels
Figure 4 : Timing diagrams for operating DeltaStream in "single channel mode" and "multiplex mode.
III. MEASURED RESULTS
All measurements have been made using electrical test pulses
to stimulated the input. An input charge of 4 fC is used to
represent the 25000 e rms produced by 1 MIP traversing a 300
µm thick fully depleted silicon sensor. The inherent parasitic
capacitance of the measurement board has been measured to
be Ci = 13.2 pF (+- 0.8 pF). Additional capacitance (CAdd)
was introduced to the inputs (up to 39 pF) to achieve a total
input loading capacitance of ~52 .2 pF.
DeltaStream can be operated in two modes with respect to
the multiplexer. These two modes are Single channel mode
and Multiplex mode.
Output (Volts)
0.4
0.38
0.36
0.34
0.32
0.3
0.28
0.26
0.24
0.22
Multiplex to
desired channel
(chan. 36 in this case)
dc offset of each
channel visible
Track Mode
Hold Mode
0.4
0.38
0.36
0.34
0.32
0.3
0.28
0.26
0.24
0.22
0.2
0. 1000. 2000. 3000. 4000. 5000. 6000. 7000. 8000
time (ns)
0.2
0. 1000. 2000. 3000. 4000. 5000. 6000. 7000. 8000
time (ns)
Figure 5 : The DeltaStream analog output in single
channel mode.
In single channel mode, the multiplexer can be used to
switch through to one particular channel and stay there
indefinitely. Keeping the track & hold circuit in “track” mode
enables the full pulse shape from the shaper to be observed.
Multiplex mode samples first the signal on the peak and
then multiplexes through all 36 channels.
Output (Volts)
Figure 4 shows a timing diagram for the control signals in
both modes of operation. Figure 5 shows the analog output in
single channel mode. In this case the last channel (36) was
selected and hence the dc values of channels 1-35 are evident
during the channel selection. Channel 36 then remains
connected and a 1 MIP signal is clearly seen during “track
mode. The insert shows the track & hold circuit maintaining
the peak of the signal response.
Figure 6 shows the analog output in multiplex mode. A
signal of 10 MIPs was injected onto channel 18 and sampled
on the peak before multiplexing at 20 MHz. A zoom of the
channel containing the signal shows an initial overshoot of the
signal value by the output buffer. The signal settles within the
first half period of multiplexing, external sampling of the
signal value should therefore be done towards the end of the
second half period when the output has settled.
Output (Volts)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Time (ns)
Figure 6 : The DeltaStream analog output in multiplex
mode.
The channel to channel spread in dc values was measured
as 91 mV peak to peak with a standard deviation around the
mean of σ = 21 mV.

Output (Volts)
0.32
0.315
0.31
0.305
0.3
0.295
0.29
3900 3950 4000 4050 4100 4150 4200 4250 4300
time (ns)
Figure 7 : The signal response for 1 MIP in high gain.
The signal response is best seen in Figure 7. The rise time
(as measured from 10% to 90%) of the signal amplitude was
independent of signal size within the dynamic range.
Measurements showed mean rise times in LG of 14.5 ns with
CAdd = 0 pF and 17.5 ns with CAdd = 39 pF. In HG the mean
rise times were 18.9 ns with CAdd = 0 pF and 21.8 ns with CAdd
= 39 pF. The channel-to-channel variation was ~ 1.5 %.
The dynamic range for CAdd = 39 pF is 50 MIPs in HG and
400 MIPs in LG as shown in Figure 8. The gain (measured by
the mean of straight line fits) was 4.62 mV/MIP in LG with
CAdd = 0 pF reducing to 3.45 mV/MIP with CAdd = 39 pF. In
HG the mean gain was 33.12 mV/MIP with CAdd = 0 pF
reducing to 24.9 mV/MIP with CAdd = 39 pF. The channel to
channel variation of the gain calculated as the standard
deviation (σ) around the mean was ~ 3.5 % (exact values
given in Table 2).
The linearity in both LG and HG is shown in Figure 9
which plots the peak amplitude divided by the input signal in
MIPs against the input signal in MIPs. A straight horizontal
line would show perfect linearity. The integral non-linearity
(INL) (measured as the standard deviation from a straight line
fit of the data in Figure 8 and expressed as a percentage of the
operating range) is 0.42% for LG and 0.21% for HG
measured over the specified ranges of 400 MIPs (LG) and 50
MIPs (HG).
Response (Volts)
1.4
1.2
1
0.8
0.6
0.4
0.2
0
High Gain
Low Gain
0 50 100 150 200 250 300 350 400 450
Input signal (mips)
Figure 8 : The measured peak amplitude for 6 channels in
LG and HG for input signals up to 400 MIPs.
Figure 10 shows the noise measured against total input
capacitance for each channel in HG and the corresponding
straight line fit. The mean fit for all 36 channels showed an
ENC of 676 e + 28 e/pF.
Response (mV/mip)
Response (mV/mip)
6
5
4
3
2
1
Low Gain, mean = 3.45 mV/mip
0
0
40
50 100 150 200 250 300 350 400 450
Input signal (mips)
35
30
25
20
15
10
High Gain, mean = 24.9 mV/mip
5
0
0 10 20 30 40 50 60
Input signal (mips)
Figure 9 : The peak amplitude against peak amplitude
divided by input charge in MIPs .
Noise (electrons)
3500
3000
2500
2000
1500
1000
500
0
2
1.5
1
0.5
Mean 675.9
0
400 600 800 1000
Intercepts (e - )
0 10 20 30 40 50 60
Capacitance (including board) (pF)
3
2
1
0
Mean 28.10
20 30 40
Noise slope (e - /pF)
Figure 10 : Measured noise as a function of the total input
capacitance for all 36 channels.
The power consumption for each module and the entire
chip is given in Table 1. The gain-bandwidth required by the
track & hold op-amp. is less in multiplex mode compared to
single channel mode. Increasing the distance in time marked
“X” in Figure 4 allows the track & hold power consumption
to be reduced in multiplex mode.
Delta pre-amp + LCC 5.12 mV / ch.
Shaper 5.6 mV / ch.
Track & hold (single chan. mode ) a 8 mW/ ch
Track & hold (multiplex mode ) b 950 µW / ch
Output Buffer 10 mW
Total Power consumption 684 mW a 430 mW b
Table 1 : The DeltaStream power consumption.
A summary of the principle results from the DeltaStream
measurements is contained within Table 2 .

Measurement type &
Low Gain High Gain
additional Capacitance pp mean V pp mean V
Rise time (0 pF)
14.5 ns 0.21 ns
18.9 ns 0.27 ns
Rise time (39 pF)
17.5 ns 0.23 ns
21.8 ns 0.38 ns
Gain (0 pF)
4.62 mV 159 µV
33.12 mV 1.16 mV
Gain (39 pF)
3.45 mV 112 µV
24.90 mV 925 µV
DC Baseline (0 pF)
(Channel to channel)
91 mV 21 mV 69 mV 18mV
Linear range & INL
(39 pF)
400 MIPs (1600 fC) with INL = 0.42% 50 MIPs (200 fC) with INL = 0.21 %
Noise (HG) ENC = 676 e + 28 e/pF
Table 2 : Summary of DC levels, gain over the full dynamic range, rise time and noise. The results of all 36 channels
are included.
Laser plus
splitter
2
Photo
sensor
Preshower
silicon sensor
1
A
D
C
DeltaStream
Passive surface
mounted components
to provide biasing
Daughter board
Position and timing laser control
Analog buffer
DeltaStream
multiplexed analog
output
DeltaStream
control signals
ADC
PCB
PC
running Labview
Figure 11 : Preshower silicon sensor laser measurement system using DeltaStream.
IV. APPLICATION EXAMPLE
DeltaStream can be used for the analog signal
processing of silicon strip/pad sensors that require low
noise and large dynamic range. The application foreseen
within the CMS Preshower development is a silicon sensor
measurement system. The Preshower sensors are to be
produced in a number of regional centres around the world.
In order to maintain consistency between test methods and
results during the production phase a common
measurement system is required. Figure 11 shows a block
diagram of the system. A laser is used to generate pulses of
light with wavelength 1060 nm. A passive “splitter” is used
to divide the light into two parts and fibre optic cables
direct the light to well focused regions on the sensor strips
and to a photo sensor. The charge from the strips are
readout by DeltaStream and digitised by an ADC. The
signal from the photo sensor is also digitised and the two
results compared on a PC.
V. CONCLUSIONS
The design and results of DeltaStream have been
presented. DeltaStream contains 36 identical channels of
pre-amplifier, 25 ns peaking time shaper and a track & hold
circuit. The analog signal from each channel is multiplexed
to a single analog output at frequencies up to 20 MHz.
DeltaStream has a selectable gain (LG and HG) offering a
FPGA
linear response over 2 dynamic range settings of 0.1-50
MIPs (HG) and 1-400 MIPs (LG). DeltaStream has been
designed to readout large silicon strip/pad sensors imposing
up to 55 pF of input capacitance per channel. The chip can
be dc connected to the sensor and is unaffected by sensor
leakage current up to 150 µA per channel.
VI. REFERENCES
[ 1 ] The CMS collaboration The Calorimeter Project
Technical Proposal (CERN/LHCC 94-43 LHCC/P2, 1994)
[ 2] E.Beuville, K.Borer, E.Chesi, E.Heijne, P.Jarron,
B.Lisowski, S.Singh AMPLEX, A low noise, low power
analog CMOS signal processor for multi-element particle
detectors. Nuclear Instruments & Methods in Physics
Research A 288 (1990) 157 North Holland
[ 3 ] P. Aspell, D.Barney, P.Bloch, P.Jarron, B.Lofstedt,
S.Reynaud, P.Tabbers Delta: A charge sensitive frontend
amplifier with switched gain for low-noise, large
dynamic range silicon detector readout. Nuclear
Instruments & Methods in Physics Research A 461 (2001)
449-455
[ 4 ] A.Go, A.Peisert The Preshower gain pre-calibration
using infrared light (CERN CMS internal note 2001)

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Production and Test of the ATLAS Hadronic Calorimeter Digitizer
S. Berglund, C. Bohm, K. Jon-And, J. Klereborn, M. Ramstedt and B. Selldén
Abstract
The pre-production stage of the full-scale production of
the ATLAS TileCal digitizer started during the summer
2001. To be able to ensure full functionality and quality, a
thorough test scheme was developed.
All components are radiation tested before start of
production. After mounting components all digitizer boards
will pass burn-in and tests in Stockholm. Custom designed
software ensures that full functionality is maintained. A
record of the test results is stored in a repository accessible
via Internet for future reference. Similar test software is later
used at the site of full electronics assembly in Clermont-
Ferrand cross referencing their results with the test data
entries.
A. The Digitizer
I. INTRODUCTION
Stockholm University is responsible for design,
manufacture and quality control of the digitizing unit of the
ATLAS Hadron Calorimeter [1]. The calorimeter is often
called TileCal because of its interleaved iron and scintillating
tiles. Heavy particles interact with the iron tiles and form
showers of charged particles that produce light in the
adjacent scintillating tiles. This light is transferred to an array
of PMTs via wave length shifting fibers. The PMTs and all
the front-end electronics are contained in so called drawers at
the base of the calorimeter modules. There are 32 or 45
PMTs in a drawer depending of its position in the detector.
The PMTs are connected to 3-in-1 cards [2] that shape and
amplify the pulses. The 3-in-1 cards are in turn connected to
digitizers that sample the pulses.
Each digitizer board serves six 3-in-1 channels. There are
two TileDMUs, a specially designed controller and readout
ASIC, on each digitizer board. Data from the TileDMUs are
read out via a G-link based interface board (Fig.1). The TTCsystem
[3] delivers timing and slow control to the interface
Stockholm University, Sweden October 2001
mank@physto.se
board via fibers. The TTC signal is then distributed to the
digitizer boards. A drawer contains eight or six digitizer
boards depending on its placement in the detector with the
interface board placed in the middle. When a digitizer board
at the far end of the drawer is read out, data and TTC signals
pass through lines with no active components on
intermediate boards. Thus, any malfunctioning components
on a digitizer board will only corrupt its own data.
TTC-rx
Tile_DMU Tile_DMU
TTC-rx
Tile_DMU Tile_DMU
TTC-rx
Tile_DMU Tile_DMU
interface
Read-out
optical fibers
TTC-rx
Tile_DMU Tile_DMU
Tile_DMU Tile_DMU Tile_DMU Tile_DMU Tile_DMU Tile_DMU Tile_DMU Tile_DMU
TTC-rx
TTC-rx
TTC-rx
TTC-rx
TTC distribution
interface optical fibers
Fig. 1 The data flow along a chain of eight digitizer boards
The main components of the digitizer board are the
ADCs, the TileDMUs and the TTCrx. The ADCs are ten bits
converters. To provide an effective dynamic range of 16 bits
there are two ADC channels per PMT channel digitizing the
two signals from the 3-in-1 card. These are high and low gain
signals with an amplification ratio of 64.
Data from all channels are stored temporarily in pipeline
memories in the TileDMUs. When the first level trigger
validates an event the TileDMU will choose the appropriate
gain, according to the amplitude of the signal, format the data
and store it in a readout buffer. Functions for tests and
calibration are also part of the TileDMU.
B. Production of the digitizer
In order to ensure the quality of the full production, the
pre-production has been made as close to the real production
as possible including all steps: manufacture, mounting, burnin,
tests and logistics. All design is now almost completed
and final manufacturer and assembly-company will soon be
chosen. A few small design modifications will be made to
take care of a yield problem that was discovered during preproduction
when mounting a high-density surface connector.

The production and the test routines will also be improved to
implement some additional features suggested by the preproduction
experience.
In the pre-production 86 boards were manufactured and
assembled with a surprisingly high fault rate level of about
35 %. The sources of these faults have been investigated and
are to a large extent understood. About 20% failed due to
badly soldered data connectors. To fix this the connector
surface mount pads will be modified. About 5% failed due to
malfunctioning TileDMUs. This number was expected since
the TileDMUs of the pre-production were not fully tested
before delivery. The remaining 10% failures are being
investigated in more detail. When this is done there will be a
final product readiness review (PRR) and the mass
production will start, most likely in November this year.
A. Test procedure
II TESTS
To ensure the quality and functionality of the digitizer
boards, tests are made at several checkpoints along the
production process. Components used on the board are
required to be radiation tolerant and are tested according to
the ATLAS recommendations [4]. Unassembled boards are
checked for breaks and shorts at the board manufacturer.
Functionality of the TileDMUs are tested before and after
packaging i.e. just before they are sent for assembly. After
mounting the components the boards will be superficially
tested before delivery to the burn-in and test facility at
Stockholm University. The burnt in boards are thoroughly
tested and then sent to the drawer assembly plant at
Clermont-Ferrand for assembly and final tests.
B. Test Bench Setup
A test drawer has been set up for the purpose of
production tests. This set-up is quite similar to a final
ATLAS drawer. A RIOII VME processor is used as readout
buffer and a TTCvi module as a source of clocks and for
configuration of the digitizer boards (Fig. 2). These tests are
all controlled by RIOII software. The main electronic parts in
the test drawer are the 3-in-1 system, the digitizer boards and
the interface link board.
Fig. 2 Schematic picture of the test bench components and signal
flow
C. Radiation Tests
Workstation
RIOII
Data (G-link)
TTCvi
Interface board
Laser Crate
TTC-signal
Digitizer x4
Digitizer x4
Most active components have been tested for radiation
tolerance and the remaining tests will take place before the
final PRR and start of production.
According to ATLAS requirements the digitizer should,
without damage, resist the following doses: 3.5 krad ionizing
radiation and 2.3*10 12 1MeV eq neutrons/cm 2 .
Corresponding numbers for components containing bipolars
are 17.5 krad and 2.3*10 12 . These figures include the
appropriate safety factors. Tests for single event effects
(SEE) [4] should also be performed. With one exception
(TTCrx), none of the digitizer components have a formal
specification on radiation tolerance from the manufacturer.
Several tests have therefore been made to select components
with the best radiation tolerance, which also are acceptable
from the price/performance point of view. During the process
several types of components have been rejected.
The full installation will contain around 22000 ADCs.
About 40 samples from various batches have been radiated
up to 50 krad and a subsample even up to 100 krad. Our
result is that all samples stand 30 krad and some even 100

krad of ionizing radiation. 18 samples have been exposed to
7.5*10 12 1 MeV eq n/cm 2 with no malfunction detected.
Between 8 and 20 samples from each of the digitizer
CMOS circuit have been exposed to 10 krad ionizing
radiation and 5*10 12 1 MeV eq n/cm 2 . No errors were
detected.
Only one sample of the TileDMU (CMOS) has been
tested with radiation levels as above. For that sample no
malfunction was detected. Eight more will be tested shortly.
A special test bench that tests the TileDMU has been
developed for the study of transient errors.
In the near future we plan to make SEE tests on system
level using a 170 MeV proton beam. Also here we need to
develop a dedicated test bench.
D. Test of the PCB
The vendor will test non-assembled boards for circuit
breaks and short circuits. Faulty boards are rejected. After
assembly the boards are visually inspected for obvious
mistakes and tested for power short circuits. A superficial
test using a dedicated test bench, similar to the one that will
be used in the board SEE tests, is planned. A more thorough
test is made after the burn in.
E. Test of data and TTC connector
In a drawer four digitizers are read out in a chain to the
interface board. Data from the TileDMU, and data and the
TTC signals from boards further away from the interface will
pass through a high-density surface mounted connector on
each digitizer board. A faulty connector can therefore
generate errors when passing signals from another board.
Before starting the full test procedure the connectors must be
thoroughly tested. This will be done using three fully
functional boards as reference boards. The board to be tested
is placed close to the interface board so all connector pins are
used. This is not the most efficient method since one would
like to test more than one board at a time in the drawer. By
testing the connector in a special connector test tool, much
time can be saved. Such a tool is being developed.
F. Functionality Test
After burn-in and test of the data connector, the
functionality of the entire board will be tested. The only way
to do this is to first configure the digitizers and the 3-in-1system
and then read out data. This is done simulating the
TileCal front-end electronics environment. It can be difficult
to identify the error in faulty boards by analyzing the data
since most components interact. However, if a board passes
the test this will guarantee that ATLAS functionality is
maintained [5].
First of all the TTCrx is tested to verify that the proper
clocks are generated and that commands can be transferred to
the digitizers. The TTC single error and double error flags
[3] are monitored to verify the TTC transmission quality.
This test also verifies that the TileDMUs are able to read out.
The next step is to exercise the TileDMU verifying that
all programming parameters can be set. The memory is tested
with different bit patterns. This is done using a test mode
where all data are generated internally.
Test pulses are produced by the 3-in-1 system to verify
that none of the ADC bits are stuck at one or zero. The
pedestal RMS is then calculated to estimate the noise level.
The pedestal levels are examined to determine whether a
component adjustment is needed. An on-board DAC is used
to scan part of the dynamic range to determine the linearity.
All readout is protected by data word parity and cyclic
redundancy check. Errors are not accepted.
G. History files and QC-Sheet
For all digitizer boards the history of modifications, test
data and some characteristics are stored in a history file.
These are auto-generated from the software and are stored in
HTML/ASCII-format for accessibility. When a board has
passed all tests a quality control sheet is generated in HTMLformat
for easy access by the collaboration.
H. Software
The test software is split into two programs, the
configuration and readout software (CRS) and the graphical
user interface and analysis software (GUI). The CRS is
running on the RIOII in the same crate as the TTCvi. It
controls the configuration of the digitizers and the 3-in-1
system via the TTCvi and receives data from the digitizers
via an S-link PCI card attached to the RIOII. This part is
called Coot-Boot. The GUI, called Baltazar, is running on a
workstation (e.g. Windows NT PC) communicating with
Coot-Boot via TCP/IP. The idea behind Baltazar is to
implement a user-friendly interface making it easy to operate
the test bench after a short introduction. The software
automatically generates the history report files and makes
them accessible from WWW.
The GUI is coded in JAVA to achieve platform
independence. JAVA is also easily available and well

documented on the web. Baltazar has also been used as
reference software in TileCal test-beam. The data analysis is
made by Baltazar requiring all data (~900kByte/run) to be
transferred from Coot-Boot. This takes only a few seconds.
The JAVA code makes the analysis sufficiently fast.
III. CONCLUSIONS
The TilCal digitizer is soon ready for full production. In
order to assure fully tested boards and a high production
yield many test procedures have been developed and inserted
in different places along the production chain. This has
required the development of different hardware and software
test benches.
However there are still a few tests that must be improved.
This will be done before the final production.
IV. ACKNOWLEDGEMENTS
We would like to thank J. Molnar and A. Fenyvesi from
Atomki in Debrecen for their help making the neutron
irradiation of our components.
V. REFERENCES
1 ATLAS Tile Calorimeter Technical Design Report,
CERN/LHCC 96-42
2 Front-end Electronics for the ATLAS Tile Calorimeter,
K. Anderson, J. Pilcher, H. Sanders, F. Tang, S.
Berglund, C. Bohm, S-O. Holmgren, K. Jon-And, G.
Blanchot, M. Cavalli-Sforza, Proceedings of the Fourth
Workshop on Electronics for LHC Experiments, Rome,
1998, p.239
3 http://www.cern.ch/TTC/intro.html
4 Atlas policy on Radiation Tolerant Electronics, ATLAS
document no ATC-TE-QA-0001 21-July 00
5 The ATLAS Tile Calorimeter Digitizer, S. Berglund, C.
Bohm, M. Engström, S.-O. Holmgren, K. Jon-And, J.
Klereborn, B. Selldén, S. Silverstein, K. Andersson, A.
Hocker, J. Pilcher, H. Sanders, F. Tang, H. Wu,
Proceedings of the Fifth Workshop on Electronics for
LHC Experiments, Snowmass, Colorado, 1999, p.255
6 S-link: a Prototype of the ATLAS Read-out Link, E. van
der Bij, O.Boyle, Z.Meggyesi, Fourth Workshop on
Electronics for LHC Experiments, Rome 1998, p. 375.

Low Voltage Control for the Liquid Argon Hadronic End-Cap
Calorimeter of ATLAS
Abstract
The strategy of the ATLAS collaboration foresees a
SCADA system for the slow control and survey of all subdetectors.
As software PVSS2 has been chosen and for the
hardware links a CanBus system is proposed.
For the Hadronic End-caps of the Liquid Argon
Calorimeter the control system for the low voltage supplies is
based on this concept. The 320 preamplifier and summing
boards, containing the cold front-end chips, can be switched
on and off individually or in groups. The voltages, currents
and temperatures are measured and stored in a database. Error
messages about over-current or wrong output voltages are
delivered.
H.Brettel * , W.D.Cwienk, J.Fent, H.Oberlack,
P.Schacht
Max-Planck-Institut für Physik, Werner-Heisenberg-Institut,
Foehringer Ring 6, D-80805 Muenchen
brettel@mppmu.mpg.de
Figure 1: DCS detector control system (principle structure)
I. DETECTOR CONTROL SYSTEM OF ATLAS
The slow control of detectors, sub-detectors and
comp onents of sub-detectors is realized by a so-called
SCADA software, installed in a computer net. It is an
industrial standard for Survey, Control And Data Acquisition.
The product, installed at CERN, is “PVSS2” from the
Austrian company “ETM”.
Links between net nodes and hardware can be realized in
different ways. Between the last node and the detector
electronics a CanBus is recommended by the collaboration for
the transfer of slow control signals and the survey of
temperatures, supply voltages and currents (figure 1).

II. LOW VOLTAGE CONTROL OF HEC
A. System Overview
The supply voltages for the cold front-end electronics of
the two Hadronic End-cap wheels are generated in 8 power
boxes near the front-end crates and distributed to the 320
preamplifier- and summing boards inside the cryostats (see
figure 3).
Graphical windows on a PC (figures 2 and 4), tailored to
operators needs, offer complete individual control und survey
of the 320 supply channels .
The application software in the PC is called a “PVSS2project”.
It establishes the link to the DCS net by an
appropriate protocol. The exchange of information with the
low voltage channels takes place via a CanBus by a CanOpen
protocol. CAN is a very reliable bus system widely used by
industry, for example in cars for motor management, brake
activation etc.
At the ATLAS DCS the PC is bus master. The
hardware interface board NICAN2 is controlled by the driver
software OPC. CanBus slaves are offered by industry for
different purposes. We use the ELMB from the CERN DCS
group, which is tailored to our needs. It has 2 microprocessors
inside, digital I/O ports, a 64-channel analog multiplexer and
an ADC.
Figure 4: PVSS2 main panel, “LV CONTROL”
Figure 2: Liquid Argon Calorimeter
Figure 3: HEC low voltage system (one end-cap)
The panel displays the structure of the system. By mouse-click on items
of this panel the operator can open other panels that show more details and offer full
access to hardware components and the database (figures 5 and 6 at next page). To
distinguish between different types of daughter panels, a colour code is applied: red
signifies an action panel and violet a display of hardware details (mechanics, circuit
diagrams).

Figure 5: PVSS2 daughter panel “CHANNEL CONTROL”
B. Hardware
Colours are changed and animated (blinking) in case of
fault conditions, like wrong voltage or excessive current.
Each of the two HEC-wheels consists of 4 quadrants
served by a feed-through with a front-end crate on top of it
(figure 2). Each quadrant is equipped with 40 PSBs, (the
preamplifier and summing boards, which contain the cold
GaAs front-end chips). A related power box, delivers the low
supply voltages. For each wheel 4 boxes are needed. The are
mounted between the fingers of the Tile Calorimeter, about
half a meter away from the front-end crates.
The input for a power box – a DC voltage in the
range of 200 to 300V – is transformed into +8V, +4V and -2V
at the 3 output lines by DC/DC converters and then split into
40 channels at two control boards (figure 7). There is an
individual ON/OFF control and a fine adjustment of the three
supply voltages for each PSB.
Figure 6: PVSS2 daughter panel “CALO QUADRANT”
3-dimensional view with animated colours

1) Original design
We intended to use the integrated low voltage
regulators L4913 and L7913 from STm. They should be
mounted on the control boards inside the power boxes
Figure 7: Low voltage control board (original design)
2) Actual problems
Meanwhile it turned out that the ELMBs are not as
radiation hard as we had expected and cannot be mounted at
the foreseen position.
The low voltage regulators from STm are confirmed
to be radiation hard, but there seems to be still problems in the
design or fabrication process.
So we have to envisage alternate solutions, at least
during the present phase of design work. Concerning the
ELMBs there is no other way than to place them outside the
Myon chambers, but we would still like to apply the above
mentioned regulators for reasons of small size and low cost.
3) Prototype designs
During the assembly of the wheels at CERN and for
combined tests, existing power supplies will be used. Control
boards, corresponding to the original plan but in non-radiation
hard technology, are in preparation. ELMBs will be mounted
on these boards. Instead of STm-regulators other products
must be used and can be replaced later by types of final
choice (STm or other radiation hard regulators).
Ongoing considerations about final solutions will
result in a second version of control board with radiation hard
components. The ELMBs, which will no more be mounted on
the boards but far outside the power box, are connected by a
multi wire cable. As a consequence of this arrangement an
together with FPGAs from QuickLogic, which contain the
necessary digital control circuitry, and the ELMBs as
interfaces to the CanBus. By this arrangement the cable
connections to the power boxes could have been minimized.
array of analogue multiplexers is needed on the boards as well
as much more complex logic in the FPGA.
4) Final Solutions
A) The American company “Modular Devices” is
developing power supply boxes for EMEC under the direction
of “BNL”. As the units will be mounted between the fingers
of the tile calorimeter, radiation hardness is mandatory. As
primary choice we envisage to adopt this solution. Only the
output voltages would be adjusted to the values required by
HEC, and two control boards from MPI mounted additionally
inside. The main disadvantages are relative high cost and the
present uncertainty about the STm-regulators.
B) Therefore a second source is highly desirable. We
are negotiating with the German company “GSG-Elektronik”
near Munich, which is experienced in radiation hard
electronics for space research. The company offered a design
study and would be able to built prototypes in an acceptable
time. Either one could apply big DC/DC converters (a certain
number in parallel for redundancy), which deliver precisely
the desired voltages, and then split the output into 40 channels
with transistor switches in series, ore use for each channel a
small DC/DC converter with remote on/off control. In any
case there would be no need to have the problematic STmregulators.
The negative aspect of these approaches is, that
the company would put the responsibility and actions for
radiation tests to MPI.

5) Safety aspects
Temperature sensors are foreseen in the power
boxes on each board as well as detectors for leaking cooling
water. In case of a serious problem the main is switched off
automatically.
The power supplies have a build-in over-voltage
protection and the low voltage regulators (or the small DC/DC
converters respectively) have a current limitation. The
maximal current is adjusted to such a low value, that the wires
in the feed-through cannot be damaged in case of a steady
short circuit inside the cryostat. In addition, in case of an
over-current, an error signal is delivered and all 3 regulators
that belong to faulty channel are switched off immediately by
the internal logic. Afterwards a detailed description of the
problem is sent to the PC.
Under normal operating conditions the temperatures
of the boards and the supply voltages and currents of all
channels are registered regularly.
Figure 8: PVSS2, a SCADA software for slow control
D. Status of Development
Tests of substantial hard and software components
have been carried out. The work on control boards is
progressing. A link between a PVSS2 test program on a PC
and an ELMB (via OPC, NICANII and CanBus) is
operational.
For the case that a computer or the bus itself would
fail, an emergency control system is planed, independent of
the CanBus. By remote switches in the measuring hut, the
operator can switch off or on all channels simultaneously.
C. Software
As mentioned before, the control program is written
in PVSS2, which is based on the ANSI C-language. It has
several graphics tools that help the programmer during the
design phase.
A data point structure and a list of data points has to
be established first. The so-called “Data Points” are variables
in the program, where the information about all hardware
items is stored. By the aid of a graphics editor, panels are
designed for various purposes (displays, actions, diagrams).
Symbols on panels are connected to control scripts (Clanguage).
At runtime the automatically generated main
program uses the scripts as subroutines.
We are gaining more and more experience with the
PVSS2 software. Many examples of graphics panels and
control scripts have been developed and are supposed to be
the basis for the low voltage control program.
A decision about a second source of power boxes
should be taken in the near future.

On the developments of the Read Out Driver for the ATLAS Tile Calorimeter.
J. Castelo 1 ,V.González 2 ,E.Sanchis 2 , J. Torres 2 ,G.Torralba 2 ,J.Martos 2
1 IFIC, Edificio Institutos de Investigación - Polígono la Coma S/N, Paterna, Valencia, Spain
Jose.Castelo@ific.uv.es
2 Dept. Electronic Engineering, Univ. Valencia, Avda. Dr. Moliner, 50, Burjassot (Valencia), Spain
Vicente.Gonzalez@uv.es, Enrique.Sanchis@uv.es, Jose.Torres@uv.es, Gloria.Torralba@uv.es, Julio.Martos@uv.es
Abstract
This works describes the present status and future
evolution of the Read Out Driver for the ATLAS Tile
Calorimeter. The developments currently under execution
include the adaptation and test of the LiAr ROD to Tile Cal
needs and the design and implementation of the PMC board
for algorithm testing at ATLAS rates.
The adaptation includes a new transition module with 4
SLINK inputs and one output which match the initial TileCal
segmentation for RODs. We also describe the work going on
in the design of a DSP-based PMC with SLINK input for real
time data processing to be used as a test environment for
optimal filtering.
I. INTRODUCTION
At the European Laboratory for Particle Physics (CERN)
in Geneva, a new particle accelerator, the Large Hadron
Collider (LHC) is presently being constructed. In the year
2006 beams of protons are expected to collide at a center of
mass energy of 14 TeV. In parallel to the accelerator, two
general purpose detectors, ATLAS and CMS, are being
developed to investigate proton-proton collisions in the new
energy domain and to study fundamental questions of particle
physics .
This new generation of detectors requires highly hardened
electronics, able to deal with a huge amount of data in real or
almost real time. The work we present here is included in the
studies and development currently carried out at the
University of Valencia for the Read Out Module (ROD) of the
hadronic calorimeter TileCal of ATLAS.
II. THE TILECAL ROD SYSTEM
TileCal is the hadronic calorimeter of the ATLAS
experiments. It consists, electronically speaking, of 10000
channel to be read each 25 ns. Data gathered from these
channels are digitized and transmitted to the data acquisition
system (DAQ) following the assertions of a three level trigger
system [1].
In the acquisition chain, place is left for a module which
has to perform preprocessing and gathering on data coming
out after a good first level trigger before sending them to the
second level. This module is called the Read Out Module
(ROD).
For TileCal, the ROD system will be built most probably
around custom VME boards which will have to treat around 2
Gbytes/s of data. Intelligence will be provided to do some
preprocessing on data.
For the reading of the channels we are working on a
baseline of 64 ROD modules. Each one will process more
than 300 channels. The studies currently going on at Valencia
focus on the adaptation of the first prototype of the LiArg
ROD to TileCal needs.
The basic schema to use is based on the ROD crate
concept in which ROD modules are grouped into VME crates
jointly with a Trigger and Busy Module (TBM) and possibly
other custom cards when needed. This ROD crate interfaces
with the TileCal Run Control and the ATLAS DAQ Run
control. Figure 1 shows this structure schematically [5].
Figure 1: TileCal ROD System
The basic functions and requirements of all ATLAS ROD
can be found in [1] and may be summarize saying that the
ROD board receives the data from the FEB which after some
processing are sent to the ROB. These data may be buffered
to be able to work with the maximum LVL1 trigger rate (100
KHz) without introducing extra dead time.
For each particular detector, some preprocessing could be
done at ROD level. For TileCal, RODs will calculate energy
and time for each cell using optimal filtering algorithms
besides evaluating a quality flag for the pulse shape (χ 2 ).
RODs will also do the data monitoring during physics runs
and make a first pass in the analysis of the calibration data

leaving the complete analysis to the local CPU of the ROD
crate.
In some cases data will not be processed and will flow raw
to LVL2. These include interesting events, large energy
depositions in a cell or debugging stages.
It will be also desirable to have the functionality to apply
corrections to the energy or time estimators for example to
correct the non-linearities in the shaper or in the ADC.
Finally ROD will monitor the Minimum Bias and pile-up
noise and will have the possibility of working in special runs
at reduced trigger rate.
III. LIARG ROD AND TILECAL ROD
As mentioned before, our work develops now in the
direction of adapting the first LiArg ROD prototype [7] to
TileCal needs exposed before. The main reason to do this is
the great similarity of the two detectors and the great
difference in the requirements which make LiArg solutions
suitable, with modifications, for TileCal.
The basic differences in the ROD concept for LiArg and
TileCal rise, in a first approximation, in the working baseline
which is summarized in table 1.
Table 1: ROD baseline for LiArg and TileCal
Input links (32 bits @
40 MHz
Number of channels
per board
Number of DSP
Processing Units
Number
channels/DSP PU
of
Output
Mb/s)
Links (800
Motherboard
ROD LiArg ROD TileCal
Baseline
2 4
256 154
(2*64b+2*31eb)
4 4
64 46b or 31eb
1 1
(1,14 Gb/s, expected)
P1
P0
P2
P3
P2
P3
Transient M odule
Input From FEB
(optical or Cu)
Input From FEB
(optical or Cu)
O utput to R O B
(S -link ,....)
Figure 3: LiArg ROD prototipe
The block diagram of the LiArg ROD prototype is shown
in figure 3. It is based in a 9U VME motherboard which holds
four DSP-based processing units (PU) as mezzanines. These
mezzanines are based on TI C6202 DSPs at 250 MHz with
some external logic: FIFOs, FPGAs and memory. Figure 2
shows the block diagram of the PUs [8].
The input and output of data is place on a 9U transition
module. For the first prototype this module has only two
inputs and one output.
To adapt this solution to TileCal needs we need to
reconsider the following aspects:
• Data input/output format and rates: we need 4 inputs
and one output at the transition module. This implies
a new design of this transition board.
• Processing power: because of its great number of
channels, LiArg DSP PU have a lot more computing
power than needed in TileCal. This issues the
question of whether it is necessary to use exactly the
same type of PUs or we could use cheaper ones even
not based on DSPs but on FPGAs.
Because of the modularity of the LiArg solution, our work
focuses on the design of a new transition module, leaving the
decision about the PU postponed.
Figure 2: Block diagram of the DSP Processing Units.
IV. THE TM4PLUS1 TRANSITION MODULE
Lets now get into the description of the new design carried
out to adapt TileCal inputs to the LiArg motherboard. This
new transition module is called TM4Plus1.

This module has been developed and implemented at CERN
by the EP/ATE group. Its block diagram is shown in figure 4.
Fifo
F1
Fifo
Aux.
Altera
Leds
F2
F3
Transceiver
Ref.
Altera
Fifo
Figure 4: TM4Plus1 block diagram.
The transition module is a modified version of the one
used by LiArg that includes 4 input SLINK channels in PMC
format and 1 GLINK output integrated in the PCB. The PMC
input channels are capable of reading 4x32 bits at 40 MHz
and allow us to test different input technologies. The output
will also run at 40 MHz with a data width of 32 bits [4] [6].
On the board there are also 4 input FIFOs, 4Kwords each,
to accommodate the differences between input speed and
processing on the FPGAs.
These lasts are implemented on two ALTERA devices.
The tasks of each of the FPGAs are:
• Reformatting Altera: data multiplexing and SLINK
control. This devices will reformat and merge data in
a 4 to 2 manner to produce data similar to what the
motherboard is expecting if used with LiArg detector.
• Auxiliary Altera: it holds the code for the integrated
ODIN output. The free space left will be used in
conjunction with the reformatting Altera.
The data flow to these FPGAs is shown in figure 5.
Following the tasks division the reformatting Altera receives
the data from the 4 input channels to perform the 4 to 2
multiplexing. Data is sent to the motherboard through P2
connector on the VME backplane with the same format as
LiArg.
Signal mapping
LD, UXOFF, URESET, Configuration
LCTRL, LWEN, LCLK, Pins
LDERR, LDOWN 10
39
bufferCLK LD[0..31], LCTRL, LDERR
34* FIFO A
UTDO, UDW0/1,
URL[3..0]
7
39
UTDO, UDW0/1,
URL[3..0] 7
Reformatting
READEN, EMPTY,
4*
Altera
FULL, UXOFF
Same lines to
(247pins)
BUSM, FWFT, FIFO B, C, D
3 MRESET*
(+10conf.pins)
2* URESET,
LDOWN
39 5
bufferCLK S-LINK A
4
Auxiliary
UTDO, UDW0/1,
7* URL[3..0]
Altera
*: these lines count 4 times, one
(243+10pins)
for each S_LINK or FIFO.
G-LINK
corner
68
Signals to
the G-LINK
45
**: LSC and LDC signals defined in the S-LINK specifications;
UD, LFF, URESET, UTEST, UDW0/1, UCTRL,
UWEN, UCLK, LRL[3..0], LDOWN, RSVD**
J2A
J2B
J3A
J3B
Figure 5: Data flow on the TM4Plus1.
Fifo
The other Altera receives some lines from the first and
hold the ODIN output code. Data once processed at the
motherboard is sent through P3 connector to this FPGA to be
sent to ROBs.
The basic data processing on the reformatting Altera
relates to the forma conversion between TileCal and LiArg.
Fortunately, front-end data format on both detectors is quite
similar and we have to deal only with a data width problem.
This problem is due to the fact that on the motherboard, the
32-bit path of P2 connector is splitted into two 16-bit paths
each one going to a PU. For TileCal with have 32-bit paths
already in the front-end data, so we have to divide these data
into 16-bit blocks and send them consecutively to the
motherboard.
There is also a problem with data control due to the way
the LiArg motherboard controls the data flow. Situations may
arise when we could have data only on one of the two input
provided to first check if this occurs and second to solve it.
Our proposal implements a time-out activated on the
arrival of the first data on one of the input links to be
multiplexed. If after the time out no data are received, the
space for that channel is filled with zeros and a flag is set on
the header to let the PU treat these data as no-data instead of
zeroes.
These two processes are depicted schematically in figure
6.
SLINK-1
SLINK-2
A
B
C
D
Data multiplexing
ALTERA
B A 1
1
D
C
1
15
Time
1
SLINK-2
C
D
SLINK-1
delay
A
B
Data present on links
ALTERA
Figure 6: Data multiplexing using FPGAs
V. PRESENT DEVELOPMENTS
At IFIC and University of Valencia there are three
development fronts undergoing.
The main is related with the tests and developments for the
TM4Plus1 board and the final ROD prototype, the second
goes towards the design and implementation of a PMC card
for algorithm tests and the third deals with the software issues
at the ROD controller.
Lets review now the current status on each of these
directions.
A. The TM4Plus1 board and final ROD
prototype
The tasks on the TM4Plus1 board currently going on are
of two kinds:
Hardware:
B
0
Time
A
0

•Test of motherboard and PUs. This is already finished.
•Test of the TM4Plus1 transition module: not yet
finished.
•Design of a custom FPGA based PU: starting.
Software:
•TM4Plus1 FPGAs: going on. This work refers to the
implementation of the processing commented before on the
two Alteras
•PUs: we need to reprogram the DSPs to do optimal
filtering and also the input FPGA.
For the final ROD prototype we are currently designing a
new PU based on FPGA instead of DSPs. These will imply a
reduction in cost, because the DSP PU are the most expensive
component in the LiArg ROD, and an increase on parallelism
as we will not be limited by the DSP architecture but by the
FPGA capacity. Our working block diagram for a final
TileCal ROD prototype is shown in next figure.
ROD Motherboard
Processing Unit (PFGA Unit)
Ttype&BCID
FIFO
Fragment FIFO
Processing Unit (PFGA Unit)
Ttype&BCID
FIFO
Fragment FIFO
Ttype &
BCID
Check
Processing Unit Slot
Not USED
TTCFPGA&TTCrx
Ttype &
BCID
Check
Processing Unit Slot
Not USED
VME
Comm
Output
Controller
P1
J2A
P2 ---
J2B
P3 J3
Transition Module
FIFO S-LINK A - LDC
FIFO S-LINK B - LDC
FIFO S-LINK C - LDC
FIFO S-LINK D - LDC
Reformatting Altera (APEX 20k)
FIFO/SLINK Control
S2P
Paroty, CRC &
data alignment
CHECK
Auxiliary Altera (APEX 20k)
SLINKControl
Energy
Fragment
Builder J2B
BCID, Ttype
extractio n
Energy & time
calculation unit "m"
Energy
Fragment
Builder J2A
Energy & time
calculation uni "n"
Energy & time
calculation unit "x"
Energy & time
calculation uni "y"
Integrated G-LINK
Figure 7: Final TileCal ROD prototype.
FEB Data
LVL2 Data
As it can be seen we keep the LiArg motherboard to have
VME access and the TM4Plus1 board, but substitute the DSP
PUs by new FPGA based ones. Also a redistribution of tasks
occurs, placing almost all processing issues on the FPGAs of
the transition module where energy an timing estimation will
take place. On the motherboard only data integrity checking
and TTC operation will be done.
By processing data on the transition module we reduce
data volume flowing to the motherboard. This opens the
possibility of increasing the number of input channels on the
transition module by previously integrating them on the PCB
(no more PMCs).
B. The SLink PMC card
Parallel to these activities we are also involved in the
design and development of the DSP based PMC card with
SLINK input for testing the optimal filtering algorithms on a
commercial VME processor.
The basic idea is to have a PMC with SLINK input
capability and with some intelligence deployed on a FPGA
and a TI 6X DSP [2]. We are currently working on the
following block diagram.
S-LINK interface
Interface
S-LINK
FPGA XILINX TEXAS INSTRUMENTS
FIFO
Data reordening
BCID checking
BCID
BCID
EMIF
Look up table
McBSP1 McBSP0
BCID L1 ID
PCI interface
Figure 8: PMC block diagram.
CPU
PCI
interface
For the DSP we are currently designing for the
TMS320C6205 which includes a PCI interface that save us
the task of implement this interface on a FPGA. For the
FPGA we are designing with XILINX X2CS100 device.
The DSP will load TTC data (BCID, EventID and Trigger
Type) using two serial channels to make the data integrity
operation and output data formatting, while the FPGA will
take care of the SLINK interface, data reordering, BCID
sequence check and the EMIF communication with the DSP.
C. The ROD Controller
Activity in this field is focuses on the adaptation of the
LiArg ROD software libraries to the setup at Valencia based
on a BIT3 VME-PC interface as ROD controller and the
TileCal ROD integration with DAQ-1.
The adaptation of the LiArg libraries is already finished
and has required some effort on the driver side. For the DAQ-
1 integration the work foreseen is the development of the
Local ROD VME software, the online software and ROS
dataflow. We expect to start this work very soon.
VI. REFERENCES
[1] ATLAS Trigger and DAQ steering group, “Trigger and Daq Interfaces
with FE systems: Requirement document. Version 2.0”, DAQ-NO-103,
1998.
[2] TEXAS INSTRUMENTS, “TMS320C6205 Data sheet,” Application
Report SPRS106, October 1999
[3] K. Castille, "TMS320C6000 EMIF to external FIFO interface,"
[4]
Application Report SPRA543, May 1999
J. Dowell, M. Pearce “ATLAS front-end read-out link requirements,”
ATLAS internal note, ATLAS-ELEC---1, July 1998
[5] C. Bee, O. Boyle, D. Francis, L. Mapelli, R. MacLaren, G. Mornacchi,
J. Petersen, “The event formatr in the ATLAS DAQ/EF prototype-1,”
Note number 050, version 1.5, October 1998
[6] O. Boyle, R. McLaren, E. van der Bij, “The S-LINK interface
specification,” ECP division CERN, March 1997
[7] The LArgon ROD working group, “The ROD Demonstrator Board for
the LArgon Calorimeter”
[8] S. Böttcher, J. Parsons, S. Simion, W. Sippach “The DSP 6202
processor board for ATLAS calorimeter”

Abstract
After reviewing the architecture and design of the CMS
data acquisition system, the requirements on the front-end data
links as well as the different possible topologies for merging
data from the front-ends are presented. The DAQ link is a standard
element for all CMS sub-detectors: its physical specification
as well as the data format and transmission protocol are
elaborated within the Readout Unit Working Group where all
sub-detectors are represented. The current state of the link definition
is described here. Finally, prototyping activities
towards the final link as well as test/readout devices for Front-
End designers and DAQ developers are described.
I. INTRODUCTION
In the case of CMS, there will be about 9 different detectors
providing ~1 MB of data per trigger to the DAQ (see Fig.
1). Interfacing these sources with the DAQ is a critical point
given the overall size and complexity of the final system (ondetector
electronics, counting room electronics and DAQ).
Trig.
Throttle
aTTS sTTS
LV1A
(binary)
Back Pressure
Back Pressure
Back Pressure
EVM
Requests
Trig. Data
Commands
Front-End
Readout
Column
Switch
Filter Column
Fig. 1 CMS DAQ block diagram
The Front-End (FE) operation is synchronous with the
machine clock and is located in the underground areas (detector
cavern and counting rooms). The distribution of fast signals
(LV1A, machine clock, resets, fast commands) is carried out
by the Timing, Trigger Control system (TTC) [1]. The TTC
provides to the FE the signals needed to signal the presence of
data on every bunch crossing and send the trigger selected data
to the Readout Column (RC). In turns, the FE can throttle back
the trigger by providing fast binary status signals to the synchronous
Trigger Trottling System (sTTS) [2].
The FE modules are read out by the RC (see Fig. 2) which
is running asynchronously w.r.t. the machine clock, the RC
being “trigger driven”. For every event, the FE pushes its data
as soon as possible through the data transportation devices
towards the RC located at the surface. The event data are then
Front-End / DAQ Interfaces in CMS
G. Antchev, E. Cano, S. Cittolin, S. Erhan, W. Funk, D. Gigi, F. Glege, P. Gras, J. Gutleber, C. Jacobs, F.
Meijers, E. Meschi, L. Orsini, L. Pollet, A. Racz, D. Samyn, W. Schleifer, P. Sphicas, C. Schwick
CERN, Div. EP, Meyrin CH-1211 Geneva 23 Switzerland
DAQ link
Computing
40 Tbytes/sec
40 MHz
512 Readout columns
100 Gbyte/sec
100 kHz
512x512 legs
> 50Gbit/sec
5.10 6 MIPS
100 Mbyte/sec
~100 Hz
buffered in the Readout Unit Input (RUI). The RC receives its
control messages through the Event Manager (EVM). The
EVM is sub-divided into a Readout Manager (RM) and a
Builder Manager (BM). The RM enables the data integrity
check in the RUI and the writing of the event fragment into the
Readout Unit Memory (RUM). The BM enables the Readout
Unit Output (RUO) to send an event fragment to a requesting
Builder Unit (BU) sitting on the other side of the switch network.
As for the FE, the DAQ can also throttle the trigger by
means of messages provided to the asynchronous TTS (aTTS)
through a control network.
RC
FED
RU
DDU/
FED/
DCC
RUI
RUI bus
RUM
RUO bus
RUO
Detector data link
RUS
Switch data link
200m
DDU/
FED/
DCC
RUI
Fig. 2 CMS Readout column block diagram
II. FRONT-END DATA SOURCES
As mentionned in the introduction, 9 sub-detectors will
provide a total of 1 MB of data for every trigger. The central
DAQ is designed to acquire this 1 MB of data at a maximum
trigger rate of 100 kHz.
According to the most up-to-date information, the data are provided
as follows:
• Pixel: 32 sources @ [850..2100] bytes
• Tracker: 442 sources @ [300..1500] bytes
• Preshower: 50 sources @ 2 kByte
• ECAL: 56 sources @ 2 kByte ± 10-20%
• HCAL: 24 sources @ 2 kByte
• Muon-DT: 60 sources @ ~170 bytes

• Muon-RPC: 5 sources @ ~300 bytes
• Muon-CSC: 36 sources @ ~120 bytes
• Trigger: 4 sources @ 1kByte
This makes a total of 709 sources with individual data sizes
ranging from 120 bytes to ~ 2kByte. In order to use efficiently
the nominal bandwidth of the DAQ hardware, a minimum
packet size must be achieved by the front-end data sources
(see Fig. 3). Given the current situation, the Pixel detector, the
Tracker detector and the Muon detectors may need an additional
concentration layer to match this requirement.
Fig. 3 Effective data throughput versus packet size
III. READOUT INTERFACE
The DAQ is the natural convergence point of the data produced
by the sub-detectors. Reducing the diversity in the electronic
devices is highly desirable if not outright necessary, in
order to facilitate the system integration (especially during the
initial debug phase) and also the maintenance operations.
Therefore, the decision to use a common interface for all subdetectors
was made at a very early stage of the DAQ design.
The interface is defined and elaborated within the Readout
Unit Working Group (RUWG) [3] where all data providers and
data consumers are represented. A common functional specification
document [4] is adopted by all CMS data producers.
A. Detector Dependent Unit
The Detector Dependent Unit (also known as Front End
Driver) is hosting the interface between the DAQ and the subdetector
readout systems. No sub-detector specific hardware is
foreseen after the DDU in the readout chain. If the event size at
the FED/DDU level is far from 2 KBytes, an intermediate Data
Concentrator Card (DCC) merges several FEDs/DDUs in
order to reach the 2 KB per event. This element is not needed
for all sub-detectors. When a DCC is present in the sub-detector
data flow, the DCC is seen by the DAQ as the interface
between the DAQ and the sub-detector.
The task of the DDU is to deal with the specificities of
each sub-detector and make available the data to the DAQ
transportation hardware according to the specifications [4].
The specifications include the minimum functionalities to be
performed by the DDU (header generation, alignment checking…)
and the description of the DAQ slot which is located on
the DDU where the DAQ transportation hardware is plugged.
B. DAQ slot
The DAQ slot is an S-LINK64 port [5]. S-LINK64 is based
on S-LINK1 [6] which has been extended to match CMS needs
(64 bits @ 100 MHz). The extension is implemented through
an additional connector, hence allowing the usage of standard
S-LINK product until the availability of the final DAQ hardware.
FED/DCC
Specific
Detector
Electronic
Detector links
S-LINK64 port
Storage
area
Link
FPGA
VME Host
Interface
Fig. 4 DAQ slot on the FED/DCC
S-LINK as well as S-LINK64 specifies a set of 2 connectors
(a sending and a receiving one) but not the physical link in
between. The design and the implementation of the S-LINK64
port on the FED is under the responsibility of the sub-detector.
IV. DAQ DATA TRANPORTATION
A. Data transportation requirements
Setup
Control
Messages
- out-of-sync
- failure
Monitoring
Fast signals:
- busy/ready
- overflow warning
The required data throughput is 200 MB/s (2 KB @ 100
KHz) over a distance of 200m (cable path between the underground
areas and the surface DAQ building). The data transportation
hardware must be able to absorb stochastic
fluctuations on the event size and provide enough contingency
to cope with large uncertainties on the LHC luminosity and the
detector occupancy/noise. However, the available bandwidth
will clearly have an upper limit that cannot be exceeded. It is
assumed that data sources in need of higher bandwidth will
have some of their channels readin by an additional FED.
In order to have a good working efficiency, the event
builder must receive a balanced traffic through its input ports
and destination clashes must be avoided as much as possible.
As shown in section II. on page 1, some detectors feature an
important data size spread at the output of their data sources
Therefore, the data transportation hardware must be able to
average the traffic over several FEDs by appropriatly grouping
FEDs with low and high data volumes per event.
Regarding the staging policy, at day 0, the trigger rate and
the event size will be far from the nominal one: the full capacity
of the DAQ will be needed only after LHC luminosity
ramping-up and nominal CMS detector efficiency. A capacity
of 25% of the nominal one is planned to be available on day 0,
doubling after 6 months of data-taking to reach 100% after one
year of operation. This staging strategy is also requested to
match the expected funding profile. Therefore, the data trans-
1.Generic FIFO interface featuring 32 bits @ 40 MHz specified at CERN by
R. McLaren and E. Van Der Bij

portation architecture must allow a progressive deployment of
the DAQ.
B. Data transportation architecture
The data transportation architecture (see Fig. 5) is strongly
driven by the event builder features and the staging strategy as
well.
The constituting elements of the data transportation are:
• DAQ short reach link: transfers the FED data to the Front-
End Readout Link card (FRL)
• Front-End Readout Link card: receives the FED data via
the short link and houses the long reach DAQ link
• DAQ pit-PC: hosts the FRL and performs its configuration/control
• DAQ long reach link: moves the data from the FED/DCC
into the intermediate data concentrator located at the surface
(200m cable path).
• Intermediate data concentrator (FED Builder): implemented
with an N x N crossbar switch. Each of the inputs
is connected to a data source and depending on the
deployment phase, up to N Readout Unit Inputs (RUI) are
connected to the switch outputs. At LHC startup, only one
RUI is connected and process the event fragments of N
sources. Hence, by connecting hot and cold data sources,
traffic balancing is performed de facto by the FEDB
Whatever the deployment scenario is, the data transportation
from pit to FEDB is never modified. Later, when
higher bandwidths will need to be deployed, this will be
achieved by connecting more RUIs in the system.
PCI card hosted by pit-PC
Underground area
Surface area
FED/DCC FED/DCC FED/DCC FED/DCC FED/DCC
FED/DCC
FED/DCC
Short link
FRL FRL FRL FRL FRL
FRL
FRL
Long
link
FE Builder
Fig. 5 Data transportation architecture
The technologies used to build the central DAQ system are
clearly those used in the telecommunication world. Hence,
both the performance and the cost of the system profit from the
evolution of this dynamic market. By adopting popular telecom/computer
standards (i.e. PCI or Infiniband), custom
developments can co-exist with commercial products. Custom
developments are at the time of this paper, the only way to
achieve the required performances (200 MB/s sustained
throughput through all the RC). As the performance of commercial
products approach the requirements, these ones will be
considered at procurement time or as replacement for the custom
implementation. Therefore, the use of popular standards
in custom design is a necessity given the most likely evolution
and the upgrades.
RU
V. PROTOTYPES
The prototyping phase will extend until Q4 2002 (DAQ
Technical Design Report submission). At this time, implementation
choices will be frozen and the pre-series production/procurement
phase will start.
A. Short reach link prototype
The current prototype is based on LVDS technology:
• S-LINK64 compliant
• max. cable length: 10m
• max. throughtput: 869 MB/s
• BER < 10 -15
The sender card plugs into a FED and the receiver card is
hosted by a multi-purpose PCI card (called Generic III or
GIII). This forms the Hardware Readout Kit (HRK) provided
to FED developers for laboratory work and beam test activities.
SDRAM SDRAM
SDRAM SDRAM
UB
APEX
-x 3.3v
-xv 5v
FLASH
LVDS
B. FRL prototype
R
PCI

32 MB
SDRAM
Altera
APEX
PCI
64bits
66 MHz
1 MB
FLASH
Fig. 8 Generic III block diagram
Fig. 9 Generic III picture
C. Long reach link prototype
As one end of this link is connected to the FED builder, its
technology will be identical to the switch technology. Currently,
Myrinet [10] is considered as the baseline technology
for the FED Builder. The possible options for implementing
such a link are the following:
• Off-the-shelf PMC hosted by the FRL card
• Myrinet protocol/core implemented in FPGA
• FRL with embedded Myrinet processor (Lanai-10)
These options are currently evaluated and discussed with
Myricom.
The final decision will be taken for DAQ TDR submission
(Q4 2002). Meanwhile, prototyping activities continue.
A. FRL housing
FPGA Bus
VI. INFRASTRUCTURES
High-speed
connectors
S-Link64
port
As presented above, there is one FRL per data source and
the FRL is a PCI card. Therefore, PCI slots must be available
in the underground counting rooms. Using PCs for hosting the
FRLs would require much more space than PCI cages. Such
cages have 13 PCI slots and an interface with the control PC.
Rack-mounted PCs with 7 free PCI slots (4U) allow to control
91 data sources within a standard 42U computer rack. A total
of height racks is needed for the entire set of front-end data
sources.
Fig. 10 A PCI cage with 13 slots
VII. CONCLUSION
An important fraction of the DAQ system (~90%) will be
based on standard commercial components from the telecom
and computing industries. The breathtaking improvments in
speed, capacity and cost of these industries is well established
and also expected to continue. Clearly, the benefits from
delaying design choices have to be balanced against the constraints
of providing readout capability to the Front End electronics
which are already in production now.
The plan described in this paper addresses both of these constraints,
by both providing hardware prototypes to the current
developers and also delaying final technology choices
upstream in the DAQ system.
VIII. REFERENCES
[1] http://ttc.web.cern.ch/TTC/intro.html
[2] http://cmsdoc.cern.ch/cms/TRIDAS/horizontal/docs/
tts.pdf
[3] http://cmsdoc.cern.ch/cms/TRIDAS/horizontal/
[4] DDU design specifications A. Racz
CMS note 1999-010
[5] The S-LINK 64 bit extension specification: S-LINK64 A.
Racz, R. McLaren, E. van der Bij
[6] The S-LINK Interface Specification
O. Boyle, R McLaren, E. van der Bij
[7] http://cmsdoc.cern.ch/~dgigi/uni_board.htm
[8] http://cmsdoc.cern.ch/cms/TRIDAS/horizontal/DDU/content.html
[9] Generic hardware for DAQ applications
G. Antchev et al.
LEB 1999 Proceedings
[10]http://www.myri.com

The Embedded Local Monitor Board (ELMB)
in the LHC Front-end I/O Control System
B. Hallgren 1 , H.Boterenbrood 2 , H.J. Burckhart 1 , H.Kvedalen 1
1 CERN, 1211 Geneva 23, Switzerland, 2 NIKHEF, NL-1009 DB Amsterdam, The Netherlands
bjorn.hallgren@cern.ch, boterenbrood@nikhef.nl, helfried.burckhart@cern.ch, hallvard.kvedalen@cern.ch
Abstract
The Embedded Local Monitor Board is a plug-on board to
be used in LHC detectors for a range of different front-end
control and monitoring tasks. It is based on the CAN serial
bus system and is radiation tolerant and can be used in
magnetic fields. The main features of the ELMB are described
and results of several radiation tests are presented.
I. INTRODUCTION
A versatile general-purpose low-cost system for the frontend
control, the Local Monitor Box (LMB) was designed in
1998 and tested by ATLAS sub-detector groups in test-beam
and other applications [1]. Based on this experience and to
match all the needs of the ATLAS sub-detector groups a
modified version, the Embedded Local Monitor Board
(ELMB) was designed. The main difference as compared to
the LMB is the plug-on feature and the small size (50x67
mm). It can either be directly put onto the sub-detector frontend
electronics, or onto a general-purpose motherboard which
adapts the I/O signals. In order to make the ELMB available
for evaluation a small-scale production of 300 boards has
been made.
A. Environmental Requirements
The ELMB is intended to be installed in the underground
cavern of LHC detectors. As an example of such radiation
environments the simulated radiation levels [2] for 10 years of
operation of the ATLAS Muon MDT detectors are given
below:
• Total Ionising Dose (TID): 6.4 Gy,
• Non-Ionising Energy Loss (NIEL): 3*10 11 neutrons/cm 2
(equivalent to 1 MeV Si)
• Single Event Effect (SEE): 4.8*10 10 hadrons/cm 2
(>20 MeV)
The magnetic field in which the Muon detectors operate is
1.5 Tesla, which makes it difficult to use DC to DC converters
and other ferromagnetic components including transformers
that are often used in commercial, off-the-shelf systems.
These components have been avoided in the design of the
ELMB. Another requirement is remote operation up to a
distance of 200 m.
II. DESCRIPTION OF THE ELMB
The ELMB has an on-board CAN-interface and is insystem
programmable, either via an on-board connector or via
CAN. There are 18 general purpose I/O lines, 8 digital inputs
and 8 digital outputs. Optionally a 16-bit ADC and
multiplexing for 64 analogue inputs is provided on-board as
shown in Figure 1.
….
….
….
Analog Power
5.5 to 12V,10mA
ANALOG GND
Voltage
Regulators ±5V
64 ch
MUX
ADC
CS5523
OPTO
OPTO
Digital Power
3.5 V - 12V, 15 mA
Voltage
Regulator
ATmega103L
MASTER
CAN bus
cable
Digital I/O
Figure 1: Simplified block diagram of the ELMB module
A. Power distribution
4
AT90S2313
SLAVE
3.3V
DIGITAL GND
DIP
switches
SAE81C91
CAN
controller
Port A Port C Port F (other)
8 8 8 10
As seen from Figure 1 the ELMB is divided into three
sections: analog, digital and CAN. They are separated with
optocouplers to prevent current loops. The three parts are each
equipped with a Low Dropout (LDO) 80 mA voltage
regulator from Micrel (MIC5203). These regulators provide
current and thermal limitations, which is a useful feature for
protection against Single Event Latch-up (SEL). The analog
circuits need ±5V, which is generated by a separate CMOS
switched-capacitor circuit. The total analog current
consumption is 10 mA. The power supply of the digital
section is 3.3V, 15mA. The CAN part of the ELMB may be
powered via the CAN cable and needs 20mA at 5.5V.
B. The Analog Circuits -ADC
OPTO
OPTO
CAN
Power
5.5 to12V,
20mA
CAN GND
Voltage
Regulator
5V
CAN
Transceiver
A 16 bit differential delta-sigma ADC with 7 bit gain
control (Crystal CS5523) is used and placed on the back-side
of the printed circuit board. The CS5523 is a highly
integrated CMOS circuit, which contains an instrumentation

chopper stabilised amplifier, a digital filter, and calibration
circuits. 16 CMOS analog differential multiplexers expand the
number of inputs to 64. The AD680JR from ANALOG
DEVICES supplies a stable voltage reference. The ADC input
can handle a range between +4.5 and –4.5V. Figure 2 shows
the backside of the printed circuit board with the ADC, the
voltage reference and 16 multiplexer circuits.
50 mm
Figure 2: The backside of the ELMB printed circuit board
C. The Digital Circuits
67 mm
The local intelligence of the ELMB is provided by 2
microcontrollers of the AVR family of 8-bit processors,
manufactured by ATMEL. This family of microcontrollers is
based on a RISC processor developed by Nordic VLSI and is
particularly efficient in power consumption and instruction
speed. The ELMB’s main processor is the ATmega103L
running at 4 MHz. This CMOS integrated circuit contains onchip
128 Kbytes of flash memory, 4 Kbytes of SRAM, 4
Kbytes of EEPROM and a range of peripherals including
timers/counters and general-purpose I/O pins. The main
monitoring and control applications are running on this
processor.
The second on-board microcontroller is a much smaller
member of the same AVR family, the AT90S2313 with 2
Kbytes flash-memory, 128 bytes of SRAM and 128 bytes of
EEPROM. The main purpose of this processor is to provide
In-System-Programming (ISP) via CAN for the ATmega103L
processor. In addition it monitors the operation of the
ATmega103L and takes control of the ELMB if necessary.
This feature is one of the protections against SEE. In turn the
ATmega103L monitors the operation of the AT90S2313 and
provides ISP for it. Figure 3 shows the front-side of the
ELMB printed circuit board with the two microcontrollers and
the CAN circuit.
Figure 3: The front side of the ELMB
D. CAN circuits
CAN is one of the three CERN recommended fieldbuses
[3]. It is especially suited for sensor readout and control
functions in the implementation of a distributed control
system because of reliability, availability of inexpensive
controller chips from different suppliers, ease of use and wide
acceptance by industry. The error checking mechanism of
CAN is of particular interest in the LHC environment where
bit errors due to SEE will occur. The CAN controller registers
a node's error and evaluates it statistically in order to take
appropriate measures. These may extend to disconnecting the
CAN node producing too many errors. Unlike other bus
systems, the CAN protocol does not use acknowledgement
messages but instead signals any error that occurs.
For error detection the CAN protocol implements three
mechanisms at the message level:
• Cyclic Redundancy Check (CRC)
• Message frame check
• Acknowledgement errors
The CAN protocol also implements two mechanisms for
error detection at the bit level:
• Monitoring
• Bit stuffing
If one or more errors are discovered by at least one station
using the above mechanisms, the current transmission is
aborted by sending an error message. This prevents other
stations accepting the faulty message and thus ensures the
consistency of data throughout the network. When the
transmission of an erroneous message has been aborted, the

sender automatically re-attempts transmission (automatic
repeat request).
The on-board CAN-controller is the Infineon SAE81C91,
a so-called ‘Full-CAN controller’ with buffers for 16
messages. It is connected to the CAN bus via high-speed
optocouplers to an interface circuit (Philips PCA82C250)
which translates the logic levels to CAN levels. This bipolar
integrated circuit has an operating temperature range of -40
to 125 °C and contains several protection features. The
microcontrollers communicate with the CAN-controller via a
serial interface.
E. Software
CANopen [4] has been chosen as the higher layer
protocol. CANopen standardises the way data is structured
and is communicated. Of particular relevance for LHC
applications is the network management. A master watches all
the nodes to see if they are operating within their
specifications. The most recent version of CANopen
recommends using heartbeat messages for the supervision of
the nodes. A general purpose CANopen embedded software
program (ELMBio) for the ELMB Master processor has been
developed [5]. 64 analog input channels, up to 16 digital
inputs (PORTF and PORTA) and up to 16 digital outputs
(PORTC and PORTA) are supported. The ELMBio conforms
to the CANopen DS-401 Device Profile for I/O-modules and
provides sufficient flexibility to make it suitable for a wide
range of applications.
The ELMBio source code is available as a framework for
further developments and additions by users, who want to add
or extend functionality, e.g. support for specific devices [6].
Backside
Front
Back
Figure 4: The ELMB motherboard
III. ELMB MOTHERBOARD
A motherboard is available in order to evaluate the ELMB
and for non-embedded applications, see Figure 4. It contains
two 100-pin SMD connectors for the ELMB and sockets for
adapters for the 64 channel ADC. The purpose of the
adapters is to convert the input signals to levels suitable for
the ADC. Adapters are available for voltage measurements
and for resistive sensors in 2- and 4-wire connections. The
motherboard may be mounted in DIN rail housing of the size
80x190 mm 2 . On the front side are connectors for the ADC
inputs, digital ports, a SPI interface, the CAN interface and
power connectors.
IV. RADIATION TESTS
Several radiation tests for TID, SEE effects and NIEL
have been performed.
A. TID tests
Three pre-selection TID tests have been made on 4
different ELMBs. Three of the ELMBs were of the first
prototype series powered with 5V, while the 4th was from the
3.3V series.
1) The Pagure test
Two ELMBs were exposed to a Co 60 γ-source [1 MeV] at
the PAGURE facility [8]. They worked without problems
until 30 Gy. At this point the power supply current started to
increase by up to a factor of 10. Except for this increase, the
ELMBs were basically working up to about 80 Gy when the
measurements were stopped. The cause for the increase in the
current was found to be the three CMOS components
ATmega103L, AT90S2313 and the SAE81C91. The dose
rate at this test was 77 Gy/h, which is 10 5 times higher than
the ELMB is expected to receive at LHC. It was therefore
decided to repeat tests at lower rates at CERN.
2) The first GIF test
The CERN Gamma Irradiation Facility (GIF) has a Cs 137
γ-source [0.6 MeV]. The dose rate can be chosen in a wide
range from 0.5 Gy/h down to 0.02 Gy/h. A test was done
with one ELMB (given the identifier ELMB3) with a dose
rate of 0.48 Gy/h [9]. The result was similar to the PAGURE
test with the current increase starting at about 35 Gy. The test
was stopped at 43 Gy when the current had increased by 20%.
Both microcontrollers were still functional. However the insystem
programming function of the master failed. The slave
processor was found to be working without any faults.
3) Accelerated ageing test
After the radiation test the ELMB3 was tested for 12 days
in a climate chamber [9]. At the same time a non-irradiated
ELMB (ELMB4) was also tested for comparison. The total
number of equivalent device hours reached was about 40000 h
at 25 °C. Figure 5 shows how the current varied during the
test. The current of the irradiated ELMB increased after each

temperature increase but then decreased exponentially. The
current of the non-irradiated ELMB did not show this
behaviour. Both ELMBs were still operating at 85 °C, but
stopped working at a temperature of 100 °C, which is outside
the specifications of the components. After the test the current
of both ELMBs returned to the original value. The master
processor had fully recovered and could be reprogrammed.
Figure 5: Current variations during the temperature test
4) GIF test 2
In order to test when the reprogramming function of the
ELMB microcontrollers cease to work, an additional test of a
3.3V ELMB (ELMB5) was performed [10]. The irradiation
was done in periods of approximately 10 hours and thereafter
14 hours break. After each step the reprogramming function
was checked. This function failed after 35 Gy. At this
moment a small current decrease could be observed. From
then on the ELMB received a continuous dose and the current
increased. Figure 6 shows how the digital currents changed
for all the TID tests.
Figure 6: Comparison of the digital current for all TID tests
5) Conclusions from the TID test of the ELMBs
It was observed that the re-programming function of the
flash memory and EEPROM in the master microcontroller
ceases to work at a total received dose of around 35 Gy. Also
the digital current increases substantially for a total dose of
about 40 Gy. However this did not influence the operation of
the ELMB up to about 80 Gy
B. SEE tests
The ELMB was irradiated with 60 MeV protons at the
CYClotron of LOuvain-la-NEuve (CYCLONE) of the
Université Catholique de Louvain, in Belgium [11]. The main
purpose was to study SEE effects on the ELMB but also some
TID measurements were made. A total fluence of 3.28*10 11
protons/cm 2 was divided among 11 ELMBs. Each ELMB
received an ionising dose of 39 Gy. Two types of tests were
performed: a systematic test of memories and register and a
functional test. They are described in detail in [11].
1) Result of the systematic memory and register tests
Special software was run in the ELMB, which in addition
to the normal program also performed systematic bit tests of
the different memories and registers in the ELMB. Figure 7
shows the addresses of the ATmega103L SRAM where the bit
errors were located versus fluence. (The total fluence reached
was 3.28*10 11 protons/cm 2) .
Figure 7: Addresses of the SRAM where SEE occurred versus
fluence
A summary of the memory and register errors is shown in
Table 1. No error was found in the flash memory or in the
EEPROM. Many errors were found in the SRAM as expected.
The SRAM is twice as sensitive as the registers in the CAN
controller SAE81C91 and ADC CS5523.
Table 1: Results of the systematic SEU test
No of bits
Tested
No of
errors
Cross-section
cm 2 /bit
SRAM 16384 2320 4.3*10 -13
EEPROM 28672

2) The result of the functional SEE test
There will be in the order of 3000 ELMBs installed in
ATLAS. For topological and operational reasons at most 64
ELMBs will form a CAN branch. As shown in this paper,
errors due to radiation will occur. Table 2 lists the different
types of errors with their symptoms, the method to recover
from them and their maximally allowed rate.
Table 2: Maximum allowed SEE rates in DCS system
SEE category / Error
Symptoms recovery
Soft SEE / Automatic
Data readout errors recovery
Soft SEE / Software
CAN node hangs reset
Soft SEE / Power
CAN branch hangs cycling
Hard SEE / Replace
Permanent error ELMB
Destructive SEE/ Power
Damage
limitation
Maximum allowed rate
1 every 10 minutes per
CAN branch
1 every 24 hours per
CAN node
1 every 24 hours per
CAN branch
1 every 2 months for
3000 ELMBs
Not allowed
In total there were 29 abnormal situations detected in
131157 CAN messages recorded for 3.28*10 11 protons/cm 2 ,
These events are divided in categories according to how the
normal behaviour was restored, see Table 3.
Table 3: Results of the SEE test compared with requirements
SEE category/
Recovery
Result of
the SEE test
Requirements
Soft SEE /
Automatic recovery
20 2604
Soft SEE /
Software reset
5 1157
Soft SEE /
Power cycling
4 18
Hard SEE 0 0.006
Of the SEEs, which required power cycling, one was due to
an increase in the digital current and therefore believed to be a
SEL. All other SEEs are soft SEE. No hard or destructive
SEEs were found. All ELMBs were working perfectly after
the test.
4) TID effects
The dose amounted to 39 Gy for 10 of the ELMBs and to
44.5 Gy for one of the ELMBs. The TID is estimated using a
conversion factor 1.0*10 10 protons/cm 2 corresponding to an
ionising dose of 13 Gy for 60 MeV protons. The average
fluence per ELMB was 3.0*10 10 protons/cm 2 . The power
supply currents were measured on-line. The change measured
was negligible (< 0.3%). All voltages of the LDO regulators
and the ADC voltage reference were also found to be
unchanged. Finally all ELMBs were checked to see if the
reprogramming function of the microcontrollers was still
working. They all proved to work perfectly.
C. NIEL
Tests on 10 ELMBs at the PROSPERO reactor with 1
MeV neutrons were done to test the bipolar components of the
ELMB. 5 of the ELMBs were irradiated to 6*10 11 n/cm 2
(equiv. 1 MeV Si) while the other 5 to 3*10 12 n/cm 2 (equiv. 1
MeV Si). All 10 were found to be perfectly working after the
test. Measurements on the bipolar LDO voltage regulators and
the voltage references AD680JR showed that they were all
within specifications.
V. CONCLUSIONS
The ELMB has proven to be a versatile general-purpose
I/O device, very well matched to the needs of the LHC
experiments. All ATLAS subdetectors have decided to use it
on a large scale - the biggest system comprising 1200
ELMBs. CAN is an excellent choice for the read-out due to its
robustness and error handling facilities. It has also been
shown that by using COTS a certain level of radiation
tolerance can be achieved. For example the requirements for
the ATLAS Muon detector MDT are fulfilled concerning SEE
and NIEL. The required TID figures including a safety factor
of 7 varies from 9.3 Gy to 44.7 Gy for the different MDT
chambers. For more than 97% of them the requirements are
fully satisfied. More investigations and possibly some special
measures may be required to use the ELMB for the rest of the
chambers.
VI. ACKNOWLEDGEMENTS
We would like to thank M.Dentan for helping us with the
definition and execution of the radiation tests. We are grateful
to the EP-ESS group for collaborating in the production of the
ELMB and to the EP division for the support as a Common
Project.
VII. REFERENCES
[1] B. Hallgren et al, “A Low-Cost I/O Concentrator using the
CAN fieldbus”, ICALEPS99conference, Trieste, Italy, 4 –
8 October, 1999
[2]_http://atlas.web.cern.ch/Atlas/GROUPS/FRONTEND/W
WW/RAD/RadWebPage/RadConstraint/Radiation_Tables
_031000.pdf
[3] G.Baribaud et al, "RECOMMENDATIONS FOR THE
USE OF FIELDBUSES AT CERN", CERN ECP 96-11,
June 1996. http://itcowww.cern.ch/fieldbus/report1.html.

[4] CAN in Automation (CiA), D-91058 Erlangen
(Germany). http://www.can-cia.de/
[5] H.Boterenbrood, “Software for the ELMB (Embedded
Local Monitor Board) CANopen module”, NIKHEF,
Amsterdam, 25 July 2001.
[6] http://www.nikhef.nl/pub/departments/ct/po/html/
ELMB/ELMBresources.html
[7] CAN in Automation (CiA), “CANopen Device Profile for
Generic I/O Modules”, CiA DS-401, Version 2.0, 20
December 1999.
[8] H.Burckhart, B. Hallgren and H. Kvedalen, ' Irradiation
Measurements of the ATLAS ELMB', CERN ATLAS
Internal Working Note, DCS- IWN9, 8 March, 2001
[9] J. Cook, B. Hallgren and H. Kvedalen, ' Radiation test at
GIF and accelerated ageing of the ELMB ', CERN
ATLAS Internal Working Note, DCS- IWN10, 2 May,
2001
[10] B. Hallgren and H. Kvedalen, ' Radiation test of the 3.3V
version ELMB at GIF ', CERN ATLAS Internal
Working Note, DCS- IWN11, 31 August, 2001
[11] H. Boterenbrood, H.J. Burckhart, B. Hallgren H.
Kvedalen and N. Roussel, 'Single Event Effect Test of
the Embedded Local Monitor Board',CERN ATLAS
Internal Working Note, DCS- IWN12, 20 September,
2001

Design of a Data Concentrator Card for the CMS Electromagnetic Calorimeter Readout
Abstract
J. C. Silva (1) ,N. Almeida (1) , V. Antonio (2) , A. Correia (2) , P. Machado (2) , I. Teixeira (2) , J. Varela (1) (3) ,
The Data Concentrator Card (DCC) is a module that in the
CMS Electromagnetic Calorimeter Readout System is
responsible for data collection in a readout crate, verification
of data integrity and data transfer to the central DAQ. The
DCC should sustain an average data flow of 200 Mbyte/s. In
the first part of the paper we summarize the physics
requirements for the ECAL readout and give results on the
expected data volumes obtained with the CMS detector
simulation (ORCA software package). In the second part we
present the module's design architecture and the adopted
engineering solutions. Finally we give results on the expected
performance derived from a detailed simulation of the
module's hardware.
1. INTRODUCTION
The CMS Electromagnetic Calorimeter comprises
approximately 77.000 crystals, organized in supermodules, in
the barrel, and D-shaped modules in the endcaps (Figure 1).
After amplification, the crystals signals are digitized (on the
detector) and then transmitted to the counting room by highspeed
optical links (800 Mbit/s). The upper level readout and
trigger boards (ROSE boards) are designed to receive 100
optical links corresponding to the same number of crystals.
Within each ROSE, data is stored in pipeline memories
waiting for the first-level trigger decision (L1A), and in
parallel it is used to compute trigger primitives that are sent to
the regional calorimeter trigger system. Seventeen ROSE
boards, filling a single VME-9U crate, handle the 1700
crystals in a barrel supermodule. Endcap crates are equipped
with 14 readout boards. In each crate, the DCC is the common
collection point of data from the ROSE boards, performing
local event building and data transmission to the DAQ
system.
If every crystal (ten data samples each) were read-out,
something like 2.4 Mbytes would need to be handled for each
triggered event. Due to several constraints this data volume is
unacceptable. By agreement, the ECAL fraction of the DAQ
bandwidth is constrained to be approximately 10% of the
CMS total, bringing the average data rate per DCC to
200 Mbyte/s, for the maximum first-level trigger rate
(100kHz). Techniques for obtaining optimal, efficient use of
the allocated bandwidth, such as zero suppression and
selective readout were studied using data generated with the
CMS physics simulation and reconstruction software (ORCA-
Object Oriented Reconstruction for CMS Analysis) [1].
(1) LIP-Lisbon, (2) INESC, Lisbon, (3) CERN
Figure 1: ECAL Endcap and Barrel geometry.
This paper presents the DCC conceptual design, validated by
a detailed modeling and simulation of the hardware using
ECAL physics data as input. In section 2 we describe ECAL
data generation process, section 3 presents the DCC
conceptual design, section 4 describes the hardware modeling
and finally in section 5 we present the hardware simulation
results.
2. ECAL RAW DATA GENERATION
To motivate the best DCC design, the DCC hardware
simulation was done using as input the expected ECAL data,
for both Endcap and Barrel, as derived from a detailed
detector simulation with ORCA version 4_4_0 optimized.
The simulation was performed for jet events, generated with
transverse energy between 50 and 100 GeV, which are
representative of the CMS triggered events. High luminosity
(L~10 34 /cm 2 /s) running was assumed, corresponding to
approximately 17 pileup events per crossing. The pileup
simulation is particularly important since a large fraction of
the ECAL data volume results from the pileup minimum-bias
events. Various scenarios of zero suppression and tower
selective readout were applied to the data, allowing the
evaluation of the DCC performance under different data rate
conditions.
The target data volume for the ECAL is approximately
2KByte per DCC, which implies a reduction factor of ~20 on
the total ECAL data volume. This data reduction can be
achieved, without hurting the ECAL physics potential,

applying selective readout and zero suppression techniques to
the data. Zero suppression implies the suppression of crystals
with energy lower than a programmable threshold (typically,
the threshold is set between zero and two r.m.s. of the
electronics noise). Zero supression is complemented by a
Selective Readout scheme based on the Trigger Towers
transverse energy sum. The tower transverse energy is
compared to two programmable thresholds, typically set at 1.0
and 2.5 GeV. Crystals in towers with ET above the lower
threshold, as well as crystals in towers surrounding a central
tower with ET larger the higher threshold, are selected for
readout. As shown in figure2 the average data volume per
DCC is reduced from ~3.3KB to ~1.3KB when Selective
Readout is used together with a milder Zero Supression. On
the other hand, the choosen organization of the readout
channels garanttees that the DCC event size is constant in the
whole detector, as it is shown in figure 2.
DATA/DCC_BARREL
NO SR ; ZS(2sigma)
DATA/DCC_BARREL
SR(2.5,1.0) ; ZS(0sigma)
Figure 2: Event size per DCC in the barrel (without and with SR).
Figure 3 shows the total ECAL event size for various
combinations of the Zero Suppression and Selective Readout
thresholds. The target value of 100 kBytes is easily achieved
using very low thresholds and consequently without loosing
significant physics data.
Figure 3: Zero Suppression and Selective Readout Scenarios
3. DCC CONCEPTUAL DESIGN
The DCC is implemented, or partitioned, in two p.c. boards: a
main 9U board (DCC Mother Board) and a 6U transition
board (DCC Input Board). In this way the interconnection at
the crate level is simplified. The DCC Input Board contains
17 input links (point to point links), input memories and
respective handlers. The DCC Mother Board houses the Event
Builder, the output memories and the output links. Two
output links are included, one transporting ECAL data to the
main DAQ, and another transporting only trigger data to the
trigger monitoring system. The DCC can be accessed via the
VME bus, for initialization, board monitoring and data
readout in spy mode.
The Event Builder is the most important and complex part of
the DCC. The main purpose of this block is to assemble the
data fragments arriving from 17 ROSE boards in a single data
packet (DCC event), and to store it in the output memories
ready for transmission. A number of checks and
complementary operations are performed by the Event
Builder. It verifies the integrity of the input data fragments,
checks the event fragments synchronization, monitors the
occupancy of the input and output memories and generate
“empty events” on special error conditions. A complete
description of the Event Builder design is described on [2].
Some technological choices have been made to fit the DCC
performance requirements. All inputs use LVDS Channel
Link that insures quality and reliability while reducing the
interconnection pins. The Input Handlers, Event Builder and
Output Handlers are implemented using re-programmable
logic circuits (ALTERA). The output ports have been defined
to be S-Link-64 compatible, the protocol adopted for
transmission to the central DAQ. The DCC Internal Data Bus,
bridging the input memories to the output link, is being now
designed to have a throughput of 528MB/s.
4. DCC MODELING ...
The modeling of the DCC hardware was done using the
Rational Rose Real Time software.
From the DCC conceptual design three main classes emerge:
the Input Handler, the Event Builder and the Output Handler.
These classes were modeled on so called “capsules” that
reproduce the behavior of the three classes using a real time
simulation. To complete the modeling two more classes are
needed, the clock emulator and L1A trigger emulator and a
Data capsule that uses the ECAL raw data as input. Each of
these classes allows us to model, configure and modify the
main parameters of the DCC design.
The Input Handler capsule, controls the occupancy of each
input memory, allows to modify the segmentation of each
input memory (technically called iFIFO’s) and to set up the
handshake timing.
The Event Builder performs all the data checks, builds the
DCC event from the different selected inputs and updates the
status and error registers.

Figure 4: DCC modeling overview
The Output Handler controls the communication with the
output link and sends each entire event to the DAQ.
The Data capsule reads from a file the input data. The data
used on the modeling and simulation is the physics data
generated by the ORCA software, as referred before.
The Clock capsule controls the clock frequency and the L1A
trigger generation.
5. ...AND SIMULATION RESULTS
In this chapter we will present the first (preliminary) results
from the simulation of the DCC conceptual design.
Two simulated data sets were applied to the Data capsule.
Both data sets were obtained with selective readout high
threshold set to 2.5GeV and low threshold set to 1GeV.
Zero suppression thresholds of 1σ and 0σ were used. The
corresponding ECAL event sizes were 53 Kbytes and
65Kbytes, respectively, per triggered event.
14000
13000
12000
11000
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
Event total time inside system, Event time until enter EB
0
Event nr. 1 Event nr. 10 Event nr. 20 Event nr. 30 Event nr. 41 Event nr. 51 Event nr. 62 Event nr. 72 Event nr. 83
Event Number
Event toal tim
Event time un
Figure 5: An example of input memory overflow. The plot shows
the event time within the system as a function of the event
number.
Various simulations for different options of the DCC Internal
Bus bandwidth, Event Builder processing speed and Output
Link speed were performed. The maximum simulated DCC
bandwidth was 320MB/s. For each condition, the occupancy
of the input and output memories and the event latency inside
the DCC were investigated. Figure 5 shows an example of a
simulation were an overflow of the input memories is
observed (simulated bandwidth was 160 MB/s).
Simulation results showed that, relatively to the 320 MB/s
deled design, either the input memory or the processing speed
needs to be increased. For 65Kbytes per triggered event we
estimated an overflow probablilty of 5.10 -8 (figure 6). This
corresponds to an overflow condition every 3 min which is far
from acceptable (even more if we aim ~100Kbytes per event).
One must notice that no trigger rules have been appiled to the
simulation inputs, and therfore this results are “whorst case”
figures. Further results are expected in the near future for the
aimed bandwidth of 528MB/s.
Number of L1A
10000
1000
100
10
1
0.1
0.01
0.001
0.0001
1E-05
1E-06
1E-07
1E-08
1E-09
Distribution of Nb events in iFIFO
Selective R eadout & Zero Supression 0 Sigm a
1E-10
0 5 10 15 20 25 30
6. CONCLUSIONS
Detailed ORCA simulations showed that a combination of
Selective Readout and Zero Suppression techniques reduces
the CMS-ECAL average data to the target value
(100KB/event) without loosing significant physics data.
A conceptual design of the ECAL data concentrator was
developed aiming a data throughput of 528MB/s.
Simulations of the DCC hardware, using physics data as
input, were used to guide the design. Further simulations are
undergoing to validate the final design choices.
7. REFERENCES
Probability of 32 events in iFIFO = 5E-8
Num ber of Events in iFIFO
Figure 6: iFIFO overflow probability.
[1] Selective Readout in the CMS ECAL, T. Monteiro, Ph. Busson,
W. Lustermann, T. Monteiro, J. C. Silva, C. Tully, J. Varela, in
Proceedings of 'Fifth Workshop on Electronics for LHC
Experiments', Snowmass, Colorado, USA, 1999.
[2] Description of the Data Concentrator Card for the CMS-ECAL,
Jose C. Da Silva, J. Varela, CMS NOTE in preparation.

Vertical Slice of the ATLAS Detector Control System
H.Boterenbrood 1 , H.J. Burckhart 2 , J.Cook 2 , V. Filimonov 3 , B. Hallgren 2 , F.Varela 2a
1 NIKHEF, Amsterdam, The Netherlands, 2 CERN, Geneva, Switzerland, 3 PNPI, St.Petersburg, Russia,
Abstract
The ATLAS Detector Control System consists of two
main components: a distributed supervisor system, running on
PCs, called Back-End system, and the different Front-End
systems. For the former the commercial Supervisory Control
And Data Acquisition system PVSS-II has been selected. As
one solution for the latter, a general purpose I/O concentrator
called Embedded Local Monitor Board has been developed.
This paper describes a full vertical slice of the detector control
system, including the interplay between the Embedded Local
Monitor Board and PVSS-II. Examples of typical control
applications will be given as well.
I. SCOPE OF DCS
The ATLAS Detector Control System (DCS) [1] must
enable a coherent and safe operation of the ATLAS detector.
It has also to provide interaction with the LHC accelerator and
the external services such as cooling, ventilation, electricity
distribution, and safety systems. Although the DCS will
operate independently from the DAQ system, efficient bidirectional
communication between both systems must be
ensured. ATLAS consists of several subdetectors, which are
operationally quite independent. DCS must be able to operate
them in both stand-alone mode and in an integrated fashion as
a homogenous experiment.
DCS is not responsible for safety, neither for personal nor
for equipment. It also does not deal with the data of the
physics events.
II. ARCHITECTURE OF DCS
The ATLAS detector is hierarchically organised, starting
with the subdetectors (e.g. Transition Radiation Tracker, Tile
Calorimeter, etc.), and on the further levels down following
their respective subsystems (e.g. barrel and end-cap parts or
High Voltage, Low Voltage, gas systems, etc.). This
organisation has to be accommodated in the DCS architecture.
The DCS equipment is geographically distributed in three
different areas as shown in figure 1. The main control room is
situated at the surface, in SCX1 and houses the supervisory
stations for the operation of the detector. This equipment is
connected via a LAN to the Local Control Stations (LCS)
placed in the underground electronics room USA15, which is
accessible during running of the experiment. The Front-End
(FE) electronics in UX15 is exposed to radiation and a strong
a also University of Santiago de Compostela, Spain
magnetic field. This equipment is distributed over the whole
volume of the detector with cable distances up to 200 m. The
communication with the equipment in USA15 is done via
fieldbuses.
Figure 1: Architecture of ATLAS DCS
A. Back-End System
The highest level is the overall supervision as performed
from the control room by the operator. Apart from the Human
Interface it includes analysis and archiving of monitor data,
‘automatic’ execution of pre-defined procedures and
corrective actions, and exchange of data with systems outside
of DCS. The middle level consists of LCSs, which operate a
sub-detector or a part of it quite independently. These two
levels form the Back-End (BE) system. The commercial
Supervisory Control And Data Acquisition (SCADA) package
PVSS-II [2] has been chosen, in the framework of the Joint
COntrols Project (JCOP) [3] at CERN, to implement the BE
systems of the 4 LHC experiments. PVSS-II gathers
information from the FE equipment and offers supervisory
control functions such as data processing, execution of control
procedures, alert handling, trending, archiving and web
interface. It has a modular architecture based on functional
units called managers, which perform these individual tasks.
PVSS-II is a device-oriented product where devices are
modelled by structures called data-points. Applications can be
distributed over many stations on the network running on both
Linux and WNT/2000. These features of modelling and
distribution facilitate the mapping of the control system onto
the different subdetectors. Due to the large number of
channels to be handled in ATLAS, the event-driven
architecture of the product was a crucial criterion during the

selection process. PVSS-II also provides a wide set of
standards to interface hardware (OPC, fieldbus drivers) and
software (ODBC, DDE, DLL, API).
B. Front-End System
The responsibility for the FE systems is with the subdetector
groups. In order to minimise development effort and
to ease maintenance load, a general purpose I/O system,
called Embedded Local Monitor Board (ELMB) has been
developed, which is described in detail in another contribution
to this workshop [4]. It comprises ADC and digital I/O
functions, is radiation tolerant for use outside of the
calorimeters of the LHC detectors and can operate in a strong
magnetic field. Further functions such as DAC and interlock
capability can be added. The readout is done via the fieldbus
CAN [5], which is an industry standard with well-supported
commercial hardware down to the chip level. Due to its very
performent error detection and correction and its flexibility,
CAN is particularly suited for distributed I/O as needed by the
LHC detectors. CANopen is used as high-level
communication protocol on the top of the physical and data
link layers defined by CAN. It comprises features such as
network management and supervision, a wide range of
communication objects for different purposes (e.g. real-time
data transfer, configuration) and special functions for network
synchronisation, time stamping, error handling, etc.
C. Connection FE-BE
The interface PVSS-CANopen is based on the industry
standard OPC (OLE for Process Control) [6]. OPC is a
middle-ware based on the Microsoft DCOM (Distributed
Compound Object Model) which comprises a set of interfaces
designed to facilitate the integration of control equipment into
Windows applications. OPC is supported by practically all
SCADA products. This standard implements a multiclient/multi-server
architecture where a server holds the
process data or OPC items in the so-called address space and
a client may read, write or subscribe to them using different
data access mechanisms (synchronous, asynchronous, refresh,
or subscribe). An OPC server may organise the items in
groups on behalf of the client assigning some common
properties (update rate, active, call-back, dead-band, etc.).
Another important aspect of OPC is that it transmits data only
on change, which results in a substantial reduction of the data
traffic.
Several firms offer CANopen OPC servers, but those
investigated are based on their own special hardware interface
and they support only limited subsets of the CANopen
protocol. Although these subsets fulfil most of the industrial
requirements, they do not provide all functionality required in
high energy physics. Therefore we have developed a
CANopen OPC Server supporting the CANopen device
profiles required. This package is organised in a part which
acts like a driver for CANopen and is specific to the PCI-
CAN interface card chosen, and a hardware-independent part
which implements all OPC interfaces and main loops
handling communication with external applications. This
CANopen-OPC server imports from a configuration file all
information needed to define its address space, the bus
topology and the communication parameters.
III. IMPLEMENTATION OF VERTICAL SLICE
A full “vertical slice” of the ATLAS DCS has been
implemented, which ranges from the I/O point (sensor or
actuator) up to the operator interface comprising all elements
described above, like ELMB, CAN, OPC Server and PVSS-II.
The software architecture of the vertical slice is shown in
figure 2.
Figure 2: Software Architecture
The system topology in terms of CANbus, ELMBs and
sensors is modelled in the PVSS-II database using data-points.
These data-points are connected to the items in the CANopen-
OPC server address space. Setting a data-point in PVSS-II
will trigger the OPC server to send the appropriate CANopen
message to the bus. In turn, when an ELMB sends a
CANopen message to the bus, the OPC server will decode it,
set the respective item in its address space and hence transmit
the information to a data-point in PVSS-II. The SCADA
application carries out the predefined calculations to convert
the raw data to physical units, possibly trigger control
procedures, and trend and archive the data. The vertical slice
also comprises PVSS-II panels to manage the configuration,
settings and status of the bus.
This vertical slice has been the basis for several control
applications of ATLAS subdetectors like the alignment
systems of the Muon Spectrometer, the cooling system of the
Pixel subdetector, the temperature monitoring system of the
Liquid Argon subdetector and the calibration of the Tile
Calorimeter at a test beam. As an example the latter will be
discussed in the next paragraph.
A subset of the Tile Calorimeter modules needs to be
calibrated with particles in a test beam. The task of DCS is to
monitor and control the three different subsystems, the high
voltage, the low voltage and the cooling system. A total of
seven ELMBs were connected to the CAN bus. For the low
voltage system, the standard functionality of the vertical slice

was easily extended in order to drive analogue output
channels by means of off-board DAC chips. This application
also interfaced to the CERN SPS accelerator in order to
retrieve the beam information for the H8 beam line. Data
coming from all subsystems were archived in the PVSS-II
historical database and then passed to the Data Acquisition
system for event data by means of the DCS-DAQ
Communication software (DDC) [7].
Figure 3 shows the PVSS graphical user interface of this
application. The states of the devices integrating the DCS are
colour-coded and the current readings of the operational
parameters are also shown in the panel. Dedicated panels for
each subsystem and graphical interfaces to the historical
database and for alert handling are also provided. The system
has proven to work very reliably.
Figure 3: Control Panel for Tile Calorimeter Calibration
IV. CAN BRANCH TEST
Several thousand ELMB nodes will be used in ATLAS,
the largest sub-detector comprising alone 1200 nodes. When
organising them in CANbuses, conflicting requirements like
performance, cost, and operational aspects have to be taken
into account. For example, a higher number of ELMBs per
branch – the maximum number possible is 127 – reduces the
cost, but also reduces performance and increases the
operational risk, i.e. in case of failure a bigger fraction of the
detector may become in-operational. Additionally, several
CAN messages having different priorities may be transferred
at the same time. This calls for an efficient design of the bus
to minimise the collisions of the frames. The priority is
defined by the so-called Communication Object Identifier
(COB-ID) in CANopen, which is built from the node
identifier and the type of message.
A 200m long CAN branch with 16 ELMBs has been set up in
order to measure its performance in terms of data volume and
readout speed, and to identify possible limiting elements in
the readout chain. The set-up used is shown in figure 4. The
ELMBs were powered via the bus using a 9 V power supply.
The total current consumption was about 0.4 A.. The total
number of channels and their transmission types are given in
table 1.
Figure 4: Set-up of CAN branch test
COB-ID Type Channels Mode
0x180 + NodeId Analogue Input 1024 Sync
0x200 + NodeId Digital Input 128 Async + Sync
0x280 + NodeId Digital Output 256 Asyn
Table 1: I/O points of the CAN branch test
Due to the large number of channels, the analogue inputs of
the ELMBs were not connected to the sensors. A special
version of the ELMB software was used to generate random
ADC data ensuring new values at each reading and therefore
maximising the traffic through the OPC server. The digital
output and input ports were interconnected to check the
transmission of CAN messages with different priorities on the
bus, i.e. output lines can be set while inputs are being read.
Figure 5 shows the bus activity after a CANopen SYNC
command is sent to the bus. All ELMBs try to reply to this
message at the same time causing collisions of the frames on
the bus. The CAN collision arbitration mechanism handles
them according to the priority of the messages. In this figure,
the Bus Period is defined as the time taken for all synchronous
messages to be received from all nodes after the SYNC
command has been sent to the bus. δ defines the time between
consecutive CAN frames on the bus and is a function of the
bus speed, which is limited by the CANbus length (typically
0.7ms at 125kbaud). The time between successive analogue
channels from a single ELMB, which is dependent upon the
ADC conversion rate, is given by ∆. The OPC Server
generates the SYNC command at predefined time intervals
and this defines the readout rate.
The SCADA application was distributed over two PCs
running WinNT (128 MB of RAM and 800 MHz clock
frequency). The hardware was connected to a PC acting as
Local Control Station (LCS), where the OPC server and
control procedures where running. All values were archived to
the PVSS-II historical database. The second PC, acting as
operator station, was used to access the database of the LCS

Figure 5: Bus activity after a SYNC
and to perform data analysis and visualisation. The
communication between the two systems was internally
handled by PVSS-II. A third PC, running as a CAN analyser,
was used to log all CAN frames on the bus to a file for later
comparison with the values stored in the SCADA database.
This CAN analyser is a powerful diagnostic tool. It allows for
debugging of the bus enabling visualisation of the traffic and
sending of messages directly to the nodes.
The test was performed for different settings of the ADC
conversion rate and of the update rate of the OPC server. This
parameter defines the polling rate of the internal cache of the
OPC server for new data to be transferred to the OPC client.
The readout rate was also varied from values much greater
than the bus period down to a value close to it. The CPU
behaviour was monitored under these sets of conditions.
We have observed excellent performance of the ATLAS DCS
vertical slice at low conversion rates (1.88 and 3.71 Hz). All
messages transmitted to the bus have been logged in the
PVSS historical database. This result is independent of the
SYNC interval as long as this parameter is kept above the bus
period. However, some ATLAS applications call for a faster
readout. Results at 15.1 and 32.5 Hz show a good behaviour
when the SYNC interval is higher than the bus period.
Performance deteriorates when the SYNC interval tends to the
bus period. Crosscheck with the CAN analyser files showed
that many messages were not in the PVSS-II database. Two
major problems were identified: overflows in the read buffer
of the NI-CAN interface card, and the PVSS-II archiving
taking close to 100% of the CPU time while the avalanche of
analogue channels is on the bus. It was also found that these
results are very sensitive to the OPC update rate. The faster
the update takes place, the more CPU time is required limiting
its availability for other processes like the PVSS archiving.
This suggests to split the PVSS application in such a manner
that only the OPC interface runs on the LCS while all
archiving is handled higher up in the hierarchy shown in
figure 4. However, further tests must be performed to
address the limitation of each of the individual elements
quantitatively.
V. CONCLUSIONS AND OUTLOOK
PVSS-II has been found to be a good solution to implement
the BE system of the ATLAS DCS. It is device oriented and
allows for system distribution to aid the direct mapping of the
DCS hierarchy. The ELMB I/O module has been shown to
fulfil the requirements of the majority of the sub-detectors.
Both PVSS-II and the ELMB are well accepted by the
ATLAS sub-detector groups. The vertical slice comprises of
these two components interconnected via the CANopen OPC
Server. Many applications have been developed using this
vertical slice and they have shown that it offers high
flexibility, good balance of the tasks, reliability and
robustness. A full branch test has been performed with the
aim of estimating its performance. Good results were obtained
for low ADC conversion rates. Tests at higher ADC
conversion rates allowed the identification of several
problems, such as the read buffer size of the PCI-CAN card
causing overflows of CAN messages. For this and other
reasons, such as cost and architecture, this interface card will
be replaced. CPU usage increases to unacceptable levels with
high data flow when the OPC Server and archiving are both
run on a single processor. The vertical slice tests have helped
to better define the load distribution amongst different PVSS-
II systems.
Further tests are required to define the CAN topology to be
used in ATLAS. The main issues to be addressed are; the
system granularity in terms of number of buses per PC, the
number of ELMBs per bus (between 16 and 32 seems to fulfil
most requirements) and powering. In addition, bus behaviour
needs to be investigated further, e.g. the ELMB may only
send data on change. In response to a sync, a status message
would be sent giving a bit flag for each channel of the ELMB
indicating whether an error had occurred. If values exceed
pre-defined acceptable limits, then this could also be signaled
by the ELMB. Bus supervision and automatic recovery must
also be investigated. It must be possible to reset individual
nodes, reset the bus or perform power cycling, depending
upon the severity of any error encountered.
VI. REFERENCES
[1] H.J. Burckhart, “Detector Control System”, Fourth
Workshop on Electronics for LHC Experiments, Rome
(Italy), September 1998, p. 19-23.
[2] PVSS-II, http://www.pvss.com/
[3] JCOP, http://itcowww.cern.ch/jcop/
[4] B.Hallgren et al., “The Embedded Local Monitor Board
(ELMB) in the LHC Front-End I/O Control System”,
contribution to this conference.
[5] CAN in Automation (CiA), D-91058 Erlangen
(Germany). http://www.can-cia.de/
[6] OLE for Proccess Control, http://www.opcfoundation.org/
[7] H.J. Burckhart et al., “Communication between
Trigger/DAQ and DCS”, International Conference on
Computing in High Energy and Nuclear Physics, Beijing
(China) September 2001, p. 109-112.

A rad-hard 8-channel 12-bit resolution ADC
for slow control applications in the LHC environment
G. Magazzù 1 ,A.Marchioro 2 ,P.Moreira 2
1 INFN-PISA, Via Livornese 1291 – 56018 S.Piero a Grado (Pisa), Italy (Guido.Magazzu@pi.infn.it)
2 CERN, 1211 Geneva 23, Switzerland
Abstract
The damage induced by radiation in detector sensors
and electronics requires that critical environmental
parameters such as leakage currents of the silicon
detectors, local temperatures and supply voltages are
carefully monitored. For the CMS central tracker, an
ASIC, the Detector Control Unit (DCU) has been
developed to monitor these quantities in a commercial
sub-micron technology. A set of layout design rules
guarantees for this device the radiation hardness that is
requested for the LHC environment. The key circuit of
the DCU is an 8-channel 12-bit resolution ADC. The
structure and the performances of this ADC are described
in this work.
I. INTRODUCTION
The CMS tracker silicon micro-strip detectors, when
exposed to the LHC high levels of radiation, are subject
to a number of damaging phenomena. The main effects
are an increase of the detector leakage current and a
change in the detector depletion voltage. Maintaining the
detector integrity and efficiency over their expected 10
years life requires careful monitoring of the detector
environmental conditions. A VLSI circuit, the Detector
Control Unit (DCU), has been developed for that purpose
in the CMS tracker.
The detector hybrid block diagram is shown in Figure
1. The figure represents the global relations between the
DCU, the Si micro-strip detectors and the readout chips
(the APVs) [1]. The detector leakage currents are
monitored using a sensing resistor. This voltage is
measured by the DCU Analogue-To-Digital Converter
(ADC) and can then be read by the slow control system
using the DCU I2C interface [2]. The sensor temperature
is measured in two different points using two Negative
Temperature Coefficient (NTC) thermistors in parallel. A
third NTC thermistor is used to monitor the temperature
near the APV ICs. Two temperature and power supply
independent currents (20µA and 10µA) are generated
inside the DCU and used to drive the thermistors. The
APV power supply voltages (2.5V and 1.25V) are
monitored by the DCU through two external resistive
dividers.
Figure 1: CMS Tracker monitoring system
A single ADC is used inside the DCU to convert the
several input voltages using an analogue 8-to-1
multiplexer.
2.
II. DCU DESCRIPTION
The global architecture of the DCU is shown in Figure
Figure 2: DCU architecture
The DCU is composed of the following blocks: an 8to-1
analogue multiplexer, a 12-bit ADC, an I2C interface
and, a band-gap voltage reference and two temperature
and power supply independent current sources. In the
final version of the ASIC a diode based integrated
temperature sensor has been added. Due to lack of
experimental results this last feature will not be described
here.
This work will be focused on the operation and
performance of the analogue multiplexer and the ADC.
The design specifications are summarised in Table 1.

Table 1: DCU Specifications
# of channels 8
Resolution 12 bits
Input Range GND→1.25V
INL 1LSB
DNL 1LSB
Power Dissipation

Figure 5: DCU test-board block diagram
Figure 6: DCU test setup
All the digital functions of the IC have been
successfully tested.
The A/D converter parameters like gain, Integral Non-
Linearity (INL), Differential Non-Linearity (DNL) and
Transition Noise (TN) RMS, have been measured for the
two operating modes on all of the input channels. The
evaluation and characterisation tests were automated
using specific test programs running in the microcontroller.
The test results were read from the micro
controlled after completion via the RS232 interface.
A sequence of 128 input voltages has been applied in
the two input ranges GND→1.25V in the LIR mode and
1.25V→VDD in the HIR mode. In both operating modes
the gain is between 2.18 and 2.20 LSB/mV corresponding
to a resolution of 500uV/LSB.
Figure 7 shows the A/D INL for input voltages in the
0 to 1.25V range (LIR). The periodic “saw-tooth” shape
observed in the picture reveals no intrinsic ADC nonlinearity
over this range, where the INL is less than 1 LSB
according to the specifications. If the extended range, 0 to
2.5 V, is taken, the non-linearity due to limited common
mode range of the comparator is revealed as can be seen
from Figure 8
Figure 7: ADC INL in the LIR mode (input range =
GND→1.25V)
Valid working
range ( in LIR
mode)
Figure 8: ADC INL in the LIR mode (input range =
GND→VDD)
The differential (Figure 9) non-linearity has been
evaluated and reveals a monotonic A/D converter
characteristic and no missing codes.

Figure 9: ADC DNL in the LIR mode (input range =
GND→1.25V)
Finally, 1024 samples of a fixed voltage were taken to
evaluate the internal A/D noise (transition noise). From
Figure 10 it can be concluded that the transition noise has
an RMS value smaller than one LSB. The RMS of the
transition noise can be evaluated applying a sequence of
very small voltage steps to the ADC input and evaluating
the steepness of the transition between two adjacent ADC
outputs. This analysis leads to an noise RMS around 0.25
LSB.
Figure 10: ADC output distribution for a fixed input
voltage
Power dissipation has been evaluated: with the ADC
working at the maximum acquisition rate: the absorbed
power is less than 40mW. A preliminary ADC
temperature characterisation shows no significant changes
in ADC performance with temperature.
Several samples of the A/D converter have been
irradiated with X-rays up to 10 Mrad (dose rate 25
Krad/min). No changes in the INL and in the transition
noise have been observed. A gain decrease of
0.4% / Mrad with the irradiation dose has been measured
(see Figure 11).
Figure 11 : A/D converter gain as a function of the dose
IV. SUMMARY
As part of the CMS tracker slow control system, a
mixed-mode ASIC has been developed to monitor the
detector leakage currents, temperatures and power supply
voltages. The IC has been implemented in a commercial
sub-micron technology using a special set of layout
design rules to guarantee the level of radiation tolerance
required in the LHC environment. The main building
block of this IC is a 12-bit ADC whose characteristics
have been described in this work. The ASIC has been
irradiated with X-rays up to 10 Mrad with only minor
changes in the circuit performance.
A second version of the IC including an integrated
temperature sensor has now been submitted for
fabrication
V. REFERENCES
[1] CMS Technical Design Report, CERN/LHCC/98-6
(1998)
[2] I2C Bus Specification, Signetics (1992)
[3] B.Razhavi, Principles of Data Conversion System
Design, IEEE Press (1995)

Design specifications and test of the HMPID’s control system in the ALICE experiment.
Abstract
The HMPID (High Momentum Particle Identification
Detector) is one of the ALICE subdetectors planned to take
data at LHC, starting in 2006. Since ALICE will be located
underground, the HMPID will be remotely controlled by a
Detector Control System (DCS).
In this paper we will present the DCS design,
accomplished via GRAFCET (GRAphe Fonctionnel de
Commande Etape/Transition), the algorithm to translate into
code readable by the PLC (the control device) and the first
results of a prototype of the Low Voltage Control System.
The results achieved so far prove that this way of proceeding
is effective and time saving, since every step of the work is
autonomous, making the debugging and updating phases
simpler.
I. INTRODUCTION
The HMPID DCS can be considered as made of five main
subsystems: High Voltage, Low Voltage, Liquid Circulation,
Physical Parameters and Gas. Each of them requires a specific
control and all of the controls have to be integrated into the
ALICE DCS mainframe. The HMPID DCS will be
represented via a single interface which will include the
above-mentioned systems and will be part of the whole
ALICE DCS.
We will deal with three main subjects:
1. Providing a common way to represent and design the
control system
2. Designing the Low Voltage control system
3. Presenting the first results of tests performed on the
Low Voltage System.
A possible software architecture of the HMPID’s control
is shown in Fig.1. It actually mirrors the hardware
architecture, since one can distinguish the three main layers:
Physical, Control and Supervisor, each characterised by a
specific functionality [1].
In fact, the lowest layer [2] will deal with PLC
programming (by mean of Instruction List language) in order
to read data from the physical devices (pressure and
temperature sensors) and to send commands to actuators
(switches, motors, valves).
E. Carrone
For the ALICE collaboration
CERN, CH 1211 Geneva 23, Switzerland,
Enzo.Carrone@cern.ch
The Control layer permits the communication between the
other two layers: indeed, it translates data from the bottom
into a language understandable by the SCADA (Supervisory
Control and Data Acquisition system) software and also
translates commands coming from the top into a language
understandable by the PLC. The communications among the
layers are accomplished via an OPC (OLE for Process
Control) server. In addition, the PVSS DBASE (a module of
the SCADA software) stores data for subsequently retrieval.
The supervisory level represents the highest control, since
it runs control programs by means of Man Machine Interfaces
remotely located.
The three layers communicate over the Ethernet via the
TCP/IP protocol.
Figure 1: DCS software architecture

II. A SYSTEMATICAL APPROACH TO DCS DESIGN
Since we have to program the whole DCS (meaning that
we have to deal with all of the three layers, and program PLC
as well as SCADA systems) it is compulsory to establish a
very well defined way of designing the system. This becomes
necessary as many people are going to make intervention on
the system itself; these people, in most cases, will not be
control specialists. Clarity and portability are the two main
concerns.
In order to satisfy to these needs, we have defined six
fundamental steps required for the DCS design:
1. Definition of the Operations List.
The Operation List is the first tool we use to understand
how the detector works. Actually, it contains as much
details as possible about the specifications of the system.
The list has to be written in strong collaboration with the
designers of the system, which are the most valuable
source to understand the actions which are to be
performed via the automatic control.
2. Description of the process as a Finite State machine
(FSM).
This step represents the first attempt to interpret the
system into a fashion closer to the control design: the
Transitions Diagram describes the evolution of the system
yet without going deep into the controls aspects, but
giving a general idea.
3. GRAFCET modelling.
The GRAFCET language [3] is a further step towards the
definition of the control system: not only it is a visual tool
near to the FSM representation, but it is a powerful
language useful for the description of whatever system. It
means that it does not matter if one is going to program
PLCs or SCADA: GRAFCET describes the system in a
fashion which is completely independent from the
hardware one will use. Furthermore, it is also simple and
clear to non-control specialists. Among the other
possibilities (i.e. Petri Nets above all) GRAFCET remains
for us the best choice
4. Coding of GRAFCET into Instruction List.
The PLCs adopted hereby belong to the family of Siemens
S-300. However, the procedures are applicable to any
PLC. Moreover, since GRAFCET allows the design of
very complex systems, the PLC language which best suits
the needs for complex instructions managing and
execution speed is the Instruction List (IL), included into
the IEC 1131-3 rules [4]. In order to accomplish this task
we developed an original algorithm to translate univocally
the GRAFCET into IL. This step corresponds to the
programming of the PLC.
5. Check of the parameters read by the PLC
Once the PLC runs its program, one needs to check how
the program is running and the values read by, e.g., the
ADC (Analog-to-Digital Converter) modules.
Siemens PLCs are supplied with the Step7 programming
environment, which comprises the Variable Table (VAT)
reading utility. It means that one can display the variables
read by the ADC modules directly on the workstation used
for programming.
6. Coding of the Man-Machine Interfaces into the
SCADA PVSS environment.
At this step the PLC is running autonomously the control
program, but the operations have to be performed by the
operator manually (e.g. pushing buttons). To operate the
system remotely one needs to program an interface at high
level, by means of synoptic panels where each
functionality of the system is represented and the user can
send commands, read values, generate historical trends
and so on. These panels are programmed into the PVSS
environment, which is the SCADA adopted by CERN for
all the LHC experiments’ DCS.
All the subdetectors’ DCS will merge into the most
general control system, the Experiment Control System
(ECS).
III. THE LOW VOLTAGE SYSTEM
The HMPID detector consists of seven modules, each
sizing about 142 x 146 x 15 cm 3 and including three radiator
vessels, a Multi Wire Proportional Chamber (MWPC), the
Front End Electronics (FEE) and the Read-Out Electronics.
In [5] we have already reported some results from the
Liquid Circulation sub-System, when the design phase was
accomplished, along with some preliminary considerations on
the High Voltage (HV) and Low Voltage (LV) subsystems.
In the following we will focus on the Low Voltage control
system, starting from the control of the Power Supply units up
to the Man-Machine Interface.
The system we will deal with represents a “custom”
solution to provide the Low Voltage supply to the HMPID
front-end and read-out electronics; as a result of the tests and
the evaluations subsequently performed (costs, reliability,
maintenance) we will be able to decide on the implementation
of this solution for the whole detector.
In order to guarantee continuity of operations, even in case
of faults, the “custom” layout is intended to split the available
power into different channels via a PLC. The power supply of
each module has been divided into six Low Voltage and High
Voltage segments, and other four segments for electronics
circuits. In this layout, a fault of a single chip will not
compromise the functioning of the entire module.
A. The apparatus set up
We set up a test bench station in order to carry out some
tests on a single Low Voltage power supply segment. A
schematic representation of the test bench is shown in Fig. 2.

Figure 2: DCS software architecture
The power supply is an Eutron BVD720S, 0-8V, 0-25 A,
0.1±1 dgt. The PLC belongs to the S-300 Siemens family,
equipped with two ADC 12 bit modules. The dummy load is
made of resistors which represent the LV segment, while the
“sensing board” is a resistors network needed for the current
detection and the signal conditioning.
In fact, we measure the current drained by the load by
means of the voltage drop on a “sensing resistor”; but, in
order to overcome the common mode voltage UCM=2.5 V,
characteristic of the ADC input preamplifier, a resistor
network has been designed and assembled. So, both the
sensing resistor and network providing the signal conditioning
have been placed on the sensing board.
Afterwards, the sensing board and the dummy load have
been connected to the ADC module of the PLC, to get voltage
and current values.
Fig.3 shows the electrical diagram of one bipolar channel,
including the sensing wires.
Figure 3: Test bench wirings
The scheme of the sensing board is shown in details in
Fig.4.
Figure 4: Sensing board scheme
The new voltage values are evaluated according to the
following equation:
V
sr+
+ V
V+
s −V−
s = Vin
⎛ R2
R4
⎞
⋅ ⎜ − ⎟ +
⎝ R1
+ R2
R3
+ R4
⎠
⎛ R4
⎞
g ⋅⎜
⎟
⎝ R3
+ R4
⎠
= +
sensin
The calibration of the sensing board let us provide the
correct algorithm to the PLC program in order to present in
the VAT the correct values of voltage and current.
Subsequently, the sensitivity obtained in this way amounts
to 2.8 mA and is enough to detect even a single FEE chip
failure.
B. The LV control system
According to the 6-steps list introduced above, first we
study the system and write the Operations List; the most
important constraint is given by the relationship with the High
Voltage system: actually, the ON/OFF switching is the most
critical, along with the current and voltage values.
When the LV chain has to be switched ON, since the FEE
requires ±2.8 V, both these polarities must be supplied
simultaneously.
When the LV is switched OFF, the facing HV segment
must be checked: it must be turned OFF before the LV. This
sequence is mandatory to prevent FEE breakdowns due to
charge accumulation on the MWPC cathode pads. (In fact the
ground reference to the MWPC sense wires is ensured
through the FE electronics, then the low voltage at the

corresponding FE electronics segment must be applied before
the HV segment is switched ON).
Current and voltage must be within ranges:
V load <
min V Vmax
< , I min I load I max <
If max
< .
I load > I , then the corresponding HV-LV segments
must be automatically switched OFF, according to the LV
switching OFF sequence.
The subsequent step is the design of the transitions
diagram, as shown in Fig. 5.
Figure 5: LV transitions diagram
After the OFF state, the first state encountered is
CALIBRATE, which is intended to set voltages and currents
out of the power supply; it means that no power is yet given to
the FEE. Then, the CONFIGURE allows the user choosing
how many (and which) segments he wants to power. In STBY
the HV power is checked: this state is indispensable for a
correct shut down procedure of the LV.
When the ON status is active, voltages and currents are
monitored over all the FEE segments active at that moment.
Whenever one of these values is out of range, the system
goes into the ALARM state, the related segment goes OFF
and a notification is sent to the HV system in order to set OFF
the facing HV segment also.
The GRAFCET design follows the states just described.
Actually, we have three Master grafcet which are needed to
manage alarm and stop conditions, and a Normal grafcet to
describe the normal evolution of the system, as in Fig. 6.
What has to be pointed out is that states 2 and 3 are
actually Macro-States, meaning that they contain some other
grafcet to manage the calibration and configuration of each
segment. This way, the grafcet shown is the most general one,
while the deeper control is demanded to the other sub-grafcet.
This is a very useful facility to simplify the view of the
system and concentrate on the general functioning.
Figure 6: Normal grafcet
The algorithm we designed operates the conversion from
grafcet (sequential and parallel processes) to Instruction List
(a strictly sequential language), as in Fig. 7.
Copy Commands from
HW Inputs buffer
yes
Start Main Cycle
Create the
Process Image
Interlock
?
Analyze Input Values
(signal conditioning)
no
Remote
?
Calculate the Transitions
Activate States
Do Actions for Active
States
Output the
Process Image
End
yes
Copy Commands from
OPC buffer
Figure 7: Grafcet → Instruction list conversion algorithm
The initialisation reads the input variables and decides
whether to put them into a local or remote buffer, in
dependence of the local/remote operation. Then, the
transitions are evaluated: each of them will be considered
crossed if the related condition is true and the preceding state

is active. If the transition is crossed, the next state is activated,
while the preceding state is deactivated.
The VAT shows the exactness of our calculations, as in
Fig. 8.
The first elements (PIW) represent the raw data read by
the ADC module: it is a decimal number in the range [-27648,
+27648]. In order to read currents and voltages, we applied
the algorithms for the offset correction. The final results are
the “Iload” and “Vload” values. The last two elements are useful
to check the real voltage going into the ADC module from the
sensing board.
PIW 288 “V sensing + ADC” --- DEC 8872
PIW 290 “V sensing – ADC” --- DEC -14440
PIW 292 “V load + ADC” --- DEC 15496
PIW 294 “V load – ADC” --- DEC -15496
MD 100 "I load +“ --- REAL 3.737275
MD 108 "I load -“ --- REAL -4.101968
MD 132 "V load +“ --- REAL 2.802372
MD 124 "V load -“ --- REAL -2.802372
MD 20 "V sensing + input ADC“ --- REAL 25.67129
MD 28 "V sensing - input ADC“ --- REAL -41.7824
Figure 8: LV VAT
Although not shown above, the VAT can also read the
states of the system; we can check whether it is in OFF or ON
or CALIBRATE, or whatsoever. Moreover, we can simulate
alarm conditions via some switches that let us produce short
circuits, or wiring interruptions.
The last point of our six-steps method consists in
programming the Man-Machine Interfaces into the PVSS
environment; these interfaces let the user operate the system,
monitor parameters, perform actions, acknowledge alarms.
For instance, we monitored the values of current and
voltage; the trend is shown in Fig. 9. It confirms subsequently
the reading of the VAT, but presents the same data into a
more readable fashion.
Figure 9: LV variables trend
In order to avoid a proliferation of interfaces different
from each other, the JCOP (Joint COntrol Project) at CERN is
releasing layouts written into PVSS and named “framework”,
in which dimensions, colours, positions of all the elements of
the panels are defined, giving a coherent look to every control
interface of whatever detector or experiment.
Our efforts are now directed towards the programming of
all the panels according to the JCOP’s framework guidelines.
The first step will consist into the integration of both the
Liquid Circulation and the low Voltage system into a single
panel. The other control systems will follow and find place
into the same framework, which will represent the whole
HMPID DCS.
IV. CONCLUSIONS
The methodology hereby introduced and adopted has
shown to be effective and time saving; in fact, it allows an
easy interaction between control engineers and physicists in
charge of the design and operation of the systems. The
GRAFCET language has proved to be powerful and useful for
the programming of the system at every level of hierarchy.
Moreover, the measurements displayed on the VAT are
readable directly also on a man-machine interface in form of
diagram, making easy a monitoring over long times in order
to check stability and performance of the power supply
system.
V. ACKNOWLEDGEMENTS
The author would like to thank A. Franco for the
fundamental contributions given during the design stage and
the hardware set up as well.
Not only he gave precious aids in programming the
SCADA systems, but also he helped in the whole PLCs
environment.
VI. REFERENCES
[1] Swoboda D., The Detector Control System for ALICE :
Architecture and Implementation, 5th Conference on
Electronics for LHC Experiments, Snowmass, 1999
[2] Lecoeur G., Määtta E., Milcent H., Swoboda D., A
control system for the ALICE-HMPID liquid distribution
prototype using off the shelf components, CERN Internal note,
Geneva, 1998
[3] David, R. Grafcet: A Powerful Tool for Specification
of Logic Controllers. IEEE transactions on control systems
technology, Vol. 3, N.3, September 1995
[4] Seok Kim H., Young Lee J., Hyun Kown W., A
compiler design for IEC 1131-3 standard languages of
programmable logic controllers, Proceeding of SICE 99,
Morioka, 28-30 luglio 1999
[5] De Cataldo G., The detector control system for the
HMPID in the ALICE experiment al LHC, 6 th Conference on
Electronics for LHC Experiments, Krakov, 2000

Abstract
THE CMS HCAL DATA CONCENTRATOR: A MODULAR,
STANDARDS-BASED IMPLEMENTATION
The CMS HCAL Upper Level Readout system processes
data from 9300 detector channels in a system of about 26
VME Crates. Each crate contains about 18 readout cards,
whose outputs are are combined on a Data Concentrator
Card, with real-time synchronization and error-checking
and a throughput of 200 Mbytes/s. The implementation is
modular and based on industry and CERN standards: PCI
bus, PCI-MIP and PMC carrier boards, S-Link and LVDS
serial links. A prototype system including front-end emulator,
HTR cards and Data Concentrator has been prototyped
and tested. A VME motherboard provides a standard platform
for the data concentrator. Implementation details and
current status are described.
200Mbytes/s
Average
DAQ
TTC
Optical
Fanout
On−detector Front End: QIE ADC
Gigabit Optical Link Tx
H
R
C
T
T
C
D
C
C
H
T
R
H
T
R
E. Hazen, J. Rohlf, S. Wu, Boston University, USA
A. Baden, T. Grassi, University of Maryland, USA
3 Channels/fiber
@ 1.6 Gbit/s
18 HTR Cards
per VME crate
LVDS Serial
80 Mbyte/s
Local TTC Fanout (BCR, ECR, CLK)
H
T
R
Figure 1: HCAL DAQ Crate
1 OVERVIEW
L1 CMS
Calorimeter
Trigger
Vitesse
800Mbit/s
Copper
The CMS HCAL trigger/DAQ system consists of about
(26) 9U VME64xP crates (Fig. 1) with up to 18 HCAL
Trigger Readout (HTR) modules, one Data Concentrator
Card (DCC), and one HCAL Readout Controller (HRC).
Front-end data is carried from the on-detector front-end
electronics to the crate by 100m optical fibers, each carrying
3 front-end channels. LVDS data links are used to
transfer data from the HTR modules to the DCC and for local
fanout of TTC (Trigger, Timing, Control) signals. The
primary DAQ output is via an S-Link/64[1] carrying an average
data volume of 200 Mbytes/s from each crate.
2 HCAL TRIGGER READOUT CARD
The HTR module is a 9U VME module (Figure 2) equipped
with optical receivers, TTCrx circuitry, outputs on serial
FE
Data
TTCRx
8 or 16 Fibers
24 or 48 Channels
Local BC0, Clock
Level 1 Pipeline
Level 1 Pipeline
Level 1 Pipeline
Level 2 Pipeline
Fanout BC0, Clock
Serial
Link
Board
Figure 2: HCAL Trigger Readout Card
Trigger
Primitives
To
Level 1
Trigger
Level 1+2
Data
To
DCC
LVDS (Channel Link) and a custom mezzanine card. The
optical inputs receive data from the HCAL front-end electronics,
with one charge sample per bunch crossing (BX).
The high-speed serial inputs require special board layout
techniques. The CMS HCAL is a trigger detector, thus
the HTR includes two data pipelines: the trigger pipeline,
which assigns Front-End data to a BX and sends them to
the CMS regional trigger, and the DAQ pipeline where the
FE-data are pipelined, triggered and sent to the Data Concentrator
Card.
9
OTE
Lineariz.
LUT
GOL
Deser
System CK
E
16
RXData
Recov.
CK
L1-TPG
Filter
Test RAM
Local
Clock
Synch
16
Fiber
to
Fiber
Alignment
E T &
Compr.
(LUT)
μ
window
8
MIP bit
¢¡¤£
E T,compr
9
Ch A
Ch B
Ch C
SLB-PMC
(ECAL
design)
Figure 3: HTR Input and Level 1 Pipeline
The HTR input processing and Level 1 Pipeline is shown
in Figure 3. The raw fiber data stream is deserialized, then
synchronized to the local clock. A programmable delay of
up to a few clocks is used to align data from different input
fibers. A test RAM can substitute for the input data stream.
Finally, the 3 channels carried on one fiber are demulti-

plexed. Each channel is then fed to a linearizing look-up
table which converts raw input data to a 16-bit linear energy
value. Next a finite-impulse response (FIR) filter is
used to subtract the pedestal and assign all the energy to
a single bunch crossing. This performs the same function
as a traditional analog shaper, but has the advange of being
easily reprogrammable. Finally, the energy is converted
to ¥§¦
and compressed to 8 bits according to a non-linear
transformation specified by the CMS level 1 calorimeter
trigger, and a comparison is done to see if the signal may
represent a muon. This compressed output plus a muon ID
bit is sent to level 1. The final synchronization and serial
transmission is performed by a Synchronization and Link
Board (SLB) described in detail elsewhere[2]. The latency
of the level 1 pipeline is critical; it must be less than ¨
23 BX periods. Currently the theoretical minimum for the
HTR implementation is 16 BX periods.
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The HTR Level 2 Pipeline is shown in Figure 4. First
is a pipeline of programmable depth which stores data during
the CMS level 1 latency period (a fixed value). Then
comes a “derandomizer” buffer into which data is copied
at each level 1 accept. The derandomizer can hold up to
10 charge samples (one per BX) per event although currently
we anticipate only processing 5 samples. Note that a
given charge sample can in principle participate in multiple
events, so the pipeline-to-derandomizer copy logic must
handle overlapping events. From the derandomizer, data
is linearized by a LUT, filtered by an FIR filter similar to
that in the level 1 pipeline, and a threshold is applied for
zero-supression. At this point either the output of the filter,
the raw data or both may be inserted into the output data
stream.
A similar pipeline is used to store the level 1 trigger
primitives, synchronized with the corresponding level 2
data. Finally the data is packaged in a variable-length block
format along with any error information from the input
links and transmitted using an LVDS serializer to the data
concentrator.
3 DATA CONCENTRATOR CARD
The Data Concentrator Card is composed of a VME motherboard,
six LVDS link receiver boards and a PMC-type
logic board. The motherboard is a VME64x 9Ux400mm
single-slot module. The motherboard[3] (Fig. 5) supports
VME access up to A64/D32, and contains three bridged
PCI busses. Six PC-MIP[4] mezzanine sites are arranged
in groups of three on two 33MHz 32-bit PCI busses. A third
33MHz 64-bit PCI bus is bridged to the VME bus using a
Tundra Universe II VME-to-PCI bridge.
PC−MIP
PC−MIP
PC−MIP
PC−MIP
PC−MIP
PC−MIP
T
T
T
T
T
T
JTAG
33MHz
PCI bus 1
Bridge
33MHz
PCI bus 2
Bridge
5V
T
Local
Control
M
M
PMC (triple)
PMC
(Standard)
M/T
Figure 5: VME 9U Motherboard
T
Universe II
VME−PCI
33MHz 64 bit
PCI bus 3
VME
64x
A single large logic mezzanine board has access to all
three PCI busses for high-speed application-specific processing,
and an additional standard PMC site is available.
A local control FPGA on the motherboard provides access
to on-board flash configuration memory, a programmable
multi-frequency clock generator, and JTAG.
The LVDS link receiver boards[5] (Fig. 6 use Channel
Link[6] technology from National Semiconductor. Each
board contains three independent link receivers which can
operate at 20–66MHz (16-bit words). Buffering for 128K
32-bit words is provided for each link with provision to
discard data if buffer occupancy exceeds a programmable
threshold. Event building, protocol checking, event number
checking and bit error correction are performed independently
for each link. A PCI target interface provides
single-word and burst access to the data stream, plus
numerous monitoring registers. A single PCI burst read
serves to build an event from fragments found in each of
the three input buffers. The expected event number (low
eight bits) is provided as part of the PCI address, and a
mis-match causes an error bit to be set in the link trailer.
LVDS Rx
DS90CR285A
LVDS Rx
DS90CR285A
LVDS Rx
DS90CR285A
Altera
ACEX 1K100
FPGA
256k x 36
Synchronous
ZBT SRAM
PCI
33MHz
32 bit
Figure 6: PC-MIP 3-Channel Link Receiver Board
The logic mezzanine board (Fig. 8) contains the core

HTR
L1A 40MHz
Derand.
Buffer
Derand.
Buffer
Derand.
Buffer
Derandomizer
Buffer Protected
against overflow
Link
Tx
Link
Tx
Link
Tx
Link
Rx
Link
Rx
Link
Rx
by trigger rules logic: no bottleneck
256kb FIFO
>500 events
LVDS link speed
same as HTR processing
data concentrator logic. The prototype was implemented
using a Xilinx XC2V1000 for the logic, plus three Altera
EP1K30 for three PCI bus interfaces.
The event builder logic merges two data streams from
the two PCI busses, and re-orders the incoming data so
that the various sub-types (Level 1, Level 2...) are in contiguous
blocks in the output stream. An on-board TTCrx
stores level 1 accepts (L1A) into a FIFO which drives the
event builder. For each L1A, the data decoder triggers a
PCI burst read on the PCI-1 and PCI-2 interfaces simultaneously.
As data is transferred it is sorted into various
sub-types and summary and monitoring information is collected.
Each sub-type is pushed into a unique FIFO. After
the end of the event has been processed (block trailer received
from LRB) an end-of-event marker is pushed into
each of the FIFOs. The event builder reads data from each
of the sub-type FIFOs in turn, inserting protocol words as
needed. The DCC logic is designed to operate continuously
at the full speed of the two input PCI busses, namely
33MHz� 32 bits� 2. The event builder and output logic must
thus run at an average rate of at least 66MHz (32-bit words)
or 264MBytes/sec.
The event builder output is sent in parallel to several destinations.
Each output path contains a filter which can be
programmed to select specific portions of events or a specific
subset of events (prescaled, specially marked, etc.).
1. The DAQ Output. Every event is sent via SLINK-64
to the CMS DAQ. The detailed contents of each event
may be controlled by configuration registers.
2. The Trigger Data Output. The trigger primitives sent
to the CMS L1 trigger are also sent to via SLINK-64
to a special “trigger DAQ” system for monitoring of
the trigger performance.
3. The Spy Output. A selected subset of events is sent to
PCI
32/33
DCC
(2) 33MHz 32 bit
PCI busses
~100MHz
Processing
Event
Builder
Figure 7: HCAL DAQ Buffering
TTCRx
PCI 1
PCI 2
8Mb Buffer
>4000 events
SLINK
LSC
Busy/Ready Overflow Level 2 Data
Warning to Readout Unit
a VME-accessible memory for monitoring and diagnostics.
L1A
FIFO
Data
Decoder
Data
Decoder
Level 2
FIFO
Level 1
FIFO
Summary
FIFO
Level 2
FIFO
Level 1
FIFO
Summary
FIFO
Monitoring (via VME to CPU)
Event
Builder
Figure 8: DCC Logic PMC
DAQ
FIFO
Trigger
FIFO
Spy
FIFO
Error detection and recovery are a primary consideration
in a large synchronous system and the DCC contains
logic dedicated to this purpose. Figure 7 shows the main
DAQ data pipeline and buffering in the HCAL readout system.
Hamming error correction is used for the LVDS links
between the HTR and DCC. All single-bit errors are corrected
and all double-bit errors are detected by this technique.
Event synchronization is checked by means of an
event number in the header and trailer of each event, which
are checked by the LRB logic against the TTC event number.
Buffer overflow is avoided by the expedient of discarding
the data payload and retaining only header and
trailer words when the LRB buffer occupancy exceeds a
programmable level. Additionally, an “overflow warning”
output is provided which is delivered to the CMS trigger
throttling system to request a reduction in the rate of L1A.
Data transfers from the LRB to DCC logic are protected by

parity checks on the PCI busses. The event builder operates
at a processing speed sufficient to handle 100% occupancy
of the two PCI busses. After the event builder is a large
memory, which can contain several thousand average-size
event.
The main bottleneck (speed limitation) in the DCC is
the two 32/33 PCI busses through which all data must
flow. The theoretical maximum bandwidth for one of these
busses is 33MHz x 4 or 132 Mbytes/s per bus. In practice
we expect to achieve about 100Mbytes/s, for a total of
200Mbytes/s throughput on the two busses. This is exactly
the maximum average data volume permitted on one input
of the CMS DAQ switch.
S-Link
TTC (fiber)
CLK
HRC TTCvx TTCvi
DCC Ch A Ch A FEE
HTR HTR
VME Bus
LVDSrx LVDStx LVDStx
S-Link
TTCrx
TTCrx TTCrx
TTCtx
Data (G-Link)
Ch B Ch B
Figure 9: HCAL Readout Demonstrator
4 PROTOTYPE TESTING
L1A
& LHC
Emulator
A “demonstrator” (first prototype) of the entire system
is being built (see Figure 9). The HTR demonstrator is
a 6U VME module with 4 G-Link receivers running at
800Mbyte/s and an Altera APEX family FPGA for the processing
logic. The (second) prototype and production HTR
modules will be 9Ux400mm VME modules using CERN
GOL links. The DCC demonstrator is built on the 9U
VME motherboard as described above, and is quite close
in hardware configuration to the anticipated production design.
A custom front-end emulator (FEE) which simulates
LHC timing and produces dummy front-end data is used
to provide simulated input data to the HTR for testing. A
G-Link based optical S-Link is used to transport data from
the DCC demonstrator to a VME CPU for verification.
As of this writing, a simplified demonstrator using one
FEE, one HTR, one DCC and S-Link to CPU has been successfully
tested for use in a high-rate radioactive source test
at Fermilab. Data was transferred through the entire chain
without error at a continuous rate of 80 Mbytes/s. The S-
Link data is received on the CPU in a large DMA buffer
(400+ Mb) and when full written to disk for off-line analysis.
We expect to complete the full demonstrator shortly,
though only highly simplified FPGA code will be implemented
in the HTR and DCC.
5 SUMMARY
A demonstrator of the CMS HCAL DAQ has been assembled
and testing has begun. The data concentrator makes
extensive use of standard interfaces and busses, and was assembled
from “multifunction” components developed separately.
This resulted in significant savings by sharing development
costs between multiple projects. The design of
the full-fuction prototypes will continue through the remainder
of 2001, with a working prototype system expected
in 2002.
6 REFERENCES
[1] “The S-LINK 64 bit extension specification: S-LINK64”,
A. Racz, R. McLaren, E. van der Bij, EP Division, CERN.
see http://hsi.web.cern.ch/HSI/s-link/
[2] See http://cmsdoc.cern.ch/carlos/SLB/.
[3] See http://ohm.bu.edu/%7Ehazen/my d0/mb9u/
[4] “PC*MIP Specification”, VITA 29. VMEbus International
Trade Association Standards Organization
[5] See http://ohm.bu.edu/%7Ehazen/my d0/TxRx/
[6] The National Semiconductor family of LVDS point-to-point
serial links. See for example the transmitter data sheet at:
http://www.national.com/pf/DS/DS90CR285.html

EMI Filter Design and Stability Assessment of DC Voltage Distribution based on
Switching Converters.
Abstract
The design of DC power distribution for LHC front-end
electronics imposes new challenges. Some CMS sub-detectors
have proposed to use a DC-power distribution based on DC-
DC power switching converters located near to the front-end
electronics.
DC-DC converters operate as a constant power load. They
exhibit at the input terminals dynamic negative impedance at
low frequencies that can generate interactions between
switching regulators and other parts of the input system
resulting in instabilities. In addition, switching converters
generate interference at both input and output terminals that
can compromise the operation of the front-end electronics and
neighbour systems. Appropriated level of filtering is
necessary to reduce this interference.
This paper addresses the instability problem and presents
methods of modelling and simulation to assess the system
stability and performance. The paper, also, addresses the
design of input and output filters to reduce the interference
and achieve the performance required.
I. INTRODUCTION
DC power distribution has been used by aerospace and
telecommunication industries [1][2]. This topology distributes
a high voltage (HV) and converts it to low voltage (LV) either
locally or near the electronics equipment. In high-energy
physics (HEP), some CMS and Atlas sub-detectors [3][4]
have proposed similar topologies to power-up the front-end
electronics. In such proposals, the AC mains is rectified in the
control room and DC high voltage (200-300V) is distributed a
distance about 120-150 mts. to the periphery of the detector.
At that location, DC-DC converters transform with high
efficiency the HV into the LV required by the front-end (FE)
electronics. Those converters are located about 10-20 mts.
from the front-end electronics due to the intense magnetic
field that exists inside the detector.
For LHC experiments, converters have to operate reliably
under high-energy neutron radiation and fringe magnetic
field. Converters have to present high efficiency, galvanic
isolation between input and output, and couple low amount of
noise to the surrounding electronic equipment. Intrinsically
switching power converters generate a noise level that, in
general, is not compatible with the sensitive electronics used
F. Arteche 1 , B. Allongue 1 , F. Szoncso 1 , C. Rivetta 2
1 CERN, 1211 Geneva 23, Switzerland
Fernando.Arteche@cern.ch
2 FERMILAB, P.O.Box 500 MS222, Batavia Il 60510 USA
rivetta@fnal.gov
in HEP experiments. Input and output filters are necessary to
attenuate the level of noise coupled by conduction and
radiation through the cables. Also, interactions among
converters with input filters and distribution lines can
deteriorate the performance or induce instabilities in the
system because the converter operate as a constant power
load.
3 phase mains
400V/50Hz.
AC/DC
+ filter
Distribution
line
~150mts
Figure 1: DC distribution system
BUS
DC-DC converter unit
DC-DC converter unit
DC-DC converter unit
N
In this paper, analysis and design approaches for the
system are presented. Section II presents an overall view of
the problem, section III resumes the standards related with
conducted interference emissions, section IV describes the
design of the system considering stability issues, while section
V addresses the design of the input filter to reduce conductive
interference.
II. PRESENTATION OF THE PROBLEM.
~20mts
Front-end
Front-end
Front-end
All switching converters generate and emit high frequency
noise. The emission can be coupled to the sensitive FE
electronics and neighbour subsystem electronics by
conduction and/or radiation. This noise can interfere with the
sensitive FE electronics and cause malfunction. The
frequency range of the electromagnetic interference (EMI)
spectrum generated by power electronics equipment can
extend up to 1GHz.
For conducted EMI there are two principal modes of
propagation, differential (DM) and common mode (CM). The
propagation of the differential mode EMI takes place between
conductor pairs, which form a conventional return circuit (e.g.
negative/positive conductors, line phase/neutral conductors).
The DM EMI is the direct result of the fundamental operation
of the switching converter. The propagation of the common
mode EMI takes place between a group of conductors and

either ground or another group of conductors. The path for the
CM EMI often includes parasitic capacitive or inductive
coupling. The origin of the CM EMI is either magnetic or
electric. CM EMI is electrically generated when a circuit with
large dv/dt has a significant parasitic capacitance to ground.
Magnetically generated CM EMI appears when a circuit loop
with large di/dt in it has significant mutual coupling to a
group of nearby conductors. Also, it is important to mention
there is an important energy exchange between modes. This
effect is known differential-common mode conversion.
In switching power converters, the same fundamental
mechanisms that are responsible for conducted EMI can also
generate radiated EMI. Metal cases around the converter tend
to attenuate the internal high frequency electromagnetic
fields. Input and output cables or improperly grounded
apparatus can still lead to substantial radiation.
Additional filtering is necessary at the input and output of
converters to reduce the conducted noise. Filters have to
provide attenuation in a wide range of frequencies between
the switching frequency and up to 30-50 MHz. To fulfil these
requirements, cascade of low-pass filters attenuating both low
and high frequency ranges are used. Figure 2 depicts the DC-
DC converter unit composed by two commercial VICOR
i+
i-
+
_
ig
GND
Cd1 Cd2
Cc1 Cc2
INPUT
III. EMI REGULATIONS AND STANDARDS.
Regulation about EMIs began in early days of electronics.
Today exists a vast collection of standards covering
equipment in industry, military, commerce and residence. In
Europe, limits for high frequency interference are specified
either by generic standards (EN50081-1 for residential,
commercial, and light industry, EN50081-2 for industrial
environment) or by standards for specific product families
(EN55014 for household appliances, EN55022 for
information technology equipment, or EN55011 for radiofrequency
equipment) for industrial, medical and scientific
applications. In USA, the Federal Communication
Commission (FCC) issues electromagnetic compatibility
(EMC) standards, with different limits for class A and class B
devices. Both FCC standards are defined for digital equipment
marketed for use in commerce, industry or business
environment (class A) and a residential environment (class B).
Typically, European standards for conducted high frequency
emissions are specified in the frequency range from 150KHz
Vicor converter
Vicor converter
Figure 2: Scheme of the DC-DC converter unit
converters [5]. Low-pass filters attenuating the high
frequency (HF) range are included at the output of each
converter to reduce both differential and common mode noise
conducted to the distribution cable located inside the detector.
A HF low-pass filter, common to both VICOR converters, is
present at the input. This filter is in cascade with the internal
input filter of the converters and the set has to be designed to
provide noise attenuation in a wide range of frequencies. The
HF filter is designed to attenuate both DM and CM in high
frequency while the internal filter is tuned to reduce DM low
frequency components. These filters can interact adversely
with the converter at low frequency, resulting in severe
performance degradation or even instability.
Power converters, operating with tight close-loop
regulation of the output voltage, present negative input
impedance in a range of frequencies where the feedback is
effective. This negative impedance interacts with the input
filter, input distribution cables, and other converters
connected to the same distribution line, giving place to
instabilities or deterioration of the dynamic performance.
Input EMI filters have to be properly designed to avoid this
problem and also to provide the adequate attenuation in a
wide frequency range.
OUTPUT
5V
to 30MHz, and in the United States form 450KHz to 30MHz.
The allowed conduction emission levels are between 46 dBuV
and 79 dBuV. These limits are imposed to the input cord of
the equipment under test and the compliance is verified
inserting a line impedance stabilization network (LISN) in
series with the unit’s AC power cord. The measured values
correspond to the voltage level registered across any input
wire when it is terminated at the source by 50 ohms
impedance to ground (LISN termination). The standards do
not distinguish between CM and DM coupling mechanism.
Military standards for conducted emissions (MIL-STD-461
CE-03) differ from the other standards. It does not use the
LISN, it directly measures the emission current using a
current probe. Also it specifies that conducted emissions have
to be measured on other cables in addition to the power cord.
The range of frequencies covered is between 14 KHz and 50
MHz and the emission level are between 86dBuA and
20dBuA [6]. To compare these standards we should normalize
the measurement to dBuA or dBuV assuming a normalized
impedance of 50 ohms. Figure 2 compares three standards
normalized in dBuV.
+
_
+
_ 7.5V

dBuV
1 0 2
1 0 1
1 0 4
1 0 5
M I L -S T D
E U
1 0 6
fre q . [ H z . ]
F C C - B
Figure 3: Conductive EMI standards [Normalized to 50 ohms]
In HEP community there has not been a systematic
approach to define both emission and susceptibility policies of
EMI signals [7]. Some experiments have written policies
considering issues about grounding and shielding. Also, they
have included as a rule to purchase equipment that complain
with either European or American standards, but there is no
quantitative limit in the emission level of power distribution
and signal cables routed inside the detectors. CMS is trying to
define limits for both emission and susceptibility of the
electronic equipment to be installed in the experiment. They
will be based on measurements of prototypes and analysis of
the cross effect among radiator-receiver electronics. The
future standards applied to power supply distributions will be
based on direct measurement of the noise current level as
required by the military standard and the level imposed will
be close to that required by commercial standards. Also it will
address some limitations on the common mode current levels
to avoid cross-talk among equipments due to ground currents.
IV. NEGATIVE INPUT IMPEDANCE OF DC-DC
CONVERTERS
DC-DC switching converters with tight output voltage
regulation operate as constant power loads. The instantaneous
value of the input impedance is positive but the incremental or
dynamic impedance is negative. Due to this negative input
impedance characteristic interaction among switching
converters and another part of the system connected to the
same distribution bus may result in system instability.
To analyse the behaviour of the converter and the
interaction with the rest of the system a reduced model of the
system is necessary. The reduced model has to represent the
behaviour of the system at low frequency in the range
between DC and frequencies near the bandwidth of the power
converter. In this frequency range, the power converter
behaves at the input as a constant power load in cascade with
the input filter. The rest of the system can be modelled as
follows: the distribution line can be approximated by a
lumped inductance in series with a resistor and the HF filter
can be reduced to the DM capacitors.
To present a qualitative behaviour of the converter at the
input terminals, let us consider first the simple equivalent
circuit depicted in figure 3. It represents a VICOR converter
connected to a primary source with short leads. Using as state
variables the inductor current il and the capacitor voltage vc,
the state equation is:
1 0 7
1 0 8
E
dv c P c
C = il
−
dt v c
di l
L = E − il.
r l − v c
dt
+
-
r l
il
L
Figure 4: Model at the input terminals of the DC-DC converter.
This equation has two real valued equilibrium points if the
condition rl < E 2 / (4.Pc) is verified. Figure 4 shows the state
portrait of eqn. 1. This picture shows there is a region of
convergence around the equilibrium point SS1 if it is stable.
The stability of this point is defined by the condition
rl > (Pc.L)/(C.vc 2 ), where vc is the capacitor voltage at
equilibrium. The equilibrium point SS2 is not depicted in the
figure, but it is located at low voltage and high current and, in
general, is unstable. In the same plot, it is possible to see an
unstable region near the origin of coordinates. Transient
operating points falling into this region does not converge to
the equilibrium point SS1 but escape at vc = 0.
Figure 5: Phase portrait of equation 1
Il [amps]
15
10
5
0
-5
To limit the operating region of the converter to the region
of convergence of the stable equilibrium point, converters
either include some limits into the dynamic range of the
control circuit or disable the operation of the power transistor
for low values of the input voltage. VICOR converters disable
the unit if the input voltage value is outside of a voltage band
around the equilibrium point (e.g. Vnom=300V, Vin=180-
375V). In this case, the converter can still be modelled by
equation 1 but including the condition, Pc ¢¡
if vc is between
180V and 375V, and Pc = 0 if vc is outside of this region.
As conclusion from this brief analysis, to analyse the
stability of the system, the converter model can be simplified
v c
C
V IC O R C O N V E R T E R
S S1
P c /v c
-10
0 50 100 150 200
Vc [volts]
250 300 350 400
(1)

y a linearized model around the equilibrium point (smallsignal
analysis). The region of convergence can be estimated
analytically or by simulation using a non-linear model of the
converter. The linearized model of the converter at input
terminal is characterized by a negative resistance of
magnitude rn = -vn / in, where the vn is the DC input voltage
and in is the DC input current. This current depends of the
load of the power converter and rn can take different values
according to the operating conditions.
Let us consider now the DC power distribution system
composed by one AC/DC converter, a distribution line of 150
mts and N converter units connected to the end-point, as it
was depicted in figure 1. Each DC-DC converter unit is
composed by 2 VICOR converters, connected in parallel at
the input. Only one input HF filter is used per unit as it was
shown in figure 2. At the distribution bus, the system can be
represented by the simplified block diagram showed in figure
6. The source sub-system contains the impedance of the AC
mains, the AC/DC converter and the HV distribution cable.
The load sub-system is composed by N DC-DC converter
units. The source sub-system is stable when loaded by a
resistor. Each DC-DC converter unit is stable if connected
directly to a power supply.
E
Source sub-system
Figure 6: Simplified block diagram
Assuming the source sub-system has an input/output
transference Fs and each DC-DC converter a transference Fc,
the overall transference between any output voltage and input
voltage is giving by.
v on
E
Fs . Fc
=
Zo
1 +
Zin
Load sub-system
Fs Fc
Zo Zin
Fs . Fc
=
1 + Tm
Von
where Zo is the output impedance of the source sub-system
and Zin is the input impedance of the load sub-system . Due to
both Fc and Fs are stable transference functions; the stability
of the system is defined by the term (1/1+Tm) that represents
the loading effect between the source and load sub-systems.
If |Zin| >> |Zo| for all frequencies, the loading effect is
negligible. This condition can be difficult to achieve in all the
frequency range. This rule prevents any noticeable interaction
between source and load sub-systems and may be overly
conservative. If |Zo| is larger than |Zin| a considerable loading
effect exists. It does not necessarily imply a stability problem.
In this case, either the Nyquist criterion or Bode based
analysis can be applied to the gain Tm to determine the system
stability [8][9].
Figure 7, in the upper plot, shows the Bode plot of the
output impedance of the source sub-system and the input
impedance of the load sub-system for different capacitance
CD= CD1 + CD2 (fig.2). This capacitance is included to
improve the LF noise filtering and improve the stability in the
high frequency region (around point B). In that area, fig. 7
shows that Tm is equal to one and the phase is near 180°. Plots
in figure 7 depict the load impedance for only one DC-DC
converter unit connected to the bus. For increasing number of
converters connected to the bus, the input impedance Zin
decreases, and the stability of the system becomes critical at
low frequency (point A). At this frequency, there exists
interaction between the AC/DC converter filter and the
negative impedance of the DC-DC converters. In this case, to
improve the stability margin is necessary to increase the
|Zo| |Zin|
|Tm|
Tm phase (deg.)
10 4
10 2
10 0
10 -2
10 5
10 0
10 -5
300
200
100
10 0
10 0
10 0
0
Zin
Zo
damping of the AC/DC converter.
Figure 7: Bode Plot of Tm
V. CONDUCTIVE EMI INPUT FILTER
The noise generated by DC-DC converters depends
strongly on the topology of the converter, layout design,
parasitic elements, etc. To prevent EMI entering to the
distribution cables, usually passive filters are inserted between
the converter and the lines.
Filters can be considered as multi-port networks, where
the input currents or output currents are linked by the
condition ig = i + − i − (figure 2), assuming there is not
radiation in the frequency range of interest. For analysis and
design those variable are decomposed into two orthogonal
components the differential and the common mode
components. These variables are defined as;
i DM
=
i
10 1
10 1
10 1
+ −
i + +
CM
− i
2
A
10 2
10 2
10 2
i
freq.[Hz.]
=
i
2
The main consideration in the filter designing is to provide
adequate attenuation to both EMI signal components using the
smallest filter circuit. Additional important considerations are
the filter damping and parasitic elements of filter components.
10 3
Cd = 0.1uF
10 3
10 3
−
Cd = 0.1uF
Cd = 5 uF
10 4
10 4
10 4
Cd = 5 uF
B
Cd = 5 uF
Cd = 0.1uF
10 5
10 5
10 5

The methodology followed in designing both the input and
output filters consisted in measuring the conducted EMI
signal generated by the power converter at both the input and
output, estimating the adequate attenuation to satisfy some
standard and defining the filter attenuation or component
values by simulation. Several measurements using a current
transformer and a spectrum analyser in peak-mode have been
performed on the input and output cables of vicor converters.
Input currents were registered for individual units and also for
both units connected in parallel at the input. Representative
spectrums normalized to 50 ohms are depicted in figure 8.
The upper plot shows the current noise of the positive input
while the lower one, the input common mode current of the
Vicor converter V300B12C250AL operating at Vin=200V,
Vout = 7.5V and Iout = 20A.
I+ dBuV
Icm dBuV
120
100
80
60
40
20
10 5
0
120
100
80
60
40
20
10 5
0
10 6
10 6
Frequency - Hz
Frequency - Hz
Figure 8: Current noise at input of the DC-DC converter
From these plots it is possible to understand the dominant
component at low frequency (up to 2MHz.) is the differential
mode component, while in high frequency both differential
and common mode components have similar magnitude.
Assuming the system has to complain with the European
norm EU55022 (fig. 3), the attenuation required in the filter
can be estimated from figure 8. It is necessary attenuations
greater than 60dB at low frequencies for DM and noise
reductions greater than 40dB in high frequency range for both
DM and CM components. It is interesting to point out if a
simple DM filter is used to attenuate the noise spectrum
depicted in fig. 8, upper plot, the result after filtering will be
similar to the noise spectrum depicted in the lower plot. The
common mode components will remain unaffected and the
system will not comply the standard.
There exists a vast variety of commercial high frequency
EMI filters. Manufactures specify the insertion loss of these
filters for DM and CM components covering the frequency
range up to 30MHz. This information allows understanding
the effect of parasitic elements in the attenuation reduction. It
also allows defining simulation models to estimate the
attenuation when the filter operates under different load
conditions. Figure 9 shows the current noise after a HF filter
and CD=5uF is included at the input of the DC-DC converter
unit. This plot is based on an estimation of the filter
attenuation calculated by simulation.
10 7
10 7
I+ dBuV
Icm dBuV
80
60
40
20
0
-20
10 5
-40
80
60
40
20
0
-20
10 5
-40
Figure 9: Current noise at the input after filtering
VI. CONCLUSIONS
Guidelines to design the EMI filters taking into account
the level of attenuation required and the stability of the overall
system have been presented. The design is based on model
simulation of the converter, filter and measurements of the
noise currents.
VII. REFERENCES
[1]- P.Lindman, L. Thorsell, “Applying Distributed Power
Modules in Telecom Systems” IEEE Trans. on Power
Electronics, Vol 11, No.2, 365-373, March 1996.-
[2]- B. Cho, F. Lee, “Modeling and Analysis of Spacecraft
Power Systems” IEEE Trans. on Power Electronics, Vol 3,
No.1 44-54, January 1988.-
[3]- J. Kierstead, H. Takai, “ Switching Power Supply
Technology for ATLAS Lar Calorimeter”, Proc. 6 th Workshop
on Electronics for LHC experiments, 380-382, Sept. 2000.-
[4]- B. Allongue et al. “Design Consideration of low Voltage
DC Power Distribution” Proc. 6 th Workshop on Electronics
for LHC experiments, 388-392, September 2000.-
[5]- Vicor Corporation. http://www.vicr.com
[6]- C. Paul, ‘Introduction to Electromagnetic Compatibility’
1992, ISBN 0-471-54927-4
[7]- Szoncso, F. ‘EMC in High Energy Physics’
http://s.home.cern.ch/s/szoncso/www/EMC/
10 6
10 6
F requenc y - Hz
F requenc y - Hz
[8] C. Wildrick et.al. “A method of defining the load
impedance specification for a Stable Distributed Power
System” IEEE Trans. on Power Electronics, Vol.10, No 3 pp
280-285. May 1995
[9] Choi, B. Cho, B. “Intermediate Line Filter Design to Meet
Both Impedance Compatibility and EMI Specifications” IEEE
Trans. on Power Electronics, Vol.10, No 5 pp 583-588.
September 1995.
10 7
10 7

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Power Supply and Power Distribution System for the ATLAS Silicon Strip Detectors
J.Bohm A
, V.Cindro D
, L.Eklund E
, S.Gadomski C&E
, E.Gornicki C
, A.A.Grillo I
, J.Grosse−Knetter E
,
S.Koperny B
, G.Kramberger D
, A.Macpherson E
, P.Malecki C
, I.Mandic D
, M.Mikuz D
, M.Morrissey H
,
H.Pernegger E
, P.W.Philips H
, I.Polak A
, N.A.Smith F
, E.Spencer I
, J.Stastny A
, M.Turala C
, A.Weidberg G
ATLAS SCT Collaboration
A
Academy of Sciences of the Czech Republic, Prague, Czech Republic
B
Faculty of Physics and Nuclear Techniques of the UMM, Cracow, Poland
C
Institute of Nuclear Physics, Cracow, Poland
D
Josef Stefan Institute and Department of Physics, University of Ljubljana, Ljubljana, Slovenia
E
CERN, Geneva, Switzerland
F
Department of Physics, Oliver Lodge Laboratory, University of Liverpool, Liverpool, UK
G
Department of Physics, Oxford University, Oxford, UK
H
Rutherford Appleton Laboratory, Chilton, Didcot, UK
I
Institute of Particle Physics, University of California, Santa Cruz, CA, USA
Piotr.Malecki@ifj.edu.pl
Abstract
The Semi−Conductor Tracker of the ATLAS experiment
has modular structure. The granularity of its power supply
system follows the granularity of the detector. This system
of 4088 multi−voltage channels providing power and control
signals for the readout electronics as well as bias voltage for
silicon detectors is described.
Problems and constraints concerning power distribution
lines are also presented. In particular, optimal choice
between concurrent requirements on material, maximum
voltage drop, space available for services, assembly
sequence etc. is discussed.
I. POWER SUPPLY SYSTEM FOR THE ATLAS SCT
The ATLAS SCT detector[1] consists of 4088 modules of
which 2112 form four barrel cylinder layers and 1976 are
mounted on end cap wheels. Single−sided micro−strip
detectors are glued back−to−back to form one double−sided
module with 1536 strips. The module is equipped with a
hybrids, a small boards carrying 12 ABCD3T readout chips
and electronics to transfer digital data from and to SCT
modules. Present barrel and end cap hybrids are
substantially different in many aspects but identical from the
point of view of power supplies.
A. Basic design principles
The ATLAS SCT readout chips and electronics for the
optical transmission of digital data to the off−detector
stations (as well as timing, trigger and control data to SCT
modules) require several low voltage supplies. In addition
silicon micro−strip detectors operating in the LHC high
radiation environment require the bias voltage which can be
regulated in 0 − 500 V range.
SCT power supply and power distribution system has
been designed according to following basic requirements:
� modularity of the power supply system follows the
modularity of the detector,
� power supply modules are fully isolated and voltages in
modules are "floating",
� every detector module is powered by separate, multiwire
line (tape or cable).
In the context of this article it seems appropriate to
underline that among other consequences for the detector
performance the above mentioned design rules allow for
the maximum flexibility in selection of optimal shielding
and grounding scheme
B. Requirements for Low Voltage power
supplies

Present requirements[2] for low voltage power supplies
result from several iterations of readout chip design and
from many beam and radiation tests of module
prototypes. Main objects of concern are Vcc, "analog"
voltage supplying analog circuits of the readout chip,
and Vdd, "digital" voltage supplying digital part of the
ABCD3T chip, as well as electronics for the optical
links (DORIC4 and VDC ASICs). These two voltages
should provide relatively high currents of the order of
1A. Their load may, in addition, vary over a wide
range.
Low voltage power supply channel should also provide
several low power voltages and control signals: bias
voltage for the photodiode, control voltage for VDC
ASIC, voltage (two current sources) for the temperature
monitoring, module reset and clock select signals.
Nominal values for voltages and signal levels with
typical and maximal loads are listed in Table 1. The
inclusion of these extra power and control signals, as
well as the temperature readout mentioned in section G
below, in the low voltage supply channel is to insure a
common reference potential for all electrical signals on
the detector module. This minimises the possibility for
electrical pick−up or extraneous noise.
Table 1: LV Power Requirements
Name Nominal
value [V]
Current
[mA]
Max.
Current
[mA]
Vcc 3.5 900 1300
Vdd 4.0 570 1300
VCSEL 1.6 − 6.6 6 8
PIN bias 10.0 0.5 1.1
Current
source 0
Current
Source 1
Max. 8.0 0.08
Max. 8.0 0.08
RESET Vdd/−0.7 0.4
SELECT Vdd/−0.7 1.3
These main requirements, together with others referring
to voltage setting resolutions, voltage and current
monitoring accuracy, over voltage and over current trip
limits and maximum output ripple, lead to specifications
for LV power supplies which have recently been fixed
[2].
C. HV requirements
Bias voltage power supplies should provide stable,
digitally controlled voltage in 0 − 500 V range and
precise measurement of the output current in 40 nA −5
mA range. One should be able to set the current trip
limit individually for each channel in range from
hundreds nA to 5 mA as well as select one of the
predefined voltage ramping rates: 50, 20, 10, 5 V/s. It is
also required that the maximum allowable noise level is
not higher than 40 mV peak to peak[3].
D. Basic block characteristics
Several low voltage modules are grouped onto one board
equipped with the board micro−controller. The low
multi−voltage power module[4] consists of separate
floating supplies for analog and digital voltages. Each
module is controlled and monitored by its own micro−
controller which receives commands and receives or
transmits data to/from the board micro−controller.
The HV power module has very similar structure and
similar basic components: rectifier, filter, regulator,
error amplifier, DAC and ADC.
Two voltages of a relatively high current, Vcc and Vdd,
differ from others by using sense wires. This is
necessary for the considerable resistance of each
transmission line and hence the considerable voltage
variation at the module side in response to variations of
the current draw. Analog data from sense wires is
converted to digital and processed by the channel
micro−controller for the appropriate output voltage
adjustment.
LV and HV channels are powered from the 48V, 48 kHz
square wave generators. An isolation of individual
channels and individual voltages is realised by HF
transformers on the power path and by optical couplers
on communication lines.
More details concerning design and performance of
prototypes of the LV power supply modules are in ref.
[4]. HV power supply module design has been
presented in the Proceedings of the previous, 6−th
Workshop on Electronics for the LHC Experiments [5].
E. LV/HV integration
Low and high voltage power supplies form together one
system. Multi−channel LV and HV 6U cards are
integrated in common 19’’ EURO crate equipped with
the custom back plane, the crate controller, the interlock
card, and a common power pack. One crate will house
48 SCT power supply multi−voltage channels mounted
on 12 LV cards, 4 channels each, and on 6 HV cards,
each containing 8 channels.
All cards in one crate are supplied from the crate 1.6 kW
power pack which provides 48V, 48 kHz square wave

for HF transformers and DC supply for the commercial
crate controller as well as for all card controllers.
All SCT LV power supply cards are identical.
Similarly, there is full interchangeability between HV
power supply cards. The card address and consequently
the channel address is determined from the card position
in the crate. The custom back plane design predefines
positions for LV and HV cards. The mechanical
construction prevents card misplacement.
It has been decided to use commercial crate controller
which communicates within the crate with the eighteen
card controllers via parallel 8−bit bus. This
communication is serviced by a simple and efficient
custom made protocol.
The crate controller is equipped with the CAN bus
interface for communication with the higher levels of
the Detector Control System.
Custom back plane bears on the back side special 48
connectors for the multi−wire cables which connect
power supply modules with the first patch panel (PP3)
on the way to detector modules. These connectors
(CONEC 17W5) have five thick pins allowing for
connection of four high cross section wires and another
wire with hv insulation. Twelve thin pins serve the rest
of low current lines (of which one is reserved for the
drain wire of the cable).
F. Location of power supplies
The choice of the power supplies location has important
implications on the power distribution system, discussed in
the next section, as well as on the power supply design and
specifications. For example, the maximum power path
length determines the maximum voltage drop and hence the
maximum output voltage which power supply must provide
to reach the nominal value at the detector side. Anticipating
some results of the following discussion it is worth to
mention here that the Vcc supply should be designed for the
maximum output voltage of 8.75 V and Vdd for 9.33 V to be
able to provide the nominal values on the detector module
side in the case of the maximum voltage drop (with 1 V
margin included)[2].
The standard location for the off−detector electronics is
in the cavern (named USA15) next to the detector hall. For
such location the length of the power path will be in range of
100 − 130 m. SCT plans to locate 50% of its power supply
crates in another cavern, on the other side of ATLAS
detector (named US15). This will shorten the path length by
30 − 40 m for that part of modules, making the longest path
about 100m.
II. POWER DISTRIBUTION FOR THE ATLAS SCT
About 23 kW are needed for the normal operation of the
ATLAS SCT. The delivery of that power to the inner part of
the Inner Detector can not be done without extra material,
more power dissipation, space for services, cost etc. In the
following short review we will concentrate on a group of
requirements which mostly concern high current lines for
Vcc and Vdd voltages. Grounding and shielding problems,
which are very important for the system of thousands of
wires distributed over large surfaces, are discussed elsewhere
[6].
G. List of lines
In the following list the first four lines, out of all
seventeen, should have considerably larger cross section to
conduct high current, 1.3 A maximum. All other lines can
practically use as thin conductor as technologically possible.
1. Vdd − digital voltage
2. DGND − digital ground
3. Vcc − analog voltage
4. AGND − analog ground
5. HV − bias voltage
6. Hvgnd
7. Vddsense
8. DGNDsense
9. Vccsense
10. AGNDsense
− bias ground
11. VCSEL − driver
12. SELECT − clock redundancy
13. RESET − clock
14. PIN − diode bias
15. TEMP1 − sensor
16. TEMP2
17. drain wire
− sensor
Several voltages (VCSEL, SELECT, RESET,
PIN.TEMP1, TEMP2) use the digital ground, DGND, as the
common return. In all present tests of SCT module
prototypes analog and digital grounds are directly connected.
AGNDsense and DGNDsense wires sense then the same
point but it has been agreed to keep both lines as the present
laboratory practice may not be continued in the final
installation.
H. Conflicting requirements
The design of the power delivery system for the detector
located in the innermost part of the ATLAS experimental
setup should satisfy several conflicting requirements. One
should minimise material, voltage drop, power dissipation
and costs. One should observe rules concerning the radiation
hardness of and flame resistance of materials used. The
design is also strongly influenced by the limited space for
services as well as by the foreseen assembly sequence.
An optimisation process has different priorities in
different regions of the detector. Consequently, it has been
decided to divide the power path between the SCT modules
and power supplies into four parts.

I. 4−fold way
Final design of the power distribution system for the
ATLAS SCT is in progress and is closely related to the
process of integration of all services.
1) Low mass tapes
In the innermost part material introduced by cables seems
to be the most critical parameter. This first part, from
detector modules to the first patch panel (PPB1 for the
barrel, PPF1 for end cap modules) located at the cryostat
wall, is served by low mass tapes [7]. These tapes are made
from 25 micron thick Kapton and 25 micron glue substrate
with 50 micron aluminium conductors covered by another
Kapton and glue layer of 25 micron. The width of conductor
lines as well as the space between conductors can −for
technological reasons −be made in steps of 0.5 mm. Our
four critical lines (for Vcc and Vdd) are chosen to be 4.5 mm
wide while all other lines have the minimal allowable width
of 0.5 mm. The length of these tapes is in range 0.7 − 1.6 m
for barrel modules and reaches about 3 m for some of end
cap modules. A contribution to the material budget is often
characterised by calculating a cumulative amount of material
in certain region of the detector and "dilute" it over some
characteristic surface. An example for 6 tapes serving one
barrel half stave averaged over the surface of one module
shows the material contribution of about 0.24% of Xo.
Total maximum power dissipated by low mass tapes is
estimated on about 3 kW. Maximum voltage drop for some
barrel tapes reaches 0.6V and for end cap tapes 1 V.
2) "Very thin" cables
It is estimated[8] that the distance from the PPB1 (barrel)
to the next patch panel PP2 should not exceed 9 m and
the corresponding one for the end cap (PPF1 − PP2) 5 m.
Final numbers depend on the PP2 location and details of
routing, subject of the decision of the ID coordination.
We have originally planed to use Al on Kapton tapes also
for this part, but with the conductor thickness increased
to 100 micron. As the maximum allowable voltage drop
become the most critical parameter it has been decided to
use the copper conductors.
Maximum allowable voltage drop requires special
attention because if it exceeds certain limit then, in case
of a sudden loss of load, the safe limit of 5.5 V for the
readout chip is exceeded.
It is planned to use the multi−wire round cable of 6 mm
outer diameter, with a thin Kapton insulation and with
the four high current lines of 0.6 mm 2
. With such choice
the maximum voltage drop will not exceed 1.6 V for Vcc
or 1.4 for Vdd what is safe providing that the some
voltage limiters are installed on the PP2. These limiters
seem to be unavoidable since another 2V drop has still to
be considered for the rest of the power path.
3) Thin conventional cables
For the part which extends from patch panels PP2 and
PP3 of length of about 20 m it is planned to use multi−
wire "conventional" cable[8] with somewhat complicated
geometry taking into an account the requirement of
twisting wires in groups belonging to the same voltage
(e.g. Vcc, AGND, Vccsense and AGNDsense). With
such requirement the cable outer diameter is about 12
mm with the cross section of our four critical lines equal
1mm 2
. Maximum voltage drop for that part is estimated
on 1.3 V.
4) Thick conventional cables
The distance from PP3 to power supply crates depends on
the final location of PS racks. ATLAS SCT considers
use of two locations in caverns on both sides of the
detector hall. That will considerably shorten the path for
thick conventional cables, and hence reduce power
dissipation, cost etc. The multi−wire cable[8] with the
geometry similar to the thin conventional cable will have
the four critical lines with the 4 mm 2
cross section and
the outer diameter of about 20 mm. The estimated
maximum voltage drop equals about 1V.
J. Final remarks
The power distribution system for the ATLAS SCT is in
the development state. Several elements require final
design and tests. In particular:
� final construction and location of patch panels as
well as final details of routing of cables. This
�
depends strongly on the overall process of
integration with other subsystem and involves
some coordination on the level of the Inner
Detector
full power dissipation by cables in all four
regions is estimated on 10 kW (for nominal
currents and maximal cable lengths)[8]. To
satisfy the "rule of thermal neutrality" of each
subdetector one has to find solution for the cable
cooling in some regions
� total voltage drop along power lines
�
considerably exceeds the safety limit for the
readout ASICs and some voltage limiters have to
be installed in the region of PP2. An appropriate
voltage limiter circuit has been designed for PP2
and is now undergoing system and radiation
testing
PP3 is being designed with common−mode
inductors to filter unwanted pick−up from the
long cable runs from the power supplies.
Prototypes have been tested in the system test
and have been shown to be quite beneficial.
III. REFERENCES
1. ATLAS Inner Detector TDR Volume 2
CERN/LHCC/97−17 p 385

2. J.Bohm, SCT Week Prague 25 − 29 June 2001
http://atlas.web.cern.ch/Atlas/GROUPS/INNER
_DETECTOR/SCT/sct_meetings.html
3. http://www.ifj.edu.pl/ATLAS/sct/scthv/
4. http://www−hep.fzu.cz/Atlas/WorkingGroups/
Projects/MSGC.html
5. P.Malecki. Multichannel System of Fully
Isolated HV Power Supplies or Silicon Strip
Detectors, 6−th Workshop on Electronics for
LHC Experiments. CERN/LHCC/2000−041.
p.376
6. Ned Spencer. ATLAS SCT/Pixel Grounding
and Shielding Note. Nov 22. 1999. UCSC.
EDMS Id:108383, Number ATL−IC−EN−0004
v.1
7. http://merlot.ijs.si/~cindro/low_mass.html
http://www−f9.ijs.si/atlas/
8. H.Pernegger.Services in:
http://perneg.home.cern.ch/perneg/

Conductive Cooling of SDD and SSD Front-End Chips for ALICE
A.van den Brink 1 ,S.Coli 2 ,F.Daudo 2 ,G.Feofilov 3 , O.Godisov 4 , G.Giraudo 2 ,S.Igolkin 4 ,
P.Kuijer 5 ,G.J.Nooren 5 ,A.Swichev 4 ,F.Tosello 2
1 Utrecht University, Netherlands
2 INFN, Torino,Italy
3 St.Petersburg, Russia, Institute for Physics of St.Petersburg State University
Ulyanovskaya,1, 198904, Petrodvorets, St.Petersburg, Russia, e-mail: feofilov@hiex.niif.spb.su
4 CKBM, St.Petersburg, Russia
5 NIKHEF, Amsterdam, Netherlands
Abstract
We present analysis, technology developments and test
results of the heat drain system of the SDD and SSD frontend
electronics for the ALICE Inner Tracker System (ITS).
Application of super thermoconductive carbon fibre thin
plates provides a practical solution for the development
of miniature motherboards for the FEE chips situated inside
the sensitive ITS volume. Unidirectional carbon fibre
motherboards of 160 -300 micron thickness ensure the
mounting of the FEE chips and an efficient heat sink to
the cooling arteries. Thermal conductivity up to 1.3 times
better than copper is achieved while preserving a negligible
multiple scattering contribution by the material (less
than 0.15 percent of X/Xo).
I. INTRODUCTION
The state-of-the art Front-end electronics (FEE) for
the coordinate-sensitive Si detectors of the ALICE Inner
Tracking System(ITS)[1] at the LHC is situated inside the
sensitive region. Therefore the heat drain of about 7kW
of power is to be done under the stringent requirement of
minimisation of any materials placed in this area containing
6 layers of coordinate-sensitive detectors. A maximum
of 0.3% of X/Xo per layer is allowed for all services including
detectors, mechanics support, cables, cooling and electronics
units. Analysis of various possible cooling schemes
was performed earlier as a starting point of the general
ITS services design [2],[3]. Solution of the local heat drain
problem from the FEE to the cooling ducts was named
as the key point in the thermal performance of the whole
ALICE ITS. The application of super thermoconductive
carbon fibre plastics was proposed in order to get the
most efficient integration of the extremely lightweight FEE
motherboards and local heat sink units. The implementation
of these ideas in a single unit called ”the heat bridge”
required the development of a new technology of thin unidirectional
carbon fibre plates manufacturing. This technology
was successfully developed and is improved further
(For the ALICE colaboration)
at present. We describe below the results of the development
and tests of the heat bridges for SDD and SSD
front-end hybrid electronics.
II. CARBON FIBRE MOTHERBOARDS
Novel carbon fibre compound motherboards of efficient
thermal conductivity (heat bridges) were proposed for the
ITS FEE chips after the analysis of the existing materials,
see Table1.
Table 1: Parameters of different materials for thermoconductive
motherboards
Material Young’s Thermal Rad.
modulus, Conductivity, Length
E,[GPa] [W/mK] Xo,[cm]
Copper 125 380 1.43
AlN 150 9
CF comp. 450 300-500 18
The application of super thermoconductive fibre Thornell
KX1100 for the manufacturing of very thin mechanically
stable plates with good thermal properties used both
for the FEE support and for efficient heat drain to the
cooling arteries was found to be the optimal solution to
the problem. The conductivity along the fibre is about
1100W/mK, while the mechanical strength is ensured at
the level of steel (E=450GPa). Carbon fibers (CF) have
a diameter of about 80 microns and are packed in unidirectional
flat sheets (prepregs) impregnated with some
compound material (about 35% for the last one). The
thermal expansion coefficient of the carbon fibre based
compounds is very low (close to zero), resulting in mechanically
stable devices. Other properties of CF compounds
measured in the present application are: density
ρ =2.2 g/cm 3 , electric conductivity 5 Ohm/m, thermal
conductivityλ = 500W/mK along the fibre,λ =40W/mK
perpendicular to the fibre.
The technological problems of making flat thin car-

on fibre composite plates (150-330 microns thickness, dimensions
up to 10 · 10cm 2 ) were studied and successfully
overcome[4], providing various options for the manufacturing
of heat drain devices in line with the technical requirements
of the Alice experiment. The programme included
the design and optimization of the unidirectional
fibre plates, ANSYS simulations and test analysis and the
optimisation of the technology for the baking of plates
with the surface quality and flatness, suitable for further
chip mounting and bonding of microcables.
Figure 1: Foto of the SSD heat bridge prepared for studying
the temperature distribution along the bridge. Thickness 320
microns, length 70mm. Thermal conductivity 300W/mK. The
heat bridge is mounted with two triangular carbon fiber cooling
arteries. The heater (representing dummy chips) is glued
below the bridge.
Various types of surface coatings were also developed
and tested: pure carbon fibre surfaces and insulating Al203
ceramic coatings.
The bridges are used as hybrid motherboards for the
FEE and ensure mounting of the chips, bonding the microcables,
fixation of the assembled modules to the cooling
artery. Miniature heat transfer clips for two types of
bridges are also foreseen. Each bridge is formed by unidirectional
layers of super thermoconductive carbon fibre.
The minimum number of CF layers that could be applied
is 2, resulting in a minimum thickness of 150 µm forthe
board.
The flat carbon unidirectional fibre plates were manufactured
ranging in thickness from 150 to 330µm microns
in order to get data on the new material conductivity and
other parameters.
A summary of the different configurations of heat
bridges produced is presented in Table . Different numbers
of CF layers were used in the manufacturing of these test
samples. Also some different orientations of the carbon
fibres were tested along with various tubes and tube-tobridge
contacts.
The experimental setup used for the multichannel temperature
map cooling studies is described in [4].
In Fig. 1 the CF heat bridge (coated with Al203) connected
to two triangular shape cooling tubes, in preparation
for heat drain studies, is shown. The front-end
electronics was simulated by minuature dummy chips producing
up to 2W of power. Five uniformly spaced temperatures
sensors along the 70mm heat bridges were used
in case a single-end cooling. We used only one half of the
carbon fibre bridge in our data sampling in the case of one
central tube or two cooling tubes spaced by 45mm due to
the symmetry. Tests were compared with a copper bridge
of the same geometry (Length =70mm, width =10.5mm).
Table 2: Types of different heat bridges and cooling arteries used in the 1st studies (see Fig.2).
Heat Bridge Material CF layers: Comments
Thickness,mm Longitudinal(L)+Perpendicular(P)
1 Copper, 0.47 one sided cooling, soldered contact
2 CF, 0.56 4L-3P one sided cooling
3 CF, 0.32 2L-4P central tube location,rectangular
4 CF, 0,32 2L-4P central tube location, circular
5 CF, 0.32 2L-4P central tube location
6 CF, 0.32 4L-3P 2 side circular tubes
7 CF, 0.56 4L-3P 2 side triangular tubes
8 CF, 0.56 4L-3P 2 side triangular tubes
9 CF, 0.37 4L 2 side triangular tubes

Tx-Tin, deg.C
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��
��
��
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� �� �� �� �� �� �� ��
X, [mm]
Figure 2: Temperature distributions along the tested heat
bridges obtained under 2 W heat load (except samples No.1
and 2 tested under 1W load). Copper bridge No.1 (see Table
2) has an ideal (soldered) contact with the cooling tube fixed
toonesideendofthebridge.
A summary of temperature distributions measured
along the length of the different heat bridges is shown
in Fig.2. One can see that the performance of the carbon
fibre bridges is better than that of the copper bridge
(e.g. dataset (No.9) Fig.2 for a completely unidirectional
orientation of fibres in the heat bridge).
1. The mean value of thermoconductivity for samples
No. 2,6,7,8,9 was measured to be about 300-310 W/mK
(i.e. about 0.78-0.8 of the value for Cu (λ=380W/mK).
2. The mean value of thermoconductivity for the samples
No. 3,4,5 (v-shaped, variable cross- section) is about
470-505 W/mK (i.e. about 1.2-1.3 of the Cu).
3. The value of contact temperature resistance for carbon
fibre bridges connected to the cooling artery could be
about 4.4-5.8deg.C for 1 W heating power.
4. Maximum temperature gradients of 0.6-0.7 deg.C
could be obtained along 70 mm carbon fibre bridge with
two cooling channels.
These data on the properties of different CF compounds
were used for the ANSYS simulations of the temperature
maps and for the further SDD and SSD cooling
scheme and technology optimization.
III. SURFACE QUALITY TESTS
The carbon fibre heat bridge surface quality tests were
done for three batches of CF plates consisting of 12,19
and 19 samples. Plates of about 170 microns thickness
had the dimensions of 72mm*6.5mm and were designed
as SSD heat bridges. Measurements of carbon fibre heat
bridges surface quality was done for 3 test batches. The
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�
�
�
�
�
�
�
roughness of the surface was measured and found to be
better than 10 microns for pure carbon fibre composite
bridges. This parameter was found to be satisfactory and
enabled to approve this technology for application in minuature
motherboards manufacturing for ALICE SDD and
SSD FEE chips.
IV. ANSYS SIMULATIONS
ANSYS simulations were done to optimise the heat
bridge layout, in particular the direction of fibres and the
location of the heat transfer clip.
Figure 3: ANSYS simulations of the carbon fibre SDD heat
bridge temperature map for the undirectional fibre orientation.
Position of the thermoconductive clip is optimised
Figure 4: ANSYS simulations of the carbon fibre SDD
heat bridge temperature map for the uniform conductivity
180W/(mK)
Some examples of simulations are represented in Fig-

ures 3 and 4 (only one half of the hybrid is shown due
to the heat dissipation symmetry). The geometry of the
SDD heat bridge used was in line with the requirements to
place FFE 4 Pascal and 4 Ambra SDD chips to serve one
half of SDD (see Figure5). Electronics chips were placed
in groups of 4 + 4 chips on one side of the heat bridge. The
total power load for one bridge was assumed to be 1.775
W, the heat release is proportional to the chip’s area (8
chips 8x8 mm and 8 chips 5x5 mm were used). The following
conductivity values were used in calculations for
carbon fibre composite:
for the panel in longitudinal direction- 300 W/(mK),
in transversal direction- 0.7 W/(m K);
for the clip in longitudinal direction - 150 W/(mK), in
transverse direction - 40.0 W/(m K).
(Longitudinal here means the direction of heat drain to
the cooling artery, i.e. perpendicular to the cooling tube).
Cooling by water and by neutral ozon-safe freon coming
at 13.0 o C as a coolant liquid were studied. The cooling
artery is a tube diameter 2mm made of stainless steel. The
influence of natural convection was neglected. The nominal
value of the heat transfer coefficient from liquid to the
tube wall was assumed to be equal 3000 W/(m 2 · K). Calculations
were done using ANSYS code. Results of these
calculations are presented in Figures 3 and4. Tests of the
unidirectional fibre heat bridge (Fig. 3) show that an operational
temperature at the surface of the FEE chip at
the level of 25 o C is obtained. This value is close to the
requirements for the SDD FEE.
A further decrease of the operational temperature
down to 20oC can be obtained by adding additional conductivity
to the transverse direction, see Fig.4.
The following conclusions can be drawn from ANSYS
simulations:
1. The maximum temperature drop between the
coolant and chips of 3-4 layer ITS is about 12oC using
the optimal position of the cooling tube and using the
unidirectional fibre orientation.
2. The value of the heat transfer coefficient from
coolant to the tube’s wall is an essential factor for the
temperature level (this factor depends on the liquid flow
regime).
3. A noticeable decrease of temperature gradients for
the SDD heat bridge is possible in using composites with
higher transversal heat conductivity.
V. SDDHEAT BRIDGES
A side view of the heat bridge for the drift detector
front-end electronics (Ambra and Pascal chips) is shown
in Figure 5. It consists of 2 main elements : (i) the cooling
panel (ii) the heat conducting clip on the panel.
Figure 5: SDD CF motherboard with chips, Side view: CF
-carbon fibre motherboard; C1,C2 - FEE SDD chips (Ambra
and Pascal); D1=2mm,D=1,9mm;H=240microns. Length of
the CF SDD board =65mm, width=20mm
The cooling panel is a flat plate 20x65 mm, 0.18mm
thick. It is made of heat-conducting C.F. THORNEL and
of 1 additional layer of ordinary carbon fiber. The panel’s
area is large enough to place the chips of the primary electronics.
The measured value of the heat conductivity in
the direction of the fibre is λ=400 W/mK. The panel’s clip
is also made of THORNEL. The orientation of the layers
is -+ 45 o . The heat conductivity is λ= 150 W/mK. The
panel’s clip plays the following role in this structure :
(i) fixation of the heat bridge on the cooling artery;
(ii) it is an element of the heat transfer from the cooling
panel to the cooling artery;
(iii) it is an element of stiffness for the heat bridge .
Test were performed for the SDD carbon fiber composite
hybrid with dummy electronics with a heat load of 2 W,
temperature gradients reached 8degrees (this corresponds
to approximately 22 degree operational temperature at the
surface of the chip when using a cooling liquid at 14 o C.
).
VI. SSD HEAT BRIDGES
There should be 6 chips of the front-end electronics per
one SSD detector side with an area of 6*8mm 2 and 300
micron thickness. The new SSD HAL25 chips are expected
to produce about 0.3 W power per SSD hybrid.
The pecularity of the double sided silicon-strip detectors
(ALICE SSD) is in the orientation of the coordinatesensitive
elements (strips) almost parallel the ITS axis .
Therefore the readout electronics is situated perpendicular
to the latter. The problem of the heat drain from this
electronics was suggested to be solved by conductive cooling
using the available highly thermoconductive materials
draining heat to the longitudinal cooling arteries.
The most recent option for the heat bridge has dimensions
(73x6.5x0.16mm 3 ). It has a unidirectional orientation
of 2 layers of THORNELL providing efficient heat
transfer supported by an additional thin (20µm) carbon
fiber layer with a transverse orientation.
The prototype SSD heat bridges were sucsessfully
tested for mounting of chips and microcable bonding technology
(see Fig.6).
������������������������������������������� ���������

Figure 6: Foto of the SDD detector for ALICE ITS equipped with real CF hybrids with chips and microcables mounted
VII. CONCLUSIONS
A novel technology for the design and manufacturing
of carbon fibre composite materials with required thermal
and mechanical characteristics is developed and tested for
application as miniature motherborads for microelectronics.
Acknowledgements: authors are grateful to
L.Abramova, V.Brzhezinski and M.Van’chkova from
Mendeleev Institute for Metrology (St.Petersburg) for
the heat bridges surface quality checks. This job was
partially supported for Russian participants by the ISTC
grants No345 and No1666, and by the Ministry of High
Education of Russian Federation grant No.520.
References
[1] ALICE ITS Technical Design Report,
CERN/LHCC,1999.
[2] G.A. Feofilov et al., 1994, ”Inner Tracking System
for ALICE: Conceptual Design of Mechanics, Cooling
and Alignment”, CERN, Workshop on Advanced
Materials for High Precision Detectors, Sept. 1994,
73-81.
[3] O.N.Godisov et al., ”Concept of the Cooling System
of the ITS for ALICE”, Proceedeings of the
1st Workshop on Electroncs and Detector Cooling”
(WELDEC), Lausanne, Oct.1994
[4] ”ITS-CMA for ALICE: Preliminary Technical
Design Report” , ISTC No345 Final Report,Ed.G.Feofilov,.
St. Petersburg, February, 1999.
(http://www.cern.ch/Alice/projects.html)

Sorting Devices for the CSC Muon Trigger System at CMS
Abstract
The electronics system of the Cathode Strip
Chamber (CSC) muon detector at the CMS
experiment needs to acquire precise muon
position and timing information and generate
muon trigger primitives for the Level-1 trigger
system. CSC trigger primitives (called Local
Charged Tracks, LCT) are formed by anode
(ALCT) and cathode (CLCT) cards [1]. ALCT
cards are mounted on chambers, while CLCT
cards are combined with the Trigger
Motherboards (TMB) that perform a time
coincidence of ALCT and CLCT. Every
combined CLCT/TMB card (one per chamber)
transmits two best combined muon tags to the
Muon Port Card (MPC) which serves one CSC
sector (8 or 9 chambers). The MPC selects the
three best muons out of 18 possible and sends
them over 100 m of optical cable to the Track
Finder (TF) crate residing in the underground
counting room In the current electronics layout
the TF crate has 12 Sector Processors (SP), each
of which receives the optical streams from
several MPC. The SP measures the transverse
momentum, pseudo-rapidity and azimuthal angle
of each muon and sends its data (up to 3 muons
each) to the CSC Muon Sorter (MS) that resides
in the middle of the TF crate. The MS selects
the four best muons out of 36 possible and
transmits them to Global Muon Trigger (GMT)
crate for further processing.
Data sorting is the primary task of two
devices in the CSC trigger chain: the MPC (“3
best muons out of 18”) and MS (“4 best muons
out of 36”). The total data reduction factor is 54.
We propose a common approach to
implementation of sorting logic and board
construction for both the MPC and MS. They
will be based on a single chip programmable
logic devices that receive data from the
previous trigger level, sort it and transmit the
sorting result to the next trigger level.
Programmable chips will incorporate input and
output FIFO buffers that would represent all
possible inputs and outputs for testing and
Matveev M., Padley P.
Rice University, Houston, TX 77005 USA
matveev@physics.rice.edu
debugging purposes. Finally we will use a
common sorting scheme [2] for both designs.
The MPC and MS functionality as well as the
first results of logic simulation and latency
estimates are presented.
I. MUON PORT CARD
In each of stations 2-4 of the CSC detector,
an MPC receives trigger primitives from nine
chambers corresponding to 60 degree sectors.
Each MPC in these regions reduces the number
of LCTs to three and sends them to the TF crate
over optical cables. In station 1, an MPC
receives signals from eight chambers
corresponding to 20 degree sector. For these
regions the number of selected LCTs is two. So
the main sorting algorithm for an MPC is “3 best
objects out of 18” while a “2 best objects out of
16” algorithm can be easily implemented as a
subset of the main one.
Muon Port Cards will reside in the middle
of 21-slot 9U*400 mm VME crates located on
the periphery of the return yoke of the CMS
detector. Other slots in a crate will be occupied
by the TMB boards (9 or 8 total), DAQ
Motherboards (9 or 8 total), Clock and Control
Board and VME Master. The CCB is the main
interface to CMS Trigger, Timing and Control
(TTC) system. The VME Master performs the
overall crate monitoring and control. All
trigger/DAQ modules in a crate will
communicate with each other over a custom
backplane residing below a VME P1 backplane.
Every bunch crossing (25 ns) an MPC will
receive data from up to 9 TMB’s, each of which
is sending up to two LCT patterns. In the present
design each LCT pattern is comprised of 32 bits
(see Table 1). Data transmission from the TMB
to the MPC at 80MHz would allow us to reduce
the number of physical lines between the MPC
and nine TMB’s down to 288 and build a 6U
backplane using industry standard 2 mm
connectors. The MPC block diagram is shown
on Figure 1. It performs a synchronization of
incoming patterns with the local master

clock, sorting “3 out of 18” and output
multiplexing of the selected patterns. The three
best patterns are transmitted at 80Mhz to three
16-bit serializers that perform a parallel-to-serial
data conversion with 8B/10B decoding for
further transmission over optical cables to SP.
The proposed serializer is a Texas Instrument
TLK2501, and proposed optical module is a
small form factor Finisar FTRJ-9519-1-2.5
transceiver [3].
The block diagram of the PLD is shown on
Figure 2. Sorting is based on a 4-bit pattern
which is a subset of the 9-bit quality code (Table
1). All 256-word deep FIFO buffers are
available for read and write operations from
VME. Data representing all input muons can be
loaded into the input FIFO and sent out of FIFO
at 80Mhz upon a specific VME command. The
selected patterns will be stored in the output
FIFO and transmitted to SP. Patterns coming
from the TMB can also be stored in an output
FIFO. This feature will allow us to test the MPC
3 OPTICAL
CABLES TO
SECTOR
PROCESSOR
OPTICAL
TRANSCEIVERS
SERIALIZERS
9U * 400 MM BOARD
OPTO
OPTO
OPTO
SER
SER
SER
SORTER
LOGIC
CCB
INTERFACE
FIFO
BIFFERS
VME
INTERFACE
CCB
TMB_1
TMB_2
TMB_3
TMB_4
TMB_5
TMB_6
TMB_7
TMB_8
TMB_9
Figure 1: MPC Block Diagram
II. MUON SORTER
VME J1
CONNECTOR
CUSTOM
PERIPHERAL
BACKPLANE
Twelve SP’s and one MS will reside in a
single VME 9U*400 mm crate in the
underground counting room. In addition to these
modules there will be a Clock and Control Board
(CCB) similar to a peripheral CCB, and a VME
Master. Every bunch crossing an MS will
receive data from 12 SP’s, each of which is
sending up to three patterns. Data transmission
at 80MHz from the Sector Processors to the MS
is envisaged; this would allow us to reduce the
number of physical lines between MS and 12
SP’s down to 360 and build a custom backplane
functionality and its communications with the
TMB and SP without having the rest of trigger
chain hardware.
Table 1: MPC Inputs and Outputs
Signal Bits per
input
muon
Bits per
output
muon
Valid Pattern Flag 1 1
Quality 9 9
Cathode ½-strip ID 8 8
Anode
ID
Wire-Group 7 7
Accelerator Muon 1 1
Bunch Crossing ID 2 2
Reserved 4 -
CSC ID - 4
Total 32 32
TMB 1
TMB 2
TMB 9
VME
CCB
VME
VME
DFF
FIFO
A
DFF
FIFO
A
CCB INTERFACE
MUX
MUX
SORTER “3 OUT OF 18”
4
4
PIPELINE
MUON 1
PIPELINE
MUON 2
54
MUX
DFF
FIFO_B
MUON
1
DFF
VME
MUON 1
MUON 2
FIFO_B
MUON
2
VME
DFF
MUON 3
FIFO_B
MUON
3
VME
Figure 2: MPC Sorter PLD Block Diagram
using industry standard 5-row 2 mm connectors.
Four such a 125-pin connectors are needed on a
MS station in the middle of the custom 6U
backplane residing below standard VME
backplane.
The MS block diagram is shown on Figure 3.
Its inputs and outputs listed in Table 2 are
described in more details in [4]. Sorting is based
on a 7-bit rank which represents the quality of
each muon. The larger the rank, the better the
muon for the sorting purpose. The MS performs
synchronization of the incoming patterns with
the local master clock, sorting “4 out of 36” and
output multiplexing of the selected four patterns.

In addition to that, the MS performs a partial
output LUT conversion to comply with the
GMT input data format [5]. Parallel data
transmission from the MS to the GMT at 40Mhz
using LVDS drivers/receivers and separate
cables for each muon was proposed by the GMT
group. The Muon Sorter also utilizes the same
idea used in the MPC of 256-word deep input
and output FIFO buffers for testing purposes.
The list of input and output signals is given in
Table 2. A block diagram of the Muon Sorter
main PLD is shown on Figure 4.
Table 2: Muon Sorter Inputs and Outputs
Inputs from Sector Processor Outputs to Global Muon Trigger
Signal Bits per Bits per
Signal Bits per Bits per
one muon three muons
one muon four muons
Valid Pattern Flag 1 3 Valid Pattern Flag 1 4
Phi Coordinate 5 15 Phi Coordinate 8 32
Muon Sign 1 3 Muon Sign 1 4
Eta Coordinate 5 15 Eta Coordinate 6 24
Rank 7 21 Quality 3 12
Bunch Crossing ID - 2 Pt Momentum 5 20
Error - 1 Bunch Crossing ID 4 16
Error 1 4
Clock 1 4
Reserved 2 8
Total 19 60 Total 32 128
GMT LVDS DRIVERS
CONNECTORS TO GMT
CABLES TO
GLOBAL MUON
TRIGGER CRATE
9U * 400 MM BOARD
SORTER
LOGIC
CCB
INTERFACE
FIFO
BUFFERS
VME
INTERFACE
CCB
SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
VME J1
CONNECTOR
CUSTOM
BACKPLANE
Figure 3: Muon Sorter Block Diagram
III. RESULTS OF SIMULATION
PLD designs are implemented for the Altera
20KC family of PLD [6] using Quartus II ver.
1.0 design software. Preliminary results of logic
simulation are shown in Table 3. They are
obtained for the fastest available devices (-7
speed grade). We assume that the actual PLD
latency means the time interval between the
latching of the input patterns into the sorter chip
at 80MHz and the moment when the selected
best patterns are available for latching into the
SP 1
.
SP 2
SP 12
VME
CCB
DFF
VME
FIFO
DFF
VME
FIFO
DFF
VME
FIFO
. . .
MUX
MUX
SORTER “4 OUT OF 36”
CCB INTERFACE
PIPELINE
MUON 1
PIPELINE
MUON 2
MUX PIPELINE
MUON 3
144
MUX
LUTs
VME
LUTs
VME
LUTs
VME
LUTs
VME
VME
VME
VME
VME
DFF
FIFO
DFF
FIFO
DFF
FIFO
DFF
FIFO
MUON 1
MUON 2
MUON 3
MUON 4
Figure 4: Muon Sorter PLD Block Diagram
external device outside the sorter chip. Board
latency for the MPC includes a delay for the
output serialization. Particularly, for the TLK
2501 serializer this delay varies between 34 and
38 bit times, or 20..24 ns. For both devices an
extra board delay of ~15ns is assumed. It
includes the delay of the custom backplane
receivers, signal propagation times and the delay
of output LVDS drivers (for MS only).

Table 3: Results of Simulation
Muon Port Card Muon Sorter
Number of data inputs 288 @ 80 Mhz 384 @ 80 Mhz
Number of data outputs 48 @ 80 Mhz 128 @ 40 Mhz
Number of bits used for sorting 4 7
Altera PLD Device EP20K400CF672C7 EP20K1000CF33-7
Number of logic cells (LC) used 9637/16640 (57%) 22716/38400 (59%)
Number of ESB bits used 184320/212992 (86%) 262144/327680 (80%)
Actual PLD latency, nanoseconds 75 150
Board latency, nanoseconds 115 165
IV. CONCLUSION
We have proposed a common approach to
design and implementation of two sorting
devices for the CSC Muon Trigger system.
These designs are targeted tosingle
programmable chips for both Muon Port Card
and Muon Sorter. Results of preliminary
simulation for the fastest Altera PLD indicate a
maximum board latency of 115 ns for the Muon
Port Card and 165 ns for the Muon Sorter. The
MPC and MS prototypes are planned to be built
in 2002 and 2003 respectively.
V. REFERENCES
[1]. J. Hauser. Primitives for the CMS Cathode
Strip Muon Trigger. Proceedings of the Fifth
Workshop on Electronics for LHC Experiments.
Snowmass, Colorado September 20-24, 1999.
CERN/LHCC/99-33. Available at:
http://hep.physics.wisc.edu/LEB99/
[2]. M.Matveev. Implementation of the Sorting
Schemes in a Programmable Logic. Proceedings
of the Sixth Workshop on Electronics for LHC
Experiments. Krakow, Poland 11-15 September
2000. Available at:
http://lebwshop.home.cern.ch/lebwshop/LEB00_
Book/posters/matveev1.pdf
[3]. M.Matveev, T.Nussbaum, P.Padley. Optical
Link Evaluation for the CSC Muon Trigger at
CMS. These proceedings.
[4].The CMS TriDAS Project Technical Design
Report, Volume 1: The Trigger System. Chapter
12. Available at:
http://cmsdoc.cern.ch/cms/TDR/TRIGGERpublic/CMSTrigTDR.pdf
[5]. Proposal for a common data link from the
RPC, DT, CSC Regional Muon triggers to the
Global Muon Trigger vers.3a. Available at:
http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/gl
obalTrigger/Hardw/Interfaces/Input/Reg_to_GT
_Muon3.pdf
[6].http://www.altera.com/products/devices/apex
/apx-index.html

Optical Link Evaluation for the CSC Muon Trigger at CMS
M. Matveev 1 , T. Nussbaum 1 , P. Padley 1 , J. Roberts 1 , M. Tripathi 2
Abstract
The CMS Cathode Strip Chamber electronic
system consists of on-chamber mounted boards,
peripheral electronics in VME 9U crates, and a
track finder in the counting room [1]. The
Trigger Motherboard (TMB) matches the anode
and cathode tags called Local Charged Tracks
(LCT) and sends the two best combined LCT’s
from each chamber to the Muon Port Card
(MPC). Each MPC collects data representing
muon tags from up to nine TMB’s, which
corresponds to one sector of the CSC chambers.
All TMB’s and the MPC are located in the
9U*400 mm VME crates mounted on the
periphery of return yoke of the endcap muon
system. The MPC selects data representing the
three best muons and sends it over optical links
to the Sector Processor (SP) residing in the
underground counting room. The current
electronics layout assumes 60 MPC modules
residing in the 60 peripheral crates for both
muon endcaps and 12 SP’s residing in one 9U
VME crate in the counting room.
1 Rice University, Houston, TX 77005 USA
2 University of California, Davis, CA 95616 USA
Paper presented by M. Matveev
matveev@physics.rice.edu
Due to the high operating frequency of
40.08MHz and the 100 m cable run from the
detector to the counting room, an optical link is
the only choice for data transmission between
these systems. Our goal was to separately
prototype this optical link intended for the
communication between the MPC and SP using
existing commercial components. Our initial
design based on the Agilent HDMP-1022/1024
chipset and Methode MDX-19-4-1-T optical
transceivers was reported at the 6 th Workshop on
Electronics for LHC Experiments [2] a year ago.
Data transmission of 120 bits representing three
muons at 40 MHz would require as many as
twelve HDMP chipsets and 12 optical
transceivers on a single receiver card. This
solution has disadvantages such as relatively
large power consumption and component areas
on both the transmitter and receiver boards.
Studies of the later triggering stages also show
that a reduction in the number of bits
representing three muons can be made without
compromising the system performance. The new
list of bits is shown in Table 1.
Table 1: Data delivered from a Muon Port Card to Sector Processor
Signal Bits per 1 muon Bits per 3 muons Description
Valid Pattern Flag 1 3 “1” when data is valid
Half-strip ID [7..0] 8 24 ½ strip ID number
Quality [7..0] 8 24 ALCT+CLCT+ bend quality
Wire ID [6..0] 7 21 Wire group ID
Accelerator muon 1 3 Straight wire pattern
CSC ID [3..0] 4 12 Chamber ID in a sector
BXN [1..0] 2 6 2 LSB of BX number
Spare 1 3
Total 32 96
Now only three links rather than the six in
our previous design are needed for
communication between the Muon Port Card and
Sector Processor. Another improvement is to
serialize and deserialize the data at 80Mhz with a
lower power chipset and use small form factor
(SFF) optical modules for a more compact
design. Test results evaluating the Texas
Instruments TLK2501 [3] gigabit transceiver and
Finisar FTRJ-8519-1-2.5 [4] optical module as
well as the functionality of our evaluation board
are presented.

I. DATA SERIALIZER AND OPTICAL
MODULE
Among several high speed data serializers
available on the market, the Texas Instruments
TLK2501 [3] is one of the most attractive. It
performs both serial-to-parallel and parallel-toserial
data conversion. The transmitter latches
16-bit parallel data at a reference clock rate and
internally encodes it using a standard 8B/10B
format. The resulting 20-bit word is transmitted
differentially at 20 times the reference clock
frequency. The receiver section performs the
serial-to-parallel conversion on the input data,
synchronizes the resulting 20-bit wide parallel
word to the extracted reference clock and applies
the 8B/10B decoding. The 80MHz to 125MHz
frequency range for the reference clock allows us
to transfer data at 80.16Mhz which is exactly
double the LHC operation frequency of
40.08Mhz.
The TLK2501 transceiver has a built-in 8-bit
pseudo-random bit stream (PRBS) generator and
some other useful features such as a loss of
signal detection circuit and power down mode.
The device is powered from +2.5V and
consumes less than 325mW. Parallel data,
control and status pins are 3.3V compatible. The
TLK2501 is available in a 64-pin VQFP package
and characterized for operation from –40C to
+85C.
A Finisar FTRJ-8519-1-2.5 2x5 pinned SFF
transceiver was chosen for the optical
transmission. It provides bidirectional
communications at data rates up to 2.125Gbps
(1.6Gbps simplex mode transmission is required
in our case). The laser technology is an 850 nm
multimode VCSEL and allows fiber lengths up
to 300 m. The transceiver operates at extended
voltages (3.15V to 3.60V) and temperature (-10C
to +85C) ranges and dissipates less than 750mW.
One advantage of the FTRJ-8519-1-2.5 module
over similar optical transceivers available from
other vendors is a metal enclosure for lower
electromagnetic interference.
II. DESIGN IMPLEMENTATION
A simplified block diagram of the evaluation
board is shown on Figure 1. It consists of two
TLK2501 and Finisar optical transceiver links
with control logic based on an Altera
EP20K100EQC240 PLD. The PLD provides
VME access to the 16-bit transmitter and
receiver data busses as well as the control/status
signals of both TLK2501 devices. In addition to
the VME A24D16 slave interface, it contains:
256-word deep input and output FIFO buffers,
two delay buffers, a 16-bit PRBS generator, error
checking logic and 2 16-bit error counters. Since
the PRBS data is not really a random, but a
predetermined sequence of ones and zeroes, the
data could also be checked for errors by
comparison to an identical, synchronized PRBS
generator.
Finisar
FTRJ-8519
Finisar
FTRJ-8519
TLK
2501
TLK
2501
6U * 160 mm
PRBS
generator
Input FIFO
Output FIFO
Error
Counters
VME A24D16
Slave
Interface
Altera
EPF20K100E
VME
Figure 1: Evaluation Board Block Diagram
There are three modes of board operation. In
mode 1, every TLK2501 transmitter can
internally generate an 8-bit PRBS and send it to
either another TLK2501 receiver or loop it back
to its own receiver input. In mode 2, a 16-bit
PRBS is generated by the PLD for both
TLK2501 transmitters simultaneously. Two
variable depth buffers, adjustable from a front
panel, are used to delay the PRBS data inside the
PLD for comparison with the receiver data. The
main control PLD can count the number of errors
using two separate (for modes 1 and 2) 8-bit
counters which are accessible from VME. Error
counting can also be implemented and displayed
with an external event counter connected to the
Receive_Error output signal.
In mode 3, random programmable data (up to
256 16-bit words) can be loaded into a FIFO
buffer from VME and sent out as an 80Mhz
burst to both TLK2501 transmitter sections upon
a specific VME command. The data from both
receivers is then captured into two FIFO input
buffers which can be read from VME.

III. PROTOTYPING RESULTS
Two evaluation boards were built and tested
in spring 2001. All tests were done in simplex
configuration over 100 m optical cable. No
PRBS data errors occurred during 3 overnight
tests for both PRBS sources (modes 1 and 2).
Another part of our test was evaluation of the
latency due to data serialization/deserialization
and encoding. The datasheet [3] specifies that
the transmit latency is between 34 and 38 bit
times, and the receive latency is between 76 and
107 bit times. At 80Mhz these numbers
correspond to a link delay (excluding cable
delay) of 69 to 91 ns. Our measurements
conducted at room temperature and 2.5V power
for both TLK2501 devices indicated that the total
link latency is between 76 and 82 ns, or more
than three bunch crossings. While the exact
value is different at each link initialization in
increments of the serial bit clock (625 ps), it has
never varied by more than the 6 ns total.
The receive and transmit latencies are
essentially fixed once the link is established.
However, due to silicon process variations and
such implementation variables as supply voltage
and temperature, the exact delay may also vary
slightly. An additional offset of about 2ns was
seen when one chip was externally heated to a
point uncomfortable to the touch. One TLK2501
was socket mounted for investigation of chip-tochip
variations. No significant difference
between 6 chips has been seen.
A receiver reference clock is required on
power-up reset, but unlike the Agilent HDMP-
1024 receiver it does not need to be of a
frequency slightly different from the frame rate.
Automatic recovery from loss of synchronization
will require periodic transmission of the “Idle”
synch character. The resynchronization takes
only 2 frames rather than ~2ms required for the
Agilent HDMP-1022/1024 chipset.
IV. RADIATION TEST
The goal of the test was to determine how well
the TLK2500/TLK2501 serializers and Finisar
optical transceivers are able to tolerate the
radiation environment and the integrated dose
expected at LHC during 10 years of operation.
Specifically, the potential for Single Event
Latch-ups (SEL) and Single Event Upsets (SEU)
in these CMOS devices due to the high flux of
secondary neutrons is of concern.
Based on simulations reported in references
[5] and [6], the Total Ionizing Dose (TID) for the
inner CSC chambers during 10 years of
operation is below 10 kRad and the neutron
fluence (for E > 100 KeV) is below 10 12 cm -2 .
On the periphery of the return yoke (where
Muon Port Cards will be located) these numbers
are approximately one order in magnitude less.
The SEU cross-section is quite independent of
the neutron energy above about 100 MeV. While
the expected energy distribution at the LHC has
a sizable population below this level, we chose a
convenient beam energy of 63 MeV to simulate
the effect of the neutron environment at the
LHC. Since the strong interactions responsible
for the energy deposition are independent of the
baryon type, our tests were conducted with a 63
MeV proton beam at the Crocker Nuclear
Laboratory cyclotron at the University of
California, Davis (UCD).
During irradiation the optical evaluation board
was positioned perpendicular to the beam which
was focused to irradiate only one
TLK2500/TLK2501 chip or Finisar optical
module at a time. The board was set to transmit
PRBS data through 100 m of fiber to a second
board located outside the beam area where data
transmission errors due to Single Event Upsets
were counted. Three serializer chips were
exposed up to approximately 270 kRad total
dose each, with no permanent damage. No SEL
was detected.
At 63 MeV, 1 rad = 7.4x10 6 protons cm -2 for
silicon. Therefore, assuming strong isospin
symmetry for SEU's, 270 Krad is equivalent to
2.1x10 12 cm -2 neutron fluence or well above the
expected levels for the peripheral electronics.
The two TLK2501 devices produced 12 and 19
data errors due to SEUs while the older TLK
2500 device produced 78. These results are
summarized in Table 2. While no errors where
observed during the exposure of 2 Finisar optical
modules, both devices failed permanently at
about 70 kRad, also well above the expected
TID. Combining the results for the three chips,
no SEL was seen for a fluence of 6.0x10 12
protons cm -2 .

V. CONCLUSION
Table 2: Measured SEU Cross Sections for TLK2500/2501 serializers
Device Proton Fluence
(10 12 cm -2 Dosage Number of SEU Xsection
) (kRad) SEUs (10 -12 cm 2 )
TLK 2501 #1 1.8 230 12 6.7
TLK 2501 #2 2.1 270 19 9.0
TLK 2500 #1 2.1 260 78 37.1
We have built and tested, in a radiation
environment, an evaluation board that comprises
the two main elements of an optical data link: a
TLK2501 gigabit serializer/deserializer and a
Finisar FTRJ-8519-1-2.5 optical transceiver.
Acceptable data error rates were observed in
testing the link at 80MHz using 8/16-bit PRBS
test sequences and programmable patterns. We
believe the components of the link can be used
for the MPC and SP designs at the CSC Trigger
System. Our evaluation board itself can be used
as a source of test data for the next SP prototype.
VI. REFERENCES
[1]. The Track-Finding Processor for the Level-1
Trigger of the CMS Endcap System. CMS Note
1999/060. Available at:
ftp://cmsdoc.cern.ch/documents/99/note99_060.
pdf
[2]. Optical Data Transmission from the CMS
Cathode Strip Chamber Peripheral Trigger
Electronics to Sector Processor Crate. 6 th
Workshop on Electronics for LHC Experiments.
CERN/LHCC/2000-041. P483-485. Available at:
http://lebwshop.home.cern.ch/lebwshop/LEB00_
Book/posters/matveev2.pdf
[3]. TLK2501 1.6 to 2.5 Gbps transceiver.
Datasheet is available at: http://wwws.ti.com/sc/psheets/slls427a/slls427a.pdf
[4]. http://www.finisar.com/pdf/2x5sff-2gig.pdf
[5]. The Compact Muon Solenoid Technical
Proposal. CERN/LHCC 94-38. 15 December
1994.
[6]. http://cmsdoc.cern.ch/~huu/tut1.pdf

DISTRIBUTED MODLAR RT-SYSTEMS FOR DETECTOR
DAQ, TRIGGER AND CONTROL APPLICATIONS
Abstract
Modular approach to development of
Distributed Modular System Architecture for
Detector Control, Data Acquisition and Trigger
Data processing is proposed. Multilevel
parallel-pipeline Model of Data Acquisition,
Processing and Control is proposed and
discussed. Multiprocessor Architecture with
SCI-based Interconnections is proposed as
good high-performance System for parallelpipeline
Data Processing. Tradition Network
(Ethernet –100) can be used for Loading,
Monitoring and Diagnostic purposes
independent of basic Interconnections. The
Modular cPCI –based Structures with Highspeed
Modular Interconnections are proposed
for DAQ and Control Applications. Distributed
Control RT-Systems. To construct the
Effective (cost-performance) systems the same
platform of Intel compatible processor board
should be used.
Basic Computer Multiprocessor Nodes consist
of high-power PC MB (Industrial Computer
Systems), which interconnected by SCI
modules and link to embedded microprocessorbased
Sub-systems for Control Applications.
Required number of Multiprocessor Nodes
should be interconnected by SCI for Parallelpipeline
Data Processing in Real Time
(according to the Multilevel Model) and link to
RT-Systems for embedded Control.
Introduction
V.I.Vinogradov,
INR RAS, ul.Prophsoyusnaya 7-a,
Moscow, 117312, Russia,
vin@inr.troitsk.ru
RT-Multiprocessor Systems should have scalable
architecture for high-performance Data
Acquisition, Trigger Processing and reliable
Control in future
Experimental Physics. Multilevel Information
Data-Flow Model for
RT-Systems in Experimental Physics Including
DAQ, Trigger Data Processing and Control
Applications
are proposed and analysed. Modular
Multiprocessor System Architectures with Scalable
Open System (SOS) Architecture for System Area
Networks (SAN) is discussed.
Information Model of data-fl0w in Experimental
includes systems –
Data Acquisition (DAQ), Trigger Processing
(TRIP) and Control systems
- all of them follow the needs and tasks of Frontend
Electronics of Modern detector. There are 3-4
equivalent vertical levels of data processing in each
system. The higher level the less data events
volume and lower data event frequencies. Highspeed
Data flows on lower level of the Model
require parallel data processing using many
microprocessors.
A lot of Experimental Research Centres (including
Physics and Medicine applications) require parallel
computing with high-speed interconnections based
on new SOS-Architecture for Distributed SAN
Data Processing. Basic. Modular SAN-components
are single-chip microprocessors on Nuclear
structure level (N-module), which connect to SMParchitecture
on the board on Atomic structure level
(A-Module). A lot of A-modules interconnected as
a node by Link modules (L-modules) on Macro
structure level (M-modules). Basic Distributed
systems organized in different topologies (Basic
Ringlet, equidistant multiprocessor, 2-D and 3-D
topologies).
One of the best approaches is to construct an
effective (cost/performance) modular
Multiprocessor system with flexible SCI-based
Network Architecture. The advanced Scalable
Open System (SOS) Network Architecture based
on SCI link-modules and PC MB or PXI/cPCI
modules for Distributed RT Systems, including
DAQ, Trigger Data Processing and Control
Applications in different fields are proposed and
discussed. The Information Model of RT-
Multiprocessor Scalable Modular Systems are
based on parallel-pipeline Interconnections for
Data Acquisition, Trigger and Control Data
processing. It can be constructed (according to the
multilevel Information Model) from a functional

single-chip multiprocessors on N-level, SMPmodules
on A-level and macro-modules of basic
structure components.
1. Multi-level Information Model of Data Flows
in RT-system
The Multilevel Information Model of automated
Complex in Experimental Area includes Data
Acquisition and Control systems, based on existing
standards. Proposed four-level Model includes
parallel-pipeline Data Acquisition (DAQ) with
reduction of data-flow from detector electronics.
Data Reduction and Processing reduce event
frequency (events selection) and volume of data on
each level of the system. Reduction of data-flow
(Volume, Frequency), Reconstruction and complex
analysis of events in real time requires highperformance
Multiprocessors working in real time
(RT-systems). Experimental Area and Control
Applications requires parallel Data Acquisition
(DAQ), optimal control and distributed data
processing according to requirements. All
Interconnections between processor on any level of
the Model require high-speed data transfer and
parallel-pipeline data processing on the base of
System oriented Network. Distributed parallelpipeline
data processing requires good scalability
of high-performance multiprocessor systems
according to Source Data Flow and topology of the
experiment. Some subsystems monitor detector
electronics and slow control equipment.
Data-Flow on each level of parallel data processing
is reduced on events volume and frequency and can
be appreciate as follows
DF (i) = I(i) *
F (i),
where I(i) – Event Data Volume on i-level
F(i) – Frequency of Data Events on i-level
Data-Flow Volume on i-level will be
I(i) = Q(i) *
I(i-1),
where Q(i) – Event Volume Reduction
Coefficient on i-level of Data processing.
Event frequency on i-level will be
F(i) = R(i) *
F (i-1),
where R(i) - Event Frequency Reduction
Coefficient on i-level of Data Processing.
Event rate for LHC detector after the first level
trigger is very high (100000 Hz).
Data Volume includes Inner Tracking (1 MB per
15 ns), calorimeter (200 Kbytes per 16 ns) and
muon tracking, which are filtered by a second level
trigger (in
local segment data buffers and overall decision).
The output event rate
F(1) = 100 kHz and F(2) = 1 kHz and F(3)= 100
Hz. . The Global decision takes 1 millisecond. The
reduction coefficient should be R(2) = 100 and
R(3) = 10.
Control Data Volume on i-level will be appreciate
as
C(i) = K(i) *
C(i-1),
where C(i) – is Control Data Volume on i-level
of the information Model.
K(i) - is Control Data Reduction
Coefficient on i-level of the Model
Effective Computer Control depends on Control
Data Reduction and distribution this functions on
subsystems. All subsystems should be connected in
Integral
High-performance Distributed multiprocessor
systems should be designed on the base of flexible
System Area Network (SAN) Architecture for
Scalable Open System (SOS) approach, using highmodular
hardware and software, working in
Compact Real Time (RT) Systems.
2. System Architectures for Parallel
Data Processing
A lot of Computer Systems architecture for
Distributed and Parallel Data Processing exist
today, including Symmetrical Multiprocessing
(SMP), Massively-Parallel Processing (MMP),
Cluster Systems (RMC and NUMA).
A RMC (Reflecting Memory Cluster) is a clustered
system with a memory replication or memory
transfer mechanism between nodes and traffic
interconnect. Some vendors use the term NUMA
(Non Uniform Memory Access) to describe their
RMC systems, others used term Shared-Memory
Cluster (SMC) to describe NUMA and RMC nodes
(can be easy confused with the shared memory
inside SMP- nodes). The Term Global sharedmemory
system is not the best descriptor also.
There are multiple memories (multiple memory
maps) and OS, reflecting a portion of memory to
one another.
Academic community sometimes uses the term
“node” to refer to the small part of processors and
memory section in a CC-NUMA systems, but
commercial community not use this term because
of the confusion with the definition of a cluster
node. For example, the first developer of SCI
systems Sequent names multi-quad system as a
single-node, since only one instance of the OS is
running over all quads. Correct terminology is

equired also for describing of modern Scalable
modular system. Structure Analysis
and Synthesis of Scalable Computer Systems with
Modular Structure in real time applications are one
of the fundamental Problems in Computer Science.
Following Sequence terminology clustered systems
with two or more nodes (running a unique copy of
the OS and applications), which share a common
pool of storage simultaneously, is considered as a
Single Computer System.
Scalable Coherent Interconnections (SCI)
developed as one of the best System Area Network,
because of bus limits a number of parallel
processors in Distributed Data Processing systems.
A first attention to SCI-based Control System was
given by author in DESY (Germany) and in KEK
(JAPAN).
This paper proposed effective Scalable RT-System
Development with high-modular structure for
DAQ, Control and Distributed Data Processing.
The system includes a Microstructure level of
general purpose (Pentium-1,-2,-Pro) or specialize
Microprocessors as a Computer Nuclear. On the
Atomic structure level they are constructed on the
board as standard A-Module of the system with 1
or more microprocessors. Functional A-Modules
can be connected by bus interface, which limits a
number of processor units on the same bus.
The first developer of SCI-based high-power
modular multiprocessor system with hardware
coherency (high-priced) was Sequent. Advanced
Integrated RT-systems with Effective SOS-
network Architecture on the base of standard
Compact-PC modules or PC-board and Linkmodules
(Dolphin’s communication modules) for
effective cost/performance systems according to
proposed multilevel Physical Model are discussed
and analysed for Advanced DAQ, Control and
Distributed Data Processing Applications. One of
the best way to construct cost/performance RTsystems
is to use PC MB, connected by System
Area Networking with different topology according
to application.
3. SAN-Architecture for Scalable Open System
Multiprocessors
The Physics Model of Scalable Modular System
includes multilevel parallel-pipeline
Communications for multiprocessor open systems
interactions working as a Big-Bus SMP system for
users. Data Acquisition, Control and Data
processing systems can be constructed as a
multilevel system from a functional single- or
multiprocessor modules (Atomic micro structure
level of a system), including micro-modules of a
Processor Chip (Nuclear structure level) on the
board, connected by bus interconnections into
the standard Macro-modules (Molecular
macrostructure level). PC MB should be select for
effective cost/performance RT-Systems. Required
number of Distributed processor modules or
macro-modules interact each other through Linkmodules,
bridges and switches on parallel-pipeline
interconnections. RT-System can be constructed in
required topology according to the application.
Success of modern Microelectronics Technology
(up to 0,1 inch) opens new possibilities in
Computer System Design in Y2K. Multilevel
Physics Model of Distributed Systems is based on
Conceptual requirements of Information Model and
includes high-modular structure on all levels of the
Model. Conceptual approach to the Structure of a
system includes basic: Nuclear structure level
(micro-module or chips), Atomic structure level
(functional module in a standard boards) and
Molecular structure level (Macro-module
integrated in a PC MB, VME/VXI Crate, Compact
PC or SCI). All high modular structure levels of
Integrated System should support effective
Interaction of distributed processor and memory
modules with help of distributed link modules on
the base of the conceptual approach to the Scalable
System Area Network (SAN) Model development.
On Nuclear level of System Model micromodules(N
–modules) include
single-chip general-purpose processor, memory,
I/O controllers and communication.. Selection of
the best type of Microprocessor depends on
application requirements. Special- or generalpurpose
processor can be selected for different
applications. For high-performance signal
processing in real-time a Single- or Multiprocessor
DSP with memory inside the chip can
be used, but for effective (cost/power) DAQ,
Control and Parallel Data Processing better to use
modern compact general-purpose processors.
Single-chip Microcomputer (processor with
Memory in the chip) has shorter link, better access
and data transfer time than out of chip on the same
board, because it has shorter connections and cache
of 1-st (and 2-nd level) inside
the chip. Power Single-chip Multi-Processors is
also reality today. New compatible L-modules for
OEM developers produced by some companies
include bridge Chips and Link Controllers. There
are 4, 8 and 16 slot version of crates for Modular
cPCI systems from Motorola, PEP Modular
Computers, AdLink and PXI version for Modular
Instrumental Systems from National Instruments
Inc.

PCI-SCI Modular Bridge Chip (PSB) with a
unique protocol converter suited for clustering and
high-performance RT-System for DAQ and Trigger
applications. The PSB-32 is designed to meet the
requirements for high availability clustering and
remote I/O applications. In a unique architecture
combining both direct memory access (DMA) and
remote memory access (RMA).
High performance message passing protocols and
transparent bus bridging operations are supported.
By using the DMA controller contents of memory
can be copied directly between PCI buses in a
single copy operation with no need for intermediate
buffering in adapter cards or buffer memories. This
feature greatly reduces latency and lowers overhead
of data transfers. The DMA controller supports
both read and write operations. The remote
memory access (RMA) feature of the PSB enables
ultra-low latency messaging
and low overhead and transparent I/O transfers. In
RMA mode, PCI bus memory transactions are
converted into corresponding SCI bus memory
transactions allowing two physically separate PCI
buses to appear as one. This feature allows
applications to send data between system memories
without using of operating system services,
reducing latency and overhead. The PSB has builtin
address translation, error detection and
protection mechanisms to support highly reliable
connections. The PSB chip is based on the
ANSI/IEEE SCI-standard.
Basic parameters of Bridge chip:
• PCI 2.1 compliant, 32 Bits, 33 MHz
• ANSI/IEEE 1596-1992 SCI standard
• Chaining (Read/Write) DMA Engine
• Up to 4096 map entries in SRAM
• 512 Kbytes page size compatible
• Host bridge capability (PCI arbiter)
• B-Link Compliant Performance104 Mbytes/sec
RMA, 73 Sec/sec DMA
SCI Link Controller Chip (LC3, compatible
backwards with LC2) is the first implementation of
the Scalable Coherent Interface standard with
duplex bandwidth of 800 Mbytes/s. The LC3
is targeted for use in a wide range of systems where
high bandwidth combined with low latency is
required. Typical target systems are computer
clusters, tightly coupled parallel computers, high
performance I/O systems and switches. The LC3
guarantees delivery of SCI packets with payloads
up to 64 bytes of data. Internal buffers allow for
pipelining of packets for high throughput operation,
yet supports virtual cut-through routing for low
latency access. The LC3 offers local high-speed
bus performance characteristics, with LAN
flexibility and scalability at a very competitive
price. The chip uses high speed single-directional
low voltage differential signaling, running on
standard low cost cables to attain a 800 Mbytes/s
(6.4 Gait/s) data transfer rate with routing latency
as low as 70 ns. System scalability is accomplished
through a high-speed backend interface
(BXBAR) with built-in switching capability
allowing system growth to beyond 1000 nodes.
LC3 SCI Link Controller parameters:
• ANSI/IEEE 1596-1992 SCI standard
• ANSI/IEEE Std 1596 LVDS Link
• ANSI/IEEE 1159.1 (JTAG) support
• BXBAR Crossbar switching
• 800 Mbytes/s Duplex link bandwidth for high
performance applications
• Virtual channel (VC) based buffer management
• Table-based packet routing supporting complex
topologies
• Two-wire serial EEPROM interface
• Queuing structure capable of storing 15 requests
and 15 responses
Atomic structure level on the Processor Boards
(A-modules) of the Model includes specialpurpose
(DSP) or general-purpose processor (PC
MB), memory and I/O subsystem components.
Typical examples are computer modules like
VME/VXI, PXI/cPCI or modern Lita-PC Mother
Board (MB). The simplest construction of effective
Distributed Data Processing system for DAQ,
Trigger and Control Application can be based on a
compact PC MB with single, two (Dual) or four
(Quad) microprocessors on the board.
Number of modules on the same bus is limited (up
to 16). Symmetrical Multiprocessing (SMP) is
basic Software Model for Multiprocessors. This is
one of a best decision for Trigger subsystems
modules.
A lot of A-Modules should be interconnected in
similar SMP mode
in different distributed topologies according to real
detector on the base
of San-architecture (using SCI). Embedded
subsystem (A-module or
M-modules) on macro level used often for slow
control and monitoring wit Ethernet10/100
interconnections.
Distributed SAN Interconnection level (L-, B- and
S-type Modules) depends of communications
requirements and link-modules parameters. The
cost of communication speed decreases faster than
the cost of pins and board space. Tradition
communications are usually based on bus, but any
practical solution would involve the use of packetbased
signaling over many independent point-to-

point links, which eliminated the bus bottleneck
problem, and introduced a new problem - how to
maintain cache-coherence in the shared-memory
model of system. Bus is used for up to 16-32
processor max on the same bus, but Scalable
Coherent Interconnections (SCI) is good
connection for SOS- architecture with many
processors
in a single system for DAQ, Control, Parallel Data
Processing and DB.
A wide range of application can cover the whole
range from high-end multiprocessors to workstation
cluster and LAN.
The distributed SCI-based SAN Architecture shares
a 64-bit address space, where the high order 16 bits
are used to rout packets to the appropriate node.
System topology can be based on a simple ringlet,
multi-ringlet, bridges or powerful switches for
Parallel-pipeline communications between
processors
and memory. Interconnection should
be based on Link modules (L-Modules)
or Switch modules (S-Modules). SCI
is based on point-to point connections
and supports transactions all processor modules at
the same time. Commercial Dolphin’s L-modules
provide 800 Mbytes/s bi-directional SCI link
effective transfer
of a large volumes of Distributed data. Applicationto-application
latency is small (2.3 micro second)
and reduces the overhead of inter node control
messages, leading to the best possible scalability
for multi-node applications. Dolphin’s S-Modules
for System Area Networks provide 4 x 800
Mbytes/s duplex ports and 2 x 800 Mbytes/s duplex
ports.
Internal Switch provides 1.28 Bytes bandwidth,
port-to-port latency of 250 nanoseconds and dual
fans for reliability. These parameters provide good
interactions between distributed modules. Large
Integrated Complex should be based on Bus-like
SOS Networks architecture with distributed
memory for effective DAQ, Trigger and Control in
Distributed Data Processing. High-performance
PXI/cPCI modules have mezanin interface for
standard PMS-modules which be effective used for
interconnections between systems components.
PMC-SCI Adapter Module is a general-purpose
interface for connecting PMC based cPCI-systems
through SCI links onto Integrated SAN-based RTsystems
(for DAQ, Trigger and Control) with
Memory-mapped Distributed data processing. The
module can be utilized in different applications
such as scalable interconnection of I/O, bus-to-bus
bridging and computer clusters. Its 800 Mbytes/s
bi-directional SCI link is good for moving large
volumes of data. Small application-to-application
latency (2.3 micro second) reduces the overhead of
inter node control messages, leading to the best
possible scalability for multi-node applications.
SCI's performance is achieved by taking maximum
advantage of fast point-to-point links, and
bypassing the time consuming operating system
calls and protocol software overhead found in
traditional networking approaches. SCI provides
hot-plug cable connections; and redundant SCI
modules can be used to increase fault tolerance. It
supports SCI ring and switch topologies. Large
Multiprocessor clusters can be built using
Dolphin's interconnect switches.
PCI-64 adapter Module opens effective way to
build PC-based System Area Networks for
Distributed data processing, clustering of computer
and servers on the base of SCI. It has similar
parameters as PMC PCI Module. PCI and VME
configurations can be combined.
Basic Technical Parameters of
PMC- PCI Module:
Link Speeds - 400 Mbytes/s
(800 Mbytes/s duplex)
SCI Standard - ANSI/IEEE 1596-1992
PMC Specification - PMC IEEE 1386.1 Standard,
32 and 64-bit,
33 MHz PCI Bus (rev. 2.1 170
Mbytes/sec operation).
Performance - Up to 170 Mbytes/sec throughputs,
2.3 microsecond latency
Power Consumption - Static: 5W,
- Dynamic: 6W
Cable Connection - Parallel STP
Copper Cable (1-7,5m)
- Parallel Optical Link
PAROLI-SCI (1-150m)
Topologies - Point-to-Point and Switch
Modular SCI Switch (MS-6E) with high data
throughput and low message latency for SAN
provides 4 x 800 Mbytes/s duplex user ports, 2 x
800 Mbytes/s duplex ports. Internal Switch
provides 1.28 Bytes bandwidth, port-to-port latency
of 250 nanoseconds,
dual fans for reliability and increased circuitry
lifespan. Clusters are supported by hot
plugging.MS-6E switch is a high-performance
solution for System Area Networks and server
clusters.
Cluster nodes connect through four duplex 400
Mbytes/s ports. For scalability to larger clusters,
the MS-6E supports redundant expansion ports,
which allow up to 12 switches to be cascaded for
System Area Networks of up to 32 ports. The MS-

6E can also be configured as a standalone 6-port
switch.
The SCI architecture is designed to grow to as
many as 64k nodes, which leaves plenty of
headroom for future expansion. The SCI Switch's
"port fencing" feature guarantees that a node failure
will not prevent the cluster from functioning. Hotplug-gable
ports allow the addition or removal of
nodes without halting cluster applications.
The switch is built around open standards and
supports the IEEE/ANSI SCI standard and adapter
module for standard buses such as PCI and Sbus.
The dual expansion ports provide highly reliable
redundant links. Dual fans increase MTBF and
circuitry life span. Cable Connection is based on
Parallel STP Copper Cable up to 5m or Parallel
Optical Link PAROLI-SCI up to 150m. It has
compatibility with 19” racks for ease of mounting
and auto- ranging power supply.
Macro-structures on Molecular level (Mmodules)
depends of system topology. A lot of
Multiprocessor cPCI Crates as a nodes can be
interconnect
by System Area Networks (“Big Bus”
Interconnections) into a large (up to
a Kilo-Processor) systems to support Distributed
Integrated RT-Systems for DAQ, Control and Data
Processing Applications. A number of A-modules
on the Bus is limited up to 16 (max 32) because of
physics parameters and not good scalability. A set
of A-Modules in single Crate or Multi-Crate
systems is sectioned as a Macro-module of the
System Model. Sectioning of modules are based on
exist standard Compact PC, VME/VXI, PC MB or
SCI. Multi-Crate systems are one of the way to
construct big systems. Big Bus-like approach is
used to develop System Area Networks (SAN). SCI
is one of the best approach to Scalable
Multiprocessor System Architecture with following
advantages.
Interactions between modules within RT-system
are based on small packet transfer with split
transactions. There are high interaction of N-
Nodes on shared memory resources (example direct
access to memory in SMP systems), weak
interactions between A-modules (example
message passing
in MPP systems) and intermediate interaction on
the base of external memory devices (disks, tapes
in Clustered systems). High SCI interactions are
based on small packet transactions (send and
response packets with echo). Packet Formats
include writexx, readxx, movexx and locksb
commands, where xx – represent one of the
allowed data block length (number of data bytes,
on the right after the packet header).
Scalability is fundamental requirement for highperformance
Modular Multiprocessor Systems. All
requirements of application are changed and can be
much more tomorrow than today. Number of
processor should be used up to Kilo-Processor
system.
Good linear Scalability is a problem for highperformance
computer system today. Addition of
A-modules, L- and S-modules in RT-system
support good scalability and provides more
performance and throughput of the Multiprocessor
system.
Distributed-memory Model for Multiprocessor
system with SOS-architecture should be
fundamental to support high-performance parallelpipeline
data processing (computing)
in RT-application. Direct access any processor to
any memory in single address space of the
Integrated System is similar to SMP model. Big
address fields (64 bits) supports or each node up to
256 Tbytes memory. Register field in high part of
node memory (256 Mbytes) includes registers with
ROM (2K), initial units space (+2K) and available
space. Much additional problems in integrated
Kilo-processor system exist with cache-coherency.
Cache coherency in multi-processor systems is
required to support data availability for all
processor during distributed data processing
(parallel computing) in real time.
Coherency is the problem in distributed
multiprocessor systems, which include many
processors, attempting to modify a single datum or
holding their own copies of it in their cache at the
same time. Coherency, implemented by software or
hardware, is request to prevent multiple processors
from trying to modify the same data at the same
time. The cache-coherency protocol based on the
snoopy bus is back plane limited and it should
migrate to a more scalable modular multiprocessor
system as hardware cache-coherency.
Topology of modular RT-Systems can be
constructed from required set of Modules (A-
Modules, L-modules, B- or S-module) according to
application.
It should be a matrix for DAQ-systems, if data
sources are based on matrix detectors, or 3Dtopology,
if experiment based on 3-D detectors.
In Control Fields the system should have topology
according to the structure of accelerator part (linear
or ring). MB-based module is connected by Lmodules
in System Area Network
with required topology. N-node as microprocessor
chip (or as a small mezzanine-board) connected by
L-modules in different system topology.

Technology Independent System architecture
are ready to support a new technology and provide
long living time of systems and up-grading modules
on different level. SCI-based SOS network
Architecture with high-modular structure not
depend on changed technology and should consist
of required modules.
Standard Construction of special Mechanics
required for SCI standard Modules and Crates. To
simplify problem PC mechanics and PC-boards
with PCI local bus should be used as a platform for
A-modules in Distributed systems. Hard disks
should be used as reliable distributed external
memory near each processor module. Tradition
Ethernet should be used as additional
communication media for system initializing, user
access and serves.
Summary.
System area Network Architecture
for Scalable Open System s should be used for
effective (performance/price) construction of
multilevel Data Processing RT-Systems for
Detector DAQ and Trigger Application on the base
of Small PC MB or PXI/cPCI and SCI Linkmodules.
Hardware coherency in multiprocessor
systems supports high-performance at high price,
but Software coherency provides good performance
at low price.
Distributed Multiprocessor System on the base of
PC MB (A-modules) and Link-modules (Lmodules
or S-modules) without hardware cachecoherency
are discussed as example of low-cost
effective approach to DAQ and Control RT-
System. There are commercial link-modules for
SOS–systems interconnections (Dolphin’s PMC-
SCI Module for modular RT-system, PCI-64
Adapter Module for PC-based distributed data
processing and Switch for high-speed
interconnections between ringlets).
Different topologies should be constructed with
these modules according to requirements of
application. DAQ and Trigger Systems with 2-D
Matrix topology should be used, which can consist
of 4x4=16 single-processors modules (A-type).
Toroidal Topology or 3-D Matrix system topology
should be used for 3-D detector.
Modules for short distance (up to 5 meters) are
based on cooper link. Long distance Module (up to
1-2 km) are based on fiber optics links. For more
performance 2-4 processor on a board SMPmodule
should be used.
Control Systems can be divided on a number of
sectors, which should have subsystems (submatrixes),
interconnected by the same way. The
best connections for long distance for Control and
Monitoring are fiber-optics modules. Control and
Experimental areas should be interconnected in
Distributed Integrated systems on the base of
system Area Networking technology. For slow
control tradition standard connections (CAN) or
Ehernet can be used. A set of functional linkmodules
(L-module without hardware coherency)
accessed from Dolphin described below.
All general problems of Scalable Microprocessor
system Developments and Applications were
discussed in conferences starting from ICSNET’91-
95 symposiums on modular systems and networks
in S-Petersburg till this year and all future
publications open on the intranet sites of Elics
Community http://elics.org.ru/ and ware published
in paper Proceedings.
.
Reference
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to Data Acquisition at LHC
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Institute.Copenhagen,DK. R.Dobinson,Stefan
Haas,Brian Martin.Minghua
Zhu,CERN,Geneva,CH. ICSNET/1995,S-
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email: Joannes.Andreas.bogaerts@cern.ch
Manfred Liebhart, Techn. Univ. of Graz,
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Multimedia Presentation and Picture for this
Manuscript are below in Appendix.

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Studies for a Detector Control System for the ATLAS Pixel Detector
Bayer, C. 1 , Berry, S. 2 , Bonneau, P. 2 , Bosteels, M. 2 , Hallewell, G. 3 , Imhäuser, M. 1 , Kersten, S. 1+ ,
Kind, P. 1 , Pimenta dos Santos, M. 2 , Vacek, V. 5
1 Physics Department, Wuppertal University, Germany; 2 CERN, Geneva, Switzerland ;
3 Centre de Physique des Particules de Marseille, Campus des Sciences de Luminy, Marseille, France;
5 Czech Technical University, Prague, Czech Republic;
Abstract
For the ATLAS experiment at the LHC, CERN, it is planned
to build a pixel detector containing around 1750 individual
detector modules. The high power density of the electronics
requires an extremely efficient thermal management system:
an evaporative fluorocarbon cooling system has been chosen
for this task. The harsh radiation environment presents
another constraint on the design of the control system, since
irradiated sensors can be irreparably damaged by heating up.
Much emphasis has been placed on the safety of the
connections between the cooling system and the power
supplies. An interlock box has been developed for this
purpose. We report on the status of the evaporative cooling
system, on the plans for the detector control system and on the
irradiation studies of the interlock box.
I. INTRODUCTION
The pixel detector is the component of the ATLAS inner
tracker closest to the interaction point. From the monitoring
point of view, the base unit is a detector module consisting of
a pixelated silicon sensor, with 16 bump-bonded front end
readout chips. A flexible hybrid circuit is attached and carries
a “Module Controller Chip” which organizes data
transmission from the module via a bi-directional optical link.
The optical link is located close to the detector module and
contains a VCSEL (vertical cavity semiconductor laser) and a
PIN diode, together with their corresponding transceiver chips
“VDC” and “DORIC” {[1], figure (1)}. Besides the voltages,
necessary to drive the different electronic components, one
temperature sensor per module must be handled by the
detector control system (DCS). The detector modules are
glued on the different support structures (“staves” in the barrel
part, disks in the “end-caps”) which contain the cooling pipes
necessary to remove the heat dissipated by the electronics.
The following three sections describe the three main
components of the pixel DCS: the cooling system, the power
supplies and the temperature monitoring and interlock
system. Emphasis is put on the characterization of the
hardware. Wherever possible we try to use ATLAS standard
components, especially the ELMB (Embedded Local Monitor
Box)[2]: a multi purpose acquisition and control unit, using
the CAN fieldbus and developed by the ATLAS DCS group.
Section V contains an overview of the whole Pixel DCS and
+ Corresponding Author : susanne.kersten@cern.ch
reports on the first steps in the implementation of a SCADA
[“Supervisory, Control and Data Acquisition”] system. The
summary in section VI includes an outlook on future plans.
Flex Hybrid Circuit
Temperature Sensor
Detector Module
MCC (Module Controller Chip)
Silicon Detector
16 Front End Chips
Cooling Pipe
VDCp (VCSEL Driver Chip) VCSEL
capton cable
optical fibre
PIN-Diode
DORICp (Digital Opto Reciever IC)
Opto Board
Vdet detector depletion voltage
Vdda
Vdd
Vpin
Vvdc
Viset
front end chips, analog part
front end chips, digital part, MCC
voltage for PIN-Diode
voltage for VDCp and DORICp
control voltage for VCSEL
Figure 1: Schematic of a pixel detector module with relevant
components of the Detector Control System
II. THE COOLING SYSTEM
A. The Challenge
For a ten-year operational lifetime in the high radiation field
close to the LHC beams, the silicon substrates of the ATLAS
pixel detectors must operate below ~ -6 °C with only short
warm-up periods each year for maintenance. Around 15 kW
of heat will be removed through ~ 80 parallel circuits, each
cooling a series pair of pixel barrel staves (208 or 290 W) or
disk sectors (96 W). Evaporative per-fluoro-n-propane (C3F8 )
cooling [3] has been chosen since it offers minimal extra
material in the tracker sensitive volume (flow rates 1/20 those
in a monophase liquid system), with a refrigerant that is nonflammable,
non-conductive and radiation resistant. Since the
pixel stave and disk sector “local supports” are of the lowest
possible mass composite construction, detectors can exhibit a
very rapid temperature rise (~ 5 Ks -1
) in the event of a loss of
coolant or cooling contact. A rapid thermal interlock with the
module power supplies is therefore indispensable. Thermal
impedances within the local supports require C3F8 evaporation in the on-detector cooling channels at ~ -20 °C
for a silicon operating temperature of ~ -6 °C.
B. The Recirculator and Principle of Operation
A large scale (6 KW) prototype circulator (Fig. 2) can supply
up to 25 parallel cooling circuits, through interconnecting
tubing replicating the lengths and hydrostatic heat differences
expected in the final installation in the ATLAS cavern.

Figure 2:
Schematic of Prototype Evaporative Recirculator
It is centred on a hermetic, oil-less piston compressor 1
operating at an aspiration pressure of ~1 bar abs and an output
pressure of ~10 bar abs . Aspiration pressure is regulated via
PID variation of the compressor motor speed from zero to
100%, based on the sensed pressure in an input buffer tank.
C 3 F 8 vapor is condensed at 10 bar abs and passed to the
detector loads in liquid form. A detailed description of the
principle of operation is given in ref [4].
In the final installation, liquid will be distributed, and vapor
collected, in fluid manifolds on the ATLAS service platforms.
This zone will be inaccessible to personnel during LHC
running, with local radiation levels and magnetic fields that
exceed acceptable levels for a wide range of commercial
control electronics. Local regulation devices will be
pneumatic: in each cooling circuit, coolant flow rate will be
proportional to the output pressure of a “dome-loaded”
pressure regulator 2 , placed ~ 25 m upstream of an injection
capillary, piloted by analog compressed air in the range 1-10
bar abs from an I2P (4-20mA input) or E2P (0-10V input)
electro-pneumatic actuator 3 . Actuators will receive analog set
points from DACs, which will either be commercial control
components 4 , or an adjunct to the ATLAS ELMB monitor and
control card [2]. Circuit boiling pressure (hence operating
temperature: at 1.9 bar abs , C 3 F 8 evaporates at –20°C) will be
controlled by a similarly piloted dome-loaded backpressure
regulator 5 .
C. PID Regulation of Coolant Mass Flow
Coolant flow in each circuit will be PID-regulated to
maintain the temperature on a NTC sensor on the exhaust 50
cm downstream of a cooled detector element ~> 10 °C above
the C 3 F 8 evaporation temperature. In this way it is not
necessary for the cooling control system to detect how many
1 Model QTOX 125 LM ; Mfr: Haug Kompressoren
CH-9015 St Gallen, Switzerland
2 Model 44-2211-242-1099: Mfr: Tescom, Elk River MN 55330, USA
3 Model PS111110-A: Mfr Hoerbiger Origa GmbH, A-2700 Wiener-
Neustadt, Austria: Input 0-10V DC, Output pressure 1-11 bar abs
4 Model 750-556: Mfr Wago GmbH, D32423 Minden, Germany
controlled through Model 750-307 CAN Coupler
5 Model 26-2310-28-208: Tescom Corp
detector modules on a cooling circuit are powered (or their
instantaneous power dissipation).
A PID algorithm has been implemented directly [4] in a
microcontroller chip 6 of the same family as that used 7 for
system programming and monitor functions in the ATLAS
ELMB. The results indicated that with proportional flow
control, stability in temperature of –6 ± 1 °C on remaining
powered modules is achievable, with > 90 % of the supplied
C 3 F 8 liquid evaporated in the on-detector tubing. In setting up
the PID parameters, care was needed to ensure that the lower
pressure limit was not less than the saturated liquid pressure at
the C 3 F 8 liquid injection temperature.
The tubing of the cooling circuits requires insulation (and
possibly local surface heating in certain critical locations) to
safely traverse the electrical services of other ATLAS subdetectors,
which are located in an ambient air atmosphere
with ~ 14 °C dew point.
The results also demonstrated PID colant flow regulation
allows a relatively simple insulation scheme to maintain the
outer surface of the exhaust tubing above the local dew-point,
reducing the insulation volume required in the extremely
restricted service passages.
A DAC adjunct is under design for the ATLAS ELMB [2].
This would allow PID flow regulation through control loops
from the ELMBs with one or more PID channels in the onboard
microcontroller of each ELMB. While it is also possible
to implement a software PID algorithm for each circuit in the
final ATLAS SCADA software, it is not known at this stage
whether the reaction time will be fast enough for our
application.
III. THE POWER SUPPLY SYSTEM
Six different voltages are necessary for the operation of each
pixel detector module, (figure 1). These must supply a
depletion bias of up to 700 V and five low voltage loads
varying between low power consumption to two which draw
2-5 Amperes. In order to support the ATLAS grounding
scheme, all voltages will be floating.
We aim to use a coherent power supply system which
accommodates these diverse requirements and has a high
level of local intelligence. A system able to make decisions
autonomously - not relying on the functionality of the network
- will reduce field-bus traffic and will enhance the safety of
the detector. Error conditions (including over-current) will be
handled in the power supply system, leaving recovery
procedures to the operator or supervisory detector control
station. The demand for significant local functionality implies
the location of the system in an radiation-free environment.
6 AT90S8515; Mfr: ATMEL Corp, San Jose CA 95131, USA:
programmed from C via GNU toolkit
7 ATMEL ATmega103 128k RISC flash µcontroller

For redundancy and grounding considerations, we require a
high granularity of power distribution, with a total of ~ 4000
separate channels. In order to handle this large number of
channels efficiently and to speed up access, a power supply
system is needed which offers the grouping of channels
according to the characteristics of the detector and its
installation: so called multi-voltage “complex channels” will
be formed to power each pixel module. This is also required
by the design of our interlock system: a single interlock signal
should simultaneously turn off all power supplies to a module.
As the front end chips of the pixel detectors are fabricated in a
0.25 µm deep submicron technology, they are very sensitive
to transients. First measurements with a prototype power
supply system have shown that line regulators are required.
These represent an additional object for the DCS. Their
location must be close to the detector, setting a specification
for their radiation hardness. The LHC4913 8
is a possible
candidate to meet our requirements, and its use is presently
under investigation.
IV. TEMPERATURE MONITORING AND
INTERLOCK SYSTEM
A. Principle
Due to the great influence of the operating temperature on
the longevity of the detector, each detector module is
equipped with its own temperature sensor. Inaccessibility
during long periods of one year or more requires a reliable
and robust solution for the temperature measurement: we
have chosen a method based on resistance variation. The
information from the sensor will be led to the ADC channels
of the ELMB for data logging. In parallel, the signal will be
fed to an interlock box, which compares it to a reference value
and creates, in the case of excessive deviation, a hardwired
logical signal which can be used for direct action on the
power supplies. This solution protects the detector against
risks associated with latch-up, de-lamination of a particular
module from its cooling channel or failure of coolant flow to a
particular parallel cooling circuit.
B. Choice of the Temperature Sensor
The very limited space requires a component available in a
SMD 0603 package, and which can be read via a two wire
connection, implying the need of a sensor in the 10 kΩ range.
A relatively large change of the resistance per Kelvin reduces
the requirements on the precision of the electronic circuit. In
order to avoid a calibration of each individual channel, we
have been searching for a resistor with small tolerance limits.
Operation in a magnetic field of up to 2.6 T and at a radiation
dose of up to 500 kGy (corresponding to 10 years of operation
in ATLAS), are pre-requisites. For this reason the package
material of the sensor was also taken into consideration.
We found that the requirements listed above were best met by
a 10 kΩ NTC resistor with a relative change of its resistance
8
developed by ST Microelectronics (Catania, Italy) in the framework of the
RD 49 project, CERN
of 4 % per Kelvin 9
, available with 1 % tolerance at 25 °C. The
type 103KT1608-1P from Semitec is additionally available in
a glass coated package.
C. The Interlock Box
Since the interlock box is so closely related to the safety of
the detector, we aimed at a pure hardware solution, which
should not rely on any initialization via software or
multiplexing. The interlock box should be able to work
completely independently from other equipment. In addition
to module heat up other error conditions including a broken
cable or temperature sensor and a short circuit must also cause
the setting of the interlock signal. Negative TTL logic is
employed.
R1
10k
+2V5
R8
1M
C1
470n
Sensor
NTC 10k
R3 1M
UHIB
+5
R2
3k9
+5
IC2
+
OPA
IC1
_
4336
+
OPA
R5 1M
_
4336
R4
3k9
+5
IC3
+
OPA
4336
_
ULO
R7 1M
R6 +5
IC4
3k9
+
OPA
_
4336
UERR
IC01
2V5
AD680
+5 V
C01
CR
22n
C02
etc. RH1
RH2
GND
+5
HI-Test
TC4S66
UHIB
UHI +
OPA
CH
_
336
RE2
IC02
RE1 UERR
CE
74LCX02
IC6
74LCX02
Discriminator section, one for each channel
RL2
RL1 ULO
Reference section, common for all channels
Figure 3: Electrical Schematic of the Interlock Box
IC5
NTC I-Box circuit P. Kind 11.2000 Uni Wuppertal
In order to reduce the influence of noise, a hysteresis of ~1 K
is required between the setting of the alarm signal and its
reset. A precision of +/- 1° K is required for the complete
chain of temperature sensor, cables and interlock box
therefore an accuracy for the interlock circuit alone of < 0.5
K is adequate.
Figure 3 shows the realization of the interlock circuit. A clean
reference voltage is created by the reference section. The
signal from the NTC is then compared to different thresholds,
the op-amps acting as discriminators. The following NORgates
create a pattern of two bits, representing the different
error condition combinations mentioned above.
Several studies [4] have demonstrated that the electrical
performance of the circuit is in good agreement with the
expected error, which is composed of the error of interlock
circuit, caused by the tolerances of the components, of ± 0.2
K and of the tolerances of the NTC of ± 0.3 K (depending on
the temperature).
9
10 kΩ @ 25°C, t(K)=1/(9.577E-4+2.404E-4ln(R)+2.341E-7ln(R) 3 ). Mfr:
Ishizuka Electronics Co. 7-7 Kinshi 1-Chome, Sumida-ku, Tokyo 130-8512,
Japan
T-Hi
T-Lo
CL

D. Irradiation Results on the Interlock Box
As the location of the interlock box will be the ATLAS
experimental cavern, the radiation tolerance of all its
components must be investigated. Three types of possible
problems must be studied in order to qualify the electronics:
damage due to ionising (“total ionising dose”: TID) and non
ionising radiation (“non-ionising energy loss”: NIEL) and
single event effects (SEE). The expected simulated radiation
levels are given in [5]. In order to determine the “radiation
tolerance criteria”, several safety factors are added, table 1
summarizes them for the interlock box based on the
calculations described in [5].
Table 1: “Radiation tolerance criteria” for the Interlock Box
RTCTID RTC NIEL
RTCSEE 10 years operation in ATLAS
93 Gy
4.8 10 11
n/cm 2
(1 MeV)
9.22 10 10
h/cm 2
(> 20 MeV)
As a pre-selection 3 irradiation campaigns were performed:
• TID studies with a 2.10 4
Ci Co- 60 source;
• A neutron irradiation at the CEA Valduc 10
research
reactor with an energy range up to a few MeV with
maximum intensity at 0.7 MeV;
• SEU studies at the 60 MeV proton beam of UCL 11
.
Usually five devices were irradiated per campaign. During all
irradiation tests the components were powered, monitored and
checked online for performance and power consumption. For
the study of single event effects additionally a special
program was developed to monitor the complete circuit for
transients or other temporary changes in the output. During
the first TID campaign, the first selected NOR-gate (type
CD74HC02M 12
) showed severe problems, manifested by an
increase of the power consumption. Several further NORgates
were tested [6]. It was found that the radiation
robustness depended not only on the logic family and the
manufacturer, but also on the input pattern sent to the device
during the irradiation. We found that the MC74LCX02D 13
best met our requirements.
Table 2: Components of the Interlock Box, which passed all three
irradiation tests
Selected Device
Op-Amp OPA336N
4 fold Op-Amp OPA4336EA
NOR-Gate MC74LCX02D
Voltage reference (2.5 V) AD680JT
Voltage regulator (3.3 V) LE33CZ
Analog switch TC4S66
Capacitors Ceramicmulti-layer, Epcos
As the offset voltage of the op-amp is critical to the accuracy
of the circuit (1 mV corresponds to 1/20 K) this quantity was
10
11
CEA, Centre de Valduc, F21120 Is-sur-Tille, France
Université Catholique de Louvain, B1348 Louvain-la-Neuve,
Belgium
12
13
Texas Instruments, USA; www.texas-instruments.com
ON Semiconductors, USA ; www.onsemi.com
measured for several input voltages. Figure 4 shows a typical
result, indicating that no deterioration is expected. The
colored band represents the acceptable variation in our
application. All other devices showed no problems, either
during or after irradiation. Table 2 summarizes the
components which finally passed the three irradiation tests.
Offset/uV
Offset/uV
Offset/uV
1000
800
600
400
200
-200
-400
-600
-800
-1000
0
1000
800
600
400
200
-200
-400
-600
-800
-1000
0
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
OPA336, Sample B3 Uin=1.0 V
14 10 11 12 13 14 15 12
19/4 ----- 20/4 ----- 21/4
begin end of irradiation
OPA336, Sample B3 Uin=1.8 V
14 10 11 12 13 14 15 12
19/4 ----- 20/4 ----- 21/4
begin end of irradiation
OPA336, Sample B3 Uin=2.5 V
14 10 11 12 13 14 15 12
19/4 ----- 20/4 ----- 21/4
begin end of irradiation
12
28/4
12
28/4
12
28/4
Time [h]
Date
Time [h]
Date
Time [h]
Date
Figure 4: Offset Voltages of the OPA-336 (TID: 100 Gy)
E. The Interlock System
CAN-Bus
Interface
DCS Station
TCP/IP
CAN-Bus
ELMB1
CAN-Bus
CAN-Bus
Test
ELMB2 Interlock ELMB1
Test
ELMB2 Interlock
Monitoring
CAN-Bus
Interface
Ethernet
Interface
ELMB3
Power Supply Lines
Power Supply System
CH CH CH CH CH CH
#01 #02 #03
#nn
Monitoring
Logic Unit
NTC NTC
Detector Module
Detector Module
Figure 5: Schematic of the Temperature Monitoring
and Interlock System
Counting Room
Cavern
Detector Inside
Figure 5 shows the complete temperature and interlock chain.
The signal from the temperature sensor is split between
interlock box and ELMB. Information from two interlock
channels are combined by the logic unit, as one power supply
channel serves two detector modules. In parallel, the digital
information from the ELMB is sent to the DCS station via the
CAN-Bus for data logging. Additionally, another ELMB
monitors the interlock bit pattern. A third ELMB can be used

to send test signals to the interlock box. This remote test
possibility is necessary because the equipment is not
accessible during data taking periods. The power consumption
of the Interlock Box is also monitored by this third ELMB
since an increase in the supply current can indicate problems
due to irradiation.
V. THE PIXEL DETECTOR SCADA SYSTEM
Endcap 1
Pixeldetector
B-Layer 1 Layer 1-2 Layer 2-3
Layer 1-1 Layer 2-2
Layer 2-1
optical link
HV
Vdda
Vdd ERROR
Temp 1
Temp 2
Interlock 1
Interlock 2
cooling info
others ?
B-Layer 2 Layer 1-3 Layer 2-4
5.0
4.9
2
3
OVC
Endcap 2
PCC #01 PCC #02 PCC #03 PCC #04 PCC #nn
BDU #01 BDU #02 BDU #03
BDU #12 BDU #13
Vset Vmon Iset Imon stat
enter new value
Figure 6: Organization of the Pixel Detector Elements inside
the SCADA System
Besides the hardware components described in the previous
three sections, the temperature management system (see
figure 5) will also be applied for the control of the opto boards
(see figure 1), as the performance of irradiated VCSELs will
decrease if their temperature exceeds 20 °C. The temperatures
of the regulators located in the supply cabling and their input
and output voltages and currents are further parameters to be
monitored.
Following the recommendations for the ATLAS experiment
we have started to implement the SCADA system for the
control of the pixel detector using the PVSS commercial
software product 14
.
Our first studies with PVSS are following geographically
oriented structures, where all information relevant for one
detector unit is given simultaneously, since this helps to trace
and analyse problems. Figure 6 shows how the different levels
of the tree structure can be arranged. Following the different
levels one can find out in which part of the detector a problem
has arisen. As the distribution of the high and low voltages is
done with granularity two, from the DCS point of view the
14
from ETM, A-7000 Eisenstadt, Austria
smallest unit DCS can act on contains 2 modules - forming a
“base detector unit”. All other information relevant to the
status of a detector module (temperature, status of the related
opto link and interlock, etc.) must be available on this level.
Information on the status of the cooling system and the
readout chain will be supplied via the “event manager”.
We have started to implement PVSS version 2.11.1 on a win-
dows NT platform. In this development system we use two
OPC servers (OLE for Process Control), one communicating
via CAN-Bus to the ELMB which monitors the hardware, and
the other handling communication with the power supplies.
With this system we have begun to implement a few BDUs,
from which larger systems can be composed.
VI. SUMMARY
The requirements of the pixel detector have made specific
developments necessary for the hardware components of the
DCS. A cooling system using the evaporation of C 3 F 8
fluorocarbon has been developed and will be used for the
ATLAS pixel and SCT detectors. Control of coolant flow in
each circuit via PID regulation has been demonstrated and is
being implemented in a 25-channel demonstrator. For the
temperature management system, a possible solution is found
based on the interlock box and the ELMB. The design of the
interlock box uses standard electronic components, which
helps to reduce its cost. Its radiation tolerance for 10 years´
operation in the ATLAS cavern can be achieved as several
pre-selection irradiation tests have shown. Before going to
production this must be verified on larger samples. The
implementation of the supervisory control system in PVSS
has started. The basic elements are defined. Future test beam
activities will allow us to test and improve the proposed
control structure.
VII. REFERENCES
[1] ATLAS Pixel Detector Technical Design Report,
CERN/LHCC/98-13, 31.05.1998
[2] B. Hallgren, The Embedded Local Monitor Board in
the LHC Detector Fron-end I/O Control System, in these
prceedings
[3] E. Anderssen et al, “Fluorocarbon Evaporative Cooling
Developments for the ATLAS Pixel and Semiconductor
Tracking Detectors”, Proc. 5 th
Workshop on Electronics for
LHC Experiments, CERN 99-09 CERN/LHCC/99-33
[4] C. Bayer et al, “Development of Fluorocarbon Evaporative
Cooling Recirculators and Controls for the ATLAS
Pixel and Semi- conductor Tracking Detectors” Proc. 6 th
workshop on Electronics for LHC Experiments, Krakow,
Poland, Sept. 1999, CERN 2000-101 CERN/LHCC/2000-041
[5] M. Dentan: ATLAS Policy on Radiation tolerant
Electronics, July 2000 Rev. No.2, ATC-TE-QA-001
[6] www.atlas.uni-wuppertal.de/dcs

Printed Circuit Board Signal Integrity Analysis at CERN.
Abstract
Printed circuit board (PCB) design layout for digital
circuits has become a critical issue due to increasing clock
frequencies and faster signal switching times. The Cadence ®
SPECCTRAQuest package allows the detailed signalintegrity
(SI) analysis of designs from the schematic-entry
phase to the board level. It is fully integrated into the
Cadence ® PCB design flow and can be used to reduce
prototype iterations and improve production robustness.
Examples are given on how the tool can help engineers to
make design choices and how to optimise board layout for
electrical performance. Case studies of work done for LHC
detectors are presented.
I. INTRODUCTION
A. High-speed digital design
Electronic Design Automation tools are becoming
essential in the design and manufacture of compact, highspeed
electronics and have been extensively used at CERN to
solve a wide range of problems [1], [2].
A typical fast digital system poses many high-speed signal
integrity questions (Figure 1).
Termination
Effect
IC Package
Effect
Silicon Speed
Effect
Stubs Effect
Termination
Effect
Backplane & Board
Impedance and
Tolerance Effects
Connector
Effect
Partially Loaded
Backplane Effect
Connector
Effect
Stubs
Effect
IC Package
Effect
SiliconSpeed
Effect
Board
Impedance
& Tolerance
Effects
Figure 1: Typical backplane and onboard bus systems
Evans, J.
Sainson, J-M.
CERN, 1211 Geneva 23, Switzerland
John.Evans@cern.ch
J-M.Sainson@cern.ch
Nearest
Neighbour
Receiver
Effect
Some rules of thumb can be applied to try and achieve a
working design. These include:
• A track should be considered as a transmission line
when:
2 tpd≥ tr
where tpd is the propagation delay for an
interconnect length and tr is the signal switching
time.
• For a digital signal with switching time tr, the
equivalent bandwidth is given by:
1 0.
32
F = ⇒
Πtr
tr
Note that this expression is dependent only on
switching speed and not clock frequency.
• For a backplane, the effective loaded transmissionline
characteristic-impedance (Zeff) can be estimated
as [3]:
1
Zeff ≅ Zo
Cload
1+
C
Zo = unloaded transmission-line characteristicimpedance
C = Total unloaded transmission-line capacitance
Cload = Total load capacitance along the backplane
line.
The above guidelines are very useful but insufficient to
ensure a working design. Other rules of thumb exist to
estimate crosstalk and reflections but it becomes impractical
to apply them all to a large design with many nets.
The Cadence SPECCTRAQuest SI Expert suite was
developed to try and overcome these problems. It has three
main components (Figure 2).
SigXplorer has been primarily used at CERN during the
pre-layout stage. It can be used to perform “what if” analyses
and to determine the effects of different design and layout
strategies on signal integrity. While fully integrated into the
Cadence flow, it is simple enough to be used as a standalone
tool.
The program represents a circuit as a number of drivers
and receivers that are linked via interconnects (Figure 3).
The user can explore different placement and routing
strategies and is free to experiment with parameters such as
track impedances and terminations and choice of IC
technology.

CADENCE's
SPECCTRAQuest TM SI expert
(Signal Integrity Analysis Package)
IBIS Models
(Behavioral)
Signal Explorer
(Topology Explorator)
Design
Choice
Layout
Guideline
Concept
(Schematic)
(Front End to Allegro)
Allegro to Front End
(Backannotaion)
Simulation
SPECCTRAQuest
Allegro
(Floor Planer)
(Board Layout)
Layout Check
&
Enhancement
SigNoise
(Behavioral Simulator)
CADENCE's
PCB System Design
Figure 2: Signal Integrity Design Flow
Import
Figure 3: Typical SigXplorer pre-layout analysis
Typical design choices to be considered would be:
• Architecture evaluation (bus, clock tree…)
• Topology exploration
• Standard ICs technologies comparison
• Termination type and value characterization
• Package type selection
• ASICs I/O cells characterization
These preferences are then transferred to the Schematic Editor
before producing an Allegro PCB netlist (Figure 2).
SigXplorer (via the SPECCTRAQuest Floorplanner
/Editor) can verify that simulation results from the routed
PCB correspond to those obtained from the pre-layout
analysis. While using the same simulator in both cases, there
is an important difference between the models used. During
pre-layout analysis, the user specified all relevant parameters
such as line delays and impedances to allow
SPECCTRAQuest to estimate the high-speed signal
phenomena. For post-layout analysis, the program calculates
these values directly from the board layout and stackup using
a built-in 2-D electromagnetic field solver.
For each interconnect type of interest, the simulator
searches its libraries for a corresponding electrical model. If
no appropriate model exists, SPECCTRAQuest automatically
derives one using the field-solver. This is then stored in the
interconnect model library so the calculation is only necessary
once for each specific cross-section.
While not providing the precision of other more
specialised tools e.g. Ansoft’s Maxwell, the solver aims to
provide a good compromise between accuracy and
computation time.
The SPECCTRAQuest SI Expert Simulation environment
is called SigNoise. It embraces tools for entering and editing
device models, simulating the circuit and displaying results.
It uses a SPICE-type simulation engine that incorporates a
lossy, coupled, frequency-dependent transmission line model
valid to the tens of GHz region.
Traditionally, an important shortcoming in the PCB flow
was that there was no formal means of passing design rules
between different stages. The latest SPECCTRAQuest SI
Expert release has seen an extension of the Constraint
Manager application. This tool can manage high-speed
electrical constraints across all stages of the design flow.
These rules can be defined, viewed and validated at any step
from schematic capture to floor planning and to PCB
realization in Allegro. For example, an electrical constraint
can be formally applied in Concept and carried through to the
PCB layout stage. If the layout designer violates this
constraint, it will be automatically flagged as an error. These
new features are currently being evaluated at CERN.
B. IBIS models
SPECCTRAQuest is delivered with a built-in library of
commercial driver and receiver models. However, the user
sometimes needs to define a new device. A SPICE model
could be used to describe fully a driver or receiver at
transistor level but this approach has some serious
disadvantages. One is the impractically long simulation times
that could arise for a large circuit. Another is that IC
manufacturers usually do not wish to disclose proprietary
information regarding their processes.
An alternative approach is to describe devices according to
the Input/Output Buffer Information Specification (IBIS)
modelling standard [4]. Here, only the input and output
stages are modelled and no attempt is made to represent the
internal circuit structure. Two basic models have been
defined for the standard (Figures 4, 5).
Contrary to the SPICE approach, the buffers are described
using behavioural modelling only. A set of tables is used to
represent various characteristics such as output stages pull-up
or pull-down capabilities (using I-V relationships) and the
output switching speed (using a V-t table).
This largely overcomes the disadvantages of the SPICE
approach:
• The system simulates quickly as there is no circuit
detail involved.
• The voltage/current/time relationships are defined
only for the external nodes of the gates. This
conceals both process and circuit intellectual
property.
There are also programs available that can translate a
SPICE netlist to an equivalent IBIS model. These have been
used at CERN to characterise ASICS’ output buffers [5].

Package Parasitic
GND
R_pkg
L
C_pkg
L_pkg
Power_Clamp
Gnd_Clamp
GND
clamp
I-V
Figure 4: IBIS Buffer input stage definition
Ramp up
or
V-t
Ramp down
or
V-t
Vcc
Pullup
I-V
Pullup
Pulldown
GND
Pulldown
I-V
Power
clamp
I-V
Power
Clamp
Ground
Clamp
GND
GND
clamp
I-V
Vcc
Silicon Behaviour
&
Die Parasitics
C_comp
GND
Figure 5: IBIS Buffer output stage definition
Vcc
GND
Power
clamp
I-V
Silicon Behaviour
&
Die Parasitics
C_comp
GND
Package Parasitics
R_pkg L_pkg
C_pkg
II. LHC DETECTORS CASE STUDIES
GND
Die
capacitor
We shall now give examples of how these tools have been
applied during the development of LHC detector electronics.
A. FPGA Bus Design application for ATLAS
LARG ROD Injector module
1) Project Overview
The Read Out Driver Injector module has been designed
to debug the ATLAS Liquid Argon Calorimeter ROD system
[6]. The module emulates the Front End Buffers output data
and generates typical Timing, Trigger and Control signals.
2) Module description
During normal operation, a Front End Buffer module
receives analogue signals from calorimeter cells. After
amplification and shaping, these signals are digitised at 40
MHz sampling frequency and the resulting data sent to the
ROD.
The injector module emulates 4 half-FEBs and the TTC
signals (Figure 6). Each function is implemented in an
ALTERA Flex 10K30E FPGA with data for each function
stored in an associated 32Kwords SRAM memory. The
module is built as a 9U VME64x card with a 16 bits data
VME interface.
There are 3 separate data busses with the following
characteristics:
ALTERA FLEX I/O Cells options?
I/O Voltage (2.5V, 3.3V), slew rate
DATA BUS lines impedance &
type?
Microstrip
Stripline
STUBS maximum length, number
& impedance?
Maximum DATA BUS length?
Is it necessary to split the BUS
in two buses?
� hardware overheads
� more complexity
PCB Board
STACKUP
specifications?
Impedance
Type
Tolerance
VME
INTERFACE
FPGA 7
ALTERA
FLEX 10K30E
High Speed DATA BUS
characteristics:
tr,tf < 500 ps, F = 40 MHz max
TERMINATION type
location and value?
Thevenin
Shunt
RC
..
16 bits
TTC/LOCAL
TTC
RECEIVER
Figure 6: LARG ROD Injector Module
16 bits DATA BUS
16 bits
16 bits
16 bits
16 bits
16 bits
12 bits
16 bits
SLINK
RECEIVER
FPGA 1
ALTERA
FLEX 10K30E
HALF FEB
DATA GEN.
FPGA 2
ALTERA
FLEX 10K30E
FEB1
12
HALF FEB
DATA GEN.
FPGA 3
ALTERA
FLEX 10K30E
12
12 bits
Clock
BCR
L1A
Busy
To ROD
HALF FEB
DATA GEN.
FPGA 4
ALTERA
FLEX 10K30E
FEB2
HALF FEB
DATA GEN.
FPGA 5
ALTERA
FLEX 10K30E
Clock, L1A, BCID,
EVTID
12
12
LHC SEQ.
GEN.
FPGA 6
ALTERA
FLEX 10K30E
• A 12 bit unidirectional data bus links the Timing
generator to the 4 half-FEB generators. Data on this
bus is transferred at 40 MHz.
• A 16-bit bi-directional data bus and a 15-bit
unidirectional address bus (this bus is not explicitly
shown on Figure 7) link these functions to the VME
interface. The busses are sampled at 40 MHz but
data is transferred at VME bus rates.
3) Design choices and layout recommendations
An extensive pre-layout analysis was undertaken on the
system busses and the clock distribution system. This
allowed some significant decisions to be made already at this
early stage.
The analysis was based on a multipoint bus using
ALTERA FLEX 10K30E devices with tf < 500pS. Using the
recommended design choices and layout rules ensures that
signals switch on the first incident wave with at least 500mV
positive noise margin at sampling time. The important
conclusions include:
• It is possible to use a single 300mm long DATA
BUS with these devices if proper termination is used
(see below). This avoids the complication of
splitting the bus into two or more segments.
• Only one termination scheme was found to provide
consistently good results. This was a combination of
an AC termination (R= 100 Ohm, C=1nF) at both
DATA_BUS ends complemented by 4.7 Ohms
STUBS SERIES terminations added near the DATA
BUS. The latter was needed to lower stubs and

•
package impedance effects. DC termination could
not be used as it overloaded the driver fan out
capabilities.
DATA BUS lines impedance and type were
confirmed to be capable of being manufactured as a
class 5, 8-layer PCB. Calculations were made for a
line impedance of 70Ω with a +/- 20 % tolerance –
this was evaluated using SigXplorer’s sweep
parameters functionality.
• Simulations showed that stub lengths could be at
least 10 mm.
• Simulation showed that design was robust enough to
allow working with worst-case driver/receiver
combinations as regards switching speeds and IC
location.
4) Post-layout check before board manufacture
The guidelines were implemented in the PCB layout
phase. Prior to board manufacture, all critical parameters
(time propagation delay, skew, first incident wave, noise
margin) were verified and found to be satisfactory.
5) Module state and future development
A prototype is fully functional and integrated with the
ROD in the current DAQ environment.
B. GTL Bus Design case study for ALICE pixel
chip carrier
1) Project overview
The ALICE Silicon Pixel Detector (SPD) is located within
the Inner Tracking System (ITS) and is the detector with the
highest active channel density. The Pixel Carriers have been
designed to physically support the detector ladders, power
them and to carry signals between the pilot and the readout
chips.
Figure 7: ALICE Pixel Chip Carrier
2) Module description
Figures 7 and 8 show different views of the ALICE pixel
chip carrier [7]. 10 Readout chips are connected to the data
bus by bonding wires. The data is then fed to the I/O Cells
Pilot chip via a series of “vertical” and “horizontal” lines.
3) Design choices and layout considerations
Due to its position in the active area, the board has to be as
transparent as possible to physics particles. This physical
constraint eventually led to a choice of a 200µm thick, 6-layer
aluminium/polymide PCB. This has important implications
for the electrical characteristics. Due to the small PCB
thickness and the need for fine lines, the track impedances
become uncomfortably low compared to the driver impedance
and to its current capabilities. There is also another mismatch
problem as the horizontal and vertical lines have different
characteristic impedances. Detailed analyses were performed
to confirm that the system would still work acceptably under
these sub-optimum conditions. Important design points are:
• The horizontal data-bus microstrip-lines signals were
estimated to have an impedance of 19Ω. The vertical
lines were calculated to be nominally 9Ω.
• For these lines and I/O cells, the optimum pull-up
termination was found to be 22Ω on one end only of
the PCB.
• The PIXEL chip was designed with GTL-like I/O
technology with output-cells switching speeds
selectable from 4 to 30ns. Simulations were made at
4, 7 and 20ns with virtual silicon using IBIS models
created at CERN from the HSPICE netlist.
The complete assembly was fully analysed before delivery
of the Carrier PCB or chips with a full load of 10 pixel chips
for all three switching times. The crosstalk was estimated as
being less than 120mV Root Sum Square.
This figure has not yet been measured on hardware.

Figure 8: ALICE Pixel System Detector
III. CONCLUSIONS
Signal integrity analysis is essential for designing reliable
sub-nanosecond switching-time circuits. We have described
SPECCTRAQuest and shown how it can help with all aspects
of the design flow from circuit design choices to PCB layout.
We have given examples of how it has been used to help in
validating IC technology choice and in developing placement
and routing guidelines for the layout designers.
Future developments will include the deployment of the
“Constraint Manager” to automatically manage high-speed
electrical constraints across all design-flow stages. We also
hope to evaluate the SUN/Cadence “Power Integrity” module
to address the issues of correct power-plane design.
The SPECCTRAQuest SI Expert tools are presently
available at CERN and fully supported by IT/CE-AE [9].
IV. ACKNOWLEDGEMENTS
The authors would like to acknowledge the contributions
of D. Charlet, LAL, M. Morel, CERN/EP and G. Perrot,
LAPP to this paper.
Cadence, SPECCTRAQuest, SigXplorer, SigNoise,
Ansoft and Maxwell are all registered trademarks.
V. REFERENCES
[1] Evans, B.J., Calvo Giraldo, E., Motos Lopez, T.,
‘Electronic Design Automation tools for high-speed electronic
systems’, proceedings of the 6 th Workshop on Electronics for
LHC experiments, Cracow, September 11-15, 2000 pp 393-7
[2] Evans, B.J., Calvo Giraldo, E., Motos Lopez, T.,
‘Minimizing crosstalk in a high-speed cable-connector
assembly’, proceedings of the 6 th Workshop on Electronics for
LHC experiments, Cracow, September 11-15, 2000 pp 572-6
[3] Novak, I., “Design of Clock Networks, Busses and
Backplanes: Measurements and Simulation Techniques in
High-Speed Digital Systems”, CEI Europe Course Notes,
Dublin 1997
[4] IBIS (I/O Buffer Information Specification) ANSI/EIA-
656-A Homepage, http://www.eigroup.org/ibis
[5] SPICE to IBIS Application Notes,
http://cern.ch/support-specctraquest/ (“How to” menu)
[6] Perrot, G., "ROD Injector User Manual", LAPP internal
note, http://wwwlapp.in2p3.fr/
[7] Antinori, F. et al, “The ALICE Silicon Pixel Detector
Readout System”, proceedings of the 6 th Workshop on
Electronics for LHC experiments, Cracow, September 11-15,
2000 pp 105-9
[8] Morel, M. “ALICE Pixel Carrier (A) and (B)”,
http://morel.web.cern.ch/morel/alice.htm
[9] SPECCTRAQuest SI Expert at CERN,
http://cern.ch/support-specctraquest/

Influence of Temperature on Pulsed Focused Laser Beam Testing
P.K.Skorobogatov, A.Y.Nikiforov
Specialized Electronic Systems, 31 Kashirskoe shosse, Moscow, 115409 Russia
pkskor@spels.ru
Abstract
Temperature dependence of radiation-induced charge
collection under 1.06 and 0.53 μm focused laser beams is
investigated in experiment and numerical simulation. The
essential sensitivity of collected charge to temperature was
obtained only for 1.06 μm wavelength.
I. INTRODUCTION
The focused laser sources are widely used for single event
effects (SEE) investigation [1-3]. Laser simulation of SEE is
based on the focused laser beam capability to induce local
ionization of IC structures. A wide range of particle linear
energy transfer (LET) and penetration depths may be
simulated varying the laser beam spot diameter and
wavelength.
The temperature dependence of the laser absorption
coefficient in semiconductor affects the equivalent LET and
must be accounted for when devices are tested at temperature
range [4]. In order to estimate the influence of temperature
on SEE laser testing parameters we have analyzed the
temperature dependence of charge collected in test structure
p-n junction.
In the present study we used a pulsed laser with 1.06 and
0.53 μm wavelengths as a source of focused ionization. The
measurements of p-n junction collected charge were
performed in the temperature range from 22 to 110 °C for
two laser beam spot positions. It was found the essential
influence of temperature on collected charge for 1.06 μm
wavelength and the negligible dependence under 0.53 μm
laser beam.
This effect is associated with the strong temperature
dependence of light absorption in silicon when the photon
energy is near the bandgap [5]. The numerical simulations
with the “DIODE-2D” 2D software simulator confirmed this
assumption.
II. EXPERIMENTAL DETAILS
The experiments were performed using the original
"PICO-2E" pulsed solid-state laser simulator (Nd 3+ passively
mode-locked, basic wavelength λ = 1.06 μm, laser pulse
duration Tp ≈ 8 ps) as a source [6]. The simulator was used in
basic (λ = 1.06 μm) and frequency-double (λ = 0.53 μm)
modes with laser spot diameter of 5 μm.
The investigated test structure is manufactured in a
conventional 2 μm bulk CMOS process and includes wellsubstrate
p-n junction (48x78 μm) with narrow (2 μm)
metallization strips to have a maximum free surface [7]. The
p-n junction collected charge temperature dependence was
measured under laser irradiation for two laser beam locations
as shown in Fig. 1. The first is located within the n-well
(location 1) and the second is localized out of junction area
(location 2).
a)
b)
Figure 1: Cross-sectional (a) and top (b) views of the test structure
The internal chip temperature was monitored with an
additional forward biased p-n junction test chip. The
experimental set-up and temperature monitoring procedures

are described in [8]. The temperature uncertainty was near
5%. The test structures were under 5 V bias. The ionizing
current transient response and collected charge were
registered with a "Tektronix TDS-220" digital oscilloscope.
III. NUMERICAL TO EXPERIMENTAL COMPARATIVE
RESULTS
In order to perform a collected charge analysis of test
structure in a temperature range the "DIODE-2D" software
simulator was used. This is a two-dimensional solver of a
fundamental system of equations that was modified to include
a temperature dependent laser absorption coefficient. It takes
into account the electrical and optical processes including
free carrier nonlinear absorption [9].
The temperature dependencies of semiconductor
parameters such as band gap and intrinsic carrier density
were taken into account in accordance with [10]. The bulk
mobility temperature dependence is described by the function
(T/300) -2.33 for electrons and holes, where T is the Kelvin
temperature. As for low level density carrier lifetimes their
temperature dependencies were modeled by a power law
(T/300) 2 . The Auger recombination coefficients were taken
slightly increasing with temperature in accordance with a 0.2
power law.
The "PICO-2E" laser simulator pulse energy has a
fluctuations from pulse to pulse. To reduce the variations of
laser pulse energy on accuracy the monitoring of every pulse
was performed. The numerical and experimental results are
presented as a dependences of SEE sensitivity coefficient Kq
= ΔQ/W versus temperature. Here ΔQ is a collected charge
in pC and W is a laser pulse energy in nJ.
The SEE sensitivity coefficients vs temperature, both
measured and calculated at laser beam location 1 are
presented in Fig. 2 for the case of 0.53 μm wavelength. This
range of wavelengths is far from bandgap and light
absorption coefficient is practically insensitive to
temperature. The theoretically predicted slight temperature
dependence may be connected with the competition of two
mechanisms: increase of minority charge carriers lifetime
and decrease of their mobility with temperature.
The pulse-to-pulse variation of laser energy during 0.53
μm wavelength experiment was in the range from 0.5 to 1.08
nJ. The 2-order linear regression of experimental data is
presented in Fig. 2 by dashed line.
The SEE sensitivity coefficient vs temperature, both
measured and calculated at laser beam location 1 are
presented in Fig. 3 for the case of 1.06 μm wavelength.
This wavelength is near the bandgap edge and light
absorption coefficient is very sensitive to temperature. The
theoretical prediction gives the approximately doubling of
collected charge in the range from 22 to 110 °C. The
experimental results show that SEE sensitivity increases at
least three times in this temperature range. This difference
between measured and simulated results may be explained by
uncertainties of laser absorption coefficient temperature
dependence near the edge of silicon fundamental band-toband
absorption zone.
Figure 2: Numerical (lines) and experimentally determined (dots)
test structure SEE sensitivity coefficient vs temperature at laser
beam location 1 for 0.53 μm wavelength
Figure 3: Numerical (lines) and experimentally determined (dots)
test structure SEE sensitivity coefficient vs temperature at laser
beam location 1 for 1.06 μm wavelength
The pulse-to-pulse variation of laser energy during 1.06
μm wavelength experiment was in the range from 2.3 to 4.5
nJ per pulse.
The experiment and calculations for laser beam location
in other surface points (both inside and outside of p-n
junction) give the similar results.
The obtained results are in a good agreement with those
described in our previous paper [5] for dose rate effects
simulation with non-focused 1.06 μm laser irradiation. The

collected charge temperature dependence under focused laser
beam is similar to that of ionizing current amplitude under
non-focused nanosecond laser pulse.
IV. CONCLUSIONS
Temperature dependence of charge collection in silicon
IC’s under 1.06 and 0.53 μm focused laser beams was
investigated in application to Single Event Effect simulation
in CMOS test structure.
It was shown that in the case of 0.53 μm laser irradiation
the temperature practically does not affect the collected
charge because of slight laser absorption coefficient
temperature dependence in this range. The theoretically
predicted variations of collected charge may be explained by
carrier lifetime and mobility temperature dependences.
In the case of 1.06 μm laser irradiation the theory and
experiment have shown the essential growth of collected
charge with temperature. It is corresponds with strong laser
absorption coefficient temperature dependence for photon
energy near the bandgap. The theoretical prediction gives the
approximately doubling of collected charge in the range from
22 to 110 °C. The experimental results show that SEE
sensitivity increases at least three times in this temperature
range. The difference between measured and simulated
results may be explained by uncertainties of laser absorption
coefficient temperature dependence near the edge of silicon
fundamental band-to-band absorption zone.
The results obtained prove that the temperature
dependence of the laser absorption coefficient in
semiconductor affects the equivalent LET and must be taken
into accounted in devices SEE selection for LHC electronic.
V. REFERENCES
[1] C.F.Gosset, B.W. Hughlock, A.H.Johnston, "Laser
simulation of single particle effects", IEEE Trans. Nucl.
Sci., vol. 37, no.6, pp. 1825-1831, Dec. 1990.
[2] R. Velazco, T. Calin, M. Nicolaidis, S.C Moss, S.D.
LaLumondiere, V.T. Tran, R. Kora, “SEU-hardening
storage cell validation using a pulsed laser”, IEEE Trans.
Nucl. Sci., vol. 43, no.6, pp. 2843-2848, Dec. 1996.
[3] J.S. Melinger, S. Buchner, D. McMorrow, W.J. Stapor,
T.R Wetherford, A.B. Campbell and H. Eisen, “Critical
evaluation of the pulsed laser method for single-event
effects testing and fundamental studies”, IEEE Trans.
Nucl. Sci., vol. 41, no.6, pp. 2574-2584, Dec. 1994.
[4] A.H. Johnston, "Charge generation and collection in p-n
junctions excited with pulsed infrared lasers", IEEE
Trans. Nucl. Sci., vol. 40, no. 6, pp. 1694 - 1702, Dec.
1993.
[5] P.K. Skorobogatov, A.Y. Nikiforov, A.A. Demidov, V.V.
Levin, “Influence of temperature on dose rate laser
simulation adequacy”, IEEE Trans. Nucl. Sci., vol. 47,
no.6, pp. under publication, Dec. 2000.
[6] A.I. Chumakov, A.N. Egorov, O.B. Mavritsky, A.Y.
Nikiforov, A.V. Yanenko, “Single Event Latchup
Threshold Estimation Based on Laser Dose Rate Test
Results”, IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2034
- 2039, Dec. 1997.
[7] P.K. Skorobogatov, A.Y. Nikiforov and A.A. Demidov,
“A way to improve dose rate laser simulation adequ
IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2659 - 2664,
Dec. 1998.
[8] A.Y. Nikiforov, V.V. Bykov, V.S. Figurov A.I.
Chumakov, P.K. Skorobogatov, and V.A.Telets "Latch-up
windows tests in high temperature range" in Proceedings
of the 4th Europ. Conf. "Radiations and Their Effects on
Devices and Systems, Cannes, France, Sept. 15-19, 1997,
pp. 366-370.
[9] A.Y. Nikiforov and P.K. Skorobogatov, "Dose rate laser
simulation tests adequacy: Shadowing and high intensity
effects analysis", IEEE Trans. Nucl. Sci., vol. 43, no.6,
pp. 3115-3121, Dec. 1996.
[10] S.M. Sze, Physics of Semiconductor devices. 2-nd ed.
John Wiley & Sons, N.Y., 1981.

The Behavior of P-I-N Diode under High Intense Laser Irradiation
P.K.Skorobogatov, A.S.Artamonov, B.A.Ahabaev
Specialized Electronic Systems, Kashirskoe shosse, 31, 115409, Moscow, Russia
pkskor@spels.ru
Abstract
The dependence of p-i-n diode ionizing current amplitude
vs 1.06 μm pulsed laser irradiation intensity is investigated.
It is shown that the analyzed dependence becomes nonlinear
beginning with relatively low laser intensities near 10
W/cm 2 .
I. INTRODUCTION
Pulsed laser sources are widely used for dose rate effects
simulation in IC’s [1]. The Nd:YAG laser with 1.06 μm
wavelength is nearly ideal for silicon devices, with a
penetration depth near 700 μm [2]. The measurements of
pulsed laser irradiation intensity and waveform monitoring
may be provided with p-i-n diode. High electric field in its
intrinsic region provides the full and fast excess carriers
collection. As a result the ionizing current pulse waveform
repeats the laser pulse within the accuracy of several
nanoseconds.
Possible nonlinear ionization effects may disturb the
behavior of p-i-n diode at high laser intensities. Here we
present the results of the recent study of typical p-i-n diode
using 2D numerical simulation and a pulsed laser simulator
with the 1.06 μm wavelength as a radiation source.
II. P-I-N DIODE STUDY
The typical p-i-n diode with a intrinsic region 380 -
micrometers thick at 300 V reverse bias was investigated. Pi-n
diode cross-section is shown in Fig. 1. The sensitive area
size is 2.3x2.3 mm. The p+ and n+ regions of diode are
doped up to 10 19 cm –3 .
To investigate the p-i-n diode possibilities at high laser
intensities the original software simulator “DIODE-2D” [3]
was used. The “DIODE-2D” is the two-dimensional solver of
the fundamental system of equations. It takes into account
carrier generation, recombination and transport, optical
effects, carrier’s lifetime and mobility dependencies on
excess carriers and doping impurity concentrations.
The calculated p-i-n diode ionizing current pulse
amplitude vs laser intensity dependence under 300 V reverse
bias is presented in Fig. 2. The radiation pulse waveform was
taken as “Gaussian” with 11 ns duration. One can see that
the direct proportionality between current pulse amplitude
and laser intensity takes place only at relatively low
intensities (up to 10 W/cm 2 ). The ionization distribution
nonuniformity connected with laser radiation attenuation
does not affect the dependence because of relatively low
excess carrier density is not enough to sufficiently change the
absorption coefficient.
Figure 1: P-i-n diode cross-section
Figure 2: P-i-n diode ionizing current pulse amplitude vs laser pulse
intensity dependence
The non-linearity is caused by the modulation of p-i-n
diode intrinsic region by excess carriers. Because of low level
of initial carriers concentration the modulation takes place at
relatively low dose rates. As a result of modulation the
distribution of electric field in the intrinsic region becomes
non-uniform that leads to decrease of excess carriers
collection. This proposal is confirmed by results of potential
distribution calculations for different laser peak intensities
presented in Fig. 3.

Figure 3: Potential distributions at time 11 ns for different
maximum laser intensities: initial (a), 10 2 (b) and 10 3 (c) W/cm 2
a)
b)
c)
The behavior of p-i-n diode becomes similar to that of
ordinary p-n junction with prompt and delayed components
of ionizing current. The prompt component repeats the laser
intensity waveform. The delayed component is connected
with the excess carriers collection from regions with low
electric fields. As a result, the ionizing current pulse form
becomes more prolonged and doesn’t repeat the laser pulse
waveform.
Fig. 4 shows the normalized calculated ionizing current
pulse waveforms for different maximum laser intensities. At
relatively low intensity the current pulse waveform repeats
the appropriate laser pulse waveform. At high intensities we
see the delayed components.
The non-linear nature of behavior and prolonged reaction
must be taken into account when p-i-n diode is used as a
laser intensity and waveform dosimeter.
Figure 4: Normalized calculated ionizing current pulse waveforms
for different maximum laser intensities:10 (1), 10 2 (2) and 10 3 (3)
W/cm 2
III. NUMERICAL TO EXPERIMENTAL COMPARATIVE
RESULTS
The numerical results were confirmed by experimental
measurement of p-i-n diode ionizing reaction within a wide
range of laser intensities.
The pulsed laser simulator "RADON-5E" with the 1.06
μm wavelength and 11 ns pulse width was used in the
experiments as a radiation source [4]. The laser pulse
maximum intensity was varied from 6· 10 2 up to 2.1· 10 6
W/cm 2 with laser spot size covering the entire chip. It
provides in silicon the equivalent dose rates up to 10 12
rad(Si)/s. The p-i-n diode ionizing current transient response
was registered with the "Tektronix TDS-220" digital
oscilloscope.
The comparative p-i-n diode ionizing current pulse
amplitude vs laser intensity dependencies under 300V reverse
bias are presented in Fig. 5. The upper limit of laser
intensity is restricted by p-i-n diode failure possibility.
One can see that the experimental results confirm the
non-linear behavior of p-i-n diode at intensities above 10 1
W/cm 2 . The reduction of reverse voltage increases the nonlinear
effects.
As for the distortion of pulse waveform at high laser
intensities it was also confirmed. The experimental p-i-n
diode current pulse waveforms are represented in Fig. 6. At
the maximum intensity 1.3 W/cm 2 the current pulse
waveform repeats the laser irradiation one. At an intensity of
27 W/cm 2 we can see prolonged behavior though this
intensity corresponds to only 3,4 10 7 rad(Si)/s equivalent
dose rate.

Figure 5: Numerical (line) and experimentally determined (dots) pi-n
diode ionizing current amplitude vs laser intensity
a)
b)
Figure 6: P-i-n diode ionizing current waveforms under laser pulses
with 1.3 (a) and 27 (b) W/cm 2 maximum intensities
IV. CONCLUSION
The simulation and experiments under p-i-n diode
structure have shown that linear dependence between pulsed
laser intensity and ionizing current pulse amplitude is valid
only at relatively low intensities up to 10 W/cm 2 . In the field
of high intensities this dependence becomes non-linear and
ionizing current increases more slowly than laser intensity.
The ionizing current pulse form becomes more prolonged
and does not repeat the laser pulse waveform.
The non-linear nature of behavior and prolonged reaction
must be taken into account when p-i-n diode is used as a
laser intensity and pulse waveform dosimeter in LHC
experiments.
V. REFERENCES
[1]. P.K. Skorobogatov, A.Y. Nikiforov B.A. Ahabaev
“Laser Simulation Adequacy of Dose Rate Induced Latchup”//Proc.
4th European Conf. on Radiations and Its Effects
on Components and Systems (RADECS 97), Sept. 15-19,
1997, Palm Beach, Cannes, France. P. 371-375.
[2]. A.H. Johnston “Charge Generation and Collection in p-n
Junctions Excited with Pulsed Infrared Lasers”//IEEE Trans.
1993. Vol. NS-40, N 6. P. 1694 - 1702.
[3]. The "DIODE-2D" Software Simulator Manual Guide,
SPELS, 1995.
[4]. "RADON-5E" Portable Pulsed Laser Simulator:
Description, Qualification Technique and Results, Dosimetry
Procedure/A.Y. Nikiforov, O.B. Mavritsky, P.K.
Skorobogatov et all//1996 IEEE Radiation Effects Data
Workshop. P. 49-54.

Estimating induced-activation of SCT barrel-modules
C. Buttar, I. Dawson, A. Moraes
Department of Physics and Astronomy, University of Sheffield,
Hicks Building, Hounsfield Road, Sheffield, S3 7RH, UK
c.m.buttar@sheffield.ac.uk, Ian.Dawson@cern.ch, a.m.moraes@sheffield.ac.uk
Abstract
Operating detector systems in the harsh radiation environment
of the ATLAS inner-detector will result in the production
of radionuclides. This paper presents the findings
of a study in which the radioactivation of SCT barrel modules
has been investigated.
I. INTRODUCTION
One of the consequences of operating detector systems
in the harsh radiation environments of the ATLAS innerdetector
[1] will be the radioactivation of the components.
If the levels of radioactivity and corresponding dose rates
are significant, then there will be implications for any access
or maintenance operations. In addition, maintenance
operations may be required on nearby detector or machine
elements, for example beam-line equipment, so the impact
of the SCT has to be considered. A further motivation
for understanding SCT activation concerns the eventual
storage or disposal of the SCT-modules at the end of the
detector lifetime, in which any radioactive material will
have to be classified.
Radionuclides are produced in the SCT modules via
the inelastic interactions of hadrons with the various target
nuclei comprising the modules. The hadrons originate
from: 1) secondaries from the p-p collisions, dominated
by pions, and 2) backsplash from hadron cascades in the
calorimeters, mainly neutrons. Therefore, the calculation
of radionuclide production requires a detailed inventory of
the target-nuclei comprising the SCT modules and a good
knowledge of the corresponding radiation backgrounds.
II. MODULE DESCRIPTION AND
MATERIAL INVENTORY
In order to make activation estimates, it is necessary
to obtain a detailed inventory of the materials involved in
the construction of a module. The relevant information is
now becoming available as SCT modules go into the production
phase [2]. Of particular importance is knowledge
of elements containing isotopes with high neutron capture
cross sections. For example, ��Au has a thermal neutron
capture cross section � 100 b for the (n,­) process and even
small quantities of such an isotope can contribute considerably,
or even dominate the activated environment.
In the SCT barrel system there are 4 layers of cylinders,
comprising 32, 40, 48 and 56 rows of 12 modules respectively.
Each SCT barrel module comprises silicon sensors,
baseboard with BeO facings, ASICs and a Cu/polymide
hybrid [3], connected to opto-packages and dog-legs [4].
Each row of modules has associated with it a cooling
pipe [5] and power tape. In total, the module mass is calculated
to weigh 34.6 g and contain 15 different elements.
Details of the elemental breakdown are given in Table 1.
Unfortunately, material details are not always given
in their elemental form and sometimes have to be derived.
Assumptions are therefore unavoidable and include:
1) Thermal adhesives assumed to be 70% polyimide and
30% BN; 2) Epoxy films, polyimide layers with adhesives
and PEEK are chemically described as C H N O�; 3) The
solder composition is assumed to be 59% Pb, 40% Sn and
1%Ag; 4) Capacitors made of AlO and resistors 20% C and
80% AlO. Perhaps the most important assumption concerns
the possible use of silver loaded conductive glues.
Silver is important due to the high thermal neutron capture
Ñ cross section and long half-life of Ag. In the current
study no silver has been assumed in the glues.
III. RADIONUCLIDE PRODUCTION
Radionuclides are produced in the SCT modules via the
inelastic interactions of hadrons with the various target nuclei
comprising the modules. However, radionuclides with
short half-lifes can be neglected as access to the irradiated
SCT material is unlikely for at least several days. In the
current study, radionuclides are only considered of radiological
interest if they have half-lifes greater than 1 hour
and less than 30 years.
Radionuclide production can be divided into two categories:

Elements Silicon
sensors
Table 1: Table of barrel module element masses.
Baseboard
with BeO
facings
ASIC’s Hybrid Cooling
pipe with
coolant
Power
tape
Opto Package
/ Dog
Leg
Total �
À 0.001 0.008 0.004 0.034 - 0.012 0.035 0.094
�� - 0.597 - - - - - 0.597
� 0.010 0.054 0.027 0.185 - - - 0.276
� 0.037 4.672 0.099 3.024 0.821 0.306 0.926 9.885
Æ 0.017 0.092 0.045 0.311 - 0.032 0.324 0.821
Ç 0.011 1.119 0.037 0.442 - 0.093 0.304 2.006
� - - - - 3.462 - - 3.462
�Р- 0.118 0.028 0.393 1.166 0.78 0.434 2.919
� 10.812 - 0.742 0.187 - - 0.029 11.770
� - - - 0.025 - - 0.015 0.040
�Ù - - - 1.501 - - 1.071 2.572
�� - - - 0.001 - - 0.0004 0.0014
ËÒ - - - 0.049 - - 0.012 0.061
�Ù - - - 0.011 - - - 0.011
� - - - 0.073 - - 0.024 0.097
Total � 10.888 6.660 0.982 6.236 5.449 1.223 3.174 34.612
1. Production via low energy (� 20MeV) neutron interactions,
eg (n,­), (n,p), (n,«), (n,np) etc.. The cross sections
for these neutron interactions are well known
for the target nuclei being considered [6]. The production
probability for each radionuclide of interest,
per target nuclei, can be obtained by convolving the
energy dependent cross sections with neutron energy
spectra. The radiation environment of the SCT environment
has previously been studied [1] and neutron
energy spectra obtained. According to these studies,
thermal neutrons account for more than a half of the
total neutron fluences in and around the SCT barrel
system. In the current study, the radionuclide production
probabilities were evaluated for all the lowenergy
neutron interactions and, as expected, the
dominant process was found to be thermal-neutron
capture (n,­).
Values of radionuclide production per p-p event per
module from (n,­) interactions are obtained simply
from Ò�� where Ò is the number of atoms of a given
isotope in the module and � is the corresponding
thermal neutron cross section, obtained from [7]; � is
the thermal neutron fluence which, according to [1],
has the value 2 ¢ 10 � ncm s over the whole SCT
barrel system. It should be noted, however, that the
inner detector thermal neutron rates are likely to be
smaller in reality than those predicted in the original
fluence simulations. This is because elements such as
boron, xenon, silver, gold etc., which have very high
thermal neutron capture cross sections, had not been
included.
2. High energy inelastic interactions, or spallation. Unlike
neutron interactions, radionuclide production
cross sections from spallation are not available for
all the target nuclei, and are often scarce for particles
such as pions. In this study, hadron interaction
models in the Monte Carlo particle transport code
FLUKA is used [8]. The results then depend on the
quality and coverage of the physics models, in particular:
nuclear evaporation, the intranuclear cascade,
nuclear fission and nuclear fragmentation. Of these
the first three are considered to be well modelled
but fragmentation, which is important for the heavier
target nuclei, is not included in the code. The
general features of residual-nuclei production predicted
by FLUKA are in reasonable agreement with
experimental data [9], exept for light-nuclei production
from heavy targets where fragmentation effects
start showing up. Fortunately, the bulk of the target
nuclei in SCT modules are in the light to medium
mass range.
IV. EVALUATING ACTIVITY
Knowledge of the various radionuclide production
rates along with their half-lifes allows the calculation of radioactivities;
defined as the number of decays per second.
The build-up and decay of activity, for each radionuclide,
is given by:
� � Æ� � �Ø� �Ø
� (1)
where t� and t are irradiation and cooling times respectively.
Æ is the number of produced radionuclides per p-p
event per module, � is the average number of p-p events
per second and � is the decay constant. In going from
radionuclide production per p-p event to activity, it is necessary
to make certain assumptions about the p-p event
rates. The design luminosity of the LHC is 10 � cm s ,

esulting in a p-p interaction rate of 8¢10 � s as predicted
by PHOJET [10]. However, the average luminosity
over longer timescales will be less due to beam-lifetimes
(a) (b)
etc. and an averaged luminosity value of 5¢10 cm s
is assumed [11].
Figure 1: Dominant activities produced by (a) (n,­) interactions and (b) spallation.
Shown in Figure 1 are the dominant contributions to activation
from (n,­) and spallation reactions. Presented in
Table 2 are activities obtained 1 day, 1 week and 1 month
after shutdown, for the two cases of one-year of highluminosity
running and ten-years of high luminosity running.
A high-luminosity year is defined as 180 days
of running (assuming the average beam-luminosity of
5 ¢ 10 cm s ) followed by 185 days of shutdown.
�­ � ���
��
�ËÚ�� (2)
where � is the activity in MBq, � is the sum of ­ energies
in MeV weighted by their emission probabilities and � is
the distance from the source in metres. The above formula
is valid for photons in the range 0.05 to 2 MeV, which is the
range covering most of the emitted ­s.
Using the activity values given in Table 2 and the relevant
gamma decay and energy information, the total
gamma dose is obtained by summing the contributions
from each radionuclide calculated using equation 2 above.
The results are given in Table 3.
V. CALCULATING DOSE RATES
B. Dose rates from ¬-emitters
The dose rate �¬ from a ¬-emitting nuclide can be approximated
[12] by:
Dose rates are obtained at distances of 10 cm, 30 cm and
100 cm from the centre of a barrel-module. The calculations
�¬ �
�
�
�ËÚ�� (3)
are facilitated by assuming each module is a point source
of radioactivity. This assumption is good for the distances
larger than the dimensions of the module (ie 30 cm and
100 cm) and will be conservative by some � 30 % for the
value obtained at 10 cm.
This expression assumes no absorption of the ¬s, which
can be appreciable depending on the ¬ energy. For example,
the average ¬ energy in H decay is 5.68 keV. The
range in air of such ¬s is a few mm and will not contribute
to external ¬-doses. However, most of the emitted ¬s have
A. Dose rates from ­-emitters
much higher energies, with ranges in air going up to several
metres. In order to avoid overly overestimating the
The dose rate �­ from a ­-emitting nuclide can be ob- ¬-doses, the maximum ranges in air of all ¬-emitters have
tained [12], for a point source, from:
been obtained and, if the range is shorter than the distance
at which the dose is calculated, then it is not included in
the total ¬-dose estimate. The results are given in Table 3.
The above strategy will still overestimate ¬-doses for two
reasons; 1) the ranges are obtained assuming the maximum
¬-energy and 2) self-shielding of the module material has
been neglected. However, the emphasis of the ¬-dose calculations
is to provide reliable upper-limits.

Table 2: Dominant radionuclides contributing to module activity.
180 days irradiation 10 years irradiation
cooling times cooling times
Radionuclide 1day 1week 1month 1day 1week 1month
H 477.87 477.43 475.74 3759.17 3755.69 3742.42
� B 4139.23 3828.54 2838.78 4175.48 3862.06 2863.64
Na 476.32 474.59 466.35 1894.87 1886.59 1855.19
� Na 505.16 0.64 - 505.16 0.64 -
Si 3.78 - - 3.78 - -
P 13.31 9.95 3.26 13.31 9.95 3.26
�� V 45.20 34.97 13.07 45.35 35.01 13.11
�� Mn 114.69 113.18 107.55 206.61 203.88 193.74
�� Co 106.19 100.73 82.28 110.65 104.96 85.74
�� Co 153.14 150.81 142.19 252.27 248.43 234.23
�� Co 541.38 510.49 407.57 557.01 525.23 419.33
�� Fe 51.79 47.17 32.97 51.97 47.33 33.08
� Co 14.24 14.21 14.09 84.72 84.54 83.85
�� Cu 22114.09 8.54 - 22114.09 8.54 -
Ñ Ag 253.97 249.78 234.35 398.90 392.32 368.07
Sn 9.81 9.64 8.24 11.04 10.65 9.27
Sn 3.10 3.01 2.66 3.61 3.50 3.09
� Sn 65.14 42.32 8.09 65.14 42.32 8.09
�� Au 5260.37 1127.36 3.07 5260.37 1127.36 3.07
C. Dose rates from Bremsstrahlung
While most of the energy of electrons or positrons
is lost through ionisation, there will also be some
bremsstrahlung, depending on the energy of the particle
and the atomic number Z of the absorbing medium. According
to [13], the total bremsstrahlung dose rate from a
point source is given by the equation:
� ¢ � �� Ñ
�
� Á � �ËÚ�� (4)
where � and � are as before, � Ñ is the maximum ¬ energy
in MeV, Á takes into account internal bremsstrahlung
and � is the mass energy absorption coefficient of x-rays in
cm g . Assuming values of 7, 5 and 0.03 for �, Á and �
respectively [13] for bremsstrahlung in air, it can be seen
that equation 4 remains several orders of magnitude lower
than equation 4 for all distances and energies. Dose rates
from bremsstrahlung can therefore be neglected.
D. Total dose rates
for whole barrel system
It is also of interest to estimate dose rates for the entire
SCT barrel system. This has been done assuming every
module in the barrel system is a point source of identical
activation. While this assumption is reasonable for the
(n,­) activation, it will overestimate spallation related dose
rates as the relevant particle rates are higher in the first SCT
barrel than in the other three barrels. Two ‘access scenarios’
are considered, shown in Figure 2; the corresponding
results are given in Tables 4 and 5.
Table 3: Total ­ (¬) dose rates (�Sv/h) resulting from the activation of a single barrel module.
180 days irradiating 10 years irradiating
Distance cooling times cooling times
from the source 1day 1week 1month 1day 1week 1month
10 cm 0.161 (28.1) 0.049 (1.3) 0.037 (0.13) 0.215 (28.4) 0.102 (1.4) 0.089 (0.24)
30 cm
1m
0.018 (3.1)
1.61¢10 (0.28)
0.005 (0.15)
0.49¢10 (0.013)
0.004 (0.015)
0.37¢10 (0.001)
0.024 (3.3)
2.15¢10 (0.28)
0.011 (0.16)
1.02¢10 (0.013)
0.010 (0.027)
0.89¢10 (0.001)
VI. CONCLUSIONS
Concerning (n,­) activation the dominant radionuclides
are �� Cu, �� Au and Ñ Ag (see Figure 1). However,
�� Cu and �� Au have half-lifes of 12.7 hours and 2.7 days
respectively. Therefore, assuming access cannot be made
to the SCT within 1 week of shutdown, module activity
Ñ will be dominated by the Ag which has a half-life of
249.9 days. Considering the small amount of silver as-

(a)
1.50m
r 0
r
Figure 2: Considered access scenarios (a) Scenario 1 and (b) Scenario 2.
sumed in the module construction (� 1 mg), it is clear that
a design using a higher silver content will result in a proportional
increase in activities.
Concerning spallation induced activation, the dominant
radionuclides are H, � Be and Na. However, when
considering external dose rates from activation, H can be
neglected as discussed in Section V.B. Also, � Be only decays
� 10% of the time into gammas, leaving Na as the
most important radionuclide resulting from spallation. Interestingly,
the target nuclei mainly responsible for Na
production is silicon and is therefore unavoidable.
Inspection of Table 3 shows that even after 10 years
of LHC running and at a distance of 10 cm, the module
­-doses will be about � 0.1 �Sv/h. The corresponding
¬-doses (Table 3) are much higher but after 1 week
drop to about 1 �Sv/h. According to the CERN radiation
safety manual [14], dose rates less than 0.1 �Sv/h at 10 cm
are considered non-radioactive, while dose rates above
0.1 �Sv/h but less than 10 �Sv/h at 10 cm are considered
slightly-radioactive. These low dose rates mean that if
(b)
Table 4: Maximum ­ (¬) doses (�Sv/h) for Scenario 1.
extraction were necessary then modules could be stored
simply in supervised areas [14]. After a cool down period of
one month, ­-dose and ¬-dose values of � 0.1 �Sv/h and
0.24 �Sv/h at 10 cm are given respectively. These values
are similar to those of natural background activity.
Inspection of Tables 4 and 5 show that dose rates from
the barrel ensemble will approach 10 �Sv/h at 10 cm after a
1 month cool-down time. As the predicted values are considered
upper-limits, if barrel extraction were necessary
then it would probably only need be kept in a supervised
area. If the dose rates were higher than 10 �Sv/h but less
than 100 �Sv/h then the barrel ensemble would have to be
stored in a ‘controlled’ area [14].
Finally, it should be stressed that the current study has
assumed a low-silver module design. If the silver content
is much higher, as would be the case if silver-loaded conductive
glues are used, then the results concerning Ñ Ag
should be scaled accordingly. However, the radiological
implications would have to be reevaluated.
180 days irradiating 10 years irradiating
Approaching cooling times cooling times
point 1day 1week 1month 1day 1week 1month
10 cm 6.2 (1084) 1.9 (50) 1.4 (4.1) 8.3 (1088) 3.9 (53) 3.4 (7.4)
30 cm 4.0 (695) 1.2 (32) 0.92 (2.4) 5.3 (697) 2.5 (34) 2.2 (4.1)
100 cm 1.3 (184) 0.38 (9.5) 0.29 (0.35) 1.7 (184) 0.79 (9.6) 0.69 (0.47)
Table 5: Maximum ­ (¬) doses (�Sv/h) for Scenario 2.
180 days irradiating 10 years irradiating
Approaching cooling times cooling times
point 1day 1week 1month 1day 1week 1month
10 cm 9.2 (1598) 2.8 (74) 2.1 (6.4) 12 (1603) 5.8 (79) 5.1 (12)
30 cm 5.1 (888) 1.6 (41) 1.2 (3.4) 6.8 (891) 3.2 (43) 2.8 (5.7)
100 cm 1.5 (254) 0.45 (11) 0.34 (0.48) 1.99 (254) 0.95 (12) 0.83 (0.66)
r 0
z
y
x

VII. REFERENCES
[1] I.Dawson, Review of the Radiation Environment in
the Inner Detector, ATL-INDET-2000-006
[2] SCT Barrel Module, Final Design Reviews: SCT-BM-
FDR-1, SCT-BM-FDR-2, SCT-BM-FDR-3 and SCT-
BM-FDR-4. Available from:
http://atlasinfo.cern.ch/Atlas/GROUPS/INNER
DETECTOR/SCT/module/SCTbarrelmod.html
[3] Table of material for the Cu/Polyimide hybrid
12 �Ñ Copper, version 4. Available from:
http://jsdhp1.kek.jp/�unno/si hybrid/k4/
KhybridXo01feb26.pdf
[4] Private communication, T.Weidberg
[5] T.Niinikoski, Evaporative Cooling - Conceptual Design
for ATLAS SCT, ATL-INDET-98-214
[6] Evaluated Nuclear Data Files (ENDF), obtained
from: http://www-nds.iaea.org/ndsstart.html
[7] Chart of the Nuclides, produced by Knowles Atomic
Power Laboratory; 14th edition - revised to April
1988. (Using National Nuclear Data Center (NNDC)
files.)
[8] A.Fasso, A.Ferrari, J.Ranft and P.Sala, Full details
can be found at FLUKA official website;
http://fluka.web.cern.ch/fluka/
[9] A.Ferrari and P.Sala, The Physics of High Energy Reactions,
ATLAS Internal note, PHYS-NO-113, 1997
[10] R.Engel and J.Ranft, Hadronic photon-photon interactions
at high-energies, Physics. Rev. D54:4244-4262,
1996
[11] K.Potter and G.Stevenson, Average Interaction Rates
for Shielding Specification in High Luminosity LHC Experiments,
CERN AC/95-01, CERN/TIS-RP/IR/95-
05.
[12] K.J.Connor and I.S.McLintock, Radiation Protection,
HHSC Handbook No. 14, 1997, ISBN 0-94237-21-X
[13] I.S.McLintock, Bremsstrahlung from Radionuclides,
HHSC Handbook No. 15, 1994, ISBN 0-948237-23-6
[14] Radiation Safety Manual, CERN – TIS/RP, 1996

Development of a DMILL radhard multiplexer for the ATLAS Glink optical link and
radiation test with a custom Bit ERror Tester.
Daniel Dzahini, on behalf of the ATLAS Liquid Argon Collaboration
Abstract
A high speed digital optical data link has been developed for
the front−end readout of the ATLAS electromagnetic
calorimeter. It is based on a commercial serialiser commonly
known as Glink, and a vertical cavity surface emitting laser.
To be compatible with the data interface requirements, the
Glink must be coupled to a radhard multiplexer that has been
designed in DMILL technology to reduce the impact of
neutron and gamma radiation on the link performance. This
multiplexer features a very severe timing constraints related
both to the Front−End Board output data and the Glink
control and input signals. The full link has been successfully
neutron and proton radiation tested by means of a custom Bit
ERror Tester.
I) INTRODUCTION
The Liquid Argon Calorimeter of the ATLAS experiment
at the LHC is a highly segmented particle detector with
approximately 200 000 channels. The signals are digitized
on the front−end board and then transmitted to data
acquisition electronics located 100m to 200m away. The
front−end electronics has a high degree of multiplexing
allowing the calorimeter to be read out over 1600 links each
transmitting 32 bits of data at the bunch crossing frequency
of 40.08 Mhz. The radiation hardness is a major
consideration in the design of the link, since the emitter side
will be exposed to an integrated fluence of 3*10 13 n(1MeV
Si) over 10 years of the LHC running.
II) OPTICAL LINK DESCRIPTION
The demonstrator link is based on an Agilent
Technologies HDMP1022/1024 serialiser/deserialiser. This
Glink is used in a double frame mode: the incoming
digitized data of 32 bit at 40.08 Mhz are multiplexed and
sent as two separate 16 bit frame segments at 80.16Mhz with
the use of an external multiplexer. The Glink chip set adds a
4 bit control field to each 16 bit data segment which results
in a total data transfert rate of 1.6 Gb/s (see figure 1).
Institut des Sciences Nucléaires
53 avenue des Martyrs,38026 Grenoble Cedex France
80.16 MHz
Transmitting end
32
Data
1.6 Gb/s
Methode
Transceiver
Tx Rx
40.08 MHz
16
HDMP-1022
Serialiser
Not Used
Latch+MUX
40.08 MHz
Radiation
80.16 MHz
Receiving end
Not Used
Methode
Transceiver
HDMP-1024
Deserialiser
Figure 1:A 1.6Gb/s optical link based on the G−link chipset.
The Glink serialiser outputs drive a VCSEL that transforms
the electrical signal into light pulses transmitted over a
Graded Index (GRIN) 50/125 mm multimode fibre to a PIN
diode located on the receiver board. For the link described in
this document the VCSEL and the PIN diode are packaged
together with driving and discriminating circuits as
transceiver modules manufactured by Methode. The PIN
diode output signals are deserialised by the GLINK receiver
chip (HDMP1024), then a Programmable Logic Array
(ALTERA EMP7128) is used for demultiplexing the 16 bits
data into the basic 32 bits format.
III ) MULTIPLEXER CHIP
The Glink is used in a double frame mode so that the full
link has the capability to transfer the 32 bit format data
(figure 2).
No Radiation
Figure 2: The Glink chipset in a double frame mode.
Tx
32
Data
Rx
1.6 Gb/s
16
MUX Tx Rx
DEMUX
CLK
CLK
DeMUX+Latch
40.08 MHz

LHC_CLK
DATA_L[15..0]
DATA_VALID_L
DATA_H[15..0]
DATA_VALID_H
16
16
Figure 3 The multiplexer block diagram.
This configuration requires an external multiplexer. One
can see in figure 3, the block diagram of the multiplexer
ASIC (MUX). Since this chip must be located on the FEB
board, it must be radiation hard, thus the design was done in
the radhard DMILL technology.
Figure 4: Schematic of the multiplexer
DAV_L, DAV_H
DATA_L [15..0]
DATA_H [15..0]
STRBOUT
STRBIN
STRBIN
FLAG
DAV_L, DAV_H
DATA_L [15..0]
DATA_H [15..0]
GL [15..0]
STRBOUT
TTL to CMOS
LVDS to CMOS
17
17
TTL to CMOS
REGISTER[33..0]
L
2:1 GL [15..0]
H MUX
t s
FLAG
1/2 FRAME
PERIOD
t s = SETUP TIME
t h = HOLD TIME
GL[15..0]
Figure 5: Transmitter data interface and timing constraints.
17
17
t h
t strb
MUX
PLL
17
1/2 FRAME
PERIOD
t s
REGISTER[17..0]
16
Transmitter
HDMP-1022
t h
t mux
DATA_L [15..0] DATA_H [15..0]
t s t h t s t h
DAV
STROBIN
FLAG
STROBOUT
HDMP1022
t strb = STRBIN TO STRBOUT DELAY
t mux = 2:1 MULTIPLEXER DELAY
The data signals sent to the multiplexer have a LVDS
logic standard, therefore the first stage of the MUX chip is a
LVDS to CMOS level translator; then at the second stage the
data are registered, and finally multiplexed. In addition to
the data signals, the FEB sends two validation signals (one
for each 16 bit segment) which go through the MUX chip via
the same logic flow. Hence in the output register there are 16
bits (for data)+ 1 bit (for validation), and 1 extra FLAG bit.
In the double frame mode, this FLAG bit is used by the
transmitter and receiver to distinguish the first or second
frame segment. The schematic of the multiplexer chip is
shown in figure 4. One could notice that the output registers
are synchronized with Strobout which is a 80.16Mhz latch
clock generated by a PLL inside the serialiser. This clock
features 50% of duty cycle which is the best configuration
for the Glink in a double frame mode. Figure 5 shows the
transmitter data interface that the multiplexer must fit in
with. The Tstrb delay is defined from the falling edge of
STRBOUT to the corresponding rising or falling edge of
STRBIN. The typical value for this delay is 4ns.
The data (at the MUX output) must be valid for a set−up
time (Ts) before it is sampled and remain valid for a hold
time (Th) after it is sampled. The minimum value required in
the data sheets [1] for both Ts and Th is 2ns.
A double channel version of the multiplexer has been
designed and tested successfully with the full optical link [2].
For the main 40.08Mhz clock the link has shown a tolerance
of the duty cycle from 32% to 65%. The limits found for the
general delays between the main clock edge and the
incoming data sampling time are 1.2ns and 13.2ns. The total
power dissipation is 0.6W, leading into 0.3W/channel.
IV ) A CUSTOM BIT ERROR TESTER
The Glink chip set provides a link−down and a single
error monitoring through a 4 bit control field which is
appended to each 16 bit data field. The control field has a
master transition (which the receiver uses for frequency
locking) and includes information regarding the data type
(control, data, fill frame). The control bits are analyzed by
the deserialiser to provide two output flags: a ’link−down
flag’ occurs when the receiver can not identify a frame to

lock onto, and a ’single error flag’ indicates an illegal
control field in the transmitted frame.
Initially the error detection was done mainly by
monitoring the Glink’s inbuilt error flags, as reported in [3],
but later a custom Bit Error Tester (BERT) has been
developed [4]. It helps to refine the testing and in particular
to discriminate between different types of errors in the link.
Besides it permits several links to be tested simultaneously.
The basic idea was to develop a system capable to send a
flow of ATLAS like data in parallel through two different
paths. One path is the reference one and the other follows the
full optical link to be tested as described in figure 1. The
BERT must also be able to synchronise, read and compare
the out−coming data from both paths.
The BERT system includes EPLD−based boards plugged
in a VME crate. It is coupled to a pseudo−random pattern
generator based on the CompuGen3250 board from Gage[5],
and provide an interface to a computer for on−line
monitoring. One can see the details on this BERT system in
figure 6.
LVDS
Pattern Generator
32 bit @ 40MHz
TTL
Pattern Gen. Interface
Errors Injection
line driver
Multiplexer chip
MUX
MUX
TX
TX
CONTROL Board
TTL output used only
For Glink test without MUX
Transmitters
Figure 6: Details of the custom BERT set−up.
Testing Computer
Configuration
Control
Errors Acquisition
PC Interface
PGI board Control
COMPAR board Control
Reference Data (VME bus)
The CONTROL board:
It provides interfaces both to the pattern generator and to
the acquisition and configuration computer. It sends data
simultaneously via the VME bus (reference data) and
through a set of optical links (including the multiplexer) to
be tested in parallel.
The COMPARISON board:
It reads the reference data sent on the VME bus and
performs a bit to bit comparison with the data transmitted
through an optical link. This comparison result is sent to the
CONTROL board via the VME bus.
The slow control of any step, from the data generation to
the comparison result acquisition, is done by a computer.
By means of this BERT system, we have successfully
tested the Glink in our laboratory for many weeks, and also
during the irradiations tests:
V) RADIATION TEST WITH THE BIT ERROR
TESTER
Several link sender boards were exposed to neutron flux
to assess the radiation tolerance of the DMILL MUX, the
Glink serialiser and the Methode transceiver. During the
radiation tests, the behaviour of the link was monitored on−
line by means of the BERT coupled to a pseudo−random
pattern generator [5].
The radiation tolerance of a G−link serialiser coupled to
a Methode transceiver has been proved under neutron
Optical fibres
Control/Acquisition (VME bus)
Data Synchronization
Comparison
Errors Processing
VME Crate
Comparison Boards
Synchronization
Comparison
Errors Processing
RX Receivers RX
integrated dose up to 5*1013 (1 Mev Si) neutrons/cm2 .
However, transient data transmission errors were observed
and identified as Single Event Upsets (SEU).
The interaction of neutrons with silicon produces
secondary charged particles, which could be located on the
active devices of the electronics chip. A fraction of the
released charge along the ionizing particle paths is collected
at one of the circuit nodes. If it is high enough the resulting
transient current might produce a SEU. In order to estimate
the SEU rate, the main parameters that need to be taken into
account are the sensitive volume of the chip within which

the ionization takes place, and the critical energy to be
exceeded before triggering an upset.
Initially the link error detection was perform by
monitoring the G−link’s inbuilt error flags as reported in [3],
and later by means of the a Bit Error Rate Tester (BERT)
coupled to a pseudo−random pattern generator.[4]
Four different types of errors were identified:
� single bit flip (relative rate 72%)
� n bit flips (relative rate 9%)
� clock corruption in the transmitted frame for a few 40.08
MHz clock counts (relative rate 9%)
� link−down error, in addition to a loss of data this error
leads to a loss of clock information (relative rate 10%)
The experimental data were then interpreted using two
different methods that are described in [3] and [6]. These
methods lead to a predicted ATLAS error rate as high as
0.65 +/− 0.30 error/link/hour.
A test was carried out with a 60 MeV proton beam at the
CRC in Louvain−La−Neuve (Belgium) in June 2001. In this
experiment, the method used to analyse the data recorded
with the BERT system was the one described in Ref [7]. A
nice agreement with the results obtained at CERI was found.
In addition, it confirms that the proton flux (as well as
neutron flux) has very little influence on the DMILL
multiplexer performance, and it induces less than 0.1% of
the total SEU error rate.
VI ) CONCLUSION
The radiation tolerance of the sender part of the link has
been demonstrated under neutron radiation up to 1014 ncm−2 .
Transient data transmission errors (Single Event Upset) were
observed by means of the BERT set−up but it has been
shown that the contribution of the DMILL MUX to this error
rate is very negligible.
VII)REFERENCES
[1] Manufactured by Hewlett Packard, Agilent
Technologies, P.O. Box 10395, Palo Alto, CA 94303,
http://www.semiconductor.agilent.com.
[2] B. Dinkespiller et al, ’Redundancy or GaAs? Two
different approches to solve the problem of SEU (Single
Event Upset) in a Digital Optical Link’, 6th Workshop on
Electronics for LHC experiments, Krakow−Poland, 11−15
September, 2000.
[3] M−L Andrieux et al., Nuclear Instr. And Meth A 456 (
2001, p342.
[4] M−L Andrieux et al. ’Single Event Upset studies und
er neutron radiation of a high speed digital optical data link’,
Proceedings of the IEEE conference , Lyon−France, October
15th −20th, 2000.
[5] Gage Applied Sciences, Inc., 2000, 32nd Avenue
Lachine, Montreal, GC Canada H8T 3H7, http://www.gage−
applied.com/.
[6]M. Huhtinen et al ’Computational method to estimate
Single Event Upset rates in an accelerator environment’ Nucl
Instr. And Meth A 450 (2000) p155−172.
[7] Ph Fartouat et al. ’ATLAS policy on radiation tolerant
electronics’ ATLAS document No ATC−TE−QA−0001, 21
July 00.

Direct Study of Neutron Induced Single-Event Effects
¢¡¤£¦¥¨§�©�����§ 1,4, J. Bro� 1�¤���¨���¤������� 2 , D. Chren 2�¤���¤�¦�¤����� �¤�����¨� 2�¤���¤��������� 2 ,
P. Kodyš 1 , C. Leroy 3 , S. Pospíšil 2 , B. Sopko 2 , A. Tsvetkov 1 and I. Wilhelm 1
Abstract
A facility for direct study of neutron induced Single Event
Effects (SEE) has been developed in Prague using collimated
and monoenergetic neutron beams available on the Charles
University van de Graaff accelerator. In this project, silicon
diodes and LHC Voltage Regulator are being irradiated by
neutrons of different energies (60 keV, 3.8 MeV, and 15
MeV). Furthermore, the associated particle method is used, in
which 15 MeV neutrons produced in the 3 H(d,n) 4 He reaction
are tagged. The measurements in progress should allow
estimating a probability of neutron interactions per sensitive
volume of the junction and a probability of SEE occurrence in
the LHC Voltage regulator chip.
I. INTRODUCTION
CMOS integrated circuits (CMOSICs) are largely used in
space, aviation and particle accelerator environments, i.e. at
high radiation environments. The use of submicron CMOS
processes in these adverse radiation environments requires the
application of special architectural and layout techniques.
Failures could come not only from total dose effects but also
from so-called Single Event Effects (SEE) believed to be
responsible for latch-up that can destroy ICs completely or
render them unusable indefinitely or for various periods of
time. Therefore, there is a need to understand the importance
of SEE in specific operational environments and to find ways
of quantifying the tolerance of the different technologies to
these effects. We tried to find out a probability of latch-up
phenomena in CMOSICs caused by fast neutrons.
The experimental tests are oriented on estimation of SEE
provoked by the following specific interactions of neutrons in
the silicon chip: Si(n,n’)Si, Si(n,n)Si, Si(n,α)C, Si(n,p)Al and
B(n,α)He.
II. STUDY OF ENERGY THRESHOLD BEHAVIOUR OF
IC-FAILURES
The experimental set-up of a collimated, monochromatic
and tagged neutron beam has been realised at the van de
Graaff accelerator of Charles University, in the collaboration
with Montreal University and Czech Technical University,
Prague. Neutrons are produced using several production
reactions. Overview of the reactions is in Table 1. Beams of
1 Charles University, Prague, Czech Republic
2 Czech Technical University in Prague, Prague, Czech Republic
3 University of Montreal, Montreal, Canada
4 corresponding author, e-mail:Zdenek.Dolezal@mff.cuni.cz
neutrons with energies of 60 keV (with an energy spread 10
keV), 3.8 MeV (100 keV) and 15 MeV (100 keV) are
available. This provides a neutron beam energy range
allowing one to estimate the expected energy threshold
behaviour of SEE.
The experimental setup of neutron production is at Fig. 1.
Beam of accelerated deuterons or protons strikes onto a
tritium or deuterium target with the molybdenum backing.
The interaction point of the beam with the target represents a
nearly point source of monochromatic neutrons.
Figure 1: Experimental arrangement of neutron production target.
d (p): beam of deuterons (protons) from the van de Graaff
accelerator, D 1:deuterium (tritium) target on molybdenum backing,
n: neutron beam
Monitoring of neutron flux is based on Bonner
spectrometer. This method allows precise determining neutron
dose for each individual irradiation at one neutron energy.
Furthermore, after calibration of its energy sensitivity,
irradiations performed at different energies can be compared.
III. DIRECT SINGLE EVENT EFFECT OBSERVATION
In the case of 3 H(d,n) 4 He reaction, so called associatedparticle
technique can be applied to obtain a tagged neutron
beam. The technique is based on the spectroscopic detection
of produced alpha particles by means of silicon diode what
brings an information about neutron emission within the time
uncertainty on the level of about 10 ns. The principle of the
technique is displayed on Fig. 2. Registered recoiled alpha
particle serves as a tag of neutron moving in a kinematically
determined direction (e.g. in a direction to an IC). The conical
neutron beam is collimated to the diameter of 3-4 mm at the
distance of the target of 15 cm. The intensity in this beam is
around 10 6 n/s, giving 10 7 n cm -2 s -1 . The detailed description
of the tagged neutron beam facility is given in [1].

Figure 2: Sketch of kinematics of the associated particle method.
The upper and lower cone denote outgoing neutrons and alpha
particles, respectively. Aluminium foils are used to absorb elastically
scattered incident deuterons.
Recoil
Particle
Detector
Fast
Discriminator
Coincidence
Unit
Scaler
Time-todigital
Converter
PC
IC
Sample
IC failure
Event
Generator
Figure 3: Block diagram for SEE monitoring using associated
particle method
To estimate a probability of SEE, neutron beam intensity
is monitored by the registration of associated particles and,
directly by neutron Bonner sphere spectrometer.
The circuitry of SEE registration is at Fig. 3. IC failure
event generator is connected to the coincidence unit together
with the associated particle detector. This ensures that effects
correlated to the neutrons are counted only. In addition to the
coincidence unit time between associated particle registration
and SEE is measured via TDC, to give more information
about particular IC failure.
IV. APPLICATIONS
Tests of two types of devices are currently in progress
using both methods. Silicon diodes of different sizes were put
to the neutron beam and their response is studied. These
measurements should allow estimating a probability of the
reaction per sensitive volume of the junction and amount of
energy deposited by reaction products in this volume using
pulse-height analysis of silicon diode signal.
The same measurements are carried out with LHC Voltage
Regulator (RD49 project [2]). The results will be published.
V. REFERENCES
[1] I. Wilhelm, P. Murali and Z. Dolezal, Production of
monoenergetic neutrons... Nuclear Instruments and Methods
in Phys.Res., A317(1992)553
[2] CERN-LHCC RD49 Project,
http://rd49.web.cern.ch/RD49/
Reaction T(p,n) 3 He D(d,n) 3 He T(d,n) 4 He
Neutron energy 60 keV 3.8 – 5 MeV (tunable) En = 15 MeV
Energy spread 10 keV 100 keV 300 keV
Reaction energy Q -0.97 MeV 4.6 MeV 17.8 MeV
Intensity 10 5 n/s 10 5 n/s 10 6 n/s
Table 1: Overview of neutron production reactions

THE ATLAS READ OUT DATA FLOW CONTROL MODULE
AND THE TTC VME INTERFACE PRODUCTION STATUS
Per Gällnö, CERN, Geneva, Switzerland
(email: per.gallno@cern.ch)
Abstract
The ATLAS detector data flow from the Front
End to the Read Out Drivers (ROD) has to be
controlled in order to avoid that the ROD data
buffers get filled up and hence data getting
lost. This is achieved using a throttling
mechanism for slowing down the Central
Trigger Processor (CTP) Level One Accept
rate. The information about the state of the
data buffers from hundreds of ROD modules
are gathered in daisy-chained fan-in ROD-
BUSY modules to produce a single Busy signal
to the CTP. The features and the design of the
ROD-BUSY module will be described in this
paper.
The RD-12 TTC system VMEbus interface,
TTCvi, will be produced by an external
electronics manufacturer and will then be
made available to the users via the CERN
EP/ESS group. The status of this project is
given.
INTRODUCTION
Dead-Time Control Review
The data flow in the ATLAS sub-detector
acquisition systems needs to be controlled in
order to prevent information losses in the case
the data buffers in the Front End, Read Out
Drivers (ROD) or Read Out Buffers (ROB) get
saturated.[1],[2]
Three different mechanisms to control the data
flow will be implemented:
• By Back pressure using a XON/XOFF
protocol on the read-out links between the
ROD's and the ROB's.
• By Throttling to slow down the level one
(LVL1) trigger rate from the CTP when
the ROD data buffers are nearly filled.
• By Prevention introducing a constant
dead-time combined with one set by a preprogrammed
algorithm in the CTP in order
to avoid buffer overflow in the Front End.
The constant dead-time is chosen to be 4
BC's after each LVL1 and the algorithm,
called "leaky bucket", limits the number of
LVL1 to 8 in any window of 80µs.[3]
1
The introduction of a dead-time by a throttling
mechanism is based on a ROD busy signalling
scheme informing the Central Trigger
Processor about the state of the ROD data
buffers as each ROD is able to produce a
ROD-Busy signal when its buffer is filled up.
The busy signals from each ROD are summed
and monitored in ROD-Busy Modules
connected in a tree structure to finally produce
a veto signal for the CTP. The ROD Busy
signalling scheme and associated hardware
will be described in this context.
ROD BUSY STATUS SUMMING
AND MONITORING
System Overview
The Read-Out Drivers (ROD), of which there
will be several hundred in the ATLAS
experiment, buffer, process and format the data
from the Front End electronics before being
sent to the Read-Out Buffers (ROB).
IfthedatabuffersintheRODareclosetoget
filled up the Level-1 trigger rate must be
reduced. A way of achieving this is to send a
busy flag to the CTP to introduce a deadtime.[4]
Busy
Sub-system-x
Busy
Sub-detector-2
Busy
Sub-detector-
Sub-detector-3
Busy
Sub-system-y
From ROD's in Sub-detector-1
15
ROD
BUSY
Module
ROD
BUSY
Module
15
From ROD's in Sub-detector-n
ROD
BUSY
Module
CTP
Veto

Figure 1. The ROD -Busy tree structure
Each ROD produces a Busy signal, which is
sent to a ROD-Busy module together with
Busy signals from other ROD's in the same
sub-system. The ROD-Busy module sums the
incoming Busy signals to produce one Busy
signal of the particular sub-system. In turn the
sub-system Busy signal is summed with other
sub-system Busy signals in another Busy
module to form a sub-detector Busy signal.
Finally all sub-detector Busy signals are
gathered to form a Busy input to the CTP.
THE ATLAS ROD-BUSY
MODULE FEATURES
Basic Operation
The ROD-Busy module [5] has been designed
to perform the following functionality:
• Collect and make a logical OR of up to 16
Busy input signals.
• Monitor the state of any input Busy signal.
• Mask off any input Busy signal in the case
a ROD is generating a false Busy state.
• Measure the integrated duration any Busy
input is asserted for a given time period.
• Store a history of the integrated Busy
duration for each input.
• Generate an interrupt if any Busy input is
asserted for longer than a pre-set time
limit.
• Generate a Busy output serving as an
input for a subsequent ROD-Busy module
in the tree structure or as a veto for the
CTP.
Software Controlled Mode
In this mode of operation are the resetting and
enabling of the integrating duration counters,
as well as the resetting, writing and reading of
the history FIFO buffers done entirely under
program control. The FIFO empty and full
status flags for each FIFO are available to the
VMEbus.
Circular Buffer Mode
In this mode of operation is the transfer of data
from the Busy duration counters to the FIFO
buffers controlled by a timed sequencer. Bits
may be set in a register in order to allow a
circular buffer operation, i.e. a word is read out
from the FIFO for each word written when the
FIFO full flag is present. The maximum time
between two consecutive data transfers, from
counter to FIFO, is 6.55 ms. This time may be
adjusted in a 16 bit VME register.
2
Busy In
1
2
16
Test Driver Test Register
10 MHz clock
Monitor Latch
Sequencer
16 bit counter FIFO
16 bit counter FIFO
16 bit counter FIFO
Mask register
VME IRQ-gen
o/p
Driver
Figure 2. ROD -Busy module block diagram
Additional Features
• Each input path may be tested by setting
bits in a VME test register.
• A status bit reflects the state of the Busy
Out.
• A bit may be set in a control register in
order to turn on a global Busy signal on all
Busy Outputs.
• The Busy Time-Out service requester may
be controlled by software functions, i.e.
enable, disable, set and clear of the service
request.
• The VMEbus interrupter may be tested
with a software function.
• The module may be globally reset by a
software function.
Modular VHDL blocks
The code for the different functional blocks
has been written in VHDL and may be
obtained on request in the case a designer
wants to implement the Busy module functions
directly in a ROD module.
The following VHDL entities are made
available:
VMEbus
Busy Out

1. Input monitoring, masking, stimulating
and summing.
2. Quad 16-bit up-counter.
3. FIFO read/write sequencer.
4. VME slave and interrupter interface.
5. Busy time-out service requester to drive
interrupter.
MODULE DESIGN DESCRIPTION
Input signal receivers and test drivers
The inputs are terminated with a Thévenin
network resulting in a 50Ω resistive input
impedanceandcalculatedtogivea+0.8V
idle voltage. A Busy TRUE input corresponds
to a 0 V level and a Busy FALSE to a + 0.8 V
level. The input voltage threshold is set to +
0.4 V and the ultra fast input comparators have
an internal hysteresis circuit producing clean
input signals even when receiving data over
long lines. All inputs may be monitored by
reading a 16 bit input status VME register.
Each input may be tested by being pulled
down by an internal open-collector driver
connected in turn to a 16 bit VME test register.
Output signal drivers
The four Busy Out outputs are driven by FAST
TTL open-collector drivers. The outputs have
the following characteristics and usage:
0. Pulledupto+5Vby10kΩ and should
be used to drive a following Busy Input or
the CTP Busy Input.
1. Same as 0.
2. Pulledupto+5Vby510Ω and should
be used for monitoring purposes, i.e.
oscilloscope etc.
3. Same as 2.
Busy Input masking and summing
The cleaned-up input signals drive the Busy
Summing circuit and the Busy Duration
counters. The input signals to the Summing
circuit may be masked off in order to isolate
faulty ROD units. The Summing circuit
produces a global Busy signal, which is fed to
the four Busy Out outputs. A control bit may
be set to produce a global Busy Out for system
test purposes. This block is implemented in a
FPGA named ip_reg_structure.
Duration Counting
The 16 bit duration counters increment at a
speed of 10 MHz as long as there are Busy In
signals on the inputs. There are global counter
enable and reset functions generated by either
accessing VME control bits or by the Buffer
3
Sequencer. The sixteen counters are
implemented in four FPGA's named
quad_count_struct.
Duration Count Buffering and Read-
Out
The 512 word deep FIFO's buffer the Duration
Counter data until read out by the VMEbus.
There are global FIFO write cycles and reset
functions generated by either accessing VME
control bits or by the Buffer Sequencer. The
FIFO read cycles are either done by the
VMEbus or by the Buffer Sequencer. Control
bits enable the FIFO's to be configured as
circular buffer, i.e. they maintain always the
history of the 512 last entered Duration Count
figures. If not configured as circular buffers
the FIFO's will only contain the first 512
entered Duration Count figures.
Duration Counter/Buffer Sequencer
The sequencer, when enabled, handles the
control of the Duration counters and the
FIFO's. A 16 bit down counter with a VME
programmable shadow register, clocked by the
10 MHz clock, is used to set the rate for
transferring the duration counts to the FIFO's.
This block is implemented in a FPGA named
fifo_sequencer.
Global Busy Time-Out Service
Requester
The Time-Out circuit monitors the duration of
the global busy signal and generates a service
request if a certain time limit is reached. Two
sets of 16 bit counters, magnitude comparators
and VME programmable registers are used for
this monitoring circuitry. An Interval
counter/comparator/register circuit sets the
frequency at which the two counters are reset.
The Limit counter/comparator/register circuit,
where the counter increments during the time
the Busy is true, generates a service request, if
the preprogrammed level is attained before
being reset by the Interval circuit. Both
counters are incremented at 10 MHz. The
Time-Out service request may be programmed
to trigger a VMEbus interrupt. This block is
implemented in a FPGA named
sreq_timer_struct.
VMEbus Data Bus Interface
The VME bus slave interface is of
conventional type and accepts only 16 bit word
data cycles (D16). The addressing can either
be standard or short (A24 or A16). Address
pipelining and address only cycles are
accepted. Four hexa-decimal switches are used

for setting the base address of the module. This
block is implemented in a FPGA named
vme_if.
VMEbus Interrupt generator
A VMEbus interrupt can be generated when a
Time-Out service request occurs. A control
register in which the VME Interrupt Request
level is programmed and the interrupter is
enabled controls the interrupt generator.
Another register contains the Status/ID
information in an 8 bit format (D). This
block is also implemented in the FPGA named
vme_if.
Module Configuration EEPROM
Manufacturer/module identification and serial
number, as well as module revision number
should be stored in this non-volatile memory
chip. There are spare locations for storing
supplementary information. A strap must be
installed in order to program this memory chip.
ISP Module Firmware programming
All ALTERA® FPGA chips, except for the
VMEbus interface chip, are programmed with
an In-System Programming scheme, using a
"Byte-Blaster" adapter connected to a PC,
where the ALTERA MAX-PLUS®
programming software is installed.
System Clock generation and
distribution
An internal 10 MHz system clock generator is
implemented and a clock driver fan-out chip is
used to drive the seven impedance matched
clock lines, each terminated with a series RC
network.
STATUS AND DOCUMENTATION
The design of the ROD-Busy module is
finished and two prototypes has been
debugged and tested which are now available
for evaluation. The prototypes are packaged as
6U/4TE form factor VME modules. A
conversion kit for implementation on larger
VME boards is also foreseen.
A technical manual has been produced for the
ROD Busy Module, which can be retrieved
from the CERN EDMS system, together with
all the engineering data.[6]
CONCLUSION
The implementation of the ROD-Busy
modules and their associated tree structured
signal gathering scheme makes it possible to
4
efficiently control the dead-time in the ATLAS
experiment and to easily detect faulty ROD
modules introducing excessive dead-time.
Figure 3. ATLAS ROD Busy Module
TTCvi PRODUCTION STATUS
The CERN EP/ESS Group will in the future
handle the out-sourcing of the fabrication of
the TTCvi modules and then make them
available to users. During the fourth quarter of
2001 will a new batch of modules be produced,
which should be available when tested by the
EP/ESS group in the beginning of 2002. The
EP/ESS group will also be responsible for the
service (maintenance, support and spares).
Teams who already have TTCvi MkII version
modules will be able to subscribe to this
service, by paying a yearly fee.

REFERENCES
[1] P. Gällnö:"Timing, Trigger and Control
Distribution and Dead-Time Control in
Atlas", LEB 2000 Workshop, Kraków,
Poland, Sept. 2000
http://lebwshop.home.cern.ch/lebwshop/LE
B00_Book/daq/gallno.pdf
[2] Ph. Farthouat; "TTC & Dead-time handling"
2 nd ATLAS ROD Workshop, University of
Geneva, Oct. 2000
http://dpnc.unige.ch/atlas/rod00/transp/P_Fa
rthouat2.pdf
[3] R. Spiwoks: "Dead-time Generation in the
Level-1 Central Trigger Processor", ATLAS
Internal Note
[4] ATLAS Level-1 TDR Chapter 20
http://atlasinfo.cern.ch/Atlas/GROUPS/DA
QTRIG/TDR/tdr.html
[5] P. Gällnö:"The ATLAS ROD Busy Module"
1 st ATLAS ROD Workshop, University of
Geneva, Nov. 1998
http://mclaren.home.cern.ch/mclaren/atlas/c
onferences/ROD/programme.htm
[6] P. Gällnö:"ATLAS ROD Busy Module -
Technical description and users manual",
EDMS Item no: CERN-0000003935
5

Optically Based Charge Injection System for Ionization Detectors.
H. Chen 1 , M. Citterio 2 , F. Lanni 1 , M.A.L. Leite 1,* , V. Radeka 1 , S. Rescia 1 and H. Takai 1
(1) Brookhaven National Laboratory, Upton, NY − 11973, USA
(*) leite@bnl.gov
Abstract
An optically coupled charge injection system for
ionization based radiation detectors which allows a test
charge to be injected without the creation of ground loops
has been developed. An ionization like signal from an
external source is brought into the detector through an
optical fiber and injected into the electrodes by means of a
photodiode. As an application example, crosstalk
measurements on a liquid Argon electromagnetic calorimeter
readout electrodes were performed.
I. INTRODUCTION
For the performance tests of ionization based radiation
detectors it is desirable to have a system which is capable of
injecting a charge of known value in a condition that is as
close as possible to the operating environment, where charge
is locally generated by the ionization of the sensitive media
in the detector. One of the main problems with the
conventional approach of the direct injection through an
electrical cable connected to the detector electrodes is the
change of the detector electrical characteristics[1]. In
particular, the grounding configuration of the system can be
completely modified by the introduction of the injection
circuit new ground path. The use of an optically coupled
injection, in which a light to current converter is placed on
the electrodes of the detector to generate the ionization
signal, allows for a full galvanic isolation between the
detector and the test pulser (Fig. 1).
Figure 1: Principle of the optically coupled injection of a test
signal to an ionization detector. The capacitance added by the
photodiode is negligible.
An optical fiber carries a light pulse, modulated to the
same waveshape of a physical signal, to a photodiode
connected in parallel to the detector. The photodiode is
biased using the same voltage distribution network for the
detector bias, using an appropriate voltage, typically 30 V −
(2) INFN, Via Celoria, 16 20100 Milano, Italy
50 V. Since no additional electrical connection to the
detector is necessary, the electrical environment of the
detector, including grounding, is left undisturbed. This
makes possible to study on a test bench issues like
crosstalk[1] or electromagnetic interference[2] where
additional ground loops might taint the results of bench tests.
A photodiode installed on the electrodes and biased by
means of the high voltage system achieves the light to
current conversion. It has a capacitance of only a few
picofarads, small if compared with detector capacitances of
the order of nanofarads. The photodiode should also have a
fast time response and low dark current. Size is also an issue,
as this device may needs to fit in spaces of only a few
millimeters. The light, generated by a laser diode stimulated
to produce a suitable signal for the detector, is brought to the
photodiode using a multimode optical fiber. Fig. 2 and Fig. 3
show the characteristics of two commercial devices which
can be used for this application. The laser diode is a VCSEL
(Vertical Cavity Surface Emitting Laser) device, capable of
generating up to 3 mW of optical power, with a peak
wavelength of 860 nm, matching the photodiode maximum
sensitivity of 850 nm. The use of a PIN photodiode allows
the generation of signals with a rise time of 2 ns, adequate
for this application.
Figure 2: PIN diode capacitance. Capacitance of a PIN diode
(Panasonic PNZ334) as a function of the bias voltage. At the
operating voltage (28 V) the capacitance is 3.6 pF.

Figure 3: VCSEL power. Power output as a function of the bias
current for VCSEL laser diode (MITEL 1A444). Eight different
devices (M1 − M8) have been measured.
II. EXAMPLE OF APPLICATION: CROSSTALK STUDY
As an example of this method, the ATLAS
Electromagnetic Liquid Argon Calorimeter[3] test stand at
BNL has been modified by adding a photodiode on a few
calorimeter channels (Fig. 5). The optical signal is created
using the VCSEL modulated to produce the same triangular
shaped pulse generated by an ionization signal. Crosstalk
studies were performed by injecting a signal in one channel
at a time and recording the crosstalk pattern on neighbor
channels. The output signal is processed using an identical
segment of the readout chain of the ATLAS barrel
calorimeter: a transimpedance preamplifier (BNL 25Ω
IO824 [4]) and a CR−RC 2 shaper, using a time constant of
15 ns (Fig. 4).
Figure 4: Pulse generation and readout signal circuit. The optical
signal is generated by LD1 (MITEL 1A444 VCSEL), biased by a
current source (ILX Lightwave LDX−3630) and driven directly by
an arbitrary signal generator (Analogic Model 2040) programmed
to give out a triangular pulse. The light signal is transmitted by
the optical fiber to PD1 (Panasonic PNZ 334). A current is then
injected in one channel of the calorimeter test module
(capacitance Cd), which is AC coupled by CAC directly to the
readout chain.
Figure 5: Experimental setup for optically coupled charge injection
of the ATLAS barrel liquid Argon electromagnetic calorimeter. A
PIN photodiode is connected (a) within the gap from the absorber
(ground) to the high voltage layer. M1 through M4 and B1, B2 are
readout channels. The signal ground is provided by two points
(GND Spring 1 and 2). The optical fiber is run along the tip of the
bending of an electrode (b), and brought to the side of the module,
where it is coupled to a laser source. The photodiode is mounted on
a carrier PC board (c), soldered to the electrode (anode) and
contacting the absorber (cathode). An indium foil is used to assure
a low resistance electrical connection.
(b)
(c)

Figure 6: Measured crosstalk. A signal is injected in one channel
(Fig. 5a M1 or M2) and the crosstalk is observed in the closest and
in the farthest neighboring channels with ground springs both to
the left (GND spring 2) and to the right (GND spring 1) of the
connector (continuous trace). Removal of the ground springs to the
left of the connector increases the distant crosstalk (dashed traces).
In this example, one of the ground connections between
the electrodes and the absorbers on the left side of the signal
connector (GND Spring 2 in Fig. 5a) was removed, and the
change in the crosstalk pattern observed by injecting a signal
in two different neighbor channels (M1 and M2). The results
(Fig. 6) show that the nearest neighbor crosstalk is
unchanged. The distant crosstalk (channel M4) is indeed
affected by the removal of the ground springs, but remains
always less than 0.2%. The optical injection allows to
reliably detect differences in crosstalk signals of less than 1
mV and to rule out any ground loop effect as the cause of
these small differences.
III. CONCLUSIONS
We showed that an ionization−like signal can be injected
by optical means, allowing measurements of small amplitude
signals in large systems without disturbing the grounding
configuration of the detector. Since the capacitance of the
photodiode is much smaller than the detector capacitance,
there is no change in the electrical characteristics of the
system. Most important, the undisturbed ground
configuration makes possible to systematically study small
amplitude effects that otherwise would be masked by
interferences caused by differences in the ground path.
This setup can be expanded for injecting signals in
multiple channels simultaneously. This may be
accomplished by the use of a direct current injection of the
laser (Fig. 7) and direct coupling to the fiber without optical
connectors, allowing injection and inter−calibration of
several channels. With this method it is possible, for
example, to reproduce the charge distribution of an EM
shower over many cells of a calorimeter, thus allowing a
more complete study of the crosstalk of the system.
Figure 7: Fast voltage−to−current converter for direct laser
modulation. This simple driver circuit allows to build many
compact driver−laser−photodiode assemblies which can be inter−
calibrated before installation on the electrodes. The optical
connections could be simply made with optical glue, thus avoiding
optical connectors and the variation in attenuation inherent in the
mating of optical connectors.
IV. ACKNOWLEDGEMENTS
We would like to express our gratitude to Dr. T. Tsang,
from the Instrumentation Division of the Brookhaven
National Laboratory, for the many helpful discussions about
the optical setup.
V. REFERENCES
[1] M. Citterio, M. Delmastro, M. Fanti. A study of the
electrical properties and of the signal shapes in the ATLAS
liquid Argon accordion calorimeter using a hardware model.
ATLAS Larg Internal Note, May 2001.
[2] B. Chase, M. Citterio, F. Lanni, D. Makowiecki, V.
Radeka, S. Rescia, H. Takai, J. Bán, J. Parsons, W.
Sippach. Characterization of the coherent noise,
electromagnetic compatibility and electromagnetic
interference of the ATLAS EM calorimeter Front End Board.
5th Conference on Electronics for LHC Experiments,
Snowmass, CO, USA, 20 − 24 Sep 1999. CERN−99−09 ;
CERN−LHCC−99−033 − pp.222−226.
[3] ATLAS Collaboration. ATLAS liquid argon
calorimeter technical desig report. CERN/LHCC/96−41,
CERN (1996).
[4] R. L. Chase and S. Rescia. A linear low power
remote preamplifier for the ATLAS liquid argon EM
calorimeter. IEEE Trans. Nucl. Sci., 44:1028, 1997.

An Emulator of Timing, Trigger and Control (TTC) System
for the ATLAS End cap Muon Trigger Electronics
Y. Ishida, C. Fukunaga, K. Tanaka and N. Takahata
Tokyo Metropolitan University, 1-1 Minami-Osawa, Hachioji, Tokyo, 192-0397 Japan
Abstract
We have developed a stand-alone TTC emulator system.
This system simulates relevant TTC signals and their
sequences needed for the ATLAS TGC electronics. Almost
all functionalities are packed in an FPGA chip, which is
mounted on the same board as one of TTCrx test board
developed by CERN EP/mic group. The signal pin
allocation is also the same as the TTCrx test board. Hence,
instead of the test board, if the emulator board is mounted,
TTC signals are generated and distributed consistently with
this board without any modification of the mother board
electronics system.
I. INTRODUCTION
In general a facility for TTC signal generation and
distribution system is indispensable for development of
electronics for an LHC experiment [1]. We need two VME
modules [2,3], TTCrx chip [4], fiber optical/electronics
converter, and software in order to implement full
functionality of the TTC signal distribution system.
Electronics development of a particular sub-detector of
an LHC experiment will be collaborated with several
institutes of universities and laboratories. Although each
institute will need more-or-less TTC signals, to facilitate
such the TTC signal distribution system in every institute is
unthrifty and inefficient.
The ATLAS Thin Gap Chamber (TGC) electronics
development team consists of seven institutes from two
countries [5]. More-or-less all the institutes will need at
least a few restricted TTC signals for their electronics
development.
The group has then developed a TTC emulator. The
emulator has a functionality to emulate relevant TTC
signals, which the TGC electronics system will use. Timing
sequences among the signals are also emulated. In the final
TGC system, a TTCrx chip will be mounted as a mezzanine
card. As we have installed the emulator system into a small
M. Ikeno and O. Sasaki
KEK, 1-1 Oho, Tsukuba, Ibaraki, 305-0801 Japan
circuit mountable on the same size daughter board, physical
consistency is also satisfied with the final TTCrx board. We
discuss the structure of the emulator in the section 2, and
show some emulator performance of several signals in the
section 3. Finally in the section 4 we summarize the results.
II. STRUCTURE AND FUNCTIONALITY
A. Hardware structure
The main functionality of the emulator is wholly packed
in a Xilinx-FPGA of SPARTAN-2 (XC2S150). Beside the
FPGA, a 40.08MHz clock generator, a PROM for storage of
the FPGA firmware, a variable delay, several jumpers and a
dip switch, Lemo connectors for external signal inputs and
a JTAG connector for the FPGA configuration are mounted
on a PC board. The size and the footprint of this PC board
are the same as the TTCrx carrier test board (TTCrx test
board) developed by the CERN EP/mic group [4]. The top
face of the emulator board is shown in Fig.1.
Figure 1: TTC emulator board
We have used about 61% of the maximum number of
available gates for the FPGA, which is 150 000. In order to
extend the emulation behavior beyond the firmware
contents, some signals can be inputted through the surface
mounted Lemo connectors. One can operate an own
electronics with specially adjusted TTC signals by inputting

them through the connectors. The jumpers and the DIP
switch are used to switch signal sources (external or
internal) or the emulation mode.
The 40.08MHz quartz oscillator is mounted to supply the
default clock. The variable delay is used to emulate the
signal called Clock40Des1. The skew of the clock signal is
adjusted with this variable delay.
B. Emulation Firmware
Situation of Emulation is summarized in Table 1. Since
the pin assignment of the emulator board is the same as the
TTCrx test board, the situation of the emulation for the
actual board is listed in the same way as the TTCrx board in
the table. Since even if pins, which are not emulated, are
connected to the FPGA, we can utilize these pins in the
future firmware upgrade. In this subsection we discuss how
the firmware emulates and handles the signals, and give
emulation recipes of some signals.
Table 1: Situation of Emulation for TTCrx board
The emulated signals are indicated with "X" in the third column.
Connector J1 Connector J2
Pin# Name Emulation Pin# Name Emulation
1 Clock40 - 1 BrcstStr2 X
2 Clock40Des1 X 2 ClockL1A -
3 Brcst X 3:4 Brcst X
4:6 Brcst - 5 EvCntRes X
7 Clock40Des2 - 6 L1Accept X
8 Brcststr1 X 7 EvCntLStr X
9 DbErrstr - 8 EvCntHStr X
10 SinErrStr - 9 BcntRes X
11:12 Subaddr X 10 GND X
13:18 Subaddr X 11:22 Bcnt X
19:22 DQ X 23:26 JTAG -
23 DoutStr X 27 I2C -
24 GND X 28 JTAG -
25:32 Dout X 29 BCntStr X
33 Reset_b X 30 Serial_B -
34 TTCReady X 31:34 GND X
35:50 GND X 35:38 PIN Vcc -
39 N.C. X
40 I2C -
41:42 GND X
43:46 TTCrx Vdd X
47:50 GND X
The bunch-crossing signal (BX), which is, although, not
outputted from the emulator, is simulated in the firmware.
The emulator generates the timing structure of BX as
exactly the same as one that the actual LHC will supply [6].
The Level1 Accept (L1A) signal must be made coincidence
with BX even if the signal is supplied externally.
L1A is generated in the firmware or can be inputted
externally through the Lemo connector. One can select the
trigger source with one of the jumpers mounted on the
board. For the internal generation, seven different
generation modes are prepared, which are the average
frequencies of 100K, 10K, 1K, 100 and 1Hz of the random
mode and the ones of 75K and 1Hz of the regular mode.
The random mode means the L1A is generated with the
time interval of Poisson distribution based on the given
average rate. Bunch crossing ID (BCID) is outputted
together with L1A, and one (two) clock later from L1A, the
Event Identification Number EVID (EVID)
is outputted. Furthermore the Trigger Type,
EVID, EVID and EVID are outputted
on the Dout with each clock after 4.4µs from the L1A
generation. The SubAddr is used to distinguish which
data fragment is on Dout bus.
Although Clock40des1 is one of the total three LHC
40.08MHz clock signals in the actual TTCrx, this is only
the one that the emulator will output. The clock deskew is
emulated through the on-board variable delay with either
the internal or external clock signal. The variable delay can
adjust the delay timing of maximum 20ns in 40 steps. As
we foresee the necessity of a variable delay of 25ns at most,
we will implement such a delay in future. The clock signal
can be generated by the 40.08MHz oscillator installed on
the board or inputted externally through the Lemo
connector. One can select the internal clock or external
input with the jumper connection. The clock of different
frequency rather than 40.08MHz can be supplied externally.
But in this case the BX timing signal is scaled with the
input frequency.
Since the emulator will not emulate Clock40 and
Clock40des2, Brcst are also synchronized with only
Clock40des1 as Brcst, whereas the actual TTCrx can
set the synchronization of Brcst optionally with the
Clock40des2.
Among the Brcst signals, the emulator simulates
Brcst and Brcst. All these five signals are
inputted through the Lemo connectors. A Lemo-input called
as RST is shared with both Brcst and Brcst. We

have two kinds of the reset signal, one is for the whole
electronics system except DCS (Detector Control System),
and the other one is for the DCS reset. Although we should
prepare two different Lemo connectors for these two reset
signals, there is no more room to install one more connector
on the board. It is foreseen to emulate hardly the DCS reset
signal with this emulation board.
III. Performance
In Figure 2, the L1A signals of the frequency 100KHz
randomly generated by the emulator are shown. In the
scope image of this figure, one division of the horizontal
axis corresponds to 10µs. The time interval between signals
will be Poisson distributed with the average interval of
10µs.
Figure 2: Internal L1A signal generation (100KHz random mode)
Figure 3 shows externally supplied L1A with the original
pulse width of 350ns and the output one produced by the
emulator. If an externally supplied pulse for L1A is longer
or shorter than 25nsec, the emulator will adjust the width as
25 ns. The latency in the emulator from the input to the
output pulse for the width modification is predicted as 53ns
by the FPGA simulation. In Fig.3, the wider pulse indicated
in the lower part is the input one, and the narrower one in
the upper part is the output, and the horizontal division is
40ns. One can find the width of the output is 25ns, and the
timing interval between the leading edges of both the input
and output is measured as 53ns, although this actual value
have uncertainty of a few 10ns due to the measurement
setup. The emulator works anyway as the simulation
indicated.
Figure 3: External L1A signal Input (Lower) and
Output (Upper) through the emulator.
After L1A signal, BCID, EVID and
EVID are loaded on BCnt lines periodically
with the clock. BCntStr is generated when BCID is
loaded on BCnt. EvCntLStr and EvCntHStr are also
generated when EVID and EVID are loaded
on the BCnt respectively. The sequence of the signal
generation has been observed with a logic analyzer, and we
show its output in Fig.4. A typical timing sequence of
relevant signals is shown for three L1A generations in the
figure. From this figure we can confirm the emulation of
BCID and EVID data loading on Bcnt
with three clock-intervals works fine.
Figure 4: Data loading sequence on Bcnt
There is another 24bit event/orbit counter, which is
implemented in the TTCvi module. Together with the

trigger type parameter (8 bit), which is received from the
Central Trigger Processor and stored in the module, these
two data are broadcasted by the module through the
B-channel of the TTC network to individual TTCrx after
approximately 4.4µs of the L1A generation. The emulator
also emulates this sequence because this emulator will be
used for the trigger and timing generation at the developing
stage of the ROD module.
In Figure 5 the Trigger Type and Event/Orbit counter
output sequence observed by a logic analyzer is shown. The
contents of the data are loaded on Dout bus with a bunch of
8bit. The data are loaded together with the DoutStr and
SubAddr. If SubAddr is 00, Trigger Type is loaded
on Dout. The next three numbers with these two bits of
SubAddr are assigned to indicate the Dout loading of three
bytes of the event/orbit counter from the most significant to
least significant bytes.
In principle in the original system, the event counter to be
loaded on BCnt and event/orbit counter to be loaded on
Dout must be different ones. In this emulator system, the
same number is used for both two operations. Hence, the
content of event/orbit counter will be reset by EvCntRes
signal.
Figure 5: Data loading sequence on Dout
IV. SUMMARY
We have made the TTC emulator. We have implemented
the system on a board, which is the same dimension and
same footprint as the TTCrx test board. In order to do that,
most of the emulation logic is installed in an FPGA. With
this emulator, signals needed for operation of TGC
electronics are all generated. The signals successfully
emulated are listed in Table 1.
Consequently we do not need a set of the whole TTC
generation system at every development cite. As TTCrx
boards are always used as mezzanine board in circuits in
which the TTC signals are required in the current TGC
electronics, instead to put TTCrx board, we can get all the
necessary TTC signals by putting the emulator. With this
emulator, we can save money, time as well as man power
resource to prepare and maintain the whole TTC system.
Although the emulator has been customized for the TGC
electronics development, it will be easily adopted by any
other electronics systems if they use the TTCrx test board
as a daughter one.
As all-in-one emulator system like the presently
discussed one is easy to handle and easy to realize the
complicated signal sequence, it will be useful for not only
the development stage but also the production stage with
various workshops.
IV. ACKNOWLEDGEMENT
This work was done in Japanese contribution framework
of the ATLAS experimental project. We would like to
acknowledge all of Japanese ATLAS TGC group as well as
KEK electronics group for their supports and discussions
throughout the work. We would like to express our
gratitude to Prof. T. Kondo of KEK for his support and
encouragement.
V. REFERENCES
[1] B.G.Taylor: “RD12 Timing, Trigger and Control (TTC)
systems for LHC Detectors” Web page
http://www.cern.ch/TTC/intro.html
[2] Ph.Farthouat and P.Gallno: “TTC-VMEbus Interface
(TTCvi-MkII)”
http://www.cern.ch/TTC/TTCviSpec.pdf
[3] P.Gallno: “TTCvx Technical Description and Users
Manual”
http://www.cern.ch/TTC/TTCvxManual1a.pdf”
[4] J.Christiansen et al.: “TTCrx Reference Manual ver3.2”
http://www.cern.ch/TTC/TTCrx_Manual3.2.pdf”
[5] K.Hasuko et al.: “First-Level Endcap Muon Trigger
System for ATLAS”, Proceedings of LEB2000,
Cracow, Poland, Sept.,2000, pp328.
[6] P. Collier: “SPS Cycles for LHC Injection”
http://sl.web.cern.ch/SL/sli/Cycles.htm

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HIGH-SPEED MULTICHANNEL ICs FOR FRONT-END ELECTRONIC
SYSTEMS
A.Goldsher*, Yu.Dokuchaev*, E.Atkin**, Yu.Volkov**
*-- State unitary enterprise “Science and Technology Enterprise “Pulsar”, Russia, 105187,
Moscow, Okruzhnoy proezd, 27.
** -- Moscow State Engineering Physics Institute (Technical University), Russia, 115409,
Moscow, Kashirskoe shosse, 31.
Abstracts
The basic set of high -speed multichannel
analog ICs for front-end electronic systems,
designed and put into production in Russia, is
considered. It is implemented as a number of
application specific ICs (ASIC) and ICs, based on an
application specific semicustom array (ASSA),
containing eight channels of analog signal collection
and preliminary processing.
By their electrical parameters the created
ICs are on a par with foreign functional analogs.
The prospects of the further development
of analog front -end ICs in Russia are expounded.
Introduction
Contemporary front-end electronic
systems, intended, particularly, to carry out
research in high-energy and elementary particle
physics, show a demand for an increase in the
number of data collecting and processing channels,
reaching nowadays some hundreds thousand and
expected to reach several millions during the
nearest 5…7 years.
Low-hoise
pream
Linear
shaper
In its turn that demands a radical change in
the approach to the creation of front-end electronics,
which should simultaneously provide a high speed,
wide dynamic range, relatively low power
consumption, high sensitivity, as well as an
increased radiation hardness, since the electronics is
placed either directly on the radiation detectors or in
the vicinity of them. Besides that, especial
importance is acquired by such factors, as
dimensions, cost, durations of design and
manufacture of printed circuit units.
The multichannel equipments of physical
experiment, of environment monitoring, of nuclear
reactor safety and fissionable material supervision
are united by common algorithms of analog signal
processing. That allowed the specialists of certain
Russian enterprises to create in short terms a basic
set of analog ICs for front-end electronic systems. It
was implemented within the framework of a project,
financed by the International Science and
Technology Center, in the forms both of application
specific ICs (ASIC) and an application specific
semicustom array (ASSA).
The generalized structural diagram of a
front-end electronic channel, considered in [1], is
shown in fig.
Fig. Generalized structural diagram of a channel of front -end electronic
Types of ICs and basic peculiarities of
their design and technology.
At present the basic set of ICs includes:
• an ASIC containing a high-speed
comparator and D-trigger, intended for
Buse line
Voltage stabilizer
restorer
High-speed
comparator
Output
stages
(drivers)
U?
application in fast timing (fractions of
nanosecond) circuits – A1181;
• a 4-channel ASIC of an amplifier -shaper
with differential input and output, intended
for amplitude data processing
(amplification, filtration) – A1182;

• a 4-channel ASIC of a differential low
power comparator of the nanosecond
range, intended for analog signal
discrimination – A1183A;
• a 4-channel ASIC of a differential
comparator of the nanosecond range,
having an output stage with open collector
and implementing the OR-function with
four inputs – A1183? ;
• the LSIC A1184, implemented with the
analog ASSA.
The use of ASSA allows by means of
changing only the plating layers the creation of
ASICs, which circuitry takes into consideration the
peculiarities of specific physical experiments, and
that is done within exceptionally short terms and at
low costs.
The circuitry of ICs, the contents of ASSA
functional modules have been elaborated by the
specialists of the Electronics Department of the
Moscow State Engineering Physics Institute
(Technical University), namely E.Atkin,
Yu.Volkov, I.Ilyushchenko, S.Kondratenko,
Yu.Mishin and A.Pleshko.
The lay -outs of all ICs are protected by
copyright documents, what witnesses on their
novelty and originality.
The set of active devices of ICs contains
NPN transistor structures, including those with
Shottky diodes, and PNP vertical transistors with
collectors in substrate [2]. The set of passive
devices contains high- and low -resistance resistors
and capacitors based on MOS structures. The range
of working currents of standard (library) elements
extends from fractions of mA to (3…5)mA, the
values of resistors – from tens of Ohm to tens of
kOhm.
The employment of such an element basis
provides simultaneously high electrical parameters
of IC, resistance to external disturbing factors,
easiness of the processes of IC manufacture, high
yield and, hence, a low cost.
The technological process of IC
manufacture is based on the planar-epitax
technology with element insulation by a reversebiased
p-n junction. The insulating boron diffusion
is then conducted by using highly doped p + -layers
with a retention of boron-silicon glass before the
second stage of diffusion. Comparing with usually
applied modes, that allowed to reduce the stray
capacitances of insulating layers by 1.5 times [3].
One should also regard as basic ones the
following technological peculiarities of ICs:
• small depths of p-n junction embedding,
equaling fractions of um (base width
hB~0.1um), what ensures (at appropriate
element lay -outs and manufacturing
processes) a unity-gain frequency about
7GHz for n-p-n transistor structures;
• the use of antimony, boron and arsenic ion
doping, what ensures high reproducibility
of layer electrophysical parameters in a
wide range of dopant concentrations;
• small sizes of elements, that influence the
IC speed to the greatest extent,
particularly, the use of the so-called full
emitter; the minimal emitter size is
restricted, in its turn, by the requirements
to the collector bulk resistance rC of
transistor structures;
• the use of molybdenum as a barrier metal
in Shottky diodes; molybdenum,
comparing with aluminum or platinum
silicide, has a considerably lower potential
barrier f B, what allowed to provide
simultaneously the specified direct voltage
drops UD and a low value of stray
capacitances C;
• the use of a double-level plating, based on
aluminum, doped with silicon (about 1%);
as an interlayer dielectric there was used
the silicon dioxide film, partially doped
with phosphorus.
Parameters of ICs
IC A1181
Functional destination: the IC is intended for use
in arrangements of nanosecond pulse processing.
The basic parameters of functional modules:
Parameters of comparator
Name of parameter, literal
designation, unit of measurement
Range of
parameter
values
? min Xmax
Input offset voltage, UOF, mV -3.0 +3.0
Input bias current, IBI, uA
Difference of input bias currents,
25.0
IDBI , uA
5.0
Range of input voltages, ^U IN, V
Current consumption from first
-2.5 +2.5
supply source, ICON.1, mA
Current consumption from second
supply source, ICON.2, mA
At ECL output
21.0
30.0
Output voltage high, U 1 OUT, V -1.00 -0.73
Output voltage low, U 0 OUT, V -1.00 -1.60
Switching time, tSW , ns 2.0
Transition time at switch-on
(switch-off), t 1,0 (t 0,1 ), ns
At TTL output
2.0
(2.0)
Output voltage high, U 1 OUT, V 2.4 4.0
Output voltage low, U 0 OUT, V 0.2 0.6
Output current, IOUT, mA 4 10
Switching time, tSW , ns 15
Transition time at switch-on
(switch-off), t 1,0 (t 0,1 ), ns
15
(15)

Parameters of ECL D-trigger
Name of parameter, literal
designation, unit of measurement
Range of
parameter
values
? min Xmax
Input current low at the D, C, R
inputs, I 0 IN , uA
Input current high at the D, C, R
0.5
inputs, I 1 IN , uA
Input voltage low, U
0.8
0 IN, V
Input voltage high, U
-2.0 -1.5
1 IN, V
Output voltage high, U
-1.1 -0.73
1 OUT, V
Output voltage low, U
-1.0 -0.73
0 OUT, V
Output current from output Q,
-1.95 -1.60
I Q OUT, mA
50
Propagation delay of signal at
inputs C and R, tPR.D, ns
0.8 1.5
Transition time at
(switch -off), t
switch-on
1,0 (t 0,1 ), ns
0.6
(0.6)
1.3
(1.3)
Current consumption, ICON, mA 60
Parameters of ECL-NIM converter
Name of parameter, literal
designation, unit of measurement
Range of
parameter
values
? min Xmax
Input current low (in statics), I 0 IN,
uA
Input current high (in statics), I
10
1 IN,
uA
Propagation delay of signal, tPR.D,
7 10
ns
0.8
Transition time at
(switch -off), t
switch-on
1,0 (t 0,1 ), ns
2.0
(2.0)
The IC has two supply sources, the
voltages of which are, correspondingly, USS1=3V,
USS2=-3V.The
voltages is ±5%.
permissible spread of supply
The IC is placed in the case H06-24-2b. It
is available also in a caseless version (modification
4).
IC A1182
Functional destination: the IC is intended to
amplify and shape signals, coming from highresistance
radiation detectors.
Basic parameters of the four-channel
amplifier -shaper IC
Name of parameter, literal
designation, unit of measurement
Typical
value of
parameter
Transimpedance, RT, kOhm 10
Input impedance, RIN, Ohm 160
Output rise-time, tR, ns
Output pulse duration at base level, tP,
5
ns
40
Output signal full swing, U, V 0.8
Range of input currents, IIN, uA 1÷100
Crosstalks of neighboring channels, % ≤1
Power consumption per channel, PCON,
mW
15
The IC has two supply sources, the
voltages of which are, correspondingly, USS1=3V,
USS2=-3V.The permissible spread of supply
voltages is ±5%.
The IC is placed in the case H09-28-1b. It
is available also in a caseless version (modification
4).
IC A1183
Functional destination: the IC is intended for
analog-to-digital signal conversion.
Basic parameters of the four-channel
comparator IC
Name of parameter, literal
designation, unit of measurement
Value of
parameter
Input currents, IIN, uA 8
Input offset voltage, UOF, mV 5
Comparator threshold, U TH, mV 10÷180*
Dynamic range, DR, V 3.0
Rise-time tR, ns 3
Fall-time t F, ns -
3
Propagation delay of signal, tPR.D, ns 6
Maximal common -mode voltage, UCM,
V
±1.1
Power consumption per channel, PCON,
mW
18
Output signal logic GTL (TTL)
Remarks:
*- the threshold voltage is given for the
case of using the comparator together with
amplifier-shaper A -1182;
**- GTL – low -level CMOS logic (logic
unity -- +1.2V, logic zero -- +0.4V).
The IC has two supply sources, the
voltages of which are, correspondingly, USS1=3V,
USS2=-3V. The permissible spread of supply
voltages is ±5%.
The IC is placed in the case H06 -24-2b. It
is available also in a caseless version (modification
4).
LSIC A1184
The LSIC contains 8 channels, collecting
and processing preliminary the analog signals from
tracking detectors. Each channel contains: a lownoise
preamp, linear shaper, comparator and output
driver. The LSIC contains also one OR-circuit,
common for the 8 chan nels. It is implemented on
the basis of an ASSA, containing 7000 elements,
including approximately 1400 n-p-n transistor
structures with a unity-gain frequency of 7GHz [3].
The printed circuit units (PCU), created in
the Research Institute of Pulse Technology
(Moscow) on the basis of the above described
ASICs and LSIC, by their electrical characteristics
are on a par with the PCUs, implemented with the
LSIC ASD/BLR, designed in the Pennsylvania
University (USA) and widely used by research
centers in the advanced countries of the world [4].
As it was marked earlier, the active devices
of the ICs A1181…A1184 are n-p-n transistor

structures. One should acknowledge, that the
absence of complementary high-frequency
transistor structures entails a complication of
circuitry, deterioration of performance of ICs and in
some cases practically excludes the possibility to
implement some important units in a differential
version. Therefore the further improvement of the
ICs for front-end electronics depends on the
creation of LSICs, containing n-p-n and p-n-p highfrequency
transistor structures with unity-gain
frequencies not less than (2…3)GHz, sufficiently
close values of their basic electrical parameters and
using dielectric insulation. That will, particularly,
allow t o:
• increase considerably the ratio of speed to
power consumption – the major quality
index of multichannel ICs; that is
especially important for amplifiers and
comparators, driving a large capacitive
load;
• increase essentially (1.5 - 2 times) the
integration scale at the expense of using pn-p
transistor structures as current setting
elements instead of resistors with high
nominal value;
• exclude practically the mutual coupling of
IC channels through supply sources at the
expense of introducing internal voltage
stabilizers, built with complementary
transistors; those stabilizers should meet
stringent requirements on the voltage drop
(not exceeding 100 – 300mV) and
efficiency (not less than 90%), whereas
practice shows, that a voltage stabilizer,
built with n-p-n transistors only, can not
have a voltage drop less than (1…1.5)V
and an efficiency greater than (60…70)%.
The elaboration of an ASSA, based on n-pn
and p-n-p high-frequency transistor structures, is
conducted at present by the specialists of a number
of Russian enterprises.
The created set of high-speed analog ICs
has successfully passed probation in the equipment
of the leading Russian and international research
centers. It can find application not only in front -end
electronic systems, but also in those of ecological
and radiational environment monitoring,
spectrometric material analysis, in space and
medical research.
Conclusion
1. At present in Russia the following ASICs and
LSIC for front-end electronic systems have been
designed and put into production:
• an ASIC containing a high-speed
comparator and D-trigger, intended for
application in fast timing (fractions of
nanosecond) circuits;
• a 4-channel ASIC of an amplifier-shaper
with differential input and output, intended
for amplitude data processing
(amplification, filtration);
• a 4-channel ASIC of a differential low
power comparator of the nanosecond
range, intended for analog signal
discrimination;
• a 4-channel ASIC of a differential
comparator of the nanosecond range,
having an output stage with open collector
and implementing the OR-function with
four inputs;
• the LSIC, implemented with the analog
ASSA.
• 2. The process of IC manufacture is based
on the planar-epitax technology with
insulation of elements by a reverse biased
p-n junction. Among the design and
technology peculiarities the following ones
should be regarded as basic:
• the use of highly doped p+-layers (NS ~
4*10 20 cm -3 ) for element insulation, what
in combination with the retention of boronsilicon
glass before the second stage of
diffusion allowed to reduce 1.5-fold the
stray capacitances of insulating junctions,
comparing with the commonly used modes
(NS ~ 4*10 18 cm -3 ).
• small depths of p-n junction embedding,
equaling fractions of um (base width
hB~0.1um), what ensures (at appropriate
element lay-outs and manufacturing
processes) a unity-gain frequency about
7GHz for n-p-n transistor structures;
• the use of antimony, boron and arsenic ion
doping, what ensures high reproducibility
of layer electrophysical parameters in a
wide range of dopant concentrations;
• small sizes of elements, that influence the
IC speed to the greatest extent,
particularly, the use of the so-called full
emitter; the minimal emitter size is
restricted, in its turn, by the requirements
to the collector bulk resistance rC of
transistor structures;
• the use of molybdenum as a barrier metal
in Shottky diodes; molybdenum,
comparing with aluminum or platinum
silicide, has a considerably lower potential
barrier f B, what allowed to provide
simultaneously the specified direct voltage
drops UD and a low value of stray
capacitances C;
• the use of a double-level plating, based on
aluminum, doped with silicon (about 1%);
as an interlayer dielectric there was used
the silicon dioxide film, partially doped
with phosphorus.
3. On the basis of the designed ASICs and LSIC
there have been implemented PCUs, by their
electrical parameters being on a par with those
implemented with the LSIC ASD/BLR, created
in the Pennsylvania University (USA) and
widely used by research centers in the advanced
countries of the world.

References
1. E.Atkin, Yu.Volkov, S.Kondratenko,
Yu.Mishin, A.Pleshko. “Analog signal
preliminary processing ICs, based on
bipolar semicustom arrays” – Scientific
Instruments, 1999, #5, pp.54-57.
2. A.Goldsher, V.Kucherskiy, V.Mashkova.
“Components of Fast Analog Integrated
Microcircuits for Front-end Electronic
Systems” – Fourth Workshop on
Electronics for LHC Experiments. Rome,
September 21-25, 1998, pp.545 – 549.
3. A.Goldsher, V.Kucherskiy, V.Mashkova.
“A Semicustom Array Chip for Creating
High-speed Front -end LSICs” – Third
Workshop on Electronics for LHC
Experiments. London, September 22 -26,
1997, pp.257 – 259.
4. E.Atkin, Yu.Volkov, Yu.Mishin,
V.Subbotin, V.Chernikov. “Electronic
units for the collection and preliminary
processing of multiwire chamber signals”
– Scientific Instruments, 1999, #5, pp.58-
62.

New building blocks for the ALICE SDD readout and detector control system in a
commercial 0.25µm CMOS technology
Abstract
This paper describes building blocks designed for the
readout and detector control systems of the Silicon Drift
Detectors (SDDs) of ALICE. In particular, the paper
focuses on a low−dropout regulator, a charge redistribution
ADC and a current steering DAC. All the parts have been
developed in a commercial 0.25µm CMOS technology, using
radiation tolerant layout practices.
I. INTRODUCTION
Silicon Drift Detectors will be used in the third and fourth
layer of the Inner Tracking System of the ALICE experiment
[1]. The specifications and the implementation of the
electronics for the SDDs are described in detail in [2], [3],
[4] and will not be covered here. For the purpose of this work
it is sufficient to remember that the SDD system requires the
development of four full−custom ASICs, which are used both
for data processing and control tasks. Two of these chips are
purely digital and two are mixed−mode designs. The
building blocks presented in this paper will be integrated in
the mixed−mode circuits.
The more complex mixed−signal component is the
front−end chip (named PASCAL), which performs the
amplification, filtering and analogue−to−digital conversion
of the detector signals. In its final implementation, the ASIC
host 64 amplifiers, each coupled with a row of a switched
capacitor array (SCA), having 256 cells. When a trigger
signal is received, 32 on board ADCs convert the analogue
data stored in the pipeline to a 10 bit digital code. A single
ADC digitises the content of two adjacent rows of the SCA.
The converter, described in detail in [5], is based on the
successive approximation technique [6], which offers a very
good trade−off between speed and power consumption. Due
to the severe space constraints on the front−end board, the
reference voltage for the ADCs must be provided on chip.
The generation of this reference is an issue, because the
voltage source will be heavily loaded by the ADCs, which
operate in parallel. For these reasons, a dedicate low dropout
regulator had to be developed. The design of this block as
well as the first results of the experimental measurements are
discussed in section II.
The chip for the Detector Control System (DCS)
performs the monitoring of vital parameters of the system
A.Rivetti, G. Mazza, M. Idzik and F. Rotondo
for the ALICE collaboration
INFN, Sezione di Torino, Via Pietro Giuria 1 − 10125 Torino −Italy
rivetti@to.infn.it
and the control of some critical voltages and currents. For
instance, this chip is used to measure the temperature of the
electronics board. Additionally, it has to generate the
amplitude−controlled signal which is needed to trigger the
calibration circuitry of the detector. Therefore, an ADC and
a DAC are the basic elements of the DCS ASIC. These
circuits need to provide a medium resolution (8 bits), while
minimising area and power consumption. They are
described in section III and in section IV of this paper,
respectively.
II. THE LOW DROPOUT REGULATOR
The low dropout regulator provides a stable DC voltage
of 1.9V that is needed by the ADCs of the front−end chip.
Depicted in fig. 1, the circuit uses a linear scheme, [7]
whose key elements are the error amplifier A1, the pass
transistor P0 and the resistive feedback network formed by R1
and R2. All these components are integrated on chip. The
output voltage is derived from the reference voltage VBG,
provided by a bandgap circuit.
The capacitor C0 serves to filter the current spikes and
provides the frequency compensation of the loop. Given the
high value required for C0 (1µF), an external discrete
component must be used. In fact, it is very important to
assure that the regulator works in all conditions with an
adequate phase margin. The value chosen for C0 guarantees
that the feedback loop has always a phase margin of 76
degrees.
Figure 1 : LDO simplified scheme.

The LDO can deliver to the load a maximum current of
100mA. The static power consumption of the circuit is
2.5mW and it occupies an area of 230 x 150 µm2 (excluding
the bandgap reference, which will be shared by several
circuits on the front−end chip.)
In order to check the functionality of the device before its
integration in the final version of the front−end ASIC, a
dedicated test chip has been produced and measured. The test
results show a good agreement with the computer
simulations. The circuit provides the required reference
voltage with an overall accuracy of 1%. As an example of
the performance of the circuit, Figure 2 reports the plot
obtained for the load regulation. The current driven by the
load is changed from zero to the maximum value of 100mA.
The maximum change in the output voltage is 13 mV,
resulting in a load regulation figure (defined as ∆V0/∆I0) of
0.13 Ω.
Voltage (V)
1.920
1.917
1.915
1.912
1.910
1.907
1.905
Load regulation
0 500 1000 1500 2000 2500 3000
time (ns)
Figure 2 : LDO load regulation performance
The line regulation has been checked for Vdd ranging
from 2.2 to 2.7 V, corresponding to the maximum power
supply variation acceptable for the front−end chip. In this
interval, the output voltage changes by 1mV giving a line
regulation (∆V0/∆Vi) of 0.002. The measured noise at the
output of the LDO is 250µV rms, but the accuracy of this
measurement is limited by the experimental set−up.
III. THE ANALOGUE TO DIGITAL CONVERTER
The ADC is an evolution of the converter embedded in
the front−end chip. In order to profit as much as possible
from existing blocks, the same successive approximation
topology used in PASCAL has been chosen. The main
modification occurs in the DAC, in which the resolution has
been traded for area. Figure 3 shows the block diagram of a
typical implementation of a 8 bit charge redistribution ADC.
The two basic elements of the circuit are a voltage
comparator and a DAC made of binary weighted capacitors.
The conversion is performed in two steps:
� In the acquisition phase, all the capacitors are
connected in parallel and are used to sample the input
signal.
� In the redistribution phase, the capacitors are used
individually to generate binary fractions of the
reference voltage, which are compared with the sample
previously stored.
VIN
VREF
VREF
C C 2C 4C 8C 16C 32C 64C 128C
GND
VREF
Figure 3 : Schematic of a generic 8 bit ADC
The conversion algorithm is described in detail in [6]. For
the purpose of our discussion, it is sufficient to observe that
if the DAC is implemented exactly with the scheme of
Figure 3, its area doubles for every extra bit of resolution
required. For instance, an 8 bit DAC occupies twice the area
needed by a 7 bit one.
In order to reduce the surface of the DAC, the scheme of
Figure 4 has been used. In this approach, the DAC has been
splitted in two blocks, each with a 5 bit capability.
VREF
VREF
C
GND
2C
4C
8C
VIN
16C
VREF
GND
Figure 4 : Schematic of the implemented ADC with
segmented DAC
The first DAC samples also the input signal and is
capacitively coupled to the second DAC, which is used only
during the redistribution phase.
In this way, two advantages are achieved:
� The total area is equivalent to the area of a 6 bit DAC,
which is four times smaller than the area of a direct 8 bit
DAC.
� Since the sampling is performed only by the main DAC,
the input capacitance of the ADC is reduced by a factor
eight with respect a straightforward 8 bit design.
The matching between the capacitors is critical to obtain
a good linearity in the ADC. To improve the matching, in
the layout only a fundamental cell is used and the bigger
capacitors are built by connecting a suitable number of
elementary cells in parallel. Actually, the structure of Figure
C
C
2C
4C
8C
16C
VREF
C
VREF
O UT
OUT

4 is more sensitive than the architecture of Figure 3 to the
effect of random mismatches. This point can be understood
by noting that in the ADC of Figure 4 the capacitor which
determines the MSB is formed by 16 unit elements, whereas
in Figure 3 it is composed by 128 individual cells. In the
latter case, the MSB capacitor will be more precise, because
it uses more elements in parallel and the random error
affecting each one tend to average out. For this reason, the
ADC is built using two 5 bit DACs instead of two 4 bit
DACs, which in principle would be sufficient to get a total 8
bit resolution.
It must also be observed that the circuit of Figure 3 could
be used to implement a 10 bit ADC. However, for the
matching reasons mentioned above this resolution can not be
assured if the individual capacitor is implemented with the
minimum size allowed by the technology. In our application
a 10 bit resolution is not required, whereas the area of the
circuit is important. Therefore, the minimum size
capacitance has been used, targeting 8 bit performance.
Nevertheless, two extra bits have been made available for
test purposes.
The layout of the circuit has an area of 300 x 800 µm2 ,
which is about 60% of what would be required by the direct
implementation of Figure 3.
A test chip containing three identical converters has
been designed and fabricated. The ADC is tested by sending
to the circuit a sinusoidal input signal and reading the digital
output codes with a logic state analyser. The data are the
processed with a dedicated software to calculate the DNL,
the INL, and the FFT. In the measurements, the ADC is
operated with a full scale range of 1V, which results in a
LSB of 4mV.
During the test, the circuit is running with a clock of
40MHz. Since two clock cycles are left to sample the input
signal and to compensate the offset in the comparator [5], 10
clock periods are required for a complete 8 bit conversion.
The sampling frequency is hence 4Msample/sec. The circuit
is powered with a single rail power supply of 2.5V and
dissipates 3mW.
Figure 5 show the result of a typical FFT that is obtained
in the measurements.
Figure 5 : FFT measured for the ADC.
As it can be seen from the figure, the second harmonic is
well below 48dB and the ADC has a very low distortion.
The converter has a maximum DNL of 0.8 LSB, which is
sufficient to guarantee a 8 bit resolution without missing
codes. To give a more intuitive view of the performance of
the circuit, Figure 6 shows the result of the conversion of a
full scale ramp.
Figure 6 : Digitization of a full scale ramp.
IV. THE DIGITAL TO ANALOGUE CONVERTER
The 8 bit DAC is the other analogue building blocks for
the DCS chip. It must be observed that switched capacitor
DAC used in the ADC is very compact, but it suffers from a
number of drawbacks. These drawbacks make it inadequate
to work as a stand−alone component. For instance, the
parasitic capacitance on the top plate attenuates the voltage
steps generated by the DAC. This and other phenomena are
of minor concern in an ADC, since they affect in the same
way both the signal and the partitions of the reference
voltage that are used in the conversion. However, they can
determine severe limitations when the DAC is used just to
convert a digital code to an analogue level. For these reasons
it has been necessary to develop a new circuit, using a
different approach.
The circuit is based on a current steering configuration
and is made of an array of current sources and a digital
control logic. In order to improve as much as possible the
matching between the sources and hence the linearity, a fully
thermometric segmentation has been chosen. Therefore, the
DAC is formed by 256 identical cells, which are organised in
a 16x16 matrix.
The schematic of the elementary bit cell is shown in
Figure 7. The cell is essentially a cascode current mirror,
which copies a reference current. The sizes of the transistor
are dictated by the need of having an adequate area and
overdrive voltage, in order to get an appropriate matching. If
the cell is selected by the control logic, the switch driven by
sel_b is closed and the current is directed towards the output
node. At the output node, all the currents generated by the
individual mirrors are summed and converted to a voltage.
The current−to−voltage conversion can be carried−out either
by a simple resistor or by a transimpedance amplifier. Both

options are available in the DAC.
Each elementary cell is biased with a tail current of 5µA,
resulting in a static power consumption 3mW for the whole
analogue part of the DAC.
The circuit has been optimised to reach a conversion
speed of at least 50Msamples/sec.
Figure 7 : Schematic of the unit cell of the DAC.
Shown if Figure 7, the layout of the complete DAC has
an area of 1 x 0.6 mm2. . The test chip is in production and no
experimental result is available at the time of writing.
Figure 8 : Layout of the full DAC
V. CONCLUSIONS
The front−end and detector control electronics of the
SDD of ALICE requires complex analogue building blocks.
The most critical circuits have been prototyped, in order to
check their functionality before their integration in the final
ASICs. These circuits are a low dropout regulators, an ADC
and a DAC with moderate resolution (8 bits) but reduced
area.
The low dropout regulator is needed to generate on board
the reference voltage for the ADC of the front−end chip. The
circuit integrates all the critical parts except the filtering
capacitor and has shown characteristics which are adequate
for the application. The output voltage change by 1mV for a
change of 0.5V in the power supply. The regulator is able to
provide a maximum current of 100mA with an output
voltage drop of 13mV. The noise is less than 200µV rms.
The analogue to digital converter uses a segmented
architecture in the DAC, in order to minimise the area as
much as possible. The area of the ADC is 0.24mm2 .The
circuit has a resolution of 8 bits over a full scale range of 1V
and operate at a speed of 4Msamples/sec, dissipating 3mV
from a 2.5V supply.
The last building block that has been developed is a
current steering digital to analogue converter. This circuit is
still in production and it will be tested in the forthcoming
months.
All the three designs discussed in this paper have been
implemented in a 0.25µm CMOS technology, using enclosed
layout transistors and guardrings to prevent the damage from
ionising radiation.
VI. REFERENCES
[1] The ALICE collaboration, "Technical proposal of the
ALICE experiment", CERN/LHCC 95−71, Dec. 1995.
[2] The ALICE collaboration, "Technical design report of
the Inner Tracking System", CERN/LHCC 99−12, June
1999, pp 83−173.
[3] A. Rivetti, G. Anelli, F. Anghinolfi, G. Mazza, P.
Jarron, "A Mixed−Signal ASIC for the Silicon Drift
Detectors of the ALICE Experiment in a 0.25µm CMOS",
Proceedings of the Sixth Workshop on Electronics for LHC
Experiments CERN, LHCC/2000−041, Oct. 2000.
[4] G. Mazza et al., "Test Results of the Front−end
System for the Silicon Drift Detectors of ALICE,
Proceedings of the Seventh Workshop on Electronics for
LHC Experiments, Stockholm, Sept. 2001.
[5] A. Rivetti, G. Anelli, F. Anghinolfi, G. Mazza and F.
Rotondo, "A Low−Poer 10 bit ADC in a 0.25µm CMOS:
Design Considerations and Test Results", IEEE Transactions
on Nuclear Science, Aug. 2001.
[6] J. L. McCreary and P. Gray, "All−MOS Charge
Redistribution Analog−to−Digital Conversion Techniques −
Part I", IEEE Journal of Solid State Circuits, vol. SC 10, no.
6, pp. 371−379, Dec. 1975.
[7] Texas Instruments, "Technical Review of low
Dropout Regulator Operation and Performance" application
note SLVA072, Aug. 1999.