ZBT Memory: One 2MB memory bank was used for this project
ZBT Memory: One 2MB memory bank was used for this project
ZBT Memory: One 2MB memory bank was used for this project
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4. Description of the Design Tree<br />
Main Directory: Project<br />
File Directory Purpose Origin<br />
Idct.vhd Xil_idct_v1_00_a RGB/greyscale XAPP529, modified<br />
converter VHDL file by Eric Wang<br />
Idct_core.vhd<br />
Xil_idct_v1_00_a Wrappers <strong>for</strong><br />
XAPP529, modified<br />
Xil_Idct_v1_00_a.vhd<br />
RGB/greyscale<br />
converter<br />
by Eric Wang<br />
Clk_align.vhd Clk_align_v1_00_a Ensure clock alignment<br />
between <strong>ZBT</strong> <strong>memory</strong><br />
and internal clk<br />
Tutorial M08<br />
Testidct.npl Testidct ISE Project file <strong>for</strong><br />
simulating<br />
RGB/Greyscale<br />
converter<br />
ISE<br />
Converter_tb.tbw Testidct Test bench <strong>used</strong> to<br />
simulate<br />
RGB/Greyscale<br />
converter.<br />
ISE
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