Switched-Capacitor Circuits - University of Toronto

Switched-Capacitor Circuits 

University of Toronto 


David Johns and Ken Martin 


(johns@eecg.toronto.edu) 

(martin@eecg.toronto.edu) 

Basic Building Blocks 

Opamps 

• Ideal opamps usually assumed. 

• Important non-idealities 

— dc gain: sets the accuracy of charge transfer, 

hence, transfer-function accuracy. 

— unity-gain freq, phase margin & slew-rate: sets 

the max clocking frequency. A general rule is that 

unity-gain freq should be 5 times (or more) higher 

than the clock-freq. 

— dc offset: Can create dc offset at output. Circuit 

techniques to combat this which also reduce 1/f 

noise. 

1 of 60 

© D. Johns, K. Martin, 1997 


© D. Johns, K. Martin, 1997

Double-Poly Capacitors 

C p1 

metal 

poly2 

poly1 



C 1 

C p2 

thin oxide 

(substrate - ac ground) 

cross-section view 

thick oxide 

metal 

bottom plate 

C p1 

• Substantial parasitics with large bottom plate 

capacitance (20 percent of ) 

• Also, metal-metal capacitors are used but have even 

larger parasitic capacitances. 

Switches 

Symbol 

p-channel 

 

v 1 

v 1 


C 1 


 

 

v 2 

v 2 

C 1 

C p2 

equivalent circuit 



 

• Mosfet switches are good switches. 

— off-resistance near G range 

— on-resistance in 100 to 5k 

range (depends on 

transistor sizing) 

• However, have non-linear parasitic capacitances. 

 

v 1 

v 1 

 

v 2 

n-channel 

transmission 

gate 

v 2 



Non-Overlapping Clocks 

1 T 

Von Voff Von Voff n – 2 

2 n – 1 n n + 1 

n – 3 2n– 

1 2n+ 

1 2 



t T 

tT • Non-overlapping clocks — both clocks are never on 

at same time 

• Needed to ensure charge is not inadvertently lost. 

• Integer values occur at end of . 

• End of is 1/2 off integer value. 

2 


f s 

1 

-- 

T 

Switched-Capacitor Resistor Equivalent 

V 1 

1 

2 

C 1 

V 2 

Q = C1V1– V2 every clock period 

 

1 

delay 

delay 

1 

2 



Qx = CxVx (1) 

• C1 charged to V1 and then V2 during each clk period. 

Q1 = C1V1– V2 (2) 

• Find equivalent average current 

Iavg = 

C1V1– V2 ----------------------------- 

T 

where T 

is the clk period. 

V 1 

R eq 

R eq 

= 

T 

----- 

C1 V 2 

(3) 



Switched-Capacitor Resistor Equivalent 

• For equivalent resistor circuit 

• Equating two, we have 

• This equivalence is useful when looking at low-freq 

portion of a SC-circuit. 

• For higher frequencies, discrete-time analysis is 

used. 



I eq 

R eq 

= 

V1 – V2 ----------------- 

R eq 

T 

= ----- = 

C 1 

1 

---------- 

C1fs Resistor Equivalence Example 

(4) 

(5) 



• What is the equivalent resistance of a 5pF 

capacitance sampled at a clock frequency of 100kHz. 

• Using (5), we have 

R eq 

1 

5 10 12 – 

100 10 3 

= -------------------------------------------------------- = 2M 

 

• Note that a very large equivalent resistance of 2M 

can be realized. 

• Requires only 2 transistors, a clock and a relatively 

small capacitance. 

• In a typical CMOS process, such a large resistor 

would normally require a huge amount of silicon 

area. 



Parasitic-Sensitive Integrator 

vci() t 

vi( n) 

= vci( nT) 

1 

vc1() t 

• Start by looking at an integrator which IS affected by 

parasitic capacitances 

• Want to find output voltage at end of 1 in relation to 

input sampled at end of . 

vci( nT – T) 


C 1 

• At end of 


vcx() t 

C 1 

2 

1 

vc2( nT) 

C 2 

vco() t 

1 

vo() n = vco( nT) 


C 2 

• But would like to know the output at end of 

• leading to 

vco( nT – T) 

vci( nT – T 2) 

1 on 2 on 

2 

C 2 



C1 vco( nT – T 2) 

C2vco( nT – T 2) 

= C2vco( nT – T) 

– C1vci( nT – T) 

C2vco( nT) 

= C2vco( nT – T 2) 

C2vco( nT) 

= 

C2vco( nT – T) 

– C1vci( nT – T) 

1 

(6) 

(7) 

(8) 




• Modify above to write 

and taking z-transform and re-arranging, leads to 

• Note that gain-coefficient is determined by a ratio of 

two capacitance values. 

• Ratios of capacitors can be set VERY accurately on 

an integrated circuit (within 0.1 percent) 

• Leads to very accurate transfer-functions. 

1 

2 

vci() t 

vcx() t 

vco() t 



vo( n) 

vo( n – 1) 

C1 = – ----- vi( n – 1) 

Hz () Vo z () 

----------- 

Vi() z 

= 

C 2 

C 1 

1 

– ----- ---------- 

z– 

1 

C 2 

Typical Waveforms 

(9) 

(10) 



t 

t 

t 

t 

t 



Low Frequency Behavior 

• Equation (10) can be re-written as 

Hz () 

• To find freq response, recall 


= 

C 1 

z 

----- 

 

12 / – 

z12 / z 12 / – 

– --------------------------- 

– 

C 2 

z ejT = = cosT+ jsinT z12 / = T ------- T 

cos + jsin------- 

 

2 2 

z 12 / – = T ------- T 

cos – jsin------- 

 

2 2 

He jT 

( ) = 

T ------- T 

cos – jsin------- 

 

C1 2 2 

– ----- --------------------------------------------------- 

C2 T 

j2 sin------- 

 

2 

Low Frequency Behavior 

• Above is exact but when T « 1 (i.e., at low freq) 


He jT 

( ) 

(11) 

(12) 

(13) 

(14) 

(15) 



• Thus, the transfer function is same as a continuoustime 

integrator having a gain constant of 

K I 

which is a function of the integrator capacitor ratio 

and clock frequency only. 

C 1 

1 

– ----- --------- 

jT 

C 1 

C 2 

----- 1 

 

-- 

T 

C 2 

(16) 

(17) 



Parasitic Capacitance Effects 

vi() n 

C p1 

1 

C p3 

• Accounting for parasitic capacitances, we have 

Hz () 

• Thus, gain coefficient is not well controlled and 

partially non-linear (due to being non-linear). 



C 1 

= 

2 

C p2 

C 2 

C1+ Cp1 1 

– --------------------- ---------- 

z– 

1 

C 2 

C p1 

C p4 

vo( n) 

Parasitic-Insensitive Integrators 

vci() t 

vi( n) 

= vci( nT) 

1 

C 1 

• By using 2 extra switches, integrator can be made 

insensitive to parasitic capacitances 

— more accurate transfer-functions 

— better linearity (since non-linear capacitances 

unimportant) 

2 

2 1 

C 2 

1 

vco() t 

vo() n = vco( nT) 

(18) 



1 



vci( nT – T) 

+ 

- 


C 2 

C1 vco( nT – T) 

• Same analysis as before except that C1 is switched 

in polarity before discharging into . 

• A positive integrator (rather than negative as before) 


vci( nT – T 2) 

1 on 2 on 

Hz () Vo z () 

----------- 

Vi() z 

= 

C 1 

C 2 

- 

+ 

1 

----- ---------- 

z– 

1 

C 2 



C 1 

C 2 

vco( nT – T 2) 

(19) 



• has little effect since it is connected to virtual gnd 

C p3 

• has little effect since it is driven by output 

C p4 

vi( n) 

1 

C 1 

2 

2 1 

C p1 

C p2 

• Cp2 has little effect since it is either connected to 

virtual gnd or physical gnd. 

C p3 

C 2 

C p4 

vo( n) 

1 




• Cp1 is continuously being charged to vi( n) 

and 

discharged to ground. 

• 1 on — the fact that Cp1 is also charged to vi( n – 1) 

does not affect charge. 

C 1 

• 2 on — Cp1 is discharged through the 2 switch 

attached to its node and does not affect the charge 

accumulating on . 

C 2 

• While the parasitic capacitances may slow down 

settling time behavior, they do not affect the discretetime 

difference equation 


Parasitic-Insensitive Inverting Integrator 

vi( n) 

Vi() z 

1 


C 1 

1 

2 2 



• Present output depends on present input(delay-free) 

C 2 

vo( n) 

Vo() z 

C2vco( nT – T 2) 

= C2vco( nT – T) 

C2vco( nT) 

= C2vco( nT – T 2) 

– C1vci( nT) 

Hz () 

• Delay-free integrator has negative gain while 

delaying integrator has positive gain. 

Vo z () C1 z 

----------- = 

– ----- ---------- 

Vi() z C2z– 1 

1 

(20) 

(21) 

(22) 



V1() z 

V2() z 

V3() z 

Signal-Flow-Graph Analysis 

V1() z 

V2() z 

V3() z 

1 C 2 

2 

1 C 3 

2 

C 1 

C1 1 z 1 – – – 

C2z 1 – 

– C3 University of Toronto 


2 

1 

1 

2 

C A 

1 

------ 1 

1z 

1 – 

--------------- 

– 

C A 

First-Order Filter 

Vo() z 

1 

Vo() z 

Vin() s 

Vout() s 

• Start with an active-RC structure and replace 

resistors with SC equivalents. 

• Analyze using discrete-time analysis. 





Vi() z 

1 C 2 

2 



C 1 

– 

C 2 

1 

2 

2 

1 C 3 

C A 

1 

------ 1 

1z 

1 – 

--------------- 

– 

C A 

1 

2 

Vo() z 

Vi() z 

Vo() z 

C1 1 z 1 – – – 


– C3 First-Order Filter 

CA 1 z 1 – – Vo() z – C3Vo() z – C2Vi() z C1 1 z 1 – 

= 

– – Vi() z 

C 1 

C A 

C1+ C2 C1 ------------------ z– 

------ 

CA CA 1 C – ---------------------------------------- 

3 

+ ------ z– 

1 

 

C A 

C 2 

Hz () Vo z () 

 

------ 1– 

z– 1+ 

------ 

CA CA ----------- 1 z 

Vi() z 

1 – 

– ----------------------------------------------------- 

C 

= 

3 

– + ------ 

= 

1 



(23) 

(24) 





• The pole of (24) is found by equating the 

denominator to zero 

z p 

C A 

------------------- 

CA + C3 • For positive capacitance values, this pole is 

restricted to the real axis between 0 and 1 

— circuit is always stable. 

• The zero of (24) is found to be given by 

z z 

• Also restricted to real axis between 0 and 1. 


= 

= 

C 1 

------------------ 

C1 + C2 First-Order Filter 

(25) 

(26) 



The dc gain is found by setting z = 1 which results in 

H( 1) 

= 

– C2 --------- 

(27) 

• Note that in a fully-differential implementation, 

effective negative capacitances for C1, C2 and C3 can 

be achieved by simply interchanging the input wires. 

• In this way, a zero at z 

setting 

= – 1 could be realized by 

C1 = 

– 0.5C2 (28) 

C 3 




First-Order Example 

• Find the capacitance values needed for a first-order 

SC-circuit such that its 3dB point is at 10kHz when a 

clock frequency of 100kHz is used. 

• It is also desired that the filter have zero gain at 

50kHz (i.e. z = – 1) 

and the dc gain be unity. 

• Assume = 10pF. 

C A 

Solution 

• Making use of the bilinear transform 

p = z – 1 

z+ 1 

the zero at – 1 is mapped to 

= . 

• The frequency warping maps the -3dB frequency of 

10kHz (or 0.2 rad/sample) 

to 



= 

0.2 

tan---------- 

2 

= 0.3249 

• in the continuous-time domain leading to the 

continuous-time pole, , required being 

p p 

• This pole is mapped back to given by 

p p 

– 0.3249 

zp = 

1 + pp -------------- 

1 – pp = 0.5095 

• Therefore, Hz () is given by 

Hz () 

= 

z p 

kz + 1 

= 

-----------------------z 

– 0.5095 



(29) 

(30) 

(31) 

(32) 



) 



• where k is determined by setting the dc gain to one 

(i.e. H( 1) 

= 1) 

resulting 

Hz () 

• or equivalently, 

= 

0.24525z+ 1 

----------------------------------z 

– 0.5095 

(33) 

Hz () = 

0.4814z + 0.4814 

----------------------------------------- 

1.9627z – 1 

(34) 

• Equating these coefficients with those of (24) (and 

assuming = 10pF) 

results in 

1 

2 

C A 

C 1 

C 2 


C 1 

C2 C3 = 4.814pF 

= – 9.628pF 

= 9.628pF 

Switch Sharing 

1 

2 

• Share switches that are always connected to the 

same potentials. 

C 3 

1 

2 

C A 

(35) 

(36) 

(37) 



Vo() z 



Fully-Differential Filters 

• Most modern SC filters are fully-differential 

• Difference between two voltages represents signal 

(also balanced around a common-mode voltage). 

• Common-mode noise is rejected. 

• Even order distortion terms cancel 

v 1 

– v1 

nonlinear 

element 

nonlinear 

element 

v p1 

v n1 

= 

= 



2 3 4 

k1v + k 

1 2v1 + k3v1 + k4v1 + 

+ 

- 

v diff 

2 

= 

3 5 

2k1v + 2k 

1 3v1 + 2k5v 1 + 

– k1v + k 

1 2v1 – k3v1 + k4v1 + 


C 1 

2 2 

3 

CA 2 4 

+ 

 

C2 1 

1 + 

Vi() z 

Vo() z 

 

1 1 

- 

- 

C2 2 

C 1 

2 

C 3 

C 3 

C A 2 

1 

1 






• Negative continuous-time input 

— equivalent to a negative C1 2 2 


C 1 

CA 2 + 

 

C2 1 

1 + 

Vi() z 

Vo() z 

 

1 1 

- 

- 

C2 2 

C 1 


2 

C 3 

C 3 

C A 2 

1 

1 


• Note that fully-differential version is essentially two 

copies of single-ended version, however ... area 

penalty not twice. 

• Only one opamp needed (though common-mode 

circuit also needed) 

• Input and output signal swings have been doubled 

so that same dynamic range can be achieved with 

half capacitor sizes (from kT 

C analysis) 

• Switches can be reduced in size since small caps 

used. 

• However, there is more wiring in fully-differ version 

but better noise and distortion performance. 





Vi() z 

Vin() s 


Low-Q Biquad Filter 

Ha() s 

Vout s () 

---------------- 

Vin() s 

o ko 1 

C A 


= 

1 

1 k1 k 2 

= 

k2s 2 

+ k1s + ko s 2 

– --------------------------------------- 

 

o 

------ 2 

+ s + o 

Q 

1 o Vc1() s 

– 1 o Q o = 1 

C B 


C 1 

2 

1 

1 

2 

1 K1C1 1 K 2 

5C2 2 

2 

2 

1 

K 2 C 2 

K 3 C 2 

1 

2 

2 

K 4 C 1 

V1() z 

1 

2 

1 

K 6 C 2 

C 2 

Vout() s 

1 

2 

(38) 



Vo() z 



1

– 

K 1 



1 

1 z 1 – 

--------------- 

– 

– K2 

– 1 z 1 – – 

K 3 

V1() z 

– 

K 4 

K5z 1 – 

– K6 1 

1 z 1 – 

--------------- 

– 

Vi() z 

Vo() z 

Hz () Vo z () 

----------- 

Vi() z 

= 


K2+ K3z 2 

+ K1K5– K2 – 2K3z + K3 1+ K6z 2 

– -------------------------------------------------------------------------------------------------- 

+ K4K5– K6 – 2z+ 

1 

Low-Q Biquad Filter Design 

Hz () 

= 

a2z 2 

+ a1z + a0 b2z 2 

– ------------------------------------- 

+ b1z + 1 

• we can equate the individual coefficients of “z” in 

(39) and (40), resulting in: 

K3 = a0 K2 = a2 – a0 K1K5 = a0 + a1 + a2 K6 = b2 – 1 

K4K5 = b1 + b2 + 1 

• A degree of freedom is available here in setting 

internal V1() z output 

(39) 



(40) 

(41) 

(42) 

(43) 

(44) 

(45) 



Low-Q Biquad Filter Design 

• Can do proper dynamic range scaling 

• Or let the time-constants of 2 integrators be equal by 

K4 = K5 = b1 + b2 + 1 

(46) 

Low-Q Biquad Capacitance Ratio 

• Comparing resistor circuit to SC circuit, we have 

K4 K5 oT (47) 

oT K6 --------- 

Q 

(48) 

• However, the sampling-rate, 1 T, 

is typically much 

larger that the approximated pole-frequency, , 



oT « 1 

Low-Q Biquad Capacitance Ratio 

• Thus, the largest capacitors determining pole 

positions are the integrating capacitors, and . 

• If Q 1, 

the smallest capacitors are K4C1 and K5C2 resulting in an approximate capacitance spread of 

1 oT. o 

(49) 



• If Q 1, 

then from (48) the smallest capacitor would 

be K6C2 resulting in an approximate capacitance 

spread of Q oT — can be quite large for Q » 

1 

C 1 

C 2 




High-Q Biquad Filter 

• Use a high-Q biquad filter circuit when Q » 1 

• Q-damping done with a cap around both integrators 

• Active-RC prototype filter 

1 o Vin() s 

o ko k1 o University of Toronto 

C 1 

1 Q 

= 1 C2 = 1 

– 1 o k 2 


C 1 

• Q-damping now performed by K6C1 Vout() s 



Vi() z 

Vo() z 

2 

1 

2 

2 

1 

1 

2 

1 K1C 1 

1 K 

2 5C 2 

K 2 C 1 

K 3 C 2 

2 

K 4 C 1 

V1() z 

1 

K 6 C 1 

C 2 

1 





• Input K1C1 : major path for lowpass 

• Input K2C1 : major path for band-pass filters 

• Input K3C2 : major path for high-pass filters 

• General transfer-function is: 

Hz () (50) 

• If matched to the following general form 

Vo z () K3z ----------- 

Vi() z 

2 

+ K1K5+ K2K5 – 2K3z + K3– K2K5 

z 2 

= – ---------------------------------------------------------------------------------------------------------------- 

+ K4K5+ K5K6 – 2z+ 

1– K5K6 

Hz () 


= 

a2z 2 

+ a1z + a0 z 2 

– ------------------------------------- 

+ b1z + b0 High-Q Biquad Filter 

K1K5 = a0 + a1 + a2 K2K5 = a2 – a0 K3 = a2 K4K5 = 1 + b0 + b1 K5K6 = 1 – b0 • And, as in lowpass case, can set 

K4 = K5 = 1 + b0 + b1 • As before, K4 and K5 approx oT « 1 but K6 

1 Q 

(51) 



(52) 

(53) 

(54) 

(55) 

(56) 

(57) 




Charge Injection 

• To reduce charge injection (thereby improving 

distortion) , turn off certain switches first. 

Vi() z 

1 C 2 

Q 1 

2 

C 1 

Q2Q3 1a 

Q4 2a • Advance 1a and 2a so that only their charge 

injection affect circuit (result is a dc offset) 


C 3 

Q 5 

C A 

Charge Injection 

1 Q6 2 

Vo() z 

1 



• Note: 2a connected to ground while 1a connected 

to virtual ground, therefore ... 

— can use single n-channel transistors 

— charge injection NOT signal dependent 

QCH = – WLCoxVeff 

= – WLCoxVGS 

– Vt (58) 

• Charge related to VGS and Vt and Vt related to 

substrate-source voltage. 

• Source of Q3 and Q4 remains at 0 volts — amount of 

charge injected by Q3 Q4 is not signal dependent 

and can be considered as a dc offset. 



Charge Injection Example 

• Estimate dc offset due to channel-charge injection 

when = 0 and C2 = CA = 10C3 = 10pF. 

C 1 

• Assume switches Q3 Q4 have Vtn = 0.8V, 

W = 30m , 

L = 0.8m , Cox 1.9 10 , and power 

supplies are . 

• Channel-charge of (when on) is 

3 – 

= pF m 2 

 

2.5V 

Q3 Q4 QCH3 = QCH4 = – 300.80.00192.5 – 0.8 

– 77.5 10 3 – 

= pC 

• dc feedback keeps virtual opamp input at zero volts. 


Charge Injection Example 

• Charge transfer into given by 

• We estimate half channel-charges of Q3, Q4 are 

injected to the virtual ground leading to 

1 

--Q 2 CH3 + QCH4 which leads to 

= QC3 University of Toronto 

Q C3 

C 3 

= 

– C3vout 

(59) 



(60) 

(61) 

77.5 10 

vout (62) 

• dc offset affected by the capacitor sizes, switch sizes 

and power supply voltage. 

3 – 

pC 

= ------------------------------------ = 

78 mV 

1pF 



vin( n) 

SC Gain Circuits — Parallel RC 

R2 K 

KC 1 


R 2 

C 1 

vin vout() t = – Kvin() t 

2 

1 

KC 2 

KC 1 

1 

2 


C 2 

1 

C 1 

2 

vout( n) 

= – Kvin( n) 

SC Gain Circuits — Resettable Gain 

C 1 

vin( n) 

vout( n) 

2 

1 

v out 

C 2 

2 

2 1 2 1 

2 

1 

V off 

= 

C 1 

 

– ----- vin( 

n) 

 

C 2 

time 





SC Gain Circuits 

Parallel RC Gain Circuit 

• circuit amplifies 1/f noise as well as opamp offset 

voltage 

Resettable Gain Circuit 

• performs offset cancellation 

• also highpass filters 1/f noise of opamp 

• However, requires a high slew-rate from opamp 


- 

+ 

C1 + 

Voff - 


+ - 

C 2 




V 

+ C1vin( 

n) 

C1 + 

Voff - 

V 

- C2+ 

C 2 

= 

vout( n) 

SC Gain Circuits — Capacitive-Reset 

• Eliminate slew problem and still cancel offset by 

coupling opamp’s output to invertering input 

vin( n) 

C 1 

• is optional de-glitching capacitor 

C 4 

2 1 1 2 

 

 

2 

1 

C 4 

C 3 

C 2 

2 

1 

vout( n) 

= 

C 1 

C 2 

C1 ----- 

C2 

– vin( 

n) 

 

 

– ----- vin( 

n) 

 





+ 

vin - 

vin SC Gain Circuits — Capacitive-Reset 

V off+ 

C 1 

+ 



- 

vin( n) 

- 

C 1 



+ 

- 


+ - 

C 2 

vout( n – 1) 

- 

C 3 

+ 

during reset 

C 2 

C 3 

vout( n – 1) 

+ Voff during valid output 

vout( n) 

C1 ----- 

C2 = – v 

in( n) 

SC Gain Circuits — Differential Cap-Reset 

1 

2 2 C 1 

C 1 

2a 

1 2a 

1a C 3 

1a 

C 2 

C 2 

C 3 

• Accepts differential inputs and partially cancels 

switch clock-feedthrough 

2 

2 

1 

1 

v out 

= 

C 1 

C 2 



+ - 

----- vin 

– vin 



Correlated Double-Sampling (CDS) 

• Preceeding SC gain amp is an example of CDS 

• Minimizes errors due to opamp offset and 1/f noise 

• When CDS used, opamps should have low thermal 

noise (often use n-channel input transistors) 

• Often use CDS in only a few stages 

— input stage for oversampling converter 

— some stages in a filter (where low-freq gain high) 

• Basic approach: 

— Calibration phase: store input offset voltage 

— Operation phase: error subtracted from signal 

v in 


Better High-Freq CDS Amplifier 

C 1 

• — C1' C2' used but include errors 

2 

2 

1 

1 

2 

C 1 

2 

1 

• 1 — C1 C2 used but here no offset errors 


C 2 

C 2 

2 

1 

1 

2 

1 



v out 



v in 

 

2 

1 

 

 

1 

2 

 

C 1 

2 

1 


CDS Integrator 

• — sample opamp offset on 

1 

• — C2' placed in series with opamp to reduce error 

2 

• Offset errors reduced by opamp gain 

• Can also apply this technique to gain amps 


1 

C 2 

C 2 

C 2 ' 

SC Amplitude Modulator 

• Square wave modulate by 1 (i.e. Vout = Vin) 

A 

B 

2 

C 1 

1 

C 3 

C 2 

v in v out 

1 

2 

ca 

• Makes use of cap-reset gain circuit. 

• is the modulating signal 

ca 

2 

A = 2ca + 1ca B = 1ca + 2ca 1 

1 

v out 



B 

A 




SC Full-Wave Rectifier 

• Use square wave modulator and comparator to make 

• For proper operation, comparator output should 

changes synchronously with the sampling instances. 

v in 

v in 

Q 1 


Square Wave 

Modulator 

ca 

SC Peak Detector 

 

comp 

C H 

v out 

v out 

• Left circuit can be fast but less accurate 

• Right circuit is more accurate due to feedback but 

slower due to need for compensation (circuit might 

also slew so opamp’s output should be clamped) 

v in 

opamp 

V DD 

Q 2 

C H 



v out

Switched-Capacitor Circuits - University of Toronto

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?