Renesas MCU M16C Family (R32C/M32C/M16C/R8C) - Glyn
Renesas MCU M16C Family (R32C/M32C/M16C/R8C) - Glyn
Renesas MCU M16C Family (R32C/M32C/M16C/R8C) - Glyn
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Basic Instructions<br />
Frequently used instructions<br />
are executed in one cycle.<br />
Advanced Instructions<br />
Many advanced instructions<br />
are supported, in addition to the<br />
basic instructions.<br />
DMA Function<br />
DMA, which transfers data without<br />
CPU intervention, supports up to<br />
four channels (<strong>M32C</strong>/80 and<br />
<strong>M16C</strong>/80 cores).<br />
The DMAII/DTC function provides<br />
many other memory transfer<br />
capabilities, such as transfer of<br />
multiple bytes by a single event and<br />
transfer of data to multiple addresses<br />
by a single event<br />
(<strong>M32C</strong>/80 core).<br />
List of Instructions with 1-Cycle Execution Addressing (36 of 108 total instructions in the <strong>M32C</strong>/80)<br />
Type Instruction Function Type Instruction Function<br />
ABS Absolute value<br />
BCLR Clear bit<br />
ADC<br />
ADCF*<br />
ADD<br />
Add with carry<br />
Add carry flag<br />
Add without carry<br />
Bit<br />
manipulation<br />
BNOT<br />
BNTST<br />
BSET<br />
Invert bit<br />
Test inverted bit<br />
Set bit<br />
CMP Compare<br />
BTST Test bit<br />
Arithmetic<br />
DEC<br />
EXTS<br />
Decrement<br />
Extend sign<br />
Shift<br />
ROLC<br />
RORC<br />
Rotate left with carry<br />
Rotate right with carry<br />
EXTZ Extend zero<br />
ROT* Rotate<br />
INC<br />
NEG<br />
Increment<br />
Two’s complement<br />
1-bit shift<br />
SHA*<br />
SHL*<br />
Shift arithmetic<br />
Shift logical<br />
SBB Subtract with borrow<br />
FCLR Clear flag register bit<br />
SBU Subtract without borrow<br />
FSET Set flag register bit<br />
AND Logical AND<br />
INDEX Index<br />
NOT Invert all bits<br />
INTO Interrupt on overflow<br />
Logic OR Logical OR<br />
Other Jcnd Jump on condition<br />
TST Test<br />
LDC Transfer to control register<br />
XOR Exclusive OR<br />
NOP No operation<br />
MOV Transfer<br />
PUSHC Save control register<br />
Transfer PUSH Save<br />
SCcnd Store on condition<br />
PUSHM Save multiple registers<br />
Note: * Supported by <strong>M32C</strong>/80 and <strong>M16C</strong>/80 cores.<br />
Transfer<br />
Jump<br />
Type Instruction Function Type Instruction Function<br />
MOVHH<br />
MOVHL<br />
MOVLH<br />
MOVLL<br />
STZ<br />
STNZ<br />
STZX<br />
SMOVF<br />
SMOVB<br />
SMOVU*<br />
SSTR<br />
SIN*<br />
SOUT*<br />
MAX*<br />
MIN*<br />
CLIP*<br />
XCHG<br />
JMP<br />
ADJNZ<br />
SBJNZ<br />
UART<br />
CPU<br />
4-bit data transfer<br />
4-bit data transfer<br />
4-bit data transfer<br />
4-bit data transfer<br />
Conditional transfer<br />
Conditional transfer<br />
Conditional transfer<br />
Transfer string forward<br />
Transfer string backward<br />
Transfer string<br />
Store string<br />
String input<br />
String output<br />
Select maximum value<br />
Select minimum value<br />
Clip<br />
Exchange<br />
Unconditional jump<br />
Add and conditional jump<br />
Subtract and conditional jump<br />
RAM<br />
C language/<br />
OS only<br />
Bit<br />
Arithmetic<br />
ENTER<br />
EXITD<br />
STCTX<br />
LDCTX<br />
BAND<br />
BNAND<br />
BOR<br />
BNOR<br />
BXOR<br />
BNXOR<br />
BMcnd<br />
DIV<br />
DIVU<br />
DIVX<br />
MUL<br />
MULU<br />
SHA<br />
SHL<br />
Note: * Supported by <strong>M32C</strong>/80 and <strong>M16C</strong>/80 cores.<br />
DMA Applications DMAII/DTC Applications<br />
• Automatic serial I/O transfers<br />
• Motor drive using microsteps<br />
• Multichannel PWM output (max. 64)<br />
(Example using UART)<br />
EVENT<br />
EVENT<br />
Build stack frame<br />
Deallocate stack frame<br />
Save context<br />
Restore context<br />
Logically AND bits<br />
Logically AND inverted bits<br />
Logically OR bits<br />
Logically OR inverted bits<br />
Exclusive OR bits<br />
Exclusive OR inverted bits<br />
Conditional bit transfer<br />
Signed divide<br />
Unsigned divide<br />
Signed divide<br />
Signed multiply<br />
Unsigned multiply<br />
Shift arithmetic<br />
Shift logical<br />
Memory Memory<br />
Port0 RAM<br />
Port1 RAM<br />
Port2 RAM<br />
• Transfer of multiple<br />
bytes by a single<br />
event<br />
• Transfer of data to<br />
multiple addresses<br />
by a single event<br />
8
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