Renesas MCU M16C Family (R32C/M32C/M16C/R8C) - Glyn
Renesas MCU M16C Family (R32C/M32C/M16C/R8C) - Glyn
Renesas MCU M16C Family (R32C/M32C/M16C/R8C) - Glyn
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ADD<br />
SUB<br />
CMP<br />
MOV<br />
PUSH/POP<br />
SHA<br />
SHL<br />
MUL* 1<br />
DIV* 2<br />
* 1 : 32bits 32bits=32bits<br />
* 2 : 32bits 32bits=32bits<br />
Concepts<br />
Clock<br />
Instruction 1 IF ID OR/OPR/OW<br />
Instruction 2 IF ID OR/OPR/OW<br />
Instruction 3 IF ID OR/OPR/OW<br />
IF ID OR1 OR2 OPR OW<br />
Instruction 2<br />
IF ID OR1 OR2 OPR OW<br />
IF ID OR1/OR2 OPR OW<br />
IF ID OR1/OR2 OPR OW<br />
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18<br />
1 2 3 4 5<br />
High-Speed Processing<br />
The <strong>M16C</strong> <strong>Family</strong> provides high-speed processing under a variety of conditions.<br />
<strong>M16C</strong> High-Speed Instruction Execution<br />
The <strong>M16C</strong> <strong>Family</strong> is designed<br />
so that each CPU execution<br />
stage takes one clock cycle. For<br />
most instructions, the execution<br />
time is equivalent to that of a<br />
general RISC <strong>MCU</strong>.<br />
High-Speed Interrupts (<strong>M32C</strong>)<br />
Interrupt Request Accepted<br />
Interrupt Request Generated<br />
<strong>M16C</strong> Core<br />
Conventional<br />
<strong>M32C</strong>/80 Core<br />
High-Speed<br />
Interrupt<br />
struction<br />
struction<br />
(One interrupt can be set as<br />
a high-speed interrupt.)<br />
Instruction<br />
Instruction<br />
32-Bit Instructions<br />
<strong>M16C</strong><br />
Conventional <strong>MCU</strong><br />
Clock<br />
Instruction 1<br />
Minimum Instruction Execution Time = 1 Clock Cycle<br />
Instruction Execution Time<br />
Minimum Instruction Execution Time<br />
General RISC<br />
Clock<br />
Instruction 1 IF ID OR1/OR2 OPR OW<br />
Instruction 2 IF ID OR1/OR2 OPR OW<br />
Instruction 3 IF ID OR1/OR2 OPR OW<br />
Instruction 4<br />
Instruction 5<br />
Interrupt Sequence<br />
High-Speed<br />
The <strong>M32C</strong>/80 provides enhanced support for 32-bit instructions.<br />
Interrupt Sequence<br />
Instructions in Interrupt<br />
Routine<br />
Instruction Function Addressing Modes<br />
Add without carry<br />
Subtract without borrow<br />
Compare<br />
Transfer<br />
Save<br />
Shift arithmetic<br />
Shift logical<br />
Signed multiply<br />
Signed divide<br />
IF: Instruction Fetch<br />
ID: Instruction Decode<br />
OR1/OR2: Operand Read<br />
OPR: Operation<br />
OW: Execute<br />
Instructions in Interrupt<br />
Routine<br />
Execution in 1/4 the Cycles Usually Required*<br />
* The interrupt recovery instruction uses three cycles (1/2 the usual).<br />
* Because there are two banks of registers, interrupt switching can<br />
be performed in a single cycle.<br />
* The normal interrupt sequence of the <strong>M32C</strong>/80 uses 14 cycles.<br />
Immediate-register, immediate-memory, register-register, register-memory, memory-register, memory-memory<br />
Immediate-register, immediate-memory, register-register, register-memory, memory-register, memory-memory<br />
Immediate-register, immediate-memory, register-register, register-memory, memory-register, memory-memory<br />
Immediate-register, immediate-memory, register-register, register-memory, memory-register, memory-memory<br />
Immediate, register, memory<br />
Register, memory (on-chip barrel shifter)<br />
Register, memory (on-chip barrel shifter)<br />
Memory-memory, register-memory<br />
Memory-memory, register-memory<br />
14
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