A Top-Down Verilog-A Design on the Analog-and-Digital

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1-2. Conventional Phase-Locked loop Depends on the different purposes, the phase-locked loop (PLL) most often deals with signals or clocks to reduce timing jitters, suppresses clock skews, synthesizes higher frequencies, and assists data and clock recoveries. Traditionally there are four kinds of phase-locked loops. They are linear PLL (LPLL), digital PLL (DPLL), all-digital PLL (ADPLL), and software PLL (SPLL) all around the world. However, the phase-locked-loop circuit is conventionally based on three essential components.[3] 1. Voltage-Controlled-Oscillator (VCO) 2. Loop Filter (LF) 3. Phase Detector (PD) The phase detector first compares the differences between the input signal and the VCO output signal. It then generates a phase error according to the difference. Passing through the loop filter, the feedback loop will present a control signal for the voltage-controlled oscillator to either increase or decrease the oscillating frequency in accordance to the controlled voltage level. Recursively, the entire phase-locked loop will be able to lock the input signal within a lock-in time. Fig.4 shows the conventional phase-locked-loop block diagrams as well as its transfer functions. 12
Fig.4 Block diagram and transfer function of a PLL 1-2-1. Voltage-Controlled-Oscillator (VCO) As its name described, a voltage-controlled oscillator has the feature that its oscillating frequency on the output port is under controlled by the input control voltage, Vcnt. The block diagram and its predicted waveform for ideal simulation are shown on Fig.5 and Fig.6 respectively. Fig.5 Block and the transfer function of a VCO 13
Page 1 and 2: A Top-Down
Page 3 and 4: Chapter 4. Test Bench Study …..
Page 5 and 6: Appendix D. Netlist Lists (D-1).Net
Page 7 and 8: Preview While many types of signal
Page 9 and 10: Fig.1 Magnetic hard-disk read chann
Page 11: cosine equalizer, phase (and level)
Page 15 and 16: 1-2-3. Phase Detector Traditionally
Page 17 and 18: Chapter 2 Matlab System-Level <stro
Page 19 and 20: function y = vco(x,range,Fs) %VCO V
Page 21 and 22: Chapter 3 Verilog-
Page 23 and 24: Fig.15 Waveform of the VCO output a
Page 25 and 26: eceives a discharge command. Fig.18
Page 27 and 28: end else begin end if ((osc_value =
Page 29 and 30: end else begin end if ((vin_up ==0)
Page 31 and 32: Fig.21 A practical phase-frequency
Page 33 and 34: generators are discussed. 4-1-1. Un
Page 35 and 36: Fig.25 Waveform of the Normal-Distr
Page 37 and 38: 4-2. Random-Bit-Generator-Included
Page 39 and 40: Chapter 5 Entire DPLL Desig
Page 41 and 42: Chapter 6 Conclusion According to t
Page 43 and 44: Refere nce A [1] Razavi, De
Page 45 and 46: 1-9. 1-10. . 31 st Processing In Th
Page 47 and 48: Appendix A: Verilog</strong
Page 49 and 50: `include "constants.h" `include "di
Page 51 and 52: end generate i (5, 0) begin end vdo
Page 53 and 54: code = 0.0; generate j (6,0) begin
Page 55 and 56: end generate k(5,0) begin end vdout
Page 57 and 58: (A-9) LevelShifter // Veril
Page 59 and 60: Appendix C: (C-1) 3-Tap FIR simulat
Page 61 and 62: (C-5) Simulation results of a low-p
Page 63 and 64:
Appendix D: (D-1) Netlist of the Ra
Page 65 and 66:
(D-2) Netlist of the Entire DPLL <s
Page 67 and 68:
delay=0 rise=1n fall=1n width=2.906
Page 69:
ahdl_include "/rcc4/student/wangc/c
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A Top-Down Verilog-A Design on the Analog-and-Digital

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