A Top-Down Verilog-A Design on the Analog-and-Digital

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waveforms. As we can see, the ideally designed waveform provided by the 7-bit digital-to-analog converter is DAC_out. It is used to drive the voltage controlled oscillator for different frequencies. Before considering noises, the designed ideal low pass filter which has 100MHz as its bandwidth is good enough to generate clear signals to drive the oscillator. However, the output waveform shows us the driving source gets worse if there were noises. Comparing the waveform comes out from the 100MHz filter (labeled 100MHz_out_pseudo on Fig.29) with that from the 15MHz filter (labeled 15MHz_out_pseudo on Fig.29), it is easily found an improvement occurs. Through such testbench experiments, we can begin to modify or improve our designs. In the future, the ideal low pass filter will be replaced with the other realistic components such as analog Butterworth or Chebyshev low pass filters. Building up more testbenches will also be our future works to more guarantee the performance of this project. DAC_out LPF_in 15MHz_out_pseudo 100MHz_out_pseudo Fig.29 Waveforms of the random-bit-generator-included test bench 38
Chapter 5 Entire DPLL <strong>Design</strong> and Simulation 5-1. Schematic of the Entire DPLL <strong>Design</strong> After establishing <strong>Verilog</strong>-A models for all the essential blocks, we build up an entire digital phase-lock loop circuit as shown on Fig.22. <strong>Verilog</strong>-A models of all the block diagrams are coded in this report. However, not all of them are discussed in details. Block diagrams and Veriolog-A models that are not included in these chapters will be covered in the appendices. Fig.30 Entire digital phase-locked loop blocks in Cadence 39
Page 1 and 2: A Top-Down
Page 3 and 4: Chapter 4. Test Bench Study …..
Page 5 and 6: Appendix D. Netlist Lists (D-1).Net
Page 7 and 8: Preview While many types of signal
Page 9 and 10: Fig.1 Magnetic hard-disk read chann
Page 11 and 12: cosine equalizer, phase (and level)
Page 13 and 14: Fig.4 Block diagram and transfer fu
Page 15 and 16: 1-2-3. Phase Detector Traditionally
Page 17 and 18: Chapter 2 Matlab System-Level <stro
Page 19 and 20: function y = vco(x,range,Fs) %VCO V
Page 21 and 22: Chapter 3 Verilog-
Page 23 and 24: Fig.15 Waveform of the VCO output a
Page 25 and 26: eceives a discharge command. Fig.18
Page 27 and 28: end else begin end if ((osc_value =
Page 29 and 30: end else begin end if ((vin_up ==0)
Page 31 and 32: Fig.21 A practical phase-frequency
Page 33 and 34: generators are discussed. 4-1-1. Un
Page 35 and 36: Fig.25 Waveform of the Normal-Distr
Page 37: 4-2. Random-Bit-Generator-Included
Page 41 and 42: Chapter 6 Conclusion According to t
Page 43 and 44: Refere nce A [1] Razavi, De
Page 45 and 46: 1-9. 1-10. . 31 st Processing In Th
Page 47 and 48: Appendix A: Verilog</strong
Page 49 and 50: `include "constants.h" `include "di
Page 51 and 52: end generate i (5, 0) begin end vdo
Page 53 and 54: code = 0.0; generate j (6,0) begin
Page 55 and 56: end generate k(5,0) begin end vdout
Page 57 and 58: (A-9) LevelShifter // Veril
Page 59 and 60: Appendix C: (C-1) 3-Tap FIR simulat
Page 61 and 62: (C-5) Simulation results of a low-p
Page 63 and 64: Appendix D: (D-1) Netlist of the Ra
Page 65 and 66: (D-2) Netlist of the Entire DPLL <s
Page 67 and 68: delay=0 rise=1n fall=1n width=2.906
Page 69: ahdl_include "/rcc4/student/wangc/c

A Top-Down Verilog-A Design on the Analog-and-Digital

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