A Top-Down Verilog-A Design on the Analog-and-Digital
A Top-Down Verilog-A Design on the Analog-and-Digital
A Top-Down Verilog-A Design on the Analog-and-Digital
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
1-9.<br />
1-10.<br />
. 31 st Processing In Theory <strong>and</strong> Practice” ASEE/IEEE Fr<strong>on</strong>tiers in<br />
Stratix GX Devices”. Altera<br />
Corporati<strong>on</strong>. April 2003.<br />
2-1. Thomas C<strong>on</strong>way, Philip Quinlan,<br />
Joe Spalding, Kevin McCall. “A CMOS<br />
2-2.<br />
Symposium <strong>on</strong><br />
3-1.<br />
Teresa M. Alemeida, Moises S. Piedade. “High Performance <strong>Analog</strong> And<br />
3-3.<br />
S. Hossein Mousavinezhad, Ikhlas M. Abdel-Qader, “<strong>Digital</strong> Signal<br />
Educati<strong>on</strong> C<strong>on</strong>ference.<br />
Chapter 7 of “Implementing High-Performance DSP Functi<strong>on</strong>s in Stratix &<br />
1-11. Applicati<strong>on</strong> Notes 005, “Implementating an FIR Filter using <strong>the</strong> VERSA1<br />
MAC”. Goal Semic<strong>on</strong>ductor.<br />
<strong>Analog</strong>-to-<strong>Digital</strong> (AD) <strong>and</strong> <strong>Digital</strong>-to-<strong>Analog</strong> (DA) C<strong>on</strong>verter:<br />
260Mbps Read Channel with EPRML Performance”. 1998<br />
VLSI Circuit Digest of Technical Papers.<br />
Johns <strong>and</strong> Martin “<strong>Analog</strong> Integrated Circuit <str<strong>on</strong>g>Design</str<strong>on</strong>g>”.<br />
Phase-Locked Loop (PLL):<br />
<strong>Digital</strong> PLL <str<strong>on</strong>g>Design</str<strong>on</strong>g>”. 1999,<br />
IEEE.<br />
3-2. Terng-Yin Hsu, Bai-Jue Shieh, Chen-Yi Lee. “An All-<strong>Digital</strong> Phase-Locked<br />
Loop (ADPLL)-Based Clock Recovery<br />
Circuit”. JSSC, Vol.34, No.8,<br />
August 1999. IEEE<br />
Y. Fouzar, M. Sawan, Y. Savaria. “Very Short Locking Time PLL Based <strong>on</strong><br />
C<strong>on</strong>trolled Gain Technique”.<br />
2000, IEEE.<br />
3-4. Razavi, “<str<strong>on</strong>g>Design</str<strong>on</strong>g> of <strong>Analog</strong> CMOS Integrated Circuits”<br />
<strong>Analog</strong>ue Hardware Descripti<strong>on</strong> Language (AHDL <strong>and</strong> <str<strong>on</strong>g>Verilog</str<strong>on</strong>g>-A):<br />
45