A Top-Down Verilog-A Design on the Analog-and-Digital

Fig.17 VCO functions in the block diagram of SONY’s paper
3-2. Practical <strong>Design</strong> of PFD in Digital Block
The phase frequency detector presented on
SONY’s paper [02] is entirely
combined
by several digital blocks. It includes a cosine equalizer, a phase
detector and an embedded 7-bit counter. Since the cosine equalizer is the same as
a 3-Tap FIR filter, we can easily recognize its function and simplify the PFD as
having approximately the phase detector plus a counter. The phase detector grabs
the filtered output signal from the cosine equalizer and compares it with the
output of the clock divider, which divides the frequency from VCO by an integer
2. Then the phase detector decides either the following charge-up or discharge
process for the 7-bit counter. If the counter receives a charge-up signal, it is
going to count up one bit. On the other hand, it will count down one bit once it
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