abstract models of noc-based mpsocs for design space exploration

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LIST OF FIGURES
Figure 1 – Examples of expected 4G applications for future portable systems. Figure extracted from
[KRE08b]. ................................................................................................................. 19!
Figure 2 – Proposed model-based design flow. ............................................................................... 22!
Figure 3 - (a) Pyramid of abstraction levels that comprises a system design from the specification to a
possible optimal solution. Figure extracted from [KIE99]. (b) Proposed approach location
according to the pyramid’s classification. ....................................................................... 25!
Figure 4 - Calibration of architectural simulation models. Figure taken from [PIM08]. ......................... 26!
Figure 5 – Structural view: actor-oriented model and its hierarchical abstraction. ............................... 27!
Figure 6 - Generic structure of the actor (a), example of actor parameters (b) and its pseudo XML
description (C). .......................................................................................................... 28!
Figure 7 - Actor behavior execution flow during simulation time. Figure based on definitions presented in
[LEE03]. .................................................................................................................... 28!
Figure 8 - Proposed design flow. Figure obtained from [PES04]. .......................................................... 33!
Figure 9 – Methodology proposed by Xu et. al. Figure obtained from [XU05]. ..................................... 34!
Figure 10 - (a) energy model extraction methodology, (b) energy-aware validation flow. Figures
extracted from [CHA05]. ............................................................................................. 36!
Figure 11 – Example of a CDCG. Figure taken from [MAR05b]. ......................................................... 37!
Figure 12 – NoC design flow proposed by Xi. Figure taken from [XI06]. ............................................. 37!
Figure 13 - Modeling the MPSoC processing element into a computational graph; (a) Typical
microprocessor architecture block diagram; (b) Microprocessor modeled as a computational
graph. Figure taken from [EIS06]. ................................................................................ 38!
Figure 14 - (a) traffic distribution graph (TDG) example and (b) its corresponding traffic distribution
matrix (λ). Figure extracted from [ELM09]. .................................................................... 40!
Figure 15 - (a) Y-chart design space exploration flow, and (b) Sesame's model layers. Figures obtained
from [PIM06] and [PIM08], respectively. ........................................................................ 44!
Figure 16 – A 3 x 4 direct Mesh NoC topology and a generic router architecture. ................................ 49!
Figure 17 - Adopted approach for NoC modeling and design space exploration. ................................. 51!
Figure 18 - UML sequence diagrams depicting interactions between components of the HERMES NoC.
Figure extended from [IND08]. ..................................................................................... 51!
Figure 19 - Example of packet flit difference between HERMES and RENATO models. ......................... 52!
Figure 20 - Implemented Round-Robin method. ............................................................................ 53!
Figure 21 - (a) JOSELITO's packted structure and (b) buffer state machine. ...................................... 54!
Figure 22- Unblocked (in the left side) and blocked packet transmission situations. ............................. 54!
Figure 23 - Estimated release times regarding blocking-free delivery scenario. ................................... 56!
Figure 24 - Packet forwarding situation regarding header blocking. ................................................... 57!
Figure 25 - Packet forwarding situation regarding header and trailer blocking. .................................... 58!
Figure 26 - ATLAS design exploration flow. ................................................................................... 59!
Figure 27 - Latency difference in clock cycles between JOSELITO and HERMES for 3 different traffic
distributions: (a) uniform, (b) normal, and (c) pareto on-off and NoC sizes (2x2, 3x3, 4x4 and
5x5), 16 flits packets. ................................................................................................. 60!
Figure 28 - Evaluated end-to-end communications (sent communications from node 00 to other NoC
nodes). For simplicity only the node 00 is illustrated in the figure. ..................................... 61!
Figure 29 - Latency difference between a 4x4 JOSELITO and a 4x4 HERMES for 3 different traffic
distributions (uniform, normal and pareto on-off) and 3 different packet sizes (16, 50 and 100
flits). ........................................................................................................................ 63!
Figure 30 - Extension of rate-based power estimation flow. ............................................................ 65!
Figure 31 - 5x5 NoC and the PowerScope. .................................................................................... 68!
Figure 32 – An example of a unified model representation. Figure extended from [MÄÄ10]. ................. 75!
Figure 33 - Proposed model-based design flow. ............................................................................. 78!