abstract models of noc-based mpsocs for design space exploration

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flow![BER05].! ! Kogel!et!al.![KOG03]!propose!a!modular!framework!for!system!level!exploration!of!the!onS chip!interconnection!architecture!using!TLM!abstraction.!The!framework!has!a!library!of!different! network! modules! with! configurable! topologies! and! arbitration! protocols,! which! can! be! used! to! define! the! NoC! architecture! that! will! be! simulated.! Besides,! it! allows! capturing! performance! metrics!as!latency!and!throughput!of!different!NoC!configurations.!However,!the!accuracy!of!such! results!was!not!discussed!in!this!work.! NoCGEN!creates!VHDL!NoC!descriptions!used!for!simulations!and!synthesis!![CHA04].!This! tool!uses!a!set!of!parameterizable!templates!to!build!routers,!varying!the!number!of!ports,!routing! algorithms,! data! width! and! buffer! depth.! Besides! NoC! parameterization,! it! uses! a! mixed! SystemC/VHDL! simulation! environment.! The! evolution! of! this! work! was! presented! in! [CHA08],! which! describes! the! NoCGEN! integration! into! a! design! methodology! for! generating! optimized! application!specific!NoC!topologies.!! The!OCCN!framework!proposed!by![COP04]!enables!the!creation!of!NoC!architectures!at! different! abstraction! levels,! protocol! refinement,! design! exploration,! and! NoC! component! development!and!verification!based!on!a!communication!API.!The!OCCN!methodology!has!been! adopted! by! Dumitrascu! et! al.! [DUM06]! in! order! to! analyze! the! effectiveness! of! interSmodule! communication!and!for!components!adaptation.!In!this!approach,!the!communication!architecture! performance!evaluation!is!based!on!cycleSaccurate!coSsimulation.! !Pestana!et!al.!present!in![PES04]!a!NoC!design!flow,!illustrated!in!Figure!8,!which!uses!a! NoC!simulator!described!in!SystemC.!Applying!the!proposed!flow,!the!designer!specifies!in!three! files! NoC! topology,! IP! to! NoC! mapping! and! detailed! interconnections.! These! files! are! used! by! a! XML!parser!to!instantiate!the!NoCSbased!system!(VHDL!description),!which!will!be!simulated.!The! simulator! also! allows! describing! traffic! generators! to! evaluate! the! performance! metrics! (e.g.! throughput)! of! NoC! instances.! A! case! study,! in! which! different! synthetic! traffic! workloads! are! injected! in! the! NoC,! was! described! in! [PES04]! to! demonstrate! the! main! steps! of! the! proposed! design!flow.!! Figure!8!S!Proposed!design!flow.!Figure!obtained!from![PES04].! Xu! et! al.! [XU05]! present! a! lowSlevel! methodology! for! modeling,! designing! and! analyzing! 33
34 different!NoC!architectures!based!on!the!application!communication!behavior.!Due!to!its!low!level! abstraction!(RTL!and!gateSlevel),!this!approach!can!accurately!estimate!the!performance,!power,! and!area!of!several!NoC!architectures.!This!work!uses!the!following!tools:!OPNET,!Design!Compiler,! and! SPICE.! Due! to! the! use! of! SPICE,! electrical! simulation,! modeling! and! simulation! are! time! consuming,!which!is!not!appropriated!for!rapid!design!space!exploration.!! ! Figure!9!–!Methodology!proposed!by!Xu!et.!al.!Figure!obtained!from![XU05].! Bertozzi!et!al.![BER05]!propose!the!NetChip!synthesis!flow,!which!allows!the!exploration!of! different!NoCs!topologies!(such!as!mesh,!torus,!hypercube,!Clos,!and!butterfly).!The!NetChip!flow! is!composed!of!three!phases:!(i)!NoC!topology!mapping,!(ii)!selection,!and!(iii)!generation!(SystemC! model!that!can!be!simulated!at!a!cycle!and!signal!accurate!level).!Additionally,!an!input!core!graph,! obtained!with!the!SUNMAP!tool,!is!used!in!the!mapping!phase![MUR04].!Then,!the!SUNFLOOR!tool! is!used!to!synthesize!the!most!power!and!performance!efficient!NoC!topology!that!satisfies!the! application!requirements![MEL06].! 3.1.1 NoC Modeling - Closing Remarks Making!an!overview!of!the!NoC!modeling!researches,!it!is!possible!to!verify!that!the!NSS2! and!OPNET!network!simulators!do!not!consider!some!particularities!that!are!necessary!to!the!NoC! design.! HighSlevel! abstract! models! of! NoCs! are! proposed! with! different! buffering! strategy,! flow! control,!arbiters!and!virtual!channels.!Besides!NoC!architectures,!an!important!effort!was!done!to! provide!faster!analyses!of!performance!metrics!of!NoCs,!which!is!a!mandatory!step!to!find!out!the! best!tradeSoff!between!architecture!and!data!rates.!! Most!proposed!techniques!or!tools!allow!the!emulation!of!the!NoC!in!different!abstraction! levels,! considering! different! architectures! (e.g! topology,! router)! and! traffic! conditions.! In! many! cases,!the!simulation!occurs!in!TLM!(transaction!level!model)!style,!which!demands!less!design!and! simulation!time!compared!to!RTL!descriptions.!However,!the!accuracy!of!those!high!level!models!is! influenced!by!the!structural!and!behavioral!abstractions.!!
Page 1: ! PONTIFÍCIA UNIVERSIDADE CATÓLIC
Page 7 and 8: ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
Page 9 and 10: ! ABSTRACT MODELS OF NOC-BASED MPSO
Page 11 and 12: Figure 34 - (a) Example of an appli
Page 13 and 14: ! LIST OF ABBREVIATIONS APD! Averag
Page 15: 5.! MODELNBASED!DESIGN!FLOW!FOR!NOC
Page 18 and 19: est!placement!for!the!application!t
Page 20 and 21: ! 2. !!!a!technique!that!can!be!app
Page 22 and 23: ! 23
Page 24 and 25: modeling,!as!proposed!in![KIE99],!i
Page 26 and 27: ! Director 1 input ports Composite
Page 28 and 29: 2.2.2.1 Initialization ! The! initi
Page 30 and 31: ! ! 31
Page 34 and 35: ! One! contribution! of! the! propo
Page 36 and 37: ! Figure!11!-!Example!of!a!CDCG.!Fi
Page 38 and 39: using! HSPICE! and! the! Berkeley!
Page 40 and 41: and!direct!connection!links!between
Page 42 and 43: 3.3 MPSoC Application Modeling and
Page 44 and 45: already! designed.! Software! can!
Page 46 and 47: ! ! ! ! ! ! 47
Page 48 and 49: ! IP ' NI Router ' IP ' NI Router '
Page 50 and 51: for!the!sake!of!simplicity!and!effi
Page 52 and 53: input! port! having! a! routing! re
Page 54 and 55: [OST08].! ! ptrt hft + pcksize * ct
Page 56 and 57: accuracy!on!blocking!other!packets.
Page 58 and 59: NoC generation 1 Traffic Generation
Page 60 and 61: eference!model!(according!to!the!av
Page 62 and 63: packets)! in! average.! In! this! s
Page 64 and 65: ate! inside! a! given! sample! peri
Page 66 and 67: presents!such!a!small!difference!to
Page 68 and 69: and!the!switching!activity!of!its!a
Page 70 and 71: ! ! Power!model\Traffic! Uniform! N
Page 72 and 73: ! ! 73
Page 74 and 75: 8 Director 1 AB1 AB2 AB3 PE 01 AB1
Page 76 and 77: execution!of!applications!running!o
Page 78 and 79: ! Application/Modeling:!in!this!ste
Page 80 and 81: extracted!is!the!real!load!imposed!
Page 82 and 83:
(a)!30%! (b)!40%! (c)!50%! Figure!3
Page 84 and 85:
! Table! XII! presents! the! maximu
Page 86 and 87:
! ! ! 87
Page 88 and 89:
! Indrusiak,!L.!S.;!Ost,!L.;!Mölle
Page 90 and 91:
! ! 91
Page 92 and 93:
[BER05]! Bertozzi,! D.;! Jalabert,!
Page 94 and 95:
[GUI08]! Guindani,! G.;! Reinbrecht
Page 96 and 97:
! Platforms”.!In:!IEEE!Symposium!
Page 98 and 99:
[PIM01]! Pimentel,! A.D.;! Hertzber
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