abstract models of noc-based mpsocs for design space exploration

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! Figure!11!–!Example!of!a!CDCG.!Figure!taken!from![MAR05b].!! Xi! et! al.! [XI06]! present! the! integration! of! mathematical! power/energy! models! of! NoC! components! (e.g.! input! buffers)! into! a! SystemC! transaction! level! NoC! simulation! framework.! During! the! simulation,! each! corresponding! mathematical! model! receives! the! number! of! transactions!occurred!in!the!router!or!among!then,!in!order!to!calculate!the!dynamic!and!leakage! power!of!each!one.!Different!traffic!patterns!(e.g.!burst!period!from!10us!to!15us)!are!applied!on! the! same! meshSNoC! to! evaluate! its! power! dissipation.! Experiments! on! eight! deep! subSmicron! CMOS!processes!(from!180nm!to!45nm),!were!used!to!validate!the!proposed!flow,!illustrated!in! Figure!12.!Authors!did!not!mention!the!accuracy!of!the!NoC!components!power!models.! Figure!12!–!NoC!design!flow!proposed!by!Xi.!Figure!taken!from![XI06].! Eisley! et.! al.! [EIS04][EIS06]! employ! a! framework! that! takes! as! input! message! flows,! and! derives!a!power!profile!of!the!network!fabric.!The!authors!map!the!CPU!datapath!as!a!graph,!and! the! application! as! a! set! of! messages! that! flow! in! this! graph,! as! illustrated! in! Figure! 13.! Those! mapped!CPUs!are!connected!into!the!network!fabric,!mapping!the!entire!MPSoC!as!a!network.!The! authors! make! use! of! a! network! power! estimation! tool,! called! LUNA,! to! evaluate! the! power! 37
38 dissipation!of!the!entire!MPSoC.! Figure!13!S!Modeling!the!MPSoC!processing!element!into!a!computational!graph;!(a)!Typical!microprocessor! architecture!block!diagram;!(b)!Microprocessor!modeled!as!a!computational!graph.!Figure!taken!from! [EIS06].!! ! Atitallah! et! al.! [ATI07][ATI07b]! use! a! stack! of! abstract! models.! The! higher! abstraction! model,! named! Timed! Programmer! View! (TPV),! omits! details! related! to! the! computation! and! communication!resources.!Such!abstract!model!enables!designers!to!select!a!set!of!solutions,!to!be! explored! at! lower! abstraction! levels.! The! second! model,! CABA! (CycleJAccurate/ BitJAccurate),! is! used!for!power!estimation!and!platform!configuration.!Results!present!an!error!of!8%!in!power! estimation!compared!to!a!physical!measure!and!17%!of!simulation!speedSup.! Beltrame!et!al.![BEL07]!develop!a!SoC!power!estimation!method!based!on!SystemC!TLM! modeling! strategy.! It! adopts! multiSaccuracy! models,! supporting! the! switch! between! different! models!at!runStime!according!to!the!desired!accuracy!level![BEL06][BEL08].!The!authors!validate! their! model! using! the! STBus! NoC,! and! an! analytical! power! model! of! this! NoC.! An! MPEG4! application!was!tested,!achieving!up!to!82%!speedSup!compared!to!TLM!BCA!(busScycle!accurate)! simulation.! Wang! et! al.! [HAN02]! present! ORION,! a! NoC! simulator! that! enables! the! evaluation! of! performance!and!the!power!dissipation!of!different!NoC!architectures.!ORION!was!built!upon!the! Liberty!Simulation!Environment!(LSE)!framework![VAC02].!In!the!LSE!framework,!hardware!blocks! are!modeled!as!logical!functional!modules!that!send!data!through!ports.!Each!functional!module!is! composed! of! parameters! and! input/ouput! ports.! For! example,! considering! a! FIFO! buffer! as! a! functional!module,!the!buffer!size!can!be!a!parameter!and!it!can!be!composed!of!read!and!write! ports.!!The!NoC!component!power!models!are!defined!from!a!set!of!equations!that!are!calibrated!
Page 1: ! PONTIFÍCIA UNIVERSIDADE CATÓLIC
Page 7 and 8: ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
Page 9 and 10: ! ABSTRACT MODELS OF NOC-BASED MPSO
Page 11 and 12: Figure 34 - (a) Example of an appli
Page 13 and 14: ! LIST OF ABBREVIATIONS APD! Averag
Page 15: 5.! MODELNBASED!DESIGN!FLOW!FOR!NOC
Page 18 and 19: est!placement!for!the!application!t
Page 20 and 21: ! 2. !!!a!technique!that!can!be!app
Page 22 and 23: ! 23
Page 24 and 25: modeling,!as!proposed!in![KIE99],!i
Page 26 and 27: ! Director 1 input ports Composite
Page 28 and 29: 2.2.2.1 Initialization ! The! initi
Page 30 and 31: ! ! 31
Page 32 and 33: flow![BER05].! ! Kogel!et!al.![KOG0
Page 34 and 35: ! One! contribution! of! the! propo
Page 38 and 39: using! HSPICE! and! the! Berkeley!
Page 40 and 41: and!direct!connection!links!between
Page 42 and 43: 3.3 MPSoC Application Modeling and
Page 44 and 45: already! designed.! Software! can!
Page 46 and 47: ! ! ! ! ! ! 47
Page 48 and 49: ! IP ' NI Router ' IP ' NI Router '
Page 50 and 51: for!the!sake!of!simplicity!and!effi
Page 52 and 53: input! port! having! a! routing! re
Page 54 and 55: [OST08].! ! ptrt hft + pcksize * ct
Page 56 and 57: accuracy!on!blocking!other!packets.
Page 58 and 59: NoC generation 1 Traffic Generation
Page 60 and 61: eference!model!(according!to!the!av
Page 62 and 63: packets)! in! average.! In! this! s
Page 64 and 65: ate! inside! a! given! sample! peri
Page 66 and 67: presents!such!a!small!difference!to
Page 68 and 69: and!the!switching!activity!of!its!a
Page 70 and 71: ! ! Power!model\Traffic! Uniform! N
Page 72 and 73: ! ! 73
Page 74 and 75: 8 Director 1 AB1 AB2 AB3 PE 01 AB1
Page 76 and 77: execution!of!applications!running!o
Page 78 and 79: ! Application/Modeling:!in!this!ste
Page 80 and 81: extracted!is!the!real!load!imposed!
Page 82 and 83: (a)!30%! (b)!40%! (c)!50%! Figure!3
Page 84 and 85: ! Table! XII! presents! the! maximu
Page 86 and 87:
! ! ! 87
Page 88 and 89:
! Indrusiak,!L.!S.;!Ost,!L.;!Mölle
Page 90 and 91:
! ! 91
Page 92 and 93:
[BER05]! Bertozzi,! D.;! Jalabert,!
Page 94 and 95:
[GUI08]! Guindani,! G.;! Reinbrecht
Page 96 and 97:
! Platforms”.!In:!IEEE!Symposium!
Page 98 and 99:
[PIM01]! Pimentel,! A.D.;! Hertzber
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