Using External Memory with PIC24F/24H/dsPIC33F ... - Microchip

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AN1210 TABLE 5: CONFIGURATION OF PMP REGISTERS FOR INTERFACING A 32K x 8-BIT MEMORY DEVICE USING PARTIAL MULTIPLEXED MODE Register Value Description PMCON 10x010110110xx00 (1) • PMP module enabled • Select to run/stop in Idle mode • Higher address byte on separate pins and lower address byte multiplexed with data pins • PMBE port disabled • PMWR port enabled • PMRD port enabled • PMCS1 functioning as PMA14 and PMCS2 as chip select (1) • Address latch signal high (for 373 latch) • PMCS2 polarity low • PMCS1 polarity is irrelevant (no PMCS1 used) • Byte enable polarity is irrelevant (no byte enable used) • Write strobe polarity, active-low • Read strobe polarity, active-low PMMODE 00xxx010xxxxxxxx • Busy status bit • Whether to get interrupted on read/write or not • Auto-increment/decrement or no auto-change of address • 8-Bit Data mode • Master mode with separate read and write strobes • Required width of the address bus on data lines • Required read/write strobe width • Required data hold time after strobe PMAEN 1111111100000001 • Enable PMCS2 port • Enable as many higher address line ports as required • Enable PMALL port PMADDR 1xxxxxxxxxxxxxxx (1) Address register (bit 15 enables PMCS2 and bits are address bits) PMDIN1 N/A Data register Note 1: If chip select is not used, PMCON = 10x01011001xxx00 and PMADDR = xxxxxxxxxxxxxxxx. FIGURE 6: READ AND WRITE TIMING WHEN ADDRESS AND DATA LINES ARE PARTIALLY MULTIPLEXED PMCS PMA PMD PMRD PMWR PMALL 1/4 TCY 1 TCY 1 TCY PMD PMA PMA 1/2 TCY 1/2 TCY 1/2 TCY 1/4 TCY 1/4 TCY PMD DS01210A-page 10 © 2008 Microchip Technology Inc. 1 TCY 1 TCY
FULLY MULTIPLEXED MODE In fully multiplexed mode, the lower and the higher address byte lines are multiplexed with PMD. The PMA0 pin becomes the PMALL pin; this latches the lower address byte. The PMA1 pin becomes the PMALH pin; this latches the higher address byte. Therefore, 13 pins (PMA) are available (free from the PMP module) for other purposes. Figure 7 illustrates the interface of a 32K x 8-bit memory device, with the lower address byte lines and the higher address byte lines, multiplexed with data lines. Figure 8 provides the timing diagram. In this mode, each read and write takes three instruction cycles. AN1210 Table 6 provides the register configurations for associated registers. To use the APIs provided with this application note for this configuration, uncomment the following lines in the MIDefn.h file: #define Single32KBChip #define FullAddressDataMux FIGURE 7: 32K x 8-BIT MEMORY DEVICE INTERFACE USING FULLY MULTIPLEXED MODE PIC24F PMD PMALL PMALH PMCS2 PMRD PMWR 373 A Memory A 373 D A FIGURE 8: READ AND WRITE TIMING WHEN ADDRESSES ARE FULLY MULTIPLEXED WITH DATA PMC PMD PMRD PMWR PMALL PMALH 1/4 TCY PMD © 2008 Microchip Technology Inc. DS01210A-page 11 D CE OE WR Address Bus Data Bus Control Lines Address/Data Multiplexed 1 TCY 1 TCY 1 TCY 1 TCY 1 TCY 1 TCY PMA PMA PMA PMA PMD 1/2 TCY 1/2 TCY 1/2 TCY 1/2 TCY 1/2 TCY 1/2 TCY 1/4 TCY 1/4 TCY 1/4 TCY 1/4 TCY
Page 1 and 2: Author: Vidyadhar Vivekananda Micro
Page 3 and 4: FIGURE 1: MEMORY INTERFACE PMP PINS
Page 5 and 6: FUNCTIONAL IMPLEMENTATION This sect
Page 7 and 8: Interfacing a 32K x 8-Bit Memory De
Page 9: PARTIALLY MULTIPLEXED MODE In Parti
Page 13 and 14: Interfacing Two 16K x 8-Bit Memory
Page 15 and 16: Interfacing a 32K x 16-Bit Word Mem
Page 17 and 18: AN1210 FIGURE 12: READ TIMING WHEN
Page 19 and 20: EXPANSION OF EXTERNAL MEMORY Extern
Page 21 and 22: Interfacing Multiple Memory Devices
Page 23 and 24: REFERENCE CODE This section describ
Page 25 and 26: Memory Interface Application File E
Page 27 and 28: MemByteRead API The API, MemByteRea
Page 29 and 30: MemByteWrite API The API, MemByteWr
Page 31 and 32: CONCLUSION This application note di
Page 33 and 34: Note the following details of the c

Using External Memory with PIC24F/24H/dsPIC33F ... - Microchip

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