Using External Memory with PIC24F/24H/dsPIC33F ... - Microchip

PARTIALLY MULTIPLEXED MODE
In Partially Multiplexed mode, the lower address byte
lines are multiplexed with the PMD pins. The
higher address byte lines are on the PMA pins.
The PMA0 pin becomes the PMALL pin; this latches
the lower address byte. Therefore, seven pins
(PMA) are available (free from the PMP module)
for other purposes. Figure 5 illustrates the interface of
a 32K x 8-bit memory device with lower address byte
lines multiplexed with data lines. Figure 6 provides the
timing diagram. In the Partially Multiplexed mode, each
read and write operation takes two instruction cycles.
AN1210
Table 5 provides the register configurations for the
associated registers.
To use the APIs provided with this application note for
this configuration, uncomment the following lines in the
MIDefn.h file:
#define Single32KBChip
#define LowAddressDataMux
FIGURE 5: 32K x 8-BIT MEMORY DEVICE INTERFACE USING PARTIALLY MULTIPLEXED MODE
PIC24F
PMD
PMALL
PMA
PMCS2
PMRD
PMWR
A
373
D
A
Memory
© 2008 Microchip Technology Inc. DS01210A-page 9
D
CE
OE
WR
Address Bus
Data Bus
Control Lines
Address/Data Multiplexed