MB9A110 Series - Fujitsu

MB9A110 Series
BLOCK DIAGRAM
TRST X,TCK
TDI,TMS
TDO
TRACED [ 3:0],
TRACECLK
52
INITX
X0
X1
X0A
X1A
AVCC ,
AVSS,AVRH
AN [ 15:0]
ADTG[8:0]
TIOA [7:0]
TIOB [ 7:0]
AIN [1:0]
BIN [1:0]
ZIN[1:0]
IC0[3:0]
IC1[3:0]
FRCK [1:0]
DTTI [1:0]X
RTO 0[5:0]
RTO 1[ 5:0]
MB9AF111 L/ M / N , F112 L/ M / N, F114 L/ M / N , F115 M / N, F116 M / N
SWJ-DP
TPIU*
Cortex - M3 Core
@40MHz(Max.)
1 ROM
Table
Dual -Timer
Clock Reset
Generator
WatchDog Timer
(Hardware )
Main
Osc
Sub .
Osc
CSV
Unit 0
PLL
A/D Activation
Compare
3ch
16-bit Input Capture
4ch
16-bit Free - Run
Timer
3ch
16-bit Output
Compare
6ch
Waveform
Generator
3ch
16-bit PPG
3ch
ETM* 1
NVIC
WatchDog Timer
(Software )
CLK RST
CR
4MHz
12bit A / D Converter
Unit 1
Unit 2* 2
Base Timer
16-bit 8ch /
32-bit 4ch
QPRC
2ch
Multi Function Timer x 2
D
I
Sys
CR
100kHz
AHB-APB Bridge :
APB0(Max.40MHz)
AHB-APBBridge : APB1 (Max.40MHz)
AHB-APB Bridge : APB2 ( Max.40MHz)
Multi-layer AHB(Max.40MHz)
Flash I/F
Security
AHB-AHB
Bridge
External Bus IF * 2
LVD Ctrl
IRQ - Monitor
CRC
Accelerator
Watch Counter
External Interrupt
Controller
16-pin + NMI
MODE -Ctrl
GPIO
Multi Serial IF
8ch
(with FIFO ch .4 to 7)
& HW flow control (ch .4)* 2
SRAM0
8/ 16
Kbyte
On-Chip
Flash
64/ 128/ 256/ 384/ 512
Kbyte
DMAC
8ch
SRAM1
8/ 16
Kbyte
Power On
Reset
LVD
Regulator
PIN-Function -Ctrl
MAD[24:0]
MADATA[15:0]
MCSX [7:0],
MOEX ,MWEX ,
MALE
MRDY
MCLKOUT
MDQM [ 1:0]
DS706-00011-1v0-E
C
INT[15:0]
NMI X
MD [1:0]
P0[F:0],
P1[F:0],
・
・
Px[ x:0] ,
SCK [7:0]
SIN[7:0]
SOT[7:0]
CTS 4
RTS 4
*1: For the MB9AF111L/M, F112L/M, MB9AF114L/M, MB9AF315M and MB9AF316M, ETM is not
available.
*2: For the MB9AF111L, F112L and MB9AF114L, External Bus Interface and 12-bit A/D Converter (unit 2)
are not available. And Multi-function Serial Interface does not support hardware flow control in these
products.