MB9A110 Series - Fujitsu
MB9A110 Series - Fujitsu
MB9A110 Series - Fujitsu
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<strong>MB9A110</strong> <strong>Series</strong><br />
Separate Bus Access Asynchronous SRAM Mode<br />
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)<br />
Parameter Symbol Pin name Conditions<br />
Min<br />
Value<br />
Max<br />
Unit<br />
MOEX<br />
Min pulse width<br />
tOEW MOEX<br />
Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
MCLK×n-3 - ns<br />
MCSX ↓ → Address<br />
output delay time<br />
tCSL – AV<br />
MCSX[7:0]<br />
MAD[24:0]<br />
Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
-9<br />
-12<br />
9<br />
12<br />
ns<br />
MOEX ↑ →<br />
Address hold time<br />
tOEH - AX<br />
MOEX<br />
MAD[24:0]<br />
Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
0<br />
MCLK×m+9<br />
MCLK×m+12<br />
ns<br />
MCSX ↓ →<br />
MOEX ↓ delay time<br />
tCSL - OEL<br />
MOEX<br />
Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
MCLK×m-9 MCLK×m+9<br />
MCLK×m-12 MCLK×m+12<br />
ns<br />
MOEX ↑ →<br />
MCSX ↑ time<br />
tOEH - OSH<br />
MCSX[7:0] Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
0<br />
MCLK×m+9<br />
MCLK×m+12<br />
ns<br />
MCSX ↓ →<br />
MDQM ↓ delay time<br />
tCSL - RDQML<br />
MOEX<br />
MDQM[1:0]<br />
Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
MCLK×m-9 MCLK×m+9<br />
MCLK×m-12 MCLK×m+12<br />
ns<br />
Data set up →<br />
MOEX ↑ time<br />
tDS - OE<br />
MOEX<br />
MADATA[15:0]<br />
Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
20<br />
38<br />
-<br />
-<br />
ns<br />
MOEX ↑ →<br />
Data hold time<br />
tDH - OE<br />
MOEX<br />
MADATA[15:0]<br />
Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
0 - ns<br />
MWEX<br />
Min pulse width<br />
tWEW MWEX<br />
Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
MCLK×n-3 - ns<br />
MWEX ↑ → Address<br />
output delay time<br />
tWEH - AX<br />
MWEX<br />
MAD[24:0]<br />
Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
0<br />
MCLK×m+9<br />
MCLK×m+12<br />
ns<br />
MCSX ↓ →<br />
MWEX ↓ delay time<br />
tCSL - WEL<br />
MWEX<br />
Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
MCLK×n-9 MCLK×n+9<br />
MCLK×n-12 MCLK×n+12<br />
ns<br />
MWEX ↑→<br />
MCSX ↑ delay time<br />
tWEH - CSH<br />
MCSX[7:0] Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
0<br />
MCLK×m+9<br />
MCLK×m+12<br />
ns<br />
MCSX ↓ →<br />
MDQM ↓ delay time<br />
tCSL-WDQML<br />
MCSX<br />
MDQM[1:0]<br />
Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
MCLK×n-9 MCLK×n+9<br />
MCLK×n-12 MCLK×n+12<br />
ns<br />
MWEX ↓ →<br />
Data output time<br />
tWEL - DV<br />
MWEX<br />
Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
- 9<br />
-12<br />
9<br />
12<br />
ns<br />
MWEX ↑ →<br />
Data hold time<br />
tWEH - DX<br />
MADATA[15:0] Vcc ≥ 4.5V<br />
Vcc < 4.5V<br />
0<br />
MCLK×m+9<br />
MCLK×m+12<br />
ns<br />
Note: When the external load capacitance = 30pF (m = 0 to 15, n = 1 to 16).<br />
72<br />
DS706-00011-1v0-E
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