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MB9A110 Series - Fujitsu

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DS706-00011-1v0-E<br />

<strong>MB9A110</strong> <strong>Series</strong><br />

Synchronous serial(SPI = 1, SCINV = 1)<br />

(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)<br />

Parameter Symbol<br />

Vcc < 4.5V Vcc ≥ 4.5V<br />

Pin<br />

name Conditions Min Max Min Max Unit<br />

Serial clock cycle time tSCYC SCKx 4tcycp - 4tcycp - ns<br />

SCK ↓ → SOT delay time tSLOVI SCKx<br />

SOTx<br />

-30 +30 - 20 + 20 ns<br />

SIN → SCK ↑ setup time tIVSHI SCKx<br />

SCK ↑→ SIN hold time tSHIXI<br />

SINx<br />

50 - 30 - ns<br />

SCKx<br />

SINx<br />

0 - 0 - ns<br />

SOT → SCK ↑ delay time tSOVHI SCKx<br />

Internal shift<br />

clock<br />

operation<br />

SOTx<br />

2tcycp -<br />

30<br />

-<br />

2tcycp -<br />

30<br />

- ns<br />

Serial clock "L" pulse width tSLSH SCKx<br />

2tcycp -<br />

10<br />

-<br />

2tcycp -<br />

10<br />

- ns<br />

Serial clock "H" pulse width tSHSL SCKx<br />

tcycp +<br />

10<br />

-<br />

tcycp +<br />

10<br />

- ns<br />

SCK ↓ → SOT delay time tSLOVE SCKx<br />

SIN → SCK ↑ setup time<br />

SOTx<br />

tIVSHE<br />

- 50 - 30 ns<br />

SCKx<br />

SINx<br />

10 - 10 - ns<br />

SCK ↑ → SIN hold time tSHIXE SCKx<br />

External shift<br />

clock<br />

operation<br />

SINx<br />

20 - 20 - ns<br />

SCK fall time tF SCKx - 5 - 5 ns<br />

SCK rise time tR SCKx<br />

- 5 - 5 ns<br />

Notes: The above characteristics apply to CLK synchronous mode.<br />

tCYCP indicates the APB bus clock cycle time. Please see the block diagram to refer the APB bus<br />

number which UART is connected.<br />

These characteristics only guarantee the same relocate port number.<br />

For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.<br />

When the external load capacitance = 30pF.<br />

85

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