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Features • Utilizes the AVR ® RI
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Block Diagram 2543K-AVR-03/10 Figur
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Pin Descriptions VCC Digital supply
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About Code Examples 2543K-AVR-03/10
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AVR CPU Core 2543K-AVR-03/10 ATtiny
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General Purpose Register File 2543K
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2543K-AVR-03/10 ATtiny2313 Stack Po
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Interrupt Response Time 2543K-AVR-0
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SRAM Data Memory Data Memory Access
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The EEPROM Data Register - EEDR The
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2543K-AVR-03/10 ATtiny2313 The foll
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General Purpose I/O Registers Gener
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2543K-AVR-03/10 ATtiny2313 Clock So
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Calibrated Internal RC Oscillator 2
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2543K-AVR-03/10 ATtiny2313 External
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2543K-AVR-03/10 ATtiny2313 cleared
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2543K-AVR-03/10 ATtiny2313 Power-do
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System Control and Reset 2543K-AVR-
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2543K-AVR-03/10 Figure 16. MCU Star
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2543K-AVR-03/10 ATtiny2313 Watchdog
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Watchdog Timer ATtiny2313 has an En
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2543K-AVR-03/10 ATtiny2313 The foll
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2543K-AVR-03/10 Table 20. Watchdog
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2543K-AVR-03/10 ATtiny2313 The most
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Ports as General Digital I/O 2543K-
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2543K-AVR-03/10 ATtiny2313 Consider
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Alternate Port Functions 2543K-AVR-
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MCU Control Register - MCUCR Altern
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2543K-AVR-03/10 Table 26. Overridin
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2543K-AVR-03/10 ATtiny2313 Table 29
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External Interrupts Pin Change Inte
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External Interrupt Flag Register -
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2543K-AVR-03/10 ATtiny2313 Definiti
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Force Output Compare Compare Match
- Page 69 and 70: Clear Timer on Compare Match (CTC)
- Page 71 and 72: Phase Correct PWM Mode 2543K-AVR-03
- Page 73 and 74: Timer/Counter Timing Diagrams 2543K
- Page 75 and 76: 8-bit Timer/Counter Register Descri
- Page 77 and 78: 2543K-AVR-03/10 ATtiny2313 Table 39
- Page 79 and 80: Timer/Counter Register - TCNT0 Outp
- Page 81 and 82: 2543K-AVR-03/10 ATtiny2313 the flag
- Page 83 and 84: General Timer/Counter Control Regis
- Page 85 and 86: 2543K-AVR-03/10 ATtiny2313 Register
- Page 87 and 88: 2543K-AVR-03/10 Assembly Code Examp
- Page 89 and 90: Reusing the Temporary High Byte Reg
- Page 91 and 92: 2543K-AVR-03/10 ATtiny2313 The Time
- Page 93 and 94: 2543K-AVR-03/10 ATtiny2313 are used
- Page 95 and 96: Compare Match Output Unit 2543K-AVR
- Page 97 and 98: 2543K-AVR-03/10 Figure 45. CTC Mode
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- Page 103 and 104: 2543K-AVR-03/10 ATtiny2313 The Time
- Page 105 and 106: 2543K-AVR-03/10 Figure 51. Timer/Co
- Page 107 and 108: 2543K-AVR-03/10 ATtiny2313 Note: 1.
- Page 109 and 110: Timer/Counter1 Control Register B -
- Page 111 and 112: Output Compare Register 1 B - OCR1B
- Page 113 and 114: 2543K-AVR-03/10 ATtiny2313 USART Th
- Page 115 and 116: Internal Clock Generation - The Bau
- Page 117 and 118: 2543K-AVR-03/10 ATtiny2313 ing XCK
- Page 119: 2543K-AVR-03/10 ATtiny2313 More adv
- Page 123 and 124: Data Reception - The USART Receiver
- Page 125 and 126: Receive Compete Flag and Interrupt
- Page 127 and 128: Asynchronous Clock Recovery Asynchr
- Page 129 and 130: 2543K-AVR-03/10 ATtiny2313 Table 49
- Page 131 and 132: USART Register Description USART I/
- Page 133 and 134: USART Control and Status Register B
- Page 135 and 136: USART Baud Rate Registers - UBRRL a
- Page 137 and 138: Table 57. Examples of UBRR Settings
- Page 139 and 140: 2543K-AVR-03/10 Table 59. Examples
- Page 141 and 142: Functional Descriptions 2543K-AVR-0
- Page 143 and 144: SPI Slave Operation Example 2543K-A
- Page 145 and 146: 2543K-AVR-03/10 Figure 64. Two-wire
- Page 147 and 148: USI Status Register - USISR USI Con
- Page 149 and 150: 2543K-AVR-03/10 Table 60. Relations
- Page 151 and 152: Analog Comparator Analog Comparator
- Page 153 and 154: debugWIRE Onchip Debug System 2543K
- Page 155 and 156: Self- Programming the Flash Perform
- Page 157 and 158: Store Program Memory Control and St
- Page 159 and 160: Preventing Flash Corruption Program
- Page 161 and 162: 2543K-AVR-03/10 ATtiny2313 Fuse Bit
- Page 163 and 164: Parallel Programming Parameters, Pi
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- Page 169 and 170: Programming the EEPROM 2543K-AVR-03
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Programming the Lock Bits Reading t
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2543K-AVR-03/10 ATtiny2313 Figure 7
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Serial Programming Algorithm 2543K-
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Table 78. Serial Programming Instru
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Electrical Characteristics Absolute
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External Clock Drive Waveforms Exte
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ATtiny2313 Typical Characteristics
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2543K-AVR-03/10 Figure 87. Active S
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Idle Supply Current Figure 91. Idle
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2543K-AVR-03/10 Figure 95. Idle Sup
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Standby Supply Current 2543K-AVR-03
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2543K-AVR-03/10 Figure 103. Reset P
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2543K-AVR-03/10 Figure 107. I/O Pin
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2543K-AVR-03/10 Figure 111. Reset I
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2543K-AVR-03/10 Figure 115. Reset I
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2543K-AVR-03/10 Figure 119. Reset I
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2543K-AVR-03/10 Figure 123. Reset I
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Internal Oscillator Speed 2543K-AVR
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2543K-AVR-03/10 Figure 131. Calibra
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Current Consumption of Peripheral U
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Current Consumption in Reset and Re
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Register Summary 2543K-AVR-03/10 AT
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Instruction Set Summary 2543K-AVR-0
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Ordering Information Speed (MHz) (3
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20S 2543K-AVR-03/10 ATtiny2313 219
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Errata The revision in this section
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Changes from Rev. 2514F-08/04 to Re
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Table of Contents 2543K-AVR-03/10 F
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2543K-AVR-03/10 Limitations of debu