ATtiny2313 Datasheet - DCE FEL ČVUT v Praze
ATtiny2313 Datasheet - DCE FEL ČVUT v Praze
ATtiny2313 Datasheet - DCE FEL ČVUT v Praze
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Pin<br />
Configurations<br />
2<br />
<strong>ATtiny2313</strong><br />
Figure 1. Pinout <strong>ATtiny2313</strong><br />
(RESET/dW) PA2<br />
(RXD) PD0<br />
(TXD) PD1<br />
(XTAL2) PA1<br />
(XTAL1) PA0<br />
(CKOUT/XCK/INT0) PD2<br />
(INT1) PD3<br />
(T0) PD4<br />
(OC0B/T1) PD5<br />
GND<br />
(TXD) PD1<br />
XTAL2) PA1<br />
(XTAL1) PA0<br />
(CKOUT/XCK/INT0) PD2<br />
(INT1) PD3<br />
PDIP/SOIC<br />
Overview The <strong>ATtiny2313</strong> is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC<br />
architecture. By executing powerful instructions in a single clock cycle, the <strong>ATtiny2313</strong> achieves<br />
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption<br />
versus processing speed.<br />
1<br />
2<br />
3<br />
4<br />
5<br />
PD0 (RXD)<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10<br />
MLF<br />
20<br />
19<br />
18<br />
17<br />
16<br />
15<br />
14<br />
13<br />
12<br />
11<br />
20<br />
19<br />
18<br />
17<br />
16<br />
6<br />
7<br />
8<br />
9<br />
10<br />
(T0) PD4<br />
PA2 (RESET/dW)<br />
VCC<br />
PB7 (UCSK/SCK/PCINT7)<br />
(OC0B/T1) PD5<br />
GND<br />
(ICP) PD6<br />
(AIN0/PCINT0) PB0<br />
VCC<br />
PB7 (UCSK/SCL/PCINT7)<br />
PB6 (MISO/DO/PCINT6)<br />
PB5 (MOSI/DI/SDA/PCINT5)<br />
PB4 (OC1B/PCINT4)<br />
PB3 (OC1A/PCINT3)<br />
PB2 (OC0A/PCINT2)<br />
PB1 (AIN1/PCINT1)<br />
PB0 (AIN0/PCINT0)<br />
PD6 (ICP)<br />
15<br />
14<br />
13<br />
12<br />
11<br />
PB5 (MOSI/DI/SDA/PCINT5)<br />
PB4 (OC1B/PCINT4)<br />
PB3 (OC1A/PCINT3)<br />
PB2 (OC0A/PCINT2)<br />
PB1 (AIN1/PCINT1)<br />
NOTE: Bottom pad should be soldered to ground.<br />
PB6 (MISO/DO/PCINT6)<br />
2543K–AVR–03/10
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