ATtiny2313 Datasheet - DCE FEL ČVUT v Praze

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26 <strong>ATtiny2313</strong> Figure 12. Crystal Oscillator Connections The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 4. Table 4. Crystal Oscillator Operating Modes CKSEL3..1 Frequency Range (1) (MHz) 100 (2) C2 C1 XTAL2 XTAL1 GND Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 0.4 - 0.9 – 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 12 - 22 Notes: 1. The frequency ranges are preliminary values. Actual values are TBD. 2. This option should not be used with crystals, only with ceramic resonators. The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 5. 2543K–AVR–03/10
Calibrated Internal RC Oscillator 2543K–AVR–03/10 Table 5. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1..0 Start-up Time from Power-down and Power-save 0 00 258 CK (1) 0 01 258 CK (1) 0 10 1K CK (2) 0 11 1K CK (2) 1 00 1K CK (2) 1 1 1 <strong>ATtiny2313</strong> Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. The calibrated internal RC Oscillator provides a fixed 8.0 MHz clock. The frequency is nominal value at 3V and 25°C. If 8 MHz frequency exceeds the specification of the device (depends on V CC), the CKDIV8 Fuse must be programmed in order to divide the internal frequency by 8 during start-up. The device is shipped with the CKDIV8 Fuse programmed. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 6. If selected, it will operate with no external components. During reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 3V and 25°C, this calibration gives a frequency within ± 10% of the nominal frequency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 2% accuracy at any given V CC and Temperature. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page 162. Note: 1. The device is shipped with this option selected. Additional Delay from Reset (V CC = 5.0V) Recommended Usage 14CK + 4.1 ms Ceramic resonator, fast rising power 14CK + 65 ms Ceramic resonator, slowly rising power 14CK Ceramic resonator, BOD enabled 14CK + 4.1 ms Ceramic resonator, fast rising power 14CK + 65 ms Ceramic resonator, slowly rising power 01 16K CK 14CK Crystal Oscillator, BOD enabled 10 16K CK 14CK + 4.1 ms Crystal Oscillator, fast rising power 11 16K CK 14CK + 65 ms Crystal Oscillator, slowly rising power Table 6. Internal Calibrated RC Oscillator Operating Modes CKSEL3..0 Nominal Frequency 0010 - 0011 4.0 MHz 0100 - 0101 8.0 MHz (1) 27
Page 1 and 2: Features • Utilizes the AVR ® RI
Page 3 and 4: Block Diagram 2543K-AVR-03/10 Figur
Page 5 and 6: Pin Descriptions VCC Digital supply
Page 7 and 8: About Code Examples 2543K-AVR-03/10
Page 9 and 10: AVR CPU Core 2543K-AVR-03/10 ATtiny
Page 11 and 12: General Purpose Register File 2543K
Page 13 and 14: 2543K-AVR-03/10 ATtiny2313 Stack Po
Page 15 and 16: Interrupt Response Time 2543K-AVR-0
Page 17 and 18: SRAM Data Memory Data Memory Access
Page 19 and 20: The EEPROM Data Register - EEDR The
Page 21 and 22: 2543K-AVR-03/10 ATtiny2313 The foll
Page 23 and 24: General Purpose I/O Registers Gener
Page 25: 2543K-AVR-03/10 ATtiny2313 Clock So
Page 29 and 30: 2543K-AVR-03/10 ATtiny2313 External
Page 31 and 32: 2543K-AVR-03/10 ATtiny2313 cleared
Page 33 and 34: 2543K-AVR-03/10 ATtiny2313 Power-do
Page 35 and 36: System Control and Reset 2543K-AVR-
Page 37 and 38: 2543K-AVR-03/10 Figure 16. MCU Star
Page 39 and 40: 2543K-AVR-03/10 ATtiny2313 Watchdog
Page 41 and 42: Watchdog Timer ATtiny2313 has an En
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Page 45 and 46: 2543K-AVR-03/10 Table 20. Watchdog
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Page 49 and 50: Ports as General Digital I/O 2543K-
Page 51 and 52: 2543K-AVR-03/10 ATtiny2313 Consider
Page 53 and 54: Alternate Port Functions 2543K-AVR-
Page 55 and 56: MCU Control Register - MCUCR Altern
Page 57 and 58: 2543K-AVR-03/10 Table 26. Overridin
Page 59 and 60: 2543K-AVR-03/10 ATtiny2313 Table 29
Page 61 and 62: External Interrupts Pin Change Inte
Page 63 and 64: External Interrupt Flag Register -
Page 65 and 66: 2543K-AVR-03/10 ATtiny2313 Definiti
Page 67 and 68: Force Output Compare Compare Match
Page 69 and 70: Clear Timer on Compare Match (CTC)
Page 71 and 72: Phase Correct PWM Mode 2543K-AVR-03
Page 73 and 74: Timer/Counter Timing Diagrams 2543K
Page 75 and 76: 8-bit Timer/Counter Register Descri
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2543K-AVR-03/10 ATtiny2313 Table 39
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Timer/Counter Register - TCNT0 Outp
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2543K-AVR-03/10 ATtiny2313 the flag
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General Timer/Counter Control Regis
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2543K-AVR-03/10 ATtiny2313 Register
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2543K-AVR-03/10 Assembly Code Examp
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Reusing the Temporary High Byte Reg
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2543K-AVR-03/10 ATtiny2313 The Time
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2543K-AVR-03/10 ATtiny2313 are used
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Compare Match Output Unit 2543K-AVR
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2543K-AVR-03/10 Figure 45. CTC Mode
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2543K-AVR-03/10 ATtiny2313 Note tha
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2543K-AVR-03/10 ATtiny2313 value (a
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2543K-AVR-03/10 ATtiny2313 The Time
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2543K-AVR-03/10 Figure 51. Timer/Co
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2543K-AVR-03/10 ATtiny2313 Note: 1.
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Timer/Counter1 Control Register B -
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Output Compare Register 1 B - OCR1B
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2543K-AVR-03/10 ATtiny2313 USART Th
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Internal Clock Generation - The Bau
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2543K-AVR-03/10 ATtiny2313 ing XCK
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2543K-AVR-03/10 ATtiny2313 More adv
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Sending Frames with 9 Data Bit 2543
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Data Reception - The USART Receiver
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Receive Compete Flag and Interrupt
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Asynchronous Clock Recovery Asynchr
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2543K-AVR-03/10 ATtiny2313 Table 49
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USART Register Description USART I/
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USART Control and Status Register B
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USART Baud Rate Registers - UBRRL a
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Table 57. Examples of UBRR Settings
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2543K-AVR-03/10 Table 59. Examples
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Functional Descriptions 2543K-AVR-0
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SPI Slave Operation Example 2543K-A
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2543K-AVR-03/10 Figure 64. Two-wire
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USI Status Register - USISR USI Con
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2543K-AVR-03/10 Table 60. Relations
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Analog Comparator Analog Comparator
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debugWIRE Onchip Debug System 2543K
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Self- Programming the Flash Perform
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Store Program Memory Control and St
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Preventing Flash Corruption Program
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2543K-AVR-03/10 ATtiny2313 Fuse Bit
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Parallel Programming Parameters, Pi
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Serial Programming Pin Mapping Para
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Programming the Flash 2543K-AVR-03/
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Programming the EEPROM 2543K-AVR-03
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Programming the Lock Bits Reading t
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2543K-AVR-03/10 ATtiny2313 Figure 7
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Serial Programming Algorithm 2543K-
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Table 78. Serial Programming Instru
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Electrical Characteristics Absolute
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External Clock Drive Waveforms Exte
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ATtiny2313 Typical Characteristics
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2543K-AVR-03/10 Figure 87. Active S
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Idle Supply Current Figure 91. Idle
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2543K-AVR-03/10 Figure 95. Idle Sup
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Standby Supply Current 2543K-AVR-03
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2543K-AVR-03/10 Figure 103. Reset P
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2543K-AVR-03/10 Figure 107. I/O Pin
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2543K-AVR-03/10 Figure 111. Reset I
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Internal Oscillator Speed 2543K-AVR
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2543K-AVR-03/10 Figure 131. Calibra
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Current Consumption of Peripheral U
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Current Consumption in Reset and Re
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Register Summary 2543K-AVR-03/10 AT
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Instruction Set Summary 2543K-AVR-0
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Ordering Information Speed (MHz) (3
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20S 2543K-AVR-03/10 ATtiny2313 219
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Errata The revision in this section
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Changes from Rev. 2514F-08/04 to Re
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Table of Contents 2543K-AVR-03/10 F
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2543K-AVR-03/10 Limitations of debu
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ATtiny2313 Datasheet - DCE FEL ČVUT v Praze

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