13-McBSP [Compatibility Mode]

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Stereo Audio Codec TLV320AIC23B GPIO -MUX F2833x –Function Description AIC23– signal GPIO20 =2 McBSPA–MDXA Audio data out DIN GPIO21 =2 McBSPA–MDRA Audio data in DOUT GPIO22 =2 McBSPA–MCLKXA Transmit clock BCLK GPIO23 =2 McBSPA–MFSXA Transmit frame sync LRCIN GPIO58 =1 McBSPA–MCLKRA Receive Clock BCLK GPIO59 =1 McBSPA–MFRA Receive frame sync LRCOUT GPIO16 =1 SPIA–SPISIMO Control data out SDIN GPIO18 =1 SPIA–SPICLK Control data clock GPIO19 =1 SPIA–SPISTE Slave trans. enable SCLK /CS 13 - 30
Stereo Audio Codec TLV320AIC23B Reset Register: Power Down Control Register: LINE =Line Input MIC = Microphone Input ADC =InternalADC DAC =Internal DAC OUT =Output Signals OSC =Oscillator CLK =CLOCK OFF =Device Power 0=ON; 1=OFF 13 - 31
Page 1 and 2: Module 13: Multichannel Buffered Se
Page 3 and 4: CPU McBSP Block Diagram Peripheral
Page 5 and 6: • Direct interface to: • T1/E1
Page 7 and 8: CLK FS D a1 a0 Bit Definition: Bit
Page 9 and 10: Compression & Expanding Data 13 -9
Page 11 and 12: McBSP - Frame Phases Single Phase F
Page 13 and 14: McBSP - Transmission Transmission p
Page 15 and 16: McBSP - Register Set McBSP Control
Page 17 and 18: McBSP - Data Register McBSP Data Re
Page 19 and 20: McBSP - Serial Port Control Registe
Page 21 and 22: McBSP - Receive Control Register 2
Page 23 and 24: McBSP - Transmit Control Register 2
Page 25 and 26: McBSP - Sample Rate Generator (SRGR
Page 27 and 28: McBSP - Interrupt Enable Register (
Page 29: Stereo Audio Codec TLV320AIC23B Fun
Page 33 and 34: Stereo Audio Codec TLV320AIC23B Ana
Page 35 and 36: Stereo Audio Codec TLV320AIC23B Dig
Page 37 and 38: Stereo Audio Codec TLV320AIC23B Dig
Page 39 and 40: EEPROM AT25256 Exercise: Lab13_4:
Page 41 and 42: Access Status Register: EEPROM AT25
Page 43 and 44: EEPROM AT25256 Write -Enable (WREN)
Page 45 and 46: Read (READ) Timing: EEPROM AT25256

13-McBSP [Compatibility Mode]

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