13-McBSP [Compatibility Mode]

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FS D w6 w7 Definition: Word and Frame Word w0 w1 w2 w3 w4 w5 w6 w7 Frame u “Frame” - contains one or multiple words u Number of words per frame: 1-128 <strong>13</strong> -6
CLK FS D a1 a0 Bit Definition: Bit and Word b7 b6 b5 b4 b3 b2 b1 b0 Word u “Bit” - one data bit per serial clock period u “Word” or “channel” contains number of bits (8, 12, 16, 20, 24, 32) <strong>13</strong> -7
Page 1 and 2: Module 13: Multichannel Buffered Se
Page 3 and 4: CPU McBSP Block Diagram Peripheral
Page 5: • Direct interface to: • T1/E1
Page 9 and 10: Compression & Expanding Data 13 -9
Page 11 and 12: McBSP - Frame Phases Single Phase F
Page 13 and 14: McBSP - Transmission Transmission p
Page 15 and 16: McBSP - Register Set McBSP Control
Page 17 and 18: McBSP - Data Register McBSP Data Re
Page 19 and 20: McBSP - Serial Port Control Registe
Page 21 and 22: McBSP - Receive Control Register 2
Page 23 and 24: McBSP - Transmit Control Register 2
Page 25 and 26: McBSP - Sample Rate Generator (SRGR
Page 27 and 28: McBSP - Interrupt Enable Register (
Page 29 and 30: Stereo Audio Codec TLV320AIC23B Fun
Page 31 and 32: Stereo Audio Codec TLV320AIC23B Res
Page 33 and 34: Stereo Audio Codec TLV320AIC23B Ana
Page 35 and 36: Stereo Audio Codec TLV320AIC23B Dig
Page 37 and 38: Stereo Audio Codec TLV320AIC23B Dig
Page 39 and 40: EEPROM AT25256 Exercise: Lab13_4:
Page 41 and 42: Access Status Register: EEPROM AT25
Page 43 and 44: EEPROM AT25256 Write -Enable (WREN)
Page 45 and 46: Read (READ) Timing: EEPROM AT25256

13-McBSP [Compatibility Mode]

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