13-McBSP [Compatibility Mode]

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• Full - duplex communication Features of McBSP • Double-buffered transmission and triple-buffered reception, allowing a continuous data stream • Independent clocking and framing for reception and transmission • send interrupts to the CPU and send DMA events to the DMA - controller • 128 channels for transmission and reception • Multichannel selection modes that enable or disable block transfers in each of the channels • Direct interface to industry-standard CODECs, analog interface chips (AICs), and other serially connected A/D and D/A devices • Support for external generation of clock signals and frame - synchronization signals • A programmable sample rate generator for internal generation and control of clock signals and frame - synchronization signals 13 -4
• Direct interface to: • T1/E1 framers Features of McBSP • IOM-2 compliant devices • AC97-compliant devices with multiphase frame capability • I2S compliant devices • SPI devices • Variable data sizes: 8, 12, 16, 20, 24, and 32 bits • A-law (Europe) and µ-law (US & Japan) hardware compression / expanding 13 -5
Page 1 and 2: Module 13: Multichannel Buffered Se
Page 3: CPU McBSP Block Diagram Peripheral
Page 7 and 8: CLK FS D a1 a0 Bit Definition: Bit
Page 9 and 10: Compression & Expanding Data 13 -9
Page 11 and 12: McBSP - Frame Phases Single Phase F
Page 13 and 14: McBSP - Transmission Transmission p
Page 15 and 16: McBSP - Register Set McBSP Control
Page 17 and 18: McBSP - Data Register McBSP Data Re
Page 19 and 20: McBSP - Serial Port Control Registe
Page 21 and 22: McBSP - Receive Control Register 2
Page 23 and 24: McBSP - Transmit Control Register 2
Page 25 and 26: McBSP - Sample Rate Generator (SRGR
Page 27 and 28: McBSP - Interrupt Enable Register (
Page 29 and 30: Stereo Audio Codec TLV320AIC23B Fun
Page 31 and 32: Stereo Audio Codec TLV320AIC23B Res
Page 33 and 34: Stereo Audio Codec TLV320AIC23B Ana
Page 35 and 36: Stereo Audio Codec TLV320AIC23B Dig
Page 37 and 38: Stereo Audio Codec TLV320AIC23B Dig
Page 39 and 40: EEPROM AT25256 Exercise: Lab13_4:
Page 41 and 42: Access Status Register: EEPROM AT25
Page 43 and 44: EEPROM AT25256 Write -Enable (WREN)
Page 45 and 46: Read (READ) Timing: EEPROM AT25256

13-McBSP [Compatibility Mode]

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