Chapter 15 Pulse-Width Modulation Subsystem (PWMSS).

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Enhanced PWM (ePWM) Module www.ti.com Interrupt Controller EPWM1INT To eCAP1 EPWM2INT EPWMxINT Figure 15-6. Multiple ePWM Modules SYNCI ePWM1 module SYNCO SYNCI ePWM2 module SYNCO SYNCI ePWMx module SYNCO Peripheral Frame 1 EPWM1A EPWM1B EPWM2A EPWM2B EPWMxA EPWMxB xSYNCI TZ1 to TZn TZ1 to TZn xSYNCO TZ1 to TZn 1624 Pulse-Width Modulation Subsystem (PWMSS) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated GPIO MUX
www.ti.com Enhanced PWM (ePWM) Module Interrupt controller Figure 15-7. Submodules and Signal Connections for an ePWM Module EPWMxSYNCI EPWMxSYNCO EPWMxTZINT EPWMxINT Peripheral bus ePWM module Time-base (TB) module Counter-compare (CC) module Action-qualifier (AQ) module Dead-band (DB) module PWM-chopper (PC) module Event-trigger (ET) module Trip-zone (TZ) module TZ1 to TZn EPWMxA EPWMxB Figure 15-8 shows more internal details of a single ePWM module. The main signals used by the ePWM module are: • PWM output signals (EPWMxA and EPWMxB). The PWM output signals are made available external to the device through the GPIO peripheral described in the system control and interrupts guide for your device. • Trip-zone signals (TZ1 to TZn). These input signals alert the ePWM module of an external fault condition. Each module on a device can be configured to either use or ignore any of the trip-zone signals. The trip-zone signal can be configured as an asynchronous input through the GPIO peripheral. See Section 15.1.2 to determine how many trip-zone pins are available in the device. • Time-base synchronization input (EPWMxSYNCI) and output (EPWMxSYNCO) signals. The synchronization signals daisy chain the ePWM modules together. Each module can be configured to either use or ignore its synchronization input. The clock synchronization input and output signal are brought out to pins only for ePWM1 (ePWM module #1). The synchronization output for ePWM1 (EPWM1SYNCO) is also connected to the SYNCI of the first enhanced capture module (eCAP1). GPIO • Peripheral Bus. The peripheral bus is 32-bits wide and allows both 16-bit and 32-bit writes to the ePWM register file. Figure 15-8 also shows the key internal submodule interconnect signals. Each submodule is described in detail in . SPRUH73E–October 2011–Revised May 2012 Pulse-Width Modulation Subsystem (PWMSS) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated MUX 1625
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Chapter 15 Pulse-Width Modulation Subsystem (PWMSS).

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