Chapter 15 Pulse-Width Modulation Subsystem (PWMSS).

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15.2.2.4.3 Operational Highlights for the Counter-Compare Submodule
The counter-compare submodule is responsible for generating two independent compare events based on
two compare registers:
1. CTR = CMPA: Time-base counter equal to counter-compare A register (TBCNT = CMPA).
2. CTR = CMPB: Time-base counter equal to counter-compare B register (TBCNT = CMPB).
For up-count or down-count mode, each event occurs only once per cycle. For up-down-count mode each
event occurs twice per cycle, if the compare value is between 0000h and TBPRD; and occurs once per
cycle, if the compare value is equal to 0000h or equal to TBPRD. These events are fed into the actionqualifier
submodule where they are qualified by the counter direction and converted into actions if
enabled. Refer to Section 15.2.2.5.1 for more details.
The counter-compare registers CMPA and CMPB each have an associated shadow register. Shadowing
provides a way to keep updates to the registers synchronized with the hardware. When shadowing is
used, updates to the active registers only occurs at strategic points. This prevents corruption or spurious
operation due to the register being asynchronously modified by software. The memory address of the
active register and the shadow register is identical. Which register is written to or read from is determined
by the CMPCTL[SHDWAMODE] and CMPCTL[SHDWBMODE] bits. These bits enable and disable the
CMPA shadow register and CMPB shadow register respectively. The behavior of the two load modes is
described below:
• Shadow Mode: The shadow mode for the CMPA is enabled by clearing the CMPCTL[SHDWAMODE]
bit and the shadow register for CMPB is enabled by clearing the CMPCTL[SHDWBMODE] bit. Shadow
mode is enabled by default for both CMPA and CMPB.
If the shadow register is enabled then the content of the shadow register is transferred to the active
register on one of the following events:
– CTR = PRD: Time-base counter equal to the period (TBCNT = TBPRD).
– CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
– Both CTR = PRD and CTR = 0
Which of these three events is specified by the CMPCTL[LOADAMODE] and CMPCTL[LOADBMODE]
register bits. Only the active register contents are used by the counter-compare submodule to generate
events to be sent to the action-qualifier.
• Immediate Load Mode: If immediate load mode is selected (TBCTL[SHADWAMODE] = 1 or
TBCTL[SHADWBMODE] = 1), then a read from or a write to the register will go directly to the active
register.
15.2.2.4.4 Count Mode Timing Waveforms
The counter-compare module can generate compare events in all three count modes:
• Up-count mode: used to generate an asymmetrical PWM waveform.
• Down-count mode: used to generate an asymmetrical PWM waveform.
• Up-down-count mode: used to generate a symmetrical PWM waveform.
To best illustrate the operation of the first three modes, the timing diagrams in Figure 15-19 to Figure 15-
22 show when events are generated and how the EPWMxSYNCI signal interacts.
1642 Pulse-Width Modulation Subsystem (PWMSS) SPRUH73E–October 2011–Revised May 2012
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