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Chapter 15 Pulse-Width Modulation Subsystem (PWMSS).

Chapter 15 Pulse-Width Modulation Subsystem (PWMSS).

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Enhanced PWM (ePWM) Module www.ti.com<br />

CTR_dir<br />

0<br />

4<br />

0<br />

T PWM<br />

1<br />

3<br />

1<br />

2<br />

T PWM<br />

2<br />

2<br />

3<br />

1<br />

3<br />

0<br />

T PWM<br />

4<br />

PRD<br />

4 4<br />

3<br />

3<br />

2<br />

2<br />

1<br />

Up Down Down<br />

Up<br />

<strong>15</strong>.2.2.3.3.1 Time-Base Period Shadow Register<br />

Figure <strong>15</strong>-11. Time-Base Frequency and Period<br />

4<br />

0<br />

1<br />

2<br />

3<br />

1<br />

0<br />

0<br />

1<br />

4<br />

Z<br />

0<br />

2<br />

1<br />

3<br />

3<br />

2<br />

2<br />

T PWM<br />

4<br />

3<br />

1<br />

3<br />

PRD<br />

4<br />

Z<br />

0<br />

2<br />

1<br />

0<br />

For Up Count and Down Count<br />

TPWM = (TBPRD + 1) x TTBCLK FPWM = 1/ (TPWM) For Up and Down Count<br />

T PWM = 2 x TBPRD x T TBCLK<br />

F PWM = 1 / (T PWM)<br />

The time-base period register (TBPRD) has a shadow register. Shadowing allows the register update to<br />

be synchronized with the hardware. The following definitions are used to describe all shadow registers in<br />

the ePWM module:<br />

• Active Register: The active register controls the hardware and is responsible for actions that the<br />

hardware causes or invokes.<br />

• Shadow Register: The shadow register buffers or provides a temporary holding location for the active<br />

register. It has no direct effect on any control hardware. At a strategic point in time the shadow<br />

register's content is transferred to the active register. This prevents corruption or spurious operation<br />

due to the register being asynchronously modified by software.<br />

The memory address of the shadow period register is the same as the active register. Which register is<br />

written to or read from is determined by the TBCTL[PRDLD] bit. This bit enables and disables the TBPRD<br />

shadow register as follows:<br />

• Time-Base Period Shadow Mode: The TBPRD shadow register is enabled when TBCTL[PRDLD] =<br />

0. Reads from and writes to the TBPRD memory address go to the shadow register. The shadow<br />

register contents are transferred to the active register (TBPRD (Active) ← TBPRD (shadow)) when the<br />

time-base counter equals zero (TBCNT = 0000h). By default the TBPRD shadow register is enabled.<br />

• Time-Base Period Immediate Load Mode: If immediate load mode is selected (TBCTL[PRDLD] = 1),<br />

then a read from or a write to the TBPRD memory address goes directly to the active register.<br />

1634 <strong>Pulse</strong>-<strong>Width</strong> <strong>Modulation</strong> <strong>Subsystem</strong> (<strong>PWMSS</strong>) SPRUH73E–October 2011–Revised May 2012<br />

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Copyright © 2011–2012, Texas Instruments Incorporated

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