Fault Diagnostic System for Cascaded H-Bridge Multilevel Inverter ...

FIGURE 3.16. THE 3-D PLOT OF THE COMBINATION PCS FROM GA RESULTS. ............................................... 88
FIGURE 3.17. MULTILAYER FEEDFORWARD NETWORK ARCHITECTURE......................................................... 90
FIGURE 3.18. PROPOSED NEURAL NETWORK ARCHITECTURE. ....................................................................... 90
FIGURE 3.19. A FLOWCHART FOR MULTILAYER FEEDFORWARD TRAINING PARADIGM.................................. 93
FIGURE 4.1. RECONFIGURATION DIAGRAM FOR MLID WITH FIVE SDCS:................................................... 102
FIGURE 4.2. MULTILEVEL CARRIER-BASED SINUSOIDAL PWM WITH 2 KHZ SWITCHING FREQUENCY FOR 5
SDCS MLID SHOWING CARRIER BANDS, MODULATION WAVEFORM, AND INVERTER OUTPUT
WAVEFORM (M A = 0.9/1.0).................................................................................................................. 102
FIGURE 4.3. MULTILEVEL CARRIER-BASED SINUSOIDAL PWM WITH 2 KHZ SWITCHING FREQUENCY FOR 5
SDCS MLID SHOWING CARRIER BANDS, MODULATION WAVEFORM, AND INVERTER OUTPUT
WAVEFORM (M A = 1.2/1.0).................................................................................................................. 103
FIGURE 4.4. COMPENSATED GAIN OF THE MLID OPERATING AT M A > 0.8. .................................................. 104
FIGURE 4.5. RECONFIGURATION EFFECTS AT OVERMODULATION INDEX (A) NORMAL OPERATION M A = 0.9/1.0,
(B) NORMAL OPERATION M A = 1.0/1.0................................................................................................. 107
FIGURE 4.6. TOTAL HARMONIC VOLTAGE DISTORTION AT DIFFERENT MODULATION INDICES UNDER ONE
FAULTY CELL OPERATION WITH THEIR COMPENSATED GAIN. ............................................................. 108
FIGURE 4.7. OUTPUT PHASE VOLTAGES (A) AND LINE VOLTAGES (B) OF MALFUNCTIONING MLID: BYPASSING
CELL 1 ON PHASE B, CELL 1 AND 2 ON PHASE C WITH 2 KHZ SWITCHING FREQUENCY AND 60 HZ
FUNDAMENTAL FREQUENCY............................................................................................................... 109
FIGURE 5.1. FAULT DIAGNOSTIC DIAGRAM FOR 11-LEVEL MLID WITH 5 SDCS......................................... 114
FIGURE 5.2. TRAINING AND TESTING DATA SET DIAGRAM........................................................................... 116
FIGURE 5.3. THE FFT SUBSYSTEM INTERFACED WITH A SIMULINK MODEL................................................. 120
FIGURE 5.4. PCA SUBSYSTEM PERFORMING DATA TRANSFORMATION INTO PCA SPACE. .......................... 121
FIGURE 5.5. SUBSYSTEM OF NEURAL NETWORK CLASSIFICATION................................................................ 123
FIGURE 5.6. SUBSYSTEM OF (A) BINARY DECODER AND (B) RECONFIGURATION METHOD. .......................... 124
FIGURE 5.7. THE FAULT DIAGNOSTIC SYSTEM INTERFACED WITH PSIM PERFORMING POWER CIRCUIT OF A
MLID. ............................................................................................................................................... 125
FIGURE 5.8. EXPERIMENT SETUP. ................................................................................................................ 127
FIGURE 5.9. HARDWARE COMPONENT FOR OPAL RT-LAB CONFIGURATION. ............................................ 127
FIGURE 5.10. THREE-PHASE WYE-CONNECTION STRUCTURE FOR ELECTRIC VEHICLE MOTOR DRIVE........... 128
FIGURE 5.11. 11-LEVEL MLID OPERATING AT NORMAL CONDITION WITH 0.8/1.0 M A. ................................ 129
FIGURE 5.12. 11-LEVEL MLID OPERATING AT REAL OPEN CIRCUIT FAULT AT CELL 3 SWITCH SA+ WITH 0.8/1.0
M A....................................................................................................................................................... 130
FIGURE 5.13. 11-LEVEL MLID OPERATING AT LOSS OF GATE DRIVE FAULT AT CELL 3 SWITCH SA+ WITH
0.8/1.0 M A........................................................................................................................................... 130
FIGURE 5.14. 11-LEVEL MLID OPERATING AT SHORT CIRCUIT FAULT IN LOSS OF SDCS CONDITION AT CELL 3
SWITCH SA+ WITH 0.8/1.0 M A............................................................................................................... 131
FIGURE 5.15. OPEN CIRCUIT FAULTY POWER CELL AT SA+. .......................................................................... 132
FIGURE 5.16. SIMULATION RESULTS OF THE OPEN CIRCUIT FAULT AT SA+, CELL 2 OF THE MLID DURING
OPERATED AT M A = 0.8/1.0 :( A) OUTPUT VOLTAGE PHASE A, AND (B) MAGNIFIED VIEW ON CURRENT.
........................................................................................................................................................... 133
FIGURE 5.17. EXPERIMENTAL RESULTS OF THE OPEN CIRCUIT FAULT AT SA+, CELL 2 OF THE MLID AT M A =
0.8/1.0 (A) OUTPUT PHASE VOLTAGES AND LINE CURRENT (I A), (B) LINE CURRENT (I A) SHOWING
STARTING CURRENT, FAULT INTERVAL, AND FAULT CLEAR. .............................................................. 134
FIGURE 5.18. EXPERIMENTAL RESULTS OF THE LOSS OF GATE DRIVE FAULT AT SA+, CELL 2 OF THE MLID AT
M A = 0.8/1.0 (A) SIMULATION RESULT OF LINE CURRENT (I A), (B) EXPERIMENT RESULT LINE CURRENT
(I A) SHOWING STARTING CURRENT, FAULT INTERVAL, AND FAULT CLEAR.......................................... 136
FIGURE 5.19. EXPERIMENTAL RESULTS OF LINE CURRENT (I A) ON OPEN CIRCUIT FAULTS SHOWING BOTH LOSS
OF GATE DRIVE AND REAL OPEN CIRCUIT CASES AT SA+, CELL 2 OF THE MLID AT M A = 0.8/1.0. ........ 137
FIGURE 5.20. SHORT CIRCUIT FAULTY POWER CELL AT SA+. ........................................................................ 138
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