Flash - Smithsonian - The Chip Collection

FLASH
The item of most interest to us here was the repetitiveness of the cell designs employed. Both Intel
and AMD at least use a cell design that hasn't changed for years and they keep increasing memory
size simply by reducing design rules and increasing die size. It now has gotten to the point of
stacking multiple dice in one package (Intel 32 Mb)! Not only that but the alternate designs don't
seem to offer much promise of any breakthroughs either. So far, at least Flash cell size has not
surpassed DRAM on any products we've seen, although the pressure to do so should be there
based on the above. Also, the stacked cell used by AMD and Intel is inherently smaller than a
DRAM cell in the sense that is uses fewer elements (1/2 contract, 1 transistor, 1/2 diffusion run)
and it is structurally less complex as well.
The reason that these cells are remaining relatively large must thus be attributed to the electrical
requirements demanded by the structures. This of course raises the question of whether Flash can
ever catch up with DRAM in capacity and present indications are that if ever, it certainly won't be
soon.
3 - 1

FLASH
MEMORIES
HORIZONTAL DIMENSIONS (DESIGN RULES)
INTEL
E28F016SA
16/32Mb 1994
Die size 10.6 x 11.6 mm
(124 mm 2 )
AMD
AM29F016-120EC
16Mb 9436
9 x 9.7 mm
(87 mm 2 )
AMD
AMD29F040-90EC
4Mb 9406
6.6 x 7.5 mm
(50 mm 2 )
*Polycide †Physical gate length measured TABLE 3 - 1
ATMEL
AT29C040-12TC
4Mb 9411
7.8 x 13.7 mm
(107 mm 2 )
Min M2 width 0.8μm 0.75μm 1.3μm 3.4μm NA
Min M1 width 1.0μm 0.9μm 1.0μm 2.2μm 2.0μm
Min M2 space 0.9μm 1.0μm 1.2μm 1.8μm NA
Min M1 space 0.6μm 0.8μm 1.0μm 1.8μm 1.0μm
Min via (M2 to M1) 0.85μm 0.9μm 0.8μm 1.7μm NA
Min cntct (to Si) 0.7μm 0.6μm 0.65μm 1.2μm 1.2μm
SST
NH29EE010-150
1Mb 9417
4.7 x 6.1 mm
(29 mm 2 )
Min Poly 2 0.7μm * 0.55μm * 0.75μm * 0.7μm 0.95μm
Min Poly 1 0.8μm 0.55μm 0.7μm 2.6μm 1.2μm
Min gate - (N)† 0.8μm 0.6μm 0.7μm 0.8μm 0.95μm
Min gate - (P)† 0.7μm 0.65μm 0.85μm 1.5μm 1.2μm
Cell pitch 1.65 x 2μm 1.65 x 1.65μm 2.4 x 2.5μm 2.6 x 6.4μm 3 x 3.5μm
Cell area 3.3μm 2 2.7μm 2 6.0μm 2 16.6μm 2 10.5μm 2

FLASH
MEMORIES
* Polycide TABLE 3 - 2
VERTICAL DIMENSIONS
INTEL
E28F016SA
16/32Mb 1994
AMD
AM29F016-120EC
16Mb 9436
AMD
AMD29F040-90EC
4Mb 9406
ATMEL
AT29C040-12TC
4Mb 9411
SST
NH29EE010-150
1Mb 9417
Final passivation 3.4μm 1.2μm 1.5μm 1.1μm 1.0μm
Metal 2 1.1μm 0.75μm 1.0μm 1.0μm NA
Metal 1 0.5μm 0.7μm 0.5μm 0.85μm 1.3μm
Intermetal dielectric 0.55μm 0.45μm 0.4μm 0.45μm NA
Poly 2 0.3μm * 0.4μm * 0.4μm * 0.45μm 0.3μm
Poly 1 0.1μm 0.1μm 0.15μm 0.2μm 0.05μm
Recessed oxide 0.55μm 0.3μm 0.4μm 0.8μm 0.7μm
N-well 2μm 5μm 5μm 4.5μm 5.5μm
P-well 1.0μm (?) 2μm (?) 3μm (?) 2.5μm None
Epi 6.5μm (P) None None None None

FLASH
MEMORIES
INTEL
E28F016SA
16/32Mb 1994
DIE MATERIALS
AMD
AM29F016-120EC
16Mb 9436
Final passivation Glass on nitride Nitride on SOG
on glass
Metal 2 Titanium-nitride
Aluminum
Titanium
Aluminum
Titanium-nitride
Titanium
TABLE 3 - 3
AMD
AMD29F040-90EC
4Mb 9406
Nitride on SOG
on glass
Aluminum
Titanium
ATMEL
AT29C040-12TC
4Mb 9411
SST
NH29EE010-150
1Mb 9417
Nitride on glass Nitride on glass
Aluminum NA
Contact Plugs Tungsten Tungsten Tungsten NA
Metal 1 Titanium-nitride
Aluminum
Titanium-nitride
Titanium
Aluminum
Titanium-nitride
Titanium
Aluminum
Titanium-nitride
Titanium
Titanium-nitride
Titanium
Aluminum
Titanium-nitride
Titanium
Interpoly dielectric ONO ONO ONO Oxide Oxide
Reflow glass BPSG BPSG BPSG BPSG BPSG
Polycide metal Tungsten Tungsten Tungsten NA NA
Titanium-nitride
Aluminum
Titanium-nitride
Titanium

TECHNOLOGY DESCRIPTION
INTEL E28F016SA/DD28F032SA
16 AND 32 Mbit FLASH MEMORY
Introduction Ref. report SUB 9404-02
These parts (both 16 Mb and 32 Mb) were packaged in 56-pin, gull-wing lead, thin small-outline
packages (TSOPs). As usual, ICE could not decipher Intel's date code, but we believe parts were
manufactured first (16 M) and third (32 M) quarter of 1994. The 16 Mb devices were fully
functional production parts, but the 32 Mb units were engineering samples (ES). The reason both
part types are included in this analysis is that the 32 Mb part is essentially a packaging method for
two 16 Mb dice. Die technology is the same. The parts operate from a 3.3V or 5V supply
voltage.
See tables for specific dimensions and materials identification and see figures for examples of
physical structures.
Unusual/Unique Features
Quality
- Complex process.
- Deep, short birdsbeak, recessed-oxide isolation.
- New assembly (32 Mb).
Quality of process implementation was normal. Metal 2 step coverage at vias showed significant
thinning. Also, the polycide word lines showed loss of the metal silicide at every step over poly 1.
These same conditions were found previously on the 8 Mb devices and apparently have not
resulted in any real reliability concerns.
In the area of layer patterning, both etch definition and control (depth) were good.
Alignment/registration was also good.
Packaging was very good. The 32 Mb package especially was very impressive.
3 - 2

Technology
These devices were made by a twin (multiple)-well CMOS process, employing a P-epi on a P
substrate, and the process remains very similar to the 8 Mb devices (see 1994 report). In fact,
except for some shrinking of feature sizes and a very few process enhancements both the 16 and
32 Mb parts are 8 Mb die designs. The 16 Mb simply combines two 8 Mb designs on one die and
the 32 Mb combines two 16 Mb die in one package. Two levels of metal, one level of polycide
(tungsten on polysilicon) and one level of polysilicon were used. A deep, short birdsbeak
recessed-oxide isolation was employed.
The memory array used dual poly, "stacked-gate" memory cells. Polycide 2 was used for the
program/word lines, and poly 1 for the floating gates in the cell array. Everywhere else on the die
polycide 2 was used for gates except at a few of the special "UPROM" gates where poly 1 was
used as the connected gates with a floating poly 2 shield overtop. All gates used oxide sidewall
spacers that were left in place. At least three different gate oxides were used in addition to the
interpoly dielectric (ONO).
The final passivation consisted of a thick multilayer glass over an oxynitride and was not
planarized.
Both metal levels consisted of aluminum defined by dry etch techniques and both had titaniumnitride
caps. The metal 2 barrier was a titanium while the metal 1 barrier was a titanium-nitride on
titanium.
Tungsten plugs were used at contacts to silicon while standard vias were employed between M2
and M1. The use of tungsten plugs is new (not present on previous 8 Mb parts) and as in the
P54C PENTIUM microprocessor, plug height control was very good.
No buried contacts were used. Metal 2 contacted metal 1, and metal 1 contacted diffusions,
polycide, and poly 1 at UPROM gates.
Planarization of the intermetal dielectric was by deposited glass and some minor planarizing etch.
No evidence of a spin-on-glass (SOG) was found. The dielectric under metal 1 was planarized by
a reflow process. Chemical-mechanical planarization (CMP) was not used.
Numerous implants were employed including different (deep) source implants in the array. No
salicide source/drain treatment was present.
As mentioned, there are a number of different gate oxides present (at least three) plus two different
thin interpoly dielectrics.
3 - 3

The most unique features of these products were the deep, short birdsbeak, recessed-oxide
isolation, the two poly "UPROM" type gates used at some locations in the peripheral circuits, and
of course, the packaging for the 32 Mb configuration.
Overall minimum feature measured anywhere on these dice was the 0.7 micron polycide width
and contact diameter.
Minimum gate lengths measured were 0.75 micron for both N- and P-channel gates.
Memory Cell Structures
As mentioned, these parts used the "stacked" dual-gate cell design.
The floating gates were of poly 1 on a thin tunnel oxide. The word lines were made of polycide 2
and the interpoly dielectric was an ONO.
Metal 1 provided the bit lines.
Transistor sources had a deep phosphorus diffusion to support the programming voltage required.
The shortened birdsbeak local oxide is especially effective in the array where it reduces pitch in the
long direction of the floating gates to 1.65 microns. Along with this, a significant reduction in
wordline pitch to 1.5 micron minimum (2.0 microns average) was implemented. This 1.5 micron
pitch leaves a separation of only 0.2 micron between neighboring transistor sidewalls (the same as
on the AMD device). Overall cell size was thus reduced to 3.3 microns 2 .
Packaging/Assembly
A. 16 Mb
Devices were packaged in 56-pin, gull-wing lead, thin small outline packages (TSOPs). Pins 29
and 30 were not connected. Die attach was by a silver epoxy to an offset and dimpled
header/paddle. Standard thermocompression wirebonds using gold wire were used. Internally the
iron-nickel leadframe was spot-plated with silver.
No evidence of a die coat was found.
B. 32 Mb
This "dual die" package was practically identical to that of the 16 M device (including pins 29 and
30 no connects) except that the header/paddle was not vertically offset from center and did not have
dimples.
3 - 4

A barely visible seam in the plastic, level with one face of the paddle, may indicate a two-step
molding process i.e., assemble and mold one-half, then assemble and mold the second side.
Assembly was beautifully done and results in a very clean looking structure. Quality appeared to
be excellent.
3 - 5

The Intel E28F016SA Flash Memory circuit die. Mag. 17x.
®

OXIDE
POLYCIDE GATE
N+ S/D
W PLUG
Intel 28F016SA. SEM views illustrating device structures.
section,
Mag. 9000x
section,
Mag. 40,000x
section,
Mag. 40,000x
®

LEADFRAME
PIN 1
Mag. 5x
Mag. 28x
PADDLE
16MB DIE
16MB DIE
Intel DDF032SA (32Mb Flash). X-ray and section view of package construction.
®

Mag. 25x
Mag. 50x
Intel DDF032SA (32Mb Flash). Internal assembly.
®

TECHNOLOGY DESCRIPTION
AMD Am29F016-120EC
16 Mbit FLASH MEMORY
Introduction Ref. report SCA 9412-378
This part was packaged in a 48-pin, gull-wing lead, thin small-outline plastic package (TSOP)
date coded week 36 of 1994 and it was an engineering sample provided by AMD, and apparently
fabbed by AMD. Memory organization was 2 MBytes of 8 bits in 32 sectors of 64 K bytes, and
the design used a NOR gate approach. These parts operate from a standard 5V only power
source.
See tables for specific dimensions and materials identification and see figures for examples of
physical structures.
Unusual/Unique Features
Quality
- Small die size (for the 16 M capacity).
- Unusual local oxide birdsbeaks.
- Planarized final passivation.
Quality of process implementation was normal. No items of real concern were found.
In the area of layer patterning, etch definition was good but control (depth) was poor at contact etch
resulting in overetch into the silicon.
Alignment/registration was good at all layers.
Packaging/assembly was also of normal quality workmanship.
3 - 6

Technology
This device was made by a twin (multiple)-well CMOS process, employing a P substrate (no epi).
Two levels of metal, one level of polycide (polysilicon on tungsten on polysilicon) and one level of
polysilicon were used. A fairly deep, recessed-oxide isolation was employed.
The memory array used dual poly, "stacked-gate" memory cells. Polycide 2 was used for the
program/word lines, and poly 1 for the floating gates in the cell array. Everywhere else on the die
polycide 2 was used for gates. All gates used oxide sidewall spacers that were left in place.
Standard vias were used for vertical interconnect between M2 and M1. Tungsten plugs were
employed for M1 contacts to silicon. No salicide source/drain treatment was present.
No buried contacts were used. Metal 2 contacted metal 1, and metal 1 contacted diffusions and
polycide.
Final passivation consisted of two layers of nitride separated by a spin-on-glass (SOG). This is
unusual and it is not known whether the SOG is used for planarization or as a stress relief layer,
but stress relief would appear to make more sense. Both metal levels consisted of aluminum
defined by dry etch techniques, and both had titanium-nitride caps. The metal 2 barrier was a
titanium while the metal 1 barrier was a titanium on titanium-nitride on titanium sandwich.
Planarization of the intermetal dielectric was by deposited glass and planarizing etch and used a
spin-on-glass (SOG). No evidence of chemical-mechanical planarization (CMP) was found. The
dielectric under metal 1 was planarized by a reflow process.
The local oxide isolation was somewhat unique. It was thick and etched back severely at
birdsbeaks to the point where these were level with the substrate. This seemed fairly ineffective in
shortening the birdsbeak areas however, since below the substrate surface level they had a normal
shape.
Two gate oxides (one for peripheral and one under floating gates) and one oxide-nitride-oxide
(ONO) were present.
Overall minimum feature measured anywhere on these dice was the 0.55 micron polycide width
and contact diameter.
Minimum gate lengths measured were 0.6 micron N-channel and 0.65 micron for P-channel.
Memory Cell Structures
As mentioned, these parts used the "stacked" dual-gate cell design.
3 - 7

The floating gates were of poly 1 on a thin tunnel oxide. The word lines were made of polycide 2
and the interpoly dielectric was an ONO.
Metal 1 provided the bit lines.
Transistor sources had a deep diffusion to support the programming voltage required.
In these cells, minimum wordline pitch was 1.3 micron, thus like the Intel device, leaving a space
between sidewalls of 0.2 micron. Average pitch was 1.65 x 1.65 micron resulting in a very small
2.7 microns 2 cell size.
Packaging/Assembly
Devices were packaged in standard 48-pin, gull-wing lead, thin small outline plastic packages
(TSOPs). Pins 1, 2, 23, 24, 25, 26, 45, 47 and 48 were not connected. Die attach was by a silver
epoxy on a dimpled header/paddle. Standard thermocompression wirebonds using gold wire were
used.
No evidence of a die coat was found.
3 - 8

Portion ofthe AMD Am29F016 Flash Memory circuit die. Mag. 23x.
®

Remaining portion ofthe AMD Am29F016 Flash Memory circuit die. Mag. 23x.
®

W SILICIDE
POLYCIDE GATE
AMD Am29F016. SEM views illustrating device structures.
section,
Mag. 13,000x
section,
Mag. 40,000x
section (glass etch),
Mag. 45,000x
®

BIT
CONTACT
FLOATING
GATE
OXIDE
section, Mag. 25,000x
section, Mag. 50,000x
POLYCIDE (WORD)
METAL 2
AMD Am29F016. SEM views of the memory cell area.
®

TECHNOLOGY DESCRIPTION
AMD Am29F040-90EC
4 Mbit FLASH MEMORY
Introduction Ref. report SCA 9407-339
These parts were packaged in 32-pin, gull-wing lead, thin small-outline plastic packages
(TSOPs). Parts were dated coded week 6 of 1994 and were fully functional production samples.
Memory organization was 512 KBytes of 8 bits in 8 sectors of 64 K bytes, and the design used a
NOR gate approach. They operate from a standard 5V power source.
See tables for specific dimensions and materials identification and see figures for examples of
physical structures.
Unusual/Unique Features
Quality
- Minimal process complexity.
- Three layer polycide.
- Planarized final passivation.
Quality of process implementation was normal. No items of real concern were found.
In the area of layer patterning, etch definition was good but control (depth) was not at contact etch,
resulting in overetch into the silicon.
Alignment/registration was good.
Packaging/assembly was also of normal quality workmanship.
Technology
These devices were made by a twin (multiple)-well CMOS process, employing a P substrate (no
epi). Two levels of metal, one level of polycide (polysilicon on tungsten on polysilicon) and one
level of standard polysilicon were used. A normal recessed-oxide isolation was employed. The
memory array used dual poly, "stacked-gate" memory cells. Polycide 2 was used for the word
lines, and poly 1 for the floating gates in the cell array. Everywhere else on the die polycide 2 was
3 - 9

used for gates. It appeared that only N-channel gates had used sidewall spacers. These had been
removed.
Standard vias were used for vertical interconnect between M2 and M1. Tungsten plugs were
employed for M1 contacts to silicon. No salicide source/drain treatment was present.
No buried contacts were used. Metal 2 contacted metal 1, and metal 1 contacted diffusions and
polycide.
Both metal levels consisted of aluminum defined by dry etch techniques and neither had caps.
Metal 2 had a barrier of titanium while the metal 1 barrier was a titanium-nitride on titanium.
As mentioned, the final passivation was planarized, using a spin-on-glass (SOG) to do so. As on
the 16 M part, the purpose may be more for stress relief than planarization. Planarization of the
intermetal dielectric was by deposited glass and planarizing etch and also used a spin-on-glass. No
evidence of chemical-mechanical planarization (CMP) was found. The dielectric under metal 1
was planarized by a reflow process. The local oxide isolation was of normal thickness and left
rather long birdsbeaks in the array area (under poly 1).
Two gate oxides (one for peripheral and one under floating gates) and one oxide-nitride-oxide
(ONO) were present.
Overall minimum feature measured anywhere on these dice was the 0.55 micron polycide width
and contact diameter.
Minimum gate lengths measured were 0.7 micron for N-channel and 0.85 micron for P-channel.
Memory Cell Structures
As mentioned, these parts used the standard "stacked" dual-gate cell design, with no unusual
features.
The floating gates were of poly 1 on a thin tunnel oxide. The word lines were made of polycide 2
and the interpoly dielectric was an ONO.
Metal 1 provided the bit lines.
Transistor sources had a deep diffusion to support the programming voltage required.
The cell size was measured to be 6 microns 2 .
3 - 10

Packaging/Assembly
Devices were packaged in standard 32-pin, gull-wing lead, thin small-outline plastic packages
(TSOPs). All pins were connected. Die attach was by a silver epoxy on a dimpled header/paddle.
Standard thermocompression wirebonds using gold wire were used.
No evidence of a die coat was found.
3 - 11

The AMD Am29F040-90EC Flash Memory circuit die. Mag. 27x.
®

N+ S/D
SOG
section, Mag. 8400x
section, Mag. 12,500x
AMD Am29F040-90EC. SEM views illustrating device structures.
®

POLY 1
FLOATING GATE
PASSIVATION
SILICIDE
N+ S/D
POLYCIDE
WORD LINE
AMD Am29F040-90EC. SEM views of memory cell structures.
section,
Mag. 8400x
section (glass etch),
Mag. 47,500x
section,
Mag. 50,000x
®

TECHNOLOGY DESCRIPTION
ATMEL AT29C040
4 Mbit Flash EPROM (PEROM)
Introduction Ref. report SCA 9407-342
These parts were packaged in 40-pin, thin small outline plastic packages (TSOP) date coded week
11 of 1994. All samples were marked ES (engineering samples). Memory organization was
512 Kwords x 8 bits. These are 5V only devices and they were the latest version of this product
type from Atmel evaluated by ICE.
See tables for specific dimensions and materials identification and see figures for examples of
physical structures.
Unusual/Unique Features
Quality
- These parts employ Atmel's standard EEPROM cell design.
- Stacked M2 vias over M1 contacts.
Quality of process implementation was normal. Metal 1 thinning was significant at some contacts,
but did not appear out of control.
In the area of layer patterning, both etch definition and control (depth) were good.
Alignment/registration was good.
Packaging/assembly quality was good but included the unusual feature of having five wires
connected to pin 30 (GND).
Technology
These devices were made by a twin (multiple)-well CMOS process, employing a P substrate. No
evidence of an epi layer was found. Two levels of metal and two levels of polysilicon (no
polycides) were used. A normal recessed-oxide isolation was employed.
Both metal levels consisted of aluminum defined by dry etch techniques. Metal 2 used no cap or
barrier layers but metal 1 had a titanium-nitride on titanium cap and barrier.
3 - 12

No plugs were present at vias or contacts and buried contacts were not used. Metal 2 contacted
metal 1, and metal 1 contacted diffusions and poly 2. In some cases, metal 2 contacted metal 1
directly over a metal 1 to diffusion contact (i.e., via over contact). This is very unusual.
Planarization of the intermetal dielectric was by deposited glass and planarizing etch. No evidence
of a spin-on-glass (SOG) was found. The dielectric under metal 1 was planarized by a reflow
process which was done after contact cuts.
Poly 2 was used for all gates. Although no evidence of an LDD process was found (no signs of
any sidewall spacers) the select gates in the cell array were short enough that sidewall spacers must
have been used. We thus assume they were of photoresist and were removed after implantation.
No silicide metallization treatment was used on diffusions or poly.
No evidence of unusual gate oxide or dielectric materials was found.
Overall minimum feature measured anywhere on these dice was the 0.8 micron poly 2.
Minimum physical gate lengths measured were 0.8 micron for N-channel and 1.5 micron for P-channel.
Memory Cell Structures
These parts used a type of "stacked" dual-gate cell design that is a smaller version of Atmel's
standard EEPROM cell.
The floating gates were of poly 1 on a thin oxide that had a small window of very thin "tunnel"
oxide. The program and word lines were made of poly 2 and the interpoly dielectric was an oxide.
Metal 1 provided the bit lines.
The cell size was measured to be 16.6 microns 2 which is very large for a "Flash" memory, but
small for this type of EEPROM design.
Packaging/Assembly
Devices were packaged in standard 40-pin plastic TSOPs. Pins 1, 2, 19, 20, 21, 22, 39 and 40
were not connected. Pin 30 (GND) had four wires connecting to the die surface and one to the
header/paddle. Internally the iron-nickel leadframe was spot-plated with silver while external leads
were plated with lead-tin solder. Die attach was by a silver-epoxy and standard thermosonic
wirebonds using gold wire were used.
No evidence of a die coat was found.
3 - 13

The Atmel AT29C040-12TC Flash Memory circuit die. Mag. 16x.
PIN 3
®

N+
POLY 2 (WORD)
POLY 2
(PGM)
N+
BIT Q1 Q2
TUNNEL OXIDE
WINDOW
GND
INTERMEDIATE
GLASS
POLY 1
N+
(GND)
Atmel AT29C040. SEM views of device structures.
section,
Mag. 7000x
Mag. 6800x, 0°
section,
Mag. 10,000x
®

TECHNOLOGY DESCRIPTION
SST NH29EE010-150
1 Mbit Flash Memory
Introduction Ref. report SCA 9412-380
These parts were packaged in 32-pin, Plastic Leaded Chip Carriers (PLCCs) date coded week 17
of 1994. All were fully functional production parts. Memory organization was 128 Kwords x 8
bits. These are standard 5V only flash memories made by a foundry (possibly Sanyo) for SST.
They were the first flash memory parts from Silicon Storage Technology evaluated by ICE.
See tables for specific dimensions and materials identification and see figures for examples of
physical structures.
Unusual/Unique Features
Quality
- Unique memory cell design.
- Simple (low cost) process.
Quality of process implementation was normal to poor mainly due to apparent microcracks at the
bottom periphery of some metal contacts. Significant metal thinning was also present at some
locations.
In the area of layer patterning, both etch control (depth) and definition were good.
Alignment/registration was good at all layers.
Packaging/assembly quality was normal although porosity of the plastic material was greater than
we normally see. This is not considered serious but could certainly be improved.
Technology
These devices were made by an N-well CMOS process, employing a P substrate. No evidence of
an epi layer was found. One level of metal and two levels of polysilicon were used. A normal
recessed-oxide isolation was employed. The memory cells use a two poly "split gate" design.
Metal consisted of aluminum patterned by a standard dry etch. It used titanium-nitride cap and
barrier layers. A titanium adhesion layer was employed as well.
3 - 14

Final passivation consisted of nitride on glass and was not planarized. Planarization under the
metal was by a standard BPSG reflow glass, reflowed after contact cuts to slope these edges.
Metal contacts were standard. No plugs were used and no buried contacts (poly to diffusion)
were present.
Poly 2 was used for program (word) lines in the memory array and for all standard gates on the
die. All gates used oxide sidewall spacers that were left in place. No silicide metallization
treatment of the diffusions or poly was present.
The implants included a deep source implant in the array to support the programming voltage.
No evidence of unusual gate oxide or dielectric materials was found.
Overall minimum feature measured anywhere on these dice were the 0.85 micron poly 1 floating
gates.
Minimum physical gate lengths in the periphery measured 0.95 micron for N-channel and 1.2
micron for P-channel. These N-channel dimensions are obviously not very aggressive making
future "shrinks" highly likely.
Memory Cell Structures
These parts used a unique split gate memory cell design in which the erase/word lines were made
of poly 2 and placed partly overtop and beside the floating gates (see figures). The interpoly
dielectric was an oxide.
The floating gates were of very thin poly 1 and metal provided the bit lines.
Programming of the floating gates uses the standard hot electron injection method, while erase
employs Fowler-Nordheim tunneling between the edge of the floating gate and the poly 2 word
line.
Transistor sources had deep diffusions to support the programming voltage required.
The cell size was measured to be rather large 10.5 microns 2 .
3 - 15

Packaging/Assembly
Devices were packaged in standard 32-pin, J-lead PLCCs. All pins were connected. Internally the
copper leadframe was spot-plated with silver, while external leads were plated with lead-tin solder.
Die attach was by a silver epoxy, and standard thermosonic wirebonds using gold wire were used.
No evidence of a die coat was found.
3 - 16

The SST SH29EE010-150-4CF Flash EEPROM circuit die. Mag. 35x.
®

S/D
POLY 2
SST SH29EE010-150-4CF. SEM views of device structures.
section,
Mag. 5000x
section,
Mag. 10,000x
section,
Mag. 30,000x
®

N+
BIT
N+
BIT
POLY 2 (WORD)
POLY 1
OXIDE
POLY 2
(WORD)
Q1
SOURCE
N+
POLY 1
SST SH29EE010-150-4CF. SEM details of the cell area.
Q2
N+ DIFFUSION
(SOURCE)
Mag. 12,000x, 60°
Mag. 10,000x, 0°
section,
Mag. 20,000x
®