SRAMs - Smithsonian - The Chip Collection

SRAMs 

These devices seem to have acquired a fairly high dose of technology stagnation 

although companies in Taiwan are pushing gate lengths down to 0.3 micron. 

Only two out of the five selections for this year used TFT pullups. It seems to be 

safe to say the TFT revolution fizzled out before it got really started. 

Cell sizes appear to be stabilizing between ten and twenty microns. The wide 

organizations (x32) are the most significant changes we saw in 1996. 

2-1 

Integrated Circuit Engineering Corporation


Die size 

Min. M2 width/space 

Min. M1 width/space 

Min. via (Met. to Met) 

Min contact (Met. to Si) 

Min. Poly 4 

Min. Poly 3 

Min. Poly 2 

Min. Poly 1 

Min. gate-(N)† 

Min. gate-(P)† 

Cell pitch 

Cell area 

* Polycide + Plugs † Physical gate length 

HORIZONTAL DIMENSIONS (DESIGN RULES) 

UMC 

UM61L3264F-7 

2Mb (x32) 

9631 

6.1 x 6.7mm 

(41mm2) 

0.6µm/0.6µm 

0.6µm/0.6µm 

0.5µm 

0.5µm 

NA 

NA 

0.6µm 

0.3µm* 

0.3µm 

0.4µm 

2.5µm x 4.5µm 

11.25µm2 Tm TECH 

T32L3232A-7Q 

1Mb (x32) 

9530 

5.9 x 6.0mm 

(35mm2) 

0.75µm/0.75µm 

0.85µm/0.75µm 

0.7µm 

0.6µm + 

NA 

NA 

0.4µm 

0.35µm* 

0.35µm 

0.35µm 

4.15µm x 4.65µm 

19µm2 Table 2-1 

WINBOND 

W25P010AF-8 

1Mb (x32) 

9612 

5.0 x 6.5mm 

(32.5mm2) 

0.95µm/0.85µm 

0.65µm/0.85µm 

0.75µm 

0.8µm 

NA 

NA 

0.7µm 

0.45µm 

0.45µm 

0.55µm 

4.0µm x 4.7µm 

19.6µm2 SAMSUNG 

KM684000ALG-7 

4Mb (x8) 

9606 

6.6 x 11.8mm 

(78mm2) 

1.4µm/1.4µm 

0.6µm/0.8µm 

1.3µm 

0.85µm 

0.4µm 

0.8µm 

0.35µm* 

0.65µm 

0.65µm 

0.8µm 

2.6µm x 4.5µm 

11.7µm2 SONY 

CXK5B16120J-12 

1Mb (x16) 

9604 

5.6 x 10.6mm 

(59mm2) 

2.0µm/2.9µm 

0.6µm/1.0µm 

1.6µm 

0.7µm 

0.4µm 

0.7µm 

0.5µm* 

0.5µm* 

0.5µm 

0.55µm 

3.7µm x 5.4µm 

20µm2 Integrated Circuit Engineering Corporation


Die Coat 

Final passivation 

Metal 2 

Metal 1 

Intermetal dielectric 

Poly 4 

Poly 3 

Poly 2 

Poly 1 

Recessed oxide 

N-well 

P-well 

UMC 

UM61L3264F-7 

2Mb (x32) 

9631 

None 

1.0µm 

1.0µm 

0.75µm 

1.2µm 

NA 

NA 

0.015µm 

0.3µm* 

0.3µm 

NA 

3.5µm 

* Polycide ❶ Could not delineate. ❷P-well inside N-well in array area. 

VERTICAL DIMENSIONS 

Tm TECH 

T32L3232A-7Q 

1Mb (x32) 

9530 

None 

0.75µm 

0.95µm 

0.6µm 

0.65µm 

NA 

NA 

0.04µm 

0.25µm* 

0.4µm 

NA 

3µm 

None 

0.85µm 

0.9µm 

0.65µm 

0.5µm 

NA 

NA 

0.08µm 

0.3µm 

0.4µm 

3.5µm 

NA 

Table 2-2 

WINBOND 

W25P010AF-8 

1Mb (x32) 

9612 

SAMSUNG 

KM684000ALG-7 

4Mb (x8) 

9606 

9.5µm 

0.6µm 

0.9µm 

0.9µm 

0.85µm 

0.02µm 

0.1µm 

0.2µm* 

0.15µm 

0.35µm 

6µm 

?❶3µm❷ 

SONY 

CXK5B16120J-12 

1Mb (x16) 

9604 

15µm 

0.9µm 

1.1µm 

0.45µm 

0.5µm 

0.03µm 

0.04µm 

0.09µm* 

0.15µm* 

0.25µm 

2µm 

?❶ 



Final passivation 

Metal 2 

Metal 1 

Plugs 

Intermetal dielectric 

Pre-metal glass 

Polycide metal 

Die coat 

UMC 

UM61L3264F-7 

2Mb (x32) 

9631 

Nitride on glass 

Titanium-Nitride 

Aluminum 

Titanium 


Aluminum 


Titanium 

NA 

glass/SOG/glass 

BPSG 

Tungsten 

NA 

DIE MATERIALS 

Tm TECH 

T32L3232A-7Q 

1Mb (x32) 

9530 



Aluminum 

Titanium 


Aluminum 


Titanium 

Tungsten 


BPSG 

Tungsten 

NA 

Table 2-3 

WINBOND 

W25P010AF-8 

1Mb (x32) 

9612 



Aluminum 

Titanium 


Aluminum 


Titanium 

NA 


BPSG 

NA 

NA 

SAMSUNG 

KM684000ALG-7 

4Mb (x8) 

9606 


Aluminum 


Aluminum 


Titanium 

NA 


BPSG 

Tungsten 

Polyimide 

SONY 

CXK5B16120J-12 

1Mb (x16) 

9604 

Nitride 

Aluminum 

Titanium 


Aluminum 


Titanium 

NA 


BPSG 

Tungsten 

Polyimide 


UMC UM61L3264F-7 

TECHNOLOGY DESCRIPTION 


Synchronous 2Mbit (64K x 32) CMOS SRAM 

Introduction Ref. report SCA 9609-511 

These parts were packaged in 100-pin Quad Flat Packs (QFPs) with gull-wing leads. They were 

fully functional production devices organized in a 64K word x 32-bit design and provide synchronous 

operation. The date code was 9631 (week 31 of 1996). 

See tables for specific dimensions and materials identification and see figures for examples of 

physical structures. 

Important/Unique Features 

– Most aggressive design rules (smallest cell size seen in 1996)! 

– Relatively uncomplicated process. 

Quality 

Quality of the process implementation was very good. No areas of concern were found anywhere. 

In the area of layer patterning, etch definition and control were both good. 

Alignment and registration were also good. 

Technology 

These devices were manufactured by a P-well, selective oxidation CMOS process on an N substrate 

(no epi). They employ two levels of metal and two levels of poly. 

Passivation consisted of a layer of nitride over silicon-dioxide. 

Integrated Circuit Engineering Corporation 

The two levels of metal were defined by standard dry-etch techniques. Metal 2 consisted of 

aluminum with a titanium-nitride cap and titanium barrier. Metal 1 also employed a titaniumnitride 

cap and barrier and a thin titanium adhesion layer under the barrier. 

2-2


Aluminum filled standard style vias were used for vertical interconnect between M2 and M1, 

while tungsten plugs were used at contacts between M1 and silicon. Since via holes were of 

very small diameter and the aluminum of metal 2 was quite thick, we could not determine with 

certainly whether an aluminum reflow was used or if vias were simply filled during the deposition 

process. 

The tungsten plugs all used liners under the tungsten only (none between the tungsten and the 

M1 aluminum). 

Intermetal dielectric between metal 2 and metal 1 consisted of two layers of glass with a spinon-glass 

(SOG) between for planarization. The SOG had been subjected to an etchback. 

Pre-metal dielectric was a single layer of reflow glass (BPSG) over densified oxides. This layer 

was reflowed prior to contact cuts. 

Two layers of polysilicon were used. Poly 2 was only used in the memory array. Polycide 1 

(poly 1 and tungsten silicide) was used to form all gates and fuses on the die. No unusual 

structures were noted. 

Oxide sidewall spacers were used on the gates and were left in place. Buried contacts were 

only used in the cell array (see below). 

No evidence of unusual gate oxides or other dielectrics was found. Standard LOCOS 

isolation was employed and well implemented. No step was present and no other signs of twinwells 

was found. 

Polycide 1 redundancy fuses were present. Passivation and oxide were cleared over the fuse 

locations. No blown fuses were noted. 

Standard source/drain implants were used (not silicided) and we found no evidence of anything 

but the single type P-wells. 

Memory Cell Structures 


Memory cells consisted of a standard 4T NMOS SRAM cell design. Polycide 1 formed word 

lines, select and storage gates. Metal 2 distributed GND and metal 1 formed the bit lines. 

2-3


Selectively doped poly 2 formed the pull-up resistors and distributed Vcc and was used for contact 

pads at bit contacts. The SRAM cell size was 11.25 microns2 , the smallest cell size seen in 

1996! Gate length of the select transistors in the cell was 0.55 micron. 

Overall minimum feature size measured anywhere on these dice was the 0.3 micron poly used 

for some N-channel gates. 

Packaging/Assembly 

As mentioned, these parts were packaged in 100-pin Quad Flat Packs (QFPs) with gull-wing 

leads date coded 9631 (week 31 of 1996) 

The die was mounted to the paddle with silver-epoxy die attach. Wirebond pads on the die had 

a pitch of 125 microns with 20 micron spacing. Pads were 105 microns wide with a 100 

micron windows. 

No die coat was used on these devices. 

2-4 



Whole die photograph of the UMC UM61L3264F-7. Mag. 26x. 



PASSIVATION 2 

PASSIVATION 1 

METAL 2 

POLY 1 

PRE-METAL 

DIELECTRIC 

Mag. 13,000x 

INTERLEVEL DIELECTRIC 

METAL 1 

W PLUG 

Mag. 26,000x 

PLUG 

N +S/D 

SEM section views illustrating general structure. 


METAL 1 

POLY 1


BIT 

1 

BIT 

WORD 

2 

WORD 

POLY 1 

SELECT 

GATE 

BIT LINE CONTACT 

R1 

POLY 2 “PULL UP” 

RESISTOR 

Perspective and section SEM views of SRAM cell array. Mag. 13,000x. 

R2 

4 

3 

V CC 


V CC 

GND 

GND 

delayered, 0° 

delayered, 60°

tm Tech T32L3232A-7Q 


Tm TECH T32L3232A-7Q 

Synchronous Burst 

1Mbit (32K x 32) CMOS SRAM 


These parts were packaged in 100-pin plastic Thin Quad Flat Packs (TQFPs) with gull-wing 

leads. They were fully functional production devices organized in a 32K word x 32-bit design 

providing synchronous burst operation. These parts offer a 7 nsec. access time and they operate 

from a 3.3V power source. They were date coded 9530 (week 30 of 1995). 




– Standard CMOS with tungsten plugs, SOG planarization, and 4T cells. 

– Sub-micron gate lengths (0.35 micron). 

Quality 

Quality of the process implementation was good although metal 2 thinned up to 85 percent at 

vias. 



Technology 

These devices were manufactured by a P-well, selective oxidation CMOS process on an N substrate 

(no epi). They employed two levels of metal and two levels of poly. 

Final passivation consisted of a layer of nitride over silicon-dioxide. 

2-5 



The two levels of metal were defined by standard dry-etch techniques. Both consisted of aluminum 

with titanium-nitride caps. Metal 2 had a titanium barrier/adhesion layer, while metal 1 

employed a titanium adhesion layer under a titanium-nitride barrier. 

Vertical interconnect between metal 2 and metal 1 employed standard vias. Metal 1 used tungsten 

plugs at all contacts to silicon. The plugs appeared to have a titanium-nitride on titanium 

liner underneath only. No sign of any layer between the tungsten and aluminum 1 above it was 

observed. 

Intermetal dielectric between metal 2 and metal 1 consisted of three layers of glass including a 

spin-on-glass (SOG) for planarization. The SOG had been subjected to an etchback. It was 

located between two standard deposited layers (TEOS?). 

Pre-metal dielectric was a single layer of reflow glass (BPSG) over densified oxides. The BPSG 

was reflowed prior to contact cuts only. 

Two layers of polysilicon were used. Poly 2 was used to form the pull-up resistors in the array. 

Polycide 1 (poly 1 and tungsten silicide) was used to form all gates and fuses on the die. No 

unusual features were present. 

Oxide sidewall spacers were used and were left in place. 

Buried contacts were used only at poly 2 resistors in the cell array. 

No evidence of unusual gate oxides or other dielectrics was found. Standard LOCOS isolation 

was employed and well implemented. No step was present in the LOCOS and no other indications 

of the use of twin-wells was found. 

Polycide 1 redundancy fuses were present. Passivation and oxide was cleared over the fuse 

locations. No blown fuses were present. 

Standard source/drain implants were used and we only found evidence of the single type Pwells. 

Diffusions were not silicided. 



Memory cells consisted of a standard 4T NMOS SRAM design. Polycide 1 formed word lines, 

select and storage gates. Metal 2 was used as “piggyback” word lines (via metal 1 links). Metal 

1 formed bit lines throughout the array and also distributed GND. Selectively doped poly 2 

2-6


formed the pull-up resistors and distributed Vcc. Poly 2 also provided the interpoly/buried 

interconnection. Select gates were 0.45 micron long while the cell size was 19 microns2 . 

Overall minimum feature size measured anywhere on the die was the 0.35 micron poly used for 

both P and N-channel gates. 


As mentioned, parts were packaged in 100-pin plastic Thin Quad Flat Packs (TQFPs) with gullwing 

leads date coded 9530. 


a pitch of 160 microns with 50 micron spacing. Pads were 110 microns wide with 9 micron 

windows. Both metal 1 and metal 2 were present and in direct contact in the entire pad areas. 

No die coat was used. 

2-7 



PIN 2 

The tm Tech T32L3232A-7Q intact circuit die. Mag. 30x. 



POLISHING 

ARTIFACT 

LOCAL OXIDE 

PASSIVATION 


POLYCIDE 1 GATE 

TiN BARRIER 1 

Mag. 13,000x 

Mag. 40,000x 

METAL 

2 

METAL 1 

W 

PLUG 

SEM section views illustrating general construction. Silicon etch. 

N+ 

W 

PLUG 

ALUMINUM 1 

P+ 


SOG 

TiN CAP 1 

INTERMEDIATE GLASS 

POLYCIDE 1


BIT 

Example of poly 1 structures. Mag. 10,000x, 0°. 

BIT 

“PIGGYBACK” 

WORD LINES 

POLYCIDE 1 

SELECT GATE 

N+ 

1 

2 

GND 

R1 

4 

R2 


W 

PLUG 

METAL 1 

3 

V CC 

PASSIVATION 

METAL 2 

POLY 2 RESISTOR 

Topological and section SEM views of the tm Tech SRAM cell. 


unlayered, 

Mag. 13,000x, 0° 

Mag. 10,000x

Winbond W25P010AF-8 


WINBOND W25P010AF-8 

Synchronous Burst 

1Mbit (32K x 32) CMOS SRAM 


The parts were packaged in 100-pin plastic Quad Flat Packs (QFPs) with gull wing leads. They 

were fully functional production devices organized in a 32K word x 32-bit design providing 

synchronous burst operation. They have an 8 nsec. access time and operate from a 3.3V power 

source. They were date coded 9612 (week 12 of 1996) 




– Standard N-well CMOS with SOG planarization (no CMP). 


Quality 

Quality of the process implementation was normal to poor. Some 95 to 100 percent aluminum 

thinning was noted at metal contacts and vias. 

In the area of layer patterning, etch definition was normal to poor, while control was good. 

Alignment and registration was normal. 

Technology 

These devices were manufactured by an N-well, selective oxidation CMOS process on a P substrate 

(no epi). They employ two levels of metal and two levels of poly. 

Passivation consisted of a layer of nitride over glass. 

2-8 



The two levels of metal were defined by standard dry-etch techniques. Metal 2 consisted of 

aluminum with a titanium-nitride cap and titanium barrier. Metal 1 was also aluminum and 

employed a titanium-nitride cap and barrier, plus a titanium adhesion layer under the barrier. 

Standard contacts and vias were used for vertical interconnect (no plugs). 

Interlevel dielectric between metal 2 and metal 1 consisted of two layers of glass with a spinon- 

glass (SOG) between for planarization. The SOG had been subjected to an etchback. 

Pre-metal dielectric was a single layer of reflow glass (BPSG) over densified oxides. This layer 

was reflowed prior to contact cuts only. 

Two levels of polysilicon were used. Poly 2 was used only in the memory array. Poly 1 was 

used to form all gates and fuses on the die. Both consisted of standard polysilicon (no silicide). 

Oxide sidewall spacers were used on the gates and were left in place. 

Both poly 1 and poly 2 made direct contact to N+ diffusions (buried contacts) and poly 2 also 

made direct contact to poly 1. 

No evidence of unusual gate oxides or other dielectrics was found. Standard LOCOS 

isolation was employed and well implemented. No step was present in the LOCOS and no 

other signs of the presence of twin-wells was found. 

Standard source/drain implants were used (not silicided). 

Polycide 1 redundancy fuses were present. Passivation and most dielectric were cleared over the 

fuse locations. No blown fuses were noted. 



Memory cells consisted of a standard 4T NMOS SRAM cell design. Poly 1 formed word lines, 

select and storage gates. Metal 2 formed “piggyback” word lines and distributed GND (via 

metal 1). Metal 1 was used to form bit lines. Selectively doped poly 2 formed the pull-up resistors 

and distributed Vcc. The SRAM cell size was 19.6 microns2 . 

Overall minimum feature size measured anywhere on these dice was the 0.45 micron poly (Nchannel 

gates). 

2-9



As mentioned, these parts were packaged in 100-pin plastic Quad Flat Packs (QFPs) with gullwing 

leads date coded 9612 (week 12 of 1996) 



windows. 

No die coat was used. 

2-10 



Whole die photograph of the Winbond W25P010AF-8 SRAM. Mag. 35x. 



METAL 1 

P+ S/D 

PASSIVATION 1 

POLY 1 

POLY 1 

GATE 

GATE OXIDE 

PASSIVATION 2 

METAL 2 

SOG 

N+ S/D 

P+ S/D 

SEM section views illustrating general device structures. 


POLY GATE 

silicon etch, 

Mag. 10,000x 

Mag. 4600x, 60° 

P-channel, 

Mag. 26,000x


BIT 

BIT 

1 

2 

POLY 1 

SOG 

N+ S/D 

POLY 2 

N+ S/D 

R2 

R1 

POLY 1 

GATE 

SOG 

V CC 

Topological and section SEM views of SRAM cell. 

4 

3 

METAL 1 BIT LINE 

POLY 2 

N+ S/D 

POLY 1 GATE 

N+ S/D 


unlayered, 

Mag. 13,000x, 0° 

parallel to bit lines, 

Mag. 24,000x 

perpendicular to bit lines, 

Mag. 26,000x

Samsung KM68400ALG-7 


SAMSUNG KM684000ALG-7 

4Mbit (x8) CMOS SRAM 


These parts were packaged in 32-pin plastic Small Outline Packages (SOPs) with gull-wing 

leads. They were fully functional production devices organized in a 512K word x 8-bit design 

and offer a 70nsec access time. These parts operate from a 3.0 to 3.6V power source. The date 

code was 606Y (week 6 of 1996) 




– Relatively unaggressive design rules but almost the smallest cell seen in 1996. 

– Very complex four layer poly process. 

– Thin-film stacked PMOS load transistor (TFT) SRAM cell. 

– Reflowed aluminum 1 contacts. 

Quality 

Quality of the process implementation was very good. We found no areas of concern. 



Technology 

These devices were manufactured by a twin (multiple)-well, selective oxidation CMOS process 

on a P substrate (no epi). They employ two levels of metal and four levels of poly. 

Passivation consisted of a thick nitride over a thin layer of glass. 

2-11 



The two levels of metal were defined by standard dry-etch techniques. Metal 2 consisted of aluminum 

(no cap or barrier layer). Metal 1 was aluminum with a titanium-nitride cap and barrier 

on a thin titanium adhesion layer. 

Standard vias were used under metal 2, but metal 1 used reflowed aluminum contacts (no 

plugs). These are typical of Samsung’s process. 

Intermetal dielectric between metal 2 and metal 1 consisted of a multilayered glass followed by 

a spin-on-glass (SOG) for planarization, covered by another layer of glass (no CMP). 

Pre-metal dielectric used two layers of reflow glass (BPSG) in the memory array area, but 

apparently only one layer in the periphery. Each of these layers had a thin layer of nitride 

underneath (for which we could not determine the specific purpose). Poly 1 and 2 were located 

under the first pair of these dielectrics, poly 3 and 4 were located under the second pair. 

Four layers of polysilicon were used. Poly 4 and poly 3 were used in the cell array only. 

Polycide 2 (poly 2 and tungsten silicide) was used to distribute word lines and ground in the 

array. It was also used as a layer of interconnect throughout the peripheral circuitry. In addition, 

polycide 2 formed the redundancy fuses and was used for some special structures we could not 

define (most appeared to shield poly 1 gates). Poly 1 formed all standard gates on the die. 

Sidewall spacers were of oxide and were left in place. 


Buried contacts were formed by poly 2 to N+ and, poly 4 and 3 formed interpoly/buried contacts 

in the cell array only. 

No evidence of unusual gate oxides was found. Standard LOCOS isolation was employed and 

well implemented. A step in this LOCOS was present at well boundaries. 

Polycide 2 redundancy fuses were present. Passivation and oxide was cleared over the fuse 

locations, and some laser blown fuses were noted. 

Standard source/drain implants were used but wells included both deep and shallow P-wells. 

The shallow P-wells were located inside N-wells and were used in the memory array areas. Pwells 

were also used in the periphery but could not be delineated. 

Overall minimum feature size measured anywhere on these dice was the 0.4 micron poly 4. 

Minimum gate length was 0.65 micron (N-channel). 

2-12



Memory cells consisted of two select gates, two storage gates, two PMOS thin film 

transistors, and some apparent cross-coupling capacitor regions. Metal 1 formed the bit lines. 

Poly 1 was used for all the gates. Polycide 2 distributed ground (supplied from metal 1 and 2). 

Polycide 2 also formed the word lines. Poly 3 formed the PMOS thin film transistor (TFT) 

gates and was used as an interconnect for bit line contacts. Poly 4 formed the TFT bodies and 

provided Vcc distribution. The SRAM cell size was 11.7 microns2 . 

A P-well within a deep N-well was present beneath the array only. 


As mentioned, these parts were packaged in 32-pin 400 mil plastic Small Outline Packages 

(SOPs) with gull-wing leads date coded 9606. 



windows. 

A patterned polyimide die coat was used. 

2-13 


Samsung KM68V4000 ALG-7 


Whole die photograph of the Samsung KM68400ALG-7 intact circuit die. Mag. 20x.


METAL 1 

PRE-METAL GLASS 

LOCAL OXIDE 

Mag. 6500x, 60° 

ILD 

POLY 1 

PASSIVATION 

METAL 2 

silicon etch, Mag. 13,000x 

POLYCIDE 2 

POLY 1 

Topological and section SEM views illustrating general construction. 


POLYCIDE 2


V CC 

POLY 2 

6 

POLYCIDE 2 

WORD LINE 

POLY 4 

GND 

Mag. 13,000x, 0° 

ALUMINUM 1 

POLY 1 SELECT 

GATE 

Mag. 26,000x 

V CC 

POLY 3 

Topological and section SEM views of the SRAM cell. 

5 

POLY 3 


CAP 1 

BARRIER 1 

POLY 4

Sony CXK5B16120J-12 


SONY CXK5B16120J-12 

1Mbit (64K x 16) BiCMOS SRAM 


The parts were packaged in 44-pin plastic Small Outline J-lead (SOJ) packages. They were 

fully functional production devices organized in a 64K word x 16 bit asynchronous design and 

operate from a 3.3V power source. The date code was 9604 (week 4 of 1996) 




– Very complex BiCMOS process. 


– TFT pull-up devices in the SRAM array. 

Quality 

Quality of the process implementation was poor. Metal 1 aluminum at contacts thinned up to 

100 percent (barrier barely maintained continuity). In addition, cracks were noted in the barrier 

metal at sidewalls of some contacts. 



Technology 

These devices were manufactured by a twin well, selective oxidation BiCMOS process on a P 

substrate. Bipolar (NPN) devices were located in N-wells with an apparent implanted buried 

layer (retrograde well)? They employ two levels of metal and four levels of poly. 

Passivation consisted of a single layer of nitride. 

2-14 



A patterned (at bond pads) polyimide die coat was present. 

The two levels of metal were defined by standard dry-etch techniques. Metal 2 consisted of aluminum 

with a titanium barrier, while metal 1 (aluminum) employed a titanium nitride cap and 

barrier on a titanium adhesion layer. In addition, poly 2 (a tungsten polycide) was used as a 

metal substrate. 

Standard vias and contacts were used (no plugs). Elongated metal 1 contacts were used at bipolar 

devices only. Metal 1 contacted every active layer except poly 3. 

Intermetal dielectric between metal 2 and metal 1 consisted of four layers of glass. The second 

layer was a spin-on glass (SOG) and had been subjected to an etchback for planarization. 

Pre-metal dielectric used two layers of reflow glass (BPSG), one between poly 2 and poly 3, 

and one between poly 4 and metal 1. 

Five layers of polysilicon were employed. Poly 5 (?) provided diffusion source and contact at 

emitters of bipolar transistors. Poly 4 and Poly 3 (thin layers) were used exclusively in the 

SRAM cell array. Polycide 2 (tungsten silicide) was used for bit line connections and GND in 

the SRAM array and as interconnect in the periphery and decode circuitry. Polycide 1 (tungsten 

silicide) was used to form all gates on the die including the select and storage gates in the cell, 

and for redundancy fuses. 

Oxide sidewall spacers were used on the gates and were left in place. 

Standard implanted source/drain diffusions were used at MOS devices (no salicide). 


Bipolar devices (NPN) used poly emitter sources and a separate P+ diffusion for the bases. 

Deep N+ diffusions were used at collectors. All bipolar NPNs were located in N-wells and 

appeared to have buried layer diffusions assumed to be retrograde well implants since no signs 

of an epi layer were found. 

Direct poly-to-diffusion (buried) contacts were used between poly 5 and base P+ at the NPN 

emitters, between poly 1 and N+ in the array, and between poly 2 and N+ in the array. Poly 3 

made direct contact to poly 1 and to poly 4. 

No evidence of unusual gate oxides or other dielectrics was found. Standard LOCOS isolation 

was employed and well implemented. A step was present indicating the use of twin-wells. 

2-15


Poly 1 redundancy fuses were present. Passivation and oxide was cleared over the fuse locations, 

and some laser blown fuses were noted. 


The memory cells employed a 4T SRAM design with TFT pull-ups. Metal 1 formed the bit 

lines via poly 2 links. Poly 4 was used to form the body of the pull-up TFT devices and distribute 

Vcc. Poly 3 was used for cell interconnect and provided the gates for the TFTs. Poly 2 

formed the bit line connections and distributed GND. Poly 1 formed all gates and word lines. 

The SRAM cell size was 20 microns2 . 

Overall minimum feature size measured anywhere on these dice was the 0.4 micron poly 4. 

Minimum gate lengths were 0.5 micron (N-channel) found in peripheral circuitry. 


As mentioned, the parts were packaged in 44-pin plastic Small Outline J-lead (SOJ) packages 

date coded 9604. 



windows. 

A patterned polyimide die coat was used. 

2-16 



Whole die photograph of the Sony CXK5B16120J-12 die. Mag. 22x. 



N+ COLLECTOR 

PASSIVATION 

METAL 1 

DEEP N+ COLLECTOR 

N-WELL/N+ BURIED LAYER 

N+ POLY 

EMITTER 

POLY 

P+ BASE 

N+ EMITTER 

P+ BASE 

CONTACT 

Perspective and section SEM views of a bipolar device. 


Mag. 3000x, 60° 

delayered, 

Mag. 8000x, 60° 

Mag. 10,000x


IMD 

METAL 1 

POLY 4 

POLY 1 

SELECT GATE 

POLY 2 BIT LINE 

CONTACT 

POLY 3 

POLY 4 

(PULL-UP DEVICE) 

N+ 

POLY 1 

STORAGE GATE 

METAL 1 

N+ 

POLY 2 

POLY 3 

(INTERCONNECT) 

Perspective and section SEM views of the SRAM cell. 


POLY 4 

(PULL-UP DEVICE) 

POLY 2 

(GND) 

POLY 4 

POLY 1 SELECT 

GATE 

POLY 3 

Mag. 16,000x, 60° 

Mag. 26,000x 

Mag. 40,000x

SRAMs - Smithsonian - The Chip Collection

Create successful ePaper yourself

Delete template?

Save as template?