ICE Shared Construction Analysis SCA 9712-575 - Smithsonian ...

Construction Analysis 

Analog Devices ADSP-21062-KS-160 

SHARC Digital Signal Processor 

Report Number: SCA 9712-575 

Serving the Global Semiconductor Industry Since 1964 

17350 N. Hartford Drive 

Scottsdale, AZ 85255 

Phone: 602-515-9780 

Fax: 602-515-9781 

e-mail: ice@ice-corp.com 

Internet: http://www.ice-corp.com 

®

TITLE 

INDEX TO TEXT 

- i - 

PAGE 

INTRODUCTION 1 

MAJOR FINDINGS 1 

TECHNOLOGY DESCRIPTION 

Assembly 2 

Die Process 2 - 3 

ANALYSIS RESULTS I 

Assembly 4 

ANALYSIS RESULTS II 

Die Process and Design 5 - 7 

ANALYSIS PROCEDURE 8 

TABLES 

Overall Evaluation 9 

Package Markings 10 

Wirebond Strength 10 

Die Material Analysis 10 

Horizontal Dimensions 11 

Vertical Dimensions 12

INTRODUCTION 

This report describes a construction analysis of the Analog Devices ADSP-21062-KS-160 

SHARC Digital Signal Processor. Two devices which were packaged in 240-pin Plastic 

Quad Flat Packages (PQFP) were received for the analysis. The devices were date coded 

9641 and 9701. The majority of the analysis was performed on the device date coded 9701. 

Questionable Items: 1 

• none. 

Special Features: 

• Sub-micron gate lengths (0.5 micron). 

• Tungsten plugs. 

MAJOR FINDINGS 

1 These items present possible quality or reliability concerns. They should be discussed 

with the manufacturer to determine their possible impact on the intended application. 

- 1 -

Assembly: 

TECHNOLOGY DESCRIPTION 

• The devices were packaged in 240-pin Plastic Quad Flat Packages (PQFP). A 

copper heat slug (heatsink) was employed on the top of the package (cavity down 

orientation). It was internally connected to ground. 

• Wirebonding method: A thermosonic ball bond technique employing 1.2 mil O.D. 

gold wire was used. 

• Dicing: Sawn (full depth) dicing. 

• Die attach: A silver epoxy compound. 

Die Process 

• Fabrication process: Selective oxidation CMOS process employing twin-wells in an 

N substrate. 

• Die coat: No die coat was used on the devices. 

• Final passivation: A layer of nitride over a layer of silicon-dioxide. 

• Metallization: Two levels of metal defined by standard dry-etch techniques. Metal 2 

consisted of aluminum with a titanium-nitride cap and barrier. Metal 1 consisted of 

aluminum, a titanium nitride cap and barrier, and a titanium adhesion layer. 

Tungsten plugs were used as the vertical interconnect under both metal layers. They 

were lined with titanium-nitride. 

• Interlevel dielectric: Interlevel dielectric consisted of four layers of silicon-dioxide 

with a planarizing spin-on-glass (SOG) between the third and fourth layer. 

• Pre-metal dielectric: This dielectric consisted of a layer of reflow glass over 

densified oxides. 

- 2 -

TECHNOLOGY DESCRIPTION (continued) 

• Polysilicon: Two layers of polysilicon were used on the die. Poly 1 (polysilicon 

and tungsten silicide) was used to form redundancy fuses, all gates on the die, and 

word lines in the array. Poly 2 was used to form “pull-up” resistors in the cell 

array, and formed resistors in fuse blocks which were connected to one end of the 

poly 1 fuses. Both poly layers were defined by a dry-etch of good quality. 

• Diffusions: Implanted N+ and P+ diffusions formed the sources/drains of 

transistors. No silicide was present on diffusions. An LDD process was used with 

the oxide sidewall spacers left in place. N+ diffusions were “pushed down” at 

tungsten contacts. 

• Wells: Planar (no step in LOCOS) twin-well process in the N substrate. No epi 

layer. 

• Redundancy: Fuses consisting of poly 1 were present on the die. Passivation and 

interlevel dielectric cutouts were made over the fuses. One end of the fuse structure 

was connected to metal 1, while the other end was connected to a poly 2 resistor. 

Some laser blown fuses were noted. 

• Memory cells: The die employed a 2 Mbit SRAM array. The memory cells used a 

4T CMOS SRAM cell design. Metal 2 distributed GND and Vdd (via Metal 1), and 

formed the bit lines using metal 1 links. Metal 1 was used as “piggy-back” word 

lines. Poly 1 formed the word lines, select, and storage gates. Poly 2 formed “pull- 

up” resistors and distributed Vdd. 

• Both metals 1 and 2 were used in the bond pads. 

- 3 -

Assembly: 

Questionable Items: 1 None. 

Special Features: None. 

General Items: 

ANALYSIS RESULTS I 

- 4 - 

Figures 1 - 2 

• Overall package: The device was packaged in a 240-pin PQFP. A large copper heat 

slug (heatsink) was employed on the top of the package (cavity down orientation). It 

was internally connected to GND. 

• Wirebonding method: A thermosonic ball bond technique employing 1.2 mil gold 

wire was used. All bonds were well formed and placed. Bond strengths were 

normal as determined by wire pull tests. 

• Dicing: Sawn (full depth). No large chips or cracks were noted. 

• Die attach: A silver epoxy compound of normal quality. 

1 These items present possible quality or reliability concerns. They should be discussed 

with the manufacturer to determine their possible impact on the intended application.

Die Process and Design: 

Questionable Items: 1 

• None. 

Special Features: 

• Sub-micron gate lengths (0.5 micron). 

General Items: 

ANALYSIS RESULTS II 

- 5 - 

Figures 3 - 39 

• Fabrication process: Selective oxidation CMOS process employing twin-wells in an 

N substrate. 

• Process implementation: Die layout was clean and efficient. Alignment was good 

at all levels. 

• Die surface defects: None. No contamination, toolmarks or processing defects 

were noted. 

• Passivation: A layer of nitride over a layer of silicon-dioxide. Passivation coverage 

and edge seal were good. Integrity test indicated defect free passivation. 

• Metallization: Two levels of metallization were used. Metal 2 consisted of 

aluminum with a titanium-nitride cap and barrier. Metal 1 consisted of aluminum, 

titanium-nitride cap and barrier, and a titanium adhesion layer. Tungsten plugs were 

employed under both metal layers. The plugs were lined with titanium-nitride. 

• Metal patterning: All metal layers were defined by a dry etch of good quality. 

1 These items present possible quality concerns. They should be discussed with the 

manufacturer to determine their possible impact on the intended application.

ANALYSIS RESULTS II (continued) 

• Metal defects: None. No voiding, notching or cracking of the metal layers was 

found. Silicon nodules were found following removal of metal 1. 

• Metal step coverage: Virtually no metal thinning was noted due to the use of 

tungsten plugs. The tungsten plugs were nearly level with the oxide surface, so no 

large steps were present for the metal to cover. 

• Vias and contacts: Vias and contacts were defined by a dry-etch. No significant 

over-etching was noted. 

• Interlevel dielectric: Interlevel dielectric consisted of four layers of silicon-dioxide 

with a spin-on-glass (SOG) between the third and fourth layers to aid in 

planarization. No problems were noted. 

• Pre-metal dielectric: This dielectric consisted of a layer of reflow glass (BPSG) over 

densified oxide. No problems were found. 

.• Polysilicon: Two layers of polysilicon were employed. Poly 1 (polysilicon and 

tungsten silicide) formed the redundancy fuses, all gates on the die, and word lines 

in the array. Poly 2 was used to form resistors in the cell array and outside the fuse 

blocks. Definition was by a dry etch of good quality. No problems were found. 

• Isolation: LOCOS (local oxide isolation). No problems were noted at birdsbeak or 

elsewhere and no step was present at the well boundaries. 

• Diffusions: Implanted N+ and P+ diffusions were used for sources and drains. 

Oxide sidewall spacers were present to provide LDD spacing. Deep (pushed down) 

N+ diffusions were noted under contacts in N regions. Diffusions were not 

silicided. No problems were found. 

• Wells: Twin-wells were employed in an N substrate. No step was present at the 

well boundaries. No problems were noted. 

- 6 -

ANALYSIS RESULTS II (continued) 

• Buried contacts: Direct poly-to-diffusion (buried) contacts were only used in the 

SRAM array. No problems were found in these areas. 

• Redundancy: Poly 1 fuses were present along the row and column decode logic 

outside the SRAM array. Passivation and interlevel dielectric cutouts were made 

over the fuses. Laser blown fuses were noted. 

• Memory cells: The die employed a 2 Mbit SRAM array. The memory cells used a 

4T CMOS SRAM cell design. Metal 2 distributed GND and Vdd, and formed the 

bit lines using metal 1 links. Metal 1 was used as the “piggy-back” word lines. 

Poly 1 formed the word lines, select, and storage gates. Poly 2 formed “pull-up” 

resistors and distributed Vdd. Cell size was 3.3 x 5.7 microns (19 microns 2 ). 

- 7 -

PROCEDURE 

The devices were subjected to the following analysis procedures: 

External inspection 

X-ray 

Decap 

SEM of passivation 

Passivation integrity test (chemical) 

Wirepull test 

Passivation removal 

SEM inspection of metal 2 

Aluminum 2 removal and inspect 

Delayer to metal 1 and inspect 

Aluminum 1 removal and inspect barrier 

Delayer to polycide/substrate and inspect 

Die sectioning (90° for SEM) * 

Measure horizontal dimensions 

Measure vertical dimensions 

Die material analysis 

* Delineation of cross-sections is by silicon etch unless otherwise indicated. 

- 8 -

OVERALL QUALITY EVALUATION: Overall Rating: Good 

DETAIL OF EVALUATION 

Package integrity: G 

Die placement: G 

Die attach quality: G 

Wire spacing: N 

Wirebond placement: N 

Wirebond quality: G 

Dicing quality: G 

Wirebond method Thermosonic ball bonds using 1.2 mil 

- 9 - 

gold wire. 

Die attach method Silver-epoxy 

Dicing Sawn (full depth) 

Die surface integrity: 

Toolmarks (absence) G 

Particles (absence) G 

Contamination (absence) G 

Process defects (absence) G 

General workmanship G 

Passivation integrity G 

Metal definition G 

Metal integrity G 

Metal registration G 

Contact coverage G 

Contact registration G 

G = Good, P = Poor, N = Normal, NP = Normal/Poor

Sample 1 

PACKAGE MARKINGS 

TOP 

- 10 - 

Sample 2 

(LOGO) ANALOG DEVICES (LOGO) ANALOG DEVICES 

ADSP-21062 ADSP-21062 

9641 KS-160 9701 KS-160 

ED/C15598.00-2.1 (SHARC LOGO) ED/C16005.00-2.1 (SHARC 

LOGO) 

BOTTOM 

WAFER H WAFER H 

HONG KONG HONG KONG 

WIREPULL TEST 

Sample 2 

# of wires tested: 25 

Bond lifts: 0 

Force to break - high: 9g 

- low: 5.25g 

- avg.: 7.45g 

- std. dev.: 1.0 

DIE MATERIAL IDENTIFICATION 

Overlay passivation: Nitride over silicon-dioxide. 

Metallization 2: Aluminum with a titanium-nitride cap and 

barrier. 

Interlevel dielectric: Multiple layers of silicon-dioxide including 

SOG. 

Metallization 1: Aluminum with a titanium-nitride cap and 

barrier, on a titanium adhesion layer. 

Plugs: Tungsten, lined with titanium-nitride. 

Pre-metal glass: BPSG reflow glass on densified oxide. 

Silicide (Poly 1): Tungsten.

HORIZONTAL DIMENSIONS 

Die size: 11.9 x 14.9 mm (468 x 586 mils) 

Die area: 177 mm 2 (274,248 mils 2 ) 

Min pad size: 0.11 x 0.11 mm (4.4 x 4.4 mils) 

Min pad window: 0.09 x 0.09 mm (3.7 x 3.7 mils) 

Min pad space: 40 microns 

Min metal 2 width: 0.8 micron 

Min metal 2 space: 1.0 micron 

Min metal 2 pitch: 1.8 micron (uncontacted) 

Min metal 1 width: 0.6 micron 

Min metal 1 space: 0.7 micron 

Min metal 1 pitch: 1.3 micron (uncontacted) 

Min via: 0.45 micron 

Min contact: 0.5 micron 

Min polycide width: 0.5 micron 

Min polycide space: 0.7 micron 

Min gate length * - (N-channel): 0.5 micron 

- (P-channel): 0.5 micron 

Min LOCOS: 0.8 micron 

SRAM cell size: 19.0 microns 2 

SRAM cell pitch: 3.3 x 5.7 microns 

* Physical gate length. 

- 11 -

VERTICAL DIMENSIONS 

Die thickness: 0.45 mm (18 mils) 

Layers 

Passivation 2: 0.6 micron 

Passivation 1: 0.15 micron 

Metal 2 - cap: 0.04 micron (approx.) 

- aluminum: 0.7 micron 

- barrier: 0.09 micron 

- plugs: 0.8 - 1.0 micron 

Interlevel dielectric - glass 4: 0.5 micron (average) 

- glass 3: 0.15 micron (average) 

- glass 2: 0.35 - 0.75 micron 

- glass 1: 0.15 micron (average) 

Metal 1 - cap: 0.15 micron (approx.) 

- aluminum: 0.5 micron 

- barrier: 0.1 micron 

- plugs: 0.5 - 1.0 micron 

Pre-metal glass: 0.65 micron 

Polycide - silicide: 0.1 micron 

- poly: 0.13 micron 

Local oxide: 0.4 micron 

N+ S/D diffusion: 0.2 micron 

P+ S/D diffusion: 0.2 micron 

N-well: 2.5 microns (approx.) 

P-well: 2.0 microns (approx.) 

- 12 -

INDEX TO FIGURES 

ASSEMBLY Figures 1 - 2 

DIE LAYOUT AND IDENTIFICATION Figures 3 - 6 

PHYSICAL DIE STRUCTURES Figures 7 - 39 

REDUNDANCY FUSES Figures 24 - 25 

COLOR DRAWING OF DIE STRUCTURE Figure 26 

SRAM MEMORY CELL STRUCTURES Figures 27 - 35 

CIRCUIT LAYOUT AND I/O Figure 36 - 39 

- ii -


Integrated Circuit Engineering Corporation 

Figure 1. Package photographs of the Analog Devices ADSP-21062-KS-160 

SHARC Digital Signal Processor. Mag. 2.5x.


PIN 1 

top 

Figure 2. X-ray view of the package. Mag. 3x. 

Integrated Circuit Engineering Corporation



Figure 3. Portion of the Analog Devices ADSP-21062-KS-160 die. Mag. 26x.



Figure 3a. Portion of the Analog Devices ADSP-21062-KS-160 die. Mag. 26x.



Figure 3b. Portion of the Analog Devices ADSP-21062-KS-160 die. Mag. 26x.



Figure 3c. Remaining portion of the Analog Devices ADSP-21062-KS-160 die. Mag. 

26x.


Figure 4. Optical views of die markings. Mag. 500x. 



Figure 5. Optical views of die corners. Mag. 80x. 



METAL 2 


SLOT 

Figure 6. Optical views illustrating a slotted bus line and mask revision numbers. 

Mag. 400x.


EDGE OF 

PASSIVATION 

Mag. 1200x 

METAL 2 

N+ 

SUBSTRATE 

Mag. 6400x 

EDGE OF 

PASSIVATION 

METAL 1 

Figure 7. SEM section views of the die edge seal. 



N+ S/D 

LOCOS 

METAL 1 

PASSIVATION 2 

PASSIVATION 1 

PASSIVATION 2 

POLY 1 GATE 

PASSIVATION 1 

SOG 

W PLUG 

W PLUG 

N+ S/D 

METAL 2 

POLY 1 GATE 

Figure 8. SEM section views illustrating general structure. Mag. 13,000x. 


METAL 1 

METAL 2 

LOCOS


Mag. 4800x 

Mag. 9600x 

Figure 9. SEM views illustrating final passivation. 60°. 



PASSIVATION 2 

METAL 2 

INTERLEVEL DIELECTRIC 

METAL 1 

Mag. 26,000x 

ALUMINUM 2 

TiN BARRIER 

Mag. 52,000x 

TIN CAP 

Figure 10. SEM section views illustrating metal 2 line profiles. 


PASSIVATION 1


METAL 2 

METAL 2 

VIAS 

Figure 11. Topological SEM views of metal 2 patterning. 0°. 


Mag. 3250x 

Mag. 6500x 

Mag. 6500x


TiN CAP 

METAL 2 

TiN BARRIER 

TiN BARRIER 

ALUMINUM 2 

W PLUG 


Mag. 12,400x 

Mag. 26,000x 

Mag. 40,000x 

Figure 12. Perspective SEM views of metal 2 step coverage, barrier, and plug. 60°.


SOG 

INTERLEVEL 

DIELECTRIC 

SOG 

W PLUG 

LOCOS 

W PLUG 

PASSIVATION 2 

METAL 2 

METAL 1 

METAL 2 

W PLUG 

METAL 1 

METAL 2 

METAL 1 

POLY 1 


Figure 13. SEM section views of typical vias. 


Mag. 13,000x 

Mag. 26,000x 

Mag. 26,000x



TiN CAP 

ALUMINUM 1 

TiN BARRIER 

METAL 2 

METAL 1 

Mag. 26,000x 

Mag. 52,000x 

Figure 14. SEM section views of metal 1 line profiles. 



METAL 1 

CONTACT 

POLY 

METAL 1 

METAL 1 

Figure 15. Topological SEM views of metal 1 patterning. Mag. 6500x, 0°. 


VIA


TiN BARRIER 

METAL 1 

TiN CAP 

ALUMINUM 1 

Figure 16. Perspective SEM views of metal 1 step coverage. 60°. 


Mag. 6500x 

Mag. 10,000x 

Mag. 30,000x


Si 

TiN BARRIER 

Mag. 10,000x 

TiN BARRIER 

W PLUG 

Mag. 40,000x 

Figure 17. Perspective SEM views of metal 1 barrier and plugs. 60°. 



LOCOS 

LOCOS 

W PLUG 

W PLUG 

METAL 1 

W PLUG 

POLY 1 

LOCOS 

METAL 1 

METAL 1 

Ti ADHESION 

LAYER 


Figure 18. SEM section views illustrating typical metal 1 contacts. Mag. 26,000x. 

P+ 

N+


POLY 

N+ P+ 

Figure 19. Topological SEM views of poly 1 patterning. 0°. 


Mag. 3200x 

Mag. 3200x 

Mag. 6500x


LOCOS 

Mag. 9000x 

POLY 1 GATE 

DIFFUSION 

POLY 1 

Mag. 40,000x 

Figure 20. Perspective SEM views of poly 1 coverage. 60°. 



PRE-METAL GLASS 

POLY 1 GATE 

REFLOW GLASS 

POLY 1 GATE 

W SILICIDE 

POLY 1 

GATE OXIDE 

N+ S/D 

Figure 21. SEM section views of typical transistors. Mag. 52,000x. 


P+ S/D 

SIDEWALL SPACER 

N-channel 

P-channel 

glass etch


POLY 1 

LOCOS 

Figure 22. SEM section view of typical birdsbeak. Mag. 52,000x. 

P-WELL 

P+ 

LOCOS 

N- SUBSTRATE 

METAL 1 

N+ 

N- SUBSTRATE 

DENSIFIED OXIDE 

GATE OXIDE 

P-WELL 

Figure 23. Section views illustrating well structure. 


Mag. 800x 

Mag. 6500x


BLOWN FUSE 

INTACT FUSE 

LASER BLOWN FUSE 

Figure 24. Optical and SEM views of typical fuses. 


Mag. 800x 

Mag. 800x 

Mag. 1600x


POLY 2 

CUTOUT 

POLY 1 FUSE 

PASSIVATION 

POLY 1 FUSE 

CUTOUT 

PASSIVATION 

METAL 2 

METAL 1 

LOCOS 

Figure 25. Perspective and cross-section SEM views of typical fuses. 


Mag. 4800x, 60° 

Mag. 6500x 

Mag. 13,000x

,,, 

,,, 

,,, 

METAL 1 

,, 

,, 

,, 

,,, 

,,, 

,,, 

,, 

,, 

,, 

,,, 

,,, 

,,, 

,,,,,,,,,, 

,,,,,,,,,, 

,,,,,,,,,, 

W PLUG 

NITRIDE PASSIVATION 

METAL 2 


PRE-METAL GLASS 

GATE OXIDE 

N+ S/D 

P-WELL 

N SUBSTRATE 

GLASS PASSIVATION 

W SILICIDE 

POLY 1 

SOG 

LOCAL OXIDE 

P+ S/D 

Orange = Nitride, Blue = Metal, Yellow = Oxide, Green = Poly, 

Red = Diffusion, and Gray = Substrate 

Figure 26. Color cross section drawing illustrating device structure. 

DENSIFIED OXIDE 

,,, ,,,, 

,,, ,,,, 

,,,, 

N-WELL 





metal 2 

metal 1 

poly 

Figure 27. Perspective SEM views of the SRAM cell array. Mag. 5000x, 60°.


BIT 

BIT 

GND 

BIT 

BIT 

“PIGGYBACK” WORD LINE 

WORD 

GND 


metal 2 

metal 1 

poly 

Figure 28. Perspective SEM views of the SRAM cell array. Mag. 10,000x, 60°. 

GND


POLY 2 

RESISTOR 

POLY 1 

INTERLEVEL 

CONTACT 

POLY 1 

WORD LINE 

Figure 29. Detailed SEM views of the SRAM cell structures (delayered). 

Mag. 42,000x, 60°. 


POLY 2 

SELECT 

GATE 

POLY 1


BIT 

BIT 

GND 

“PIGGYBACK” WORD LINE 

WORD LINE 


metal 2 

metal 1 

poly 

Figure 30. Topological SEM views of the SRAM cell array. Mag. 3200x, 0°. 

GND


BIT 

BIT 

“PIGGYBACK” 

WORD LINE 

metal 2 

metal 1 


Figure 31. Detailed topological SEM views of an SRAM cell. Mag. 13,000x, 0°. 

GND 

BIT 

BIT 

GND


BIT 

WORD 

BIT 

1 

BIT 1 

2 

3 

unlayered 

R1 R2 

Figure 32. Detailed topological SEM view and schematic of an SRAM cell. 

Mag. 13,000x, 0°. 

R1 

4 

4 

3 

R2 

2 


GND 

BIT 

V DD 

GND


POLY 2 

METAL 1 LINK 

N+ S/D 

W PLUG 

METAL 2 BIT LINE 


METAL 1 LINK 

METAL 1 LINK 

POLY 1 SELECT GATE 

N+ S/D 

W PLUG 

W PLUG 

POLY 1 STORAGE GATE 

Figure 33. SEM section views of an SRAM cell (parallel to bit line). 


Mag. 13,000x 

Mag. 20,000x 

Mag. 26,000x


N+ S/D 

POLY 2 “PULL-UP” 

RESISTOR 

GATE OXIDE 

POLY 1 

POLY 2 

POLY 1 SELECT 

GATE 

GATE OXIDE 

POLY 1 STORAGE 

GATE 

N+ S/D 

Figure 34. SEM section views of SRAM cell details (parallel to bit line). 


LOCOS 

Mag. 35,000x 

Mag. 52,000x 

Mag. 52,000x



BIT LINE CONTACT 

POLY 1 WORD / SELECT LINE 

Mag. 13,000x 

POLY 1 WORD / SELECT LINE 

GATE OXIDE 

LOCOS 

Mag. 26,000x 


Figure 35. SEM section views of the SRAM cell array (perpendicular to bit line).


intact 

unlayered 

Figure 36. Optical views of typical I/O circuitry. Mag. 400x. 



Au 

Au 

POLY 1 

Mag. 3200x 

METAL 1 

Mag. 13,000x 

LOCOS 

Figure 37. SEM section views illustrating wirebond interface. 


EDGE OF PASSIVATION


METAL 1 

SOG 

P+ S/D 

P+ S/D 

METAL 2 

METAL 1 

Mag. 13,000x 

SOG 

POLY 1 GATE 

Mag. 26,000x 

Figure 38. SEM section views of P-channel I/O circuitry. 


POLY 1 GATE


N- channel 

P-channel 


Figure 39. SEM section views illustrating guardbands at the edge of the I/O circuitry. 

Mag. 6500x.

ICE Shared Construction Analysis SCA 9712-575 - Smithsonian ...

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