FPGA Based Network Security architecture for High Speed Networks

More documents

Recommendations

Info

1.3 Our Contribution 1.3 Our Contribution In this work, a set of computationally intensive modules are designed and and their performances are evaluated so as to verify their functionality as a separate application in a high speed network. For each and every design, the ultimate goal is to optimize the performance parameters i.e. to maximize the system throughput by maximizing the operating frequency of the design and to minimize the area requirements so that it validates the
1.4 Thesis Organization from the module.However, there may be possibility of false positives in the system. 1.4 Thesis Organization In this chapter, the motivation for hardware implementation of networks security applications, the objectives of our work and our contribution is discussed in a nut- shell. The organization of the rest of the thesis and a brief outline of the chapters in this thesis are as given below. In chapter 2, we have discussed the basic algorithm and theory of IDEA, the symmetric key block cipher, which is chosen for implementation in FPGA. More- over we have discussed the previous implementation details of IDEA in hardware. In chapter 3, we have described our proposed modulo multiplier architecture using Diminished-one number representation and Booth’s algorithm and analyzed how it reduces the modular complexity in IDEA round operations. In chapter 4, we have described the performance of IDEA on FPGA using our proposed multiplier and a combination of outer and inner round pipelining. We analyzed our architecture in terms of Alice counts and throughput. In chapter 5, we have proposed and implemented a novel string matching algorithm for a Network Based Intrusion Detection System using a memory efficient multi hashing data structure called Bloom Filter. Finally, in chapter 6, we draw our conclusion and proposed some additional ideas for our future work. 6
Page 1 and 2: FPGA Based Network Security archite
Page 3 and 4: Department of Computer Science and
Page 5 and 6: Abstract Cryptography and Network S
Page 7 and 8: 3.5 Complexity of the proposed mult
Page 9 and 10: List of Tables 3.1 Device utilizati
Page 11 and 12: Chapter 1 Introduction In the field
Page 13: 1.2 Problem Statement cannot guaran
Page 17 and 18: Chapter 2 Background 2.1 Introducti
Page 19 and 20: 2.3 Related Work transform step pro
Page 21 and 22: 2.3 Related Work put rate and the a
Page 23 and 24: 2.3 Related Work was needed to mana
Page 25 and 26: • High degree of fine grain paral
Page 27 and 28: 2.4 Conclusion efficient VLSI imple
Page 29 and 30: Chapter 3 Modulo (2 16 + 1) multipl
Page 31 and 32: 3.3 Algorithm for the proposed mult
Page 33 and 34: 3.3 Algorithm for the proposed mult
Page 35 and 36: 3.4 Proposed multiplier architectur
Page 37 and 38: or
Page 39 and 40: Design and Implementation of IDEA I
Page 41 and 42: 4.2 Design and Architecture using p
Page 43 and 44: 4.3 Result and comparison with othe
Page 45 and 46: 4.4 Conclusion Table 4.1: Compariso
Page 47 and 48: FPGA based string matching for NIDS
Page 49 and 50: 5.1 Introduction are primarily focu
Page 51 and 52: 5.2 Basic Idea and Related work tha
Page 53 and 54: filter is described in subsequent s
Page 55 and 56: 5.3 Proposed Design matching module
Page 57 and 58: 5.4.1 Implementation Constraints 5.
Page 59 and 60: Figure 5.6: Large Bloom Filter usin
Page 61 and 62: Figure 5.8: Timing Summary for Hash
Page 63 and 64: 5.5 Conclusion to in line speed. In
Page 65 and 66:
Chapter 6 Conclusion and Future Wor
Page 67 and 68:
Bibliography [8] A.V. Curiger, H. B
Page 69 and 70:
Bibliography [25] M. Thaduri, S.-M.
Page 71 and 72:
Bibliography [43] Sarang Dharmapuri
show all

FPGA Based Network Security architecture for High Speed Networks

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?