FPGA Based Network Security architecture for High Speed Networks

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Contents Certificate ii Acknowledgement iii Abstract iv List of Figures vii List of Tables viii 1 Introduction 2 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Our Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Background 8 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Symmetric key Cryptosystem . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 IDEA Encryption Algorithm . . . . . . . . . . . . . . . . . . 8 2.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 Modulo (2 16 + 1) multiplier for IDEA Cipher 20 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 Diminished-one Number Representation . . . . . . . . . . . . . . . 20 3.2.1 Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 Algorithm for the proposed multiplier . . . . . . . . . . . . . . . . . 21 3.4 Proposed multiplier architecture . . . . . . . . . . . . . . . . . . . . 26 v
3.5 Complexity of the proposed multiplier : . . . . . . . . . . . . . . . . 27 3.6 Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 Design and Implementation of IDEA cipher 31 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 Design and Architecture using pipelining . . . . . . . . . . . . . . . 31 4.3 Result and comparison with other schemes . . . . . . . . . . . . . . 34 4.3.1 Analysis and Comparison . . . . . . . . . . . . . . . . . . . 34 4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5 FPGA based string matching for Network Intrusion Detection System 39 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2 Basic Idea and Related work . . . . . . . . . . . . . . . . . . . . . . 41 5.2.1 NIDS and Multiple pattern matching . . . . . . . . . . . . . 41 5.3 Proposed Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3.1 Bloom Filter basics and overview . . . . . . . . . . . . . . . 44 5.3.2 Scenario 1: With fixed sized matching patterns: . . . . . . . 45 5.3.3 Scenario 2: With variable sized matching patterns: . . . . . 46 5.4 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.4.1 Implementation Constraints . . . . . . . . . . . . . . . . . . 48 5.4.2 Partial and Large Bloom Filter . . . . . . . . . . . . . . . . 48 5.4.3 Hash Function . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.4.4 Results and Comparison . . . . . . . . . . . . . . . . . . . . 51 5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6 Conclusion and Future Work 56 Bibliography 57 Dissemination of Work 63
Page 1 and 2: FPGA Based Network Security archite
Page 3 and 4: Department of Computer Science and
Page 5: Abstract Cryptography and Network S
Page 9 and 10: List of Tables 3.1 Device utilizati
Page 11 and 12: Chapter 1 Introduction In the field
Page 13 and 14: 1.2 Problem Statement cannot guaran
Page 15 and 16: 1.4 Thesis Organization from the mo
Page 17 and 18: Chapter 2 Background 2.1 Introducti
Page 19 and 20: 2.3 Related Work transform step pro
Page 21 and 22: 2.3 Related Work put rate and the a
Page 23 and 24: 2.3 Related Work was needed to mana
Page 25 and 26: • High degree of fine grain paral
Page 27 and 28: 2.4 Conclusion efficient VLSI imple
Page 29 and 30: Chapter 3 Modulo (2 16 + 1) multipl
Page 31 and 32: 3.3 Algorithm for the proposed mult
Page 33 and 34: 3.3 Algorithm for the proposed mult
Page 35 and 36: 3.4 Proposed multiplier architectur
Page 37 and 38: or
Page 39 and 40: Design and Implementation of IDEA I
Page 41 and 42: 4.2 Design and Architecture using p
Page 43 and 44: 4.3 Result and comparison with othe
Page 45 and 46: 4.4 Conclusion Table 4.1: Compariso
Page 47 and 48: FPGA based string matching for NIDS
Page 49 and 50: 5.1 Introduction are primarily focu
Page 51 and 52: 5.2 Basic Idea and Related work tha
Page 53 and 54: filter is described in subsequent s
Page 55 and 56: 5.3 Proposed Design matching module
Page 57 and 58:
5.4.1 Implementation Constraints 5.
Page 59 and 60:
Figure 5.6: Large Bloom Filter usin
Page 61 and 62:
Figure 5.8: Timing Summary for Hash
Page 63 and 64:
5.5 Conclusion to in line speed. In
Page 65 and 66:
Chapter 6 Conclusion and Future Wor
Page 67 and 68:
Bibliography [8] A.V. Curiger, H. B
Page 69 and 70:
Bibliography [25] M. Thaduri, S.-M.
Page 71 and 72:
Bibliography [43] Sarang Dharmapuri
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FPGA Based Network Security architecture for High Speed Networks

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