FPGA Based Network Security architecture for High Speed Networks
FPGA Based Network Security architecture for High Speed Networks
FPGA Based Network Security architecture for High Speed Networks
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3.7 Conclusion<br />
outputs are generated in the subsequent clock cycles i.e. eighth,ninth, etc. The<br />
wave<strong>for</strong>m generated in the synthesis report <strong>for</strong> the multiplier module is shown in<br />
Figure 3.2. The device utilization summary and the timing analysis is given in<br />
Table 3.1.<br />
Table 3.1: Device utilization and timing analysis <strong>for</strong> the proposed multiplier<br />
3.7 Conclusion<br />
Parameters Values<br />
Maximum Frequency 723.668 MHz<br />
Device Virtex 2 pro - XC2VP30<br />
Number of Slices 496<br />
Slices available 13696<br />
Percentage of utilization 3<br />
In this chapter, we have proposed and discussed a novel <strong>architecture</strong> <strong>for</strong> a modulo<br />
multiplier <strong>for</strong> the IDEA cipher. The multiplication approach is quite efficient in<br />
terms of number of partial products (which is less than
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