FPGA Based Network Security architecture for High Speed Networks
FPGA Based Network Security architecture for High Speed Networks
FPGA Based Network Security architecture for High Speed Networks
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Figure 2.2: IDEA Encryption key Generation<br />
2.3 Related Work<br />
as to provide the quality of service.In this scenario, a software implementations<br />
of such algorithm using general purpose processors due to delay in instruction<br />
processing.But such speed can be easily achieved when implemented in hard-<br />
ware.Although the software implementation is less costly than hardware imple-<br />
mentation, the speed up in hardware is very high.So <strong>for</strong> flexibility,availability and<br />
high functionality, there is a need of incorporating a separate cryptographic mod-<br />
ule in such applications.<br />
Although IDEA involves only simple 16-bit operations, software implemen-<br />
tations of this algorithm still cannot offer the encryption rate required <strong>for</strong> on-<br />
line encryption in high-speed networks.IDEA has been previously implemented in<br />
hardware using various <strong>FPGA</strong> devices and even ASIC. Like other renowned sym-<br />
metric key block ciphers, IDEA contains no S-Boxes or P- Boxes. So there is a less<br />
memory overhead.Instead it has some basic building blocks like EX-OR, addition<br />
modulo 2
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