FPGA Based Network Security architecture for High Speed Networks
FPGA Based Network Security architecture for High Speed Networks
FPGA Based Network Security architecture for High Speed Networks
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3.5 Complexity of the proposed multiplier :<br />
Figure 3.1: Architecture of six-stage pipelined new modulo (2 16 + 1) multiplier <strong>for</strong><br />
IDEA<br />
3.5 Complexity of the proposed multiplier :<br />
The qualitative comparison of the proposed multiplier is made using unit gate<br />
model as proposed by Tyagi [29]. According to this model, an Ex-OR/ Ex-NOR<br />
gate is charged 2 gate delay units and a delay through an elementary gate is taken<br />
as 1 gate delay units. The latency <strong>for</strong> the proposed multiplier consists of the<br />
delay of the PPDG module, the delay of the CSA tree and the delay of the final<br />
diminished-one adder. The PPDG module consists of BE, BS and one diminished-<br />
one adder. The delay in diminished-one adder as given in [28] is 2⌈log 2
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