FPGA Based Network Security architecture for High Speed Networks

List of Figures
2.1 Data flow of IDEA Cipher . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 IDEA Encryption key Generation . . . . . . . . . . . . . . . . . . . 11
3.1 Architecture of six-stage pipelined new modulo (2 16 + 1) multiplier
for IDEA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Multiplier giving output in the 7th clock cycle . . . . . . . . . . . . 28
4.1 A single inner round pipelined architecture for IDEA with 24 pipeline
stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2 Basic Iterative architecture with inner round pipelining for IDEA . 33
4.3 Partial mixed inner and outer round pipelined architecture for IDEA 33
4.4 Full mixed inner and outer round pipelined architecture for IDEA . 35
5.1 Basic Architecture for Signature based NIDS . . . . . . . . . . . . . 41
5.2 A Typical Bloom Filter with an Analyzer . . . . . . . . . . . . . . . 45
5.3 Parallel Bloom Filter Matching a fixed sized pattern [1]. . . . . . . 46
5.4 A series of Bloom Filters matching variable sized patterns at a time [1]. 47
5.5 Partial Bloom Filter accepting 2 Hash Functions [2] . . . . . . . . . 49
5.6 Large Bloom Filter using a series of PBFs [2] . . . . . . . . . . . . . 50
5.7 Test-bench for the Hash Function Generator . . . . . . . . . . . . . 51
5.8 Timing Summary for Hash Generator Module . . . . . . . . . . . . 52
5.9 Waveform for the overall design for Bloom Filter. Diagram shows
the waveform when the supplied Hash values exactly matches with
the hash values of the member string, the match signal becomes high 52
5.10 Timing Summary for the Bloom Filter . . . . . . . . . . . . . . . . 53
vii