FPGA Based Network Security architecture for High Speed Networks

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Background Introduction Symmetric key Cryptosystem Previous implementations of IDEA in Hardware Conclusion
Chapter 2 Background 2.1 Introduction In this chapter, we have discussed the basic theory and algorithm for International data Encryption algorithm (IDEA), a symmetric block cipher, which is selected as a cipher for implementation in FPGA technology. This chapter consists of two parts. In the first part, the IDEA algorithm and basics have been discussed. In the second part, a detailed literature study of the previous implementations of IDEA in hardware is covered. 2.2 Symmetric key Cryptosystem In symmetric key cryptography, the encryption and decryption process is done by the same key which is the secret key. This secret key is shared prior to the encryption process and remains constant during the process. In our work, we have used International Data Encryption Algorithm as the symmetric key block cipher module and we focussed mainly on reducing the round complexity and increasing the throughput for the overall design. 2.2.1 IDEA Encryption Algorithm The proposed Encryption Standard (PES) is a block cipher introduced by Lai and Massey [4, 5]. It was then improved by the Lai, Massey and Murphy in 1991. This version, with stronger security against differential analysis and truncated differentials, was called the Improved PES (IPES). IPES was renamed to be the 8
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Page 3 and 4: Department of Computer Science and
Page 5 and 6: Abstract Cryptography and Network S
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Page 9 and 10: List of Tables 3.1 Device utilizati
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Page 13 and 14: 1.2 Problem Statement cannot guaran
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Page 21 and 22: 2.3 Related Work put rate and the a
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Page 27 and 28: 2.4 Conclusion efficient VLSI imple
Page 29 and 30: Chapter 3 Modulo (2 16 + 1) multipl
Page 31 and 32: 3.3 Algorithm for the proposed mult
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Page 35 and 36: 3.4 Proposed multiplier architectur
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Page 39 and 40: Design and Implementation of IDEA I
Page 41 and 42: 4.2 Design and Architecture using p
Page 43 and 44: 4.3 Result and comparison with othe
Page 45 and 46: 4.4 Conclusion Table 4.1: Compariso
Page 47 and 48: FPGA based string matching for NIDS
Page 49 and 50: 5.1 Introduction are primarily focu
Page 51 and 52: 5.2 Basic Idea and Related work tha
Page 53 and 54: filter is described in subsequent s
Page 55 and 56: 5.3 Proposed Design matching module
Page 57 and 58: 5.4.1 Implementation Constraints 5.
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Page 61 and 62: Figure 5.8: Timing Summary for Hash
Page 63 and 64: 5.5 Conclusion to in line speed. In
Page 65 and 66: Chapter 6 Conclusion and Future Wor
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Bibliography [8] A.V. Curiger, H. B
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Bibliography [25] M. Thaduri, S.-M.
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Bibliography [43] Sarang Dharmapuri
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FPGA Based Network Security architecture for High Speed Networks

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