FPGA Based Network Security architecture for High Speed Networks

4.3 Result and comparison with other schemes
Figure 4.4: Full mixed inner and outer round pipelined architecture for IDEA
chosen as Virtex II pro . The design is synthesized using VHDL and the func-
tionality verification is made using Chipscope pro. The comparison shows that
as the number of pipelined stages increases, the throughput increases but the
slice counts also increases to a certain amount. Due to this, the throughput to
area ratio decreases slightly. However, this trade-off can be accepted as long as
throughput is getting optimized. It is to be noted that in this design, no embed-
ded multipliers are used and so there is no restriction in number of multipliers to
be used. While implementing IDEA on Virtex II pro, using full mixed outer and
inner round pipelining approach , it is found that all the rounds of IDEA cannot
be accommodated in the device. So only 6 rounds are unrolled and implemented
for verification.
A brief comparison of performance is made in Table 4.2 between our design
and some existing designs of [33], [32] and [24]. The comparison is made based on
the parameters like Throughput, Slice counts, Latency etc.
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