Programmable Logic and Application Specific Integrated Circuits

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technologies. These techniques are identical to those described for PALs and PLDs in the previous section, and will not be discussed further here. An alternative method to personalize FPGA devices is to physically program the routing connections. Commercial products which use programmable routing approaches have been introduced by Actel, QuickLogic, and others. In Actel FPGAs, a Programmable Low-Impedance Circuit Element (PLICE) anti-fuse element is used. 12 The anti-fuse resistance which is normally very high (>100MΩ) is permanently changed to a low resistance (200-500Ω) by the application of appropriate programming voltages. The programmed anti-fuse is used to make a direct electrical connection between two metal lines as shown in the layout view of Figure 9. The PLICE anti-fuse is manufactured by adding three specialized masks to a standard CMOS process. The physical structure, identified at the center of Figure 9, consists of an Oxide-Nitride-Oxide dielectric layer sandwiched between a top polysilicon layer and a bottom N+ diffusion layer. Programming is accomplished by applying a relatively high voltage (18V) across the device and driving a high current through the link dielectric. This causes the dielectric to melt and results in a conductive link between the top and bottom terminals. QuickLogic also adds a unique three layer structure to the standard CMOS process to create their anti-fuse element; which they call a ViaLink. 13 The ViaLink uses an amorphous silicon layer which is sandwiched between the first and second metal layers. An unprogrammed ViaLink has greater than 1GΩ resistance and, like the PLICE anti-fuse, is programmed by applying a higher than normal voltage. The resulting high current through the amorphous layer causes it to permanently change to a conductive state with a typical resistance of only 80Ω. The area occupied by these anti-fuse elements is very small when compared to the other programming alternatives. While this contributes to improved on-chip gate density, it is somewhat offset by the large area required for the high-voltage transistors needed to support programming. An additional disadvantage of the anti-fuse technologies is that they require modifications to the standard CMOS process. 18
N+ Diffusion Poly-Si 19 Anti-Fuse Metal 2 Metal 1 Figure 9. PLICE Anti-fuse Programmable Interconnect The Static Random Access Memory (SRAM) FPGA programming technology which was first introduced by Xilinx is also used in designs by Algotronix, Plessey, AT&T, and others. Programmable connections in these FPGAs are made using multiplexers, transmission gates, or pass transistors that are controlled by information stored in SRAM cells. Since the static RAM is volatile, these FPGAs must be programmed to set the circuit configuration each time that power is applied to the chip. This can be accomplished automatically through a serial connection to an attached ROM (PROM) or controller; or in parallel by an attached processor or controller which address the FPGA in parallel as a normal static RAM. The chip area required by the SRAM logic and interconnect programming circuitry is the largest of the FPGA technologies described here. A typical SRAM cell uses 5 or 6 transistors, and additional devices are needed for the transmission gates or multiplexers. However, these devices are produced using standard CMOS SRAM fabrication techniques, and thus can immediately benefit from advances in SRAM CMOS processes. The non-volatile nature of the SRAM programming can be viewed alternatively as either a disadvantage or as a major advantage. Programming imposes a system level overhead in terms of ROM storage and power-on initialization time. The fact that additional programming powersupply voltages are not required is an advantage for SRAM-based devices. However, the greatest system level benefit of this technology is that SRAM FPGAs can be re-programmed in-circuit to make system modifications and upgrades; or to perform multiple functions with the same base hardware.
Page 1 and 2: Programmable Logic and Application
Page 3 and 4: I. Introduction to ASICs and Progra
Page 5 and 6: 1. Full Custom Design In the classi
Page 7 and 8: Table 1. ASIC Market Forecast (pred
Page 9 and 10: has been slowly expanding from its
Page 11 and 12: It is a tautology in the electronic
Page 13 and 14: A. Programmable Logic Devices Progr
Page 15 and 16: programmed transistor uses a floati
Page 17: B. Field Programmable Gate Arrays F
Page 21 and 22: 2. FPGA Architectures FPGAs are com
Page 23 and 24: a) Symmetrical Array FPGA Example:
Page 25 and 26: Figure 12. Xilinx XC4000 Family Con
Page 27 and 28: A0 A1 SA S1 2:1 MUX 2:1 MUX 27 2:1
Page 29 and 30: hierarchically constructed from mac
Page 31 and 32: Logic Cell Logic Cell Logic Cell Lo
Page 33 and 34: Examples of vendor specific tools a
Page 35 and 36: operation, each CLB generated durin
Page 37 and 38: connections, to test adjacent non-F
Page 39 and 40: Toshiba America TC183/180/ Electron
Page 41 and 42: V. Standard Cell and Custom ASICs I
Page 43 and 44: combinations of full custom and sta
Page 45 and 46: functionality of the system (IC) is
Page 47 and 48: Ad hoc methods generally consist of
Page 49 and 50: D C I A B D C I A B L 1 L 1 49 L 2
Page 51 and 52: interpreting commands, a boundary s
Page 53 and 54: industrial applications such as mot
Page 55 and 56: 20 FLEX 8000 Programmable Logic Dev

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