Programmable Logic and Application Specific Integrated Circuits

c) Hierarchical PLD Example: Altera
The Altera Multiple Array MatriX (MAX) architecture is quite different from those
discussed previously in this chapter. This architecture represents a hierarchical arrangement of
Erasable Programmable Logic Devices (EPLDs) using a two-dimensional array structure. The
design provides multiple level logic, uses a programmable routing structure, and is user reprogrammable
based on EPROM or EEPROM technology. Thus, although these devices are
marketed by Altera as EPLDs, they clearly meet the criteria to be called FPGAs in the context of
this chapter.
The MAX 5000 series and second generation MAX 7000 series architectures consist of an
array of large programmable blocks, called Logic Array Blocks (LABs). 18 19 Each LAB in the
MAX 7000 family is constructed from 16 macrocells. Each macrocell in turn has a
programmable-AND / fixed-OR array and a configurable register. Thus, each macrocell
represents a small PLD with five programmable product terms, and it can be configured for either
sequential or combinatorial operation. Complex logic functions can be constructed using multiple
macrocells. In addition, the Altera LAB architecture provides both shareable and parallel
expander product terms (“expanders”) that can be used to create additional product terms directly
to any macrocell in the same LAB. Finally, at the top level of the design hierarchy, signals are
routed between LABs by a Programmable Interconnect Array (PIA). This global routing resource
connects any signal source to any destination on the chip. Figure 16 shows a portion of the MAX
7000 architecture; and illustrates the Programmable Interconnect Array (PIA), Logic Array Block
(LAB) with its constituent macrocells, and I/O Control (IOC) block.
figure 1 from MAX 7000 data book........
Figure 16. Altera MAX 7000 Internal Architecture
Table 8 lists a summary of the characteristics of the first and second generation MAX 5000
and MAX 7000 families. The FLEX 8000 series Altera design listed in the table departs from the
earlier families in its use of SRAM programming technology. 20 This series continues Altera’s
fine-grain hierarchical architecture by using 4-input look-up table Logic Elements (LEs) as the
basic functional building block. LE’s are grouped into sets of eight to create LABs as in the
earlier family designs; and these blocks are arranged into rows and columns. Connections
between LEs are provided by horizontal and vertical FastTrack interconnect channels which span
the chip. Both the Logic Elements and the FastTrack interconnects are SRAM programmed in an
analogous fashion to the Xilinx technology discussed earlier. The MAX 9000 family identified in
the table is a third generation Multiple Array MatriX architecture which has features of both the
MAX 7000 and FLEX 7000 families. 21 It uses EEPROM non-volatile programming, and logic is
28