Programmable Logic and Application Specific Integrated Circuits

etter suited for designs dominated by datapath constructs, and may be poorly suited for
synthesizing a complex control logic problem.
2.) Behavioral models generally contain little timing information; this information must be
added in the form of constraints on the synthesis process. Designs whose I/O signal timing
requires irregular patterns will be difficult to automate because the tool cannot know when
they must be scheduled. A design with extensive critical timing may require so much effort
to manually guide the tool that synthesis cannot be justified.
3.) Most behavioral synthesis tools cannot automatically generate asynchronous designs
since they assume fully synchronous circuit operation. Furthermore, most synthesis
approaches assume a single-phase edge-triggered clocking scheme. If a design requires
multiple phase clocks or multiple clock signals, then some of the less automated synthesis
tools may perform better.
The two major languages for behavioral synthesis are the Verilog HDL and the VHSIC
HDL (VHDL). Although Verilog has the advantage of a longer time on the market, the
standardization of VHDL by the military and by the IEEE standards group (IEEE 1076) has made it
a strong contender. Both languages are flourishing today and Verilog may soon be approved as an
IEEE standard. Thus, it is not clear that either language will become a dominant standard in the
near future. Commercial behavioral synthesis tools are available which use both VHDL and
Verilog, as well as a host of proprietary HDLs. An indication that behavioral synthesis is entering
the mainstream of ASIC design is given by the June 1994 survey of HDL tool vendors which
identifies 75 companies who offer HDL tools. 37
B. Design for Testability
A high confidence manufacturing test is needed to verify that fabricated ASICs or
programmed logic devices are structurally correct. End users typically apply functional test
vectors derived from simulation to verify simple low volume PLD designs. However, foundries
generally employ a high coverage Single-Stuck-At (SSA) test to meet manufacturing test
requirements. An SSA test identifies nodes within the chip which are “stuck-at-one” or “stuck-atzero”;
and may also identify many faults which fall into the other two principal static fault
categories of bridging and stuck open. 38 When designing a testable ASIC we must consider any
added hardware and I/O overhead necessary to meet manufacturing test requirements (typically
>98% SSA fault coverage). Testability enhancement techniques that can improve ASIC
manufacturing test coverage fall into three categories:
• Ad Hoc
• Structured Design for Testability
• Built-In Self-Test
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