Programmable Logic and Application Specific Integrated Circuits

In the Actel ACT family FPGAs a logic module matrix is arranged as rows of cells
separated by horizontal wiring channels, as previously illustrated in Figure 10.B. This
organization is similar to that found in the traditional style of Mask Programmed Gate Arrays
(MPGAs). Vertical interconnect segments of varying lengths are available. Vertical segments in
input tracks are permanently connected to logic module inputs, and vertical segments in output
tracks are permanently connected to logic module outputs. Long vertical segments are available
which are uncommitted and can be assigned during routing. The horizontal wiring channel
resources are also segmented into varying lengths. The minimum horizontal segment length is the
width of a single logic module, and the maximum horizontal segment length spans the full channel.
Any segment that spans more than one-third of the row length is considered a “long horizontal
segment”. Connections between interconnect segments are permanently formed using the PLICE
antifuse which was described earlier in this chapter. Dedicated routing tracks are used for global
clock distribution and for power and ground tie-off connections. Actel has three generations of
FPGAs, denoted ACT1, ACT2, and ACT3 16 , whose characteristics are listed in Table 7.
Family Series Number of
User I/O
Table 7. ACTEL FPGA Family Characteristics
Number of
Logic Modules
26
Number of
FFs
Typical Gate-Array
Equivalent Gates
ACT-1 57-69 295-547 147-273 1,200-2,000
ACT-2 83-140 451-1,232 382-998 2,500-8,000
ACT-3 80-228 200-1,377 264-1,153 1,500-10,000
In contrast to the Xilinx FPGA which uses a relatively complex CLB cell, the Actel
approach uses small and simple logic modules. This does not imply that the Actel design has
inherent disadvantages compared to the Xilinx approach. Research by Singh et. al. has shown that
both of these approaches have merit. 17 Their results indicate that the best choice for a
programmable block depends on the speed performance and the area requirements of the routing
architecture. The low-impedance and small area Actel antifuse structure is better suited for use
with a simple logic module; whereas the larger area and higher resistance Xilinx SRAM
controlled transistor switch is more appropriate for a complex logic cell.
The ACT1 family Logic Module (LM) is an 8-input, one output function which can be used
to construct the four primitive logic function (AND, OR, NAND, NOR) with two through four
inputs. Figure 15 shows how the basic ACT1 Logic Module circuit uses multiplexers to create
programmable logic functions. The LMs can also be used to construct latches, flip-flops, XORs,
AND-ORs and other logic structures. Actel does not include dedicated hardwired latches or flipflops
in the ACT1 array since they can be constructed from LMs wherever needed in the design.
The ACT1 family uses 22 metal signal wiring tracks in each horizontal channel and 13 vertical
tracks that lie on top of each column of LMs.