Programmable Logic and Application Specific Integrated Circuits

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North South East West G2 G1 North South East West 6:1 MUX 4:1 MUX X1 X2 0 1 2:1 MUX 2:1 MUX 4:1 MUX 32 Function Unit OUT Figure 20. Algotronix Logic Cell Function Unit Design A unique feature in the Algotronix I/O pad design is its capability to provide simultaneous input and output on the same pin when communicating with another Algotronix chip. This is done through a 3-level (ternary) logic signaling scheme in which I/O pads sense whenever two outputs are driving each other via a contention scheme. Even during contention, the pad can deduce the correct input value and pass it along to the internal circuitry. This makes it easier to partition a single design across multiple FPGAs because the increased connectivity reduces pin limitations on communications bandwidth. 3. FPGA Design Flow Although early PLD and FPGA designs were generated largely by hand, access to today’s complex programmable logic devices requires the use of an integrated Computer-Aided Design (CAD) system. Figure 21 illustrates the typical sequence of operations needed to go from concept to programmed chip. Both commercial CAD tool vendors and FPGA companies offer appropriate tools. For example, traditional Electronic Design Automation (EDA) vendors such as Cadence, Mentor Graphics, Synopsys, and ViewLogic all offer tools to support FPGA design. These tools are typically used for the front-end design entry and simulation operations and provide the necessary interfaces to vendor-specific back-end tools for chip placement and routing.
Examples of vendor specific tools are the Xilinx XACT system and the Altera MAX+PLUS II software. It is worth noting that Altera’s MAX+PLUS II software supports the entire design flow illustrated in Figure 21 on either PC or workstation platforms. A detailed discussion of available FPGA CAD tools is outside the scope of this chapter. Rather, the following discussion is meant to be indicative of the general operations and steps required in FPGA design. Where appropriate, examples are taken from the Xilinx and Altera CAD design flows to illustrate the generic operations. Cadence, Mentor, ViewLogic, OrCAD, MAX+II, etc SCHEMATIC CAPTURE & Simulation LOGIC OPTIMIZATION Merge Design Technology Mapping Circuit of PFGA Cells Automatic PLACEMENT Circuit Mapped to target FPGA Image Automatic ROUTING FPGA Physical Design Complete critical path timing analysis and back-annotation to simulation DOWNLOAD or PROGRAM FPGA 33 BEHAVIORAL SPECIFICATION & Simulation SYNTHESIS including Optmization Figure 21. Typical CAD System Design Flow for FPGAs VHDL, Verilog PALASM, ABEL, PLDesigner,, etc. Evaluate Design in Target Application
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Programmable Logic and Application Specific Integrated Circuits

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