Programmable Logic and Application Specific Integrated Circuits

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Table 4 provides a summary of the characteristics of the four FPGA programming styles just discussed. Exact comparisons by class are difficult since different vendors products are fabricated using different CMOS processes. Thus, the cell area and the resistance and capacitance values for the on-state of the programmable elements are only meant for relative comparison. Programming Technology Table 4. Summary of FPGA Programming Characteristics Re- Programmable Volatile Storage 20 Series Resistance Capacitance in ff. Cell Area Static RAM in-circuit yes 1KΩ 15 5X Anti-Fuse no no 50-500Ω 1.2-5.0 1X EPROM outside circuit no 2KΩ 10 1X EEPROM in-circuit no 2KΩ 10 2X
2. FPGA Architectures FPGAs are commercially available in many different architectures and organizations. Although each company’s offerings have unique characteristics, FPGA architectures can be generically classified into one of four categories: Symmetrical Array, Row Based, Hierarchical PLD, and Sea of Gates. 4 Figure 10 illustrates this classification based on the general internal organization of the design. In the interest of space, only a single vendor for each design style will be described in detail in the following four subsections. However, this does not indicate any preference or endorsement for these particular product offerings. Table 5 lists examples of the extensive range of choices in commercial FPGA products. 10 A. SYMMETRICAL ARRAY B. ROW BASED C. HIERARCHICAL PLD D. SEA-OF-GATES Figure 10. The Four FPGA Architectural Classes 21
Page 1 and 2: Programmable Logic and Application
Page 3 and 4: I. Introduction to ASICs and Progra
Page 5 and 6: 1. Full Custom Design In the classi
Page 7 and 8: Table 1. ASIC Market Forecast (pred
Page 9 and 10: has been slowly expanding from its
Page 11 and 12: It is a tautology in the electronic
Page 13 and 14: A. Programmable Logic Devices Progr
Page 15 and 16: programmed transistor uses a floati
Page 17 and 18: B. Field Programmable Gate Arrays F
Page 19: N+ Diffusion Poly-Si 19 Anti-Fuse M
Page 23 and 24: a) Symmetrical Array FPGA Example:
Page 25 and 26: Figure 12. Xilinx XC4000 Family Con
Page 27 and 28: A0 A1 SA S1 2:1 MUX 2:1 MUX 27 2:1
Page 29 and 30: hierarchically constructed from mac
Page 31 and 32: Logic Cell Logic Cell Logic Cell Lo
Page 33 and 34: Examples of vendor specific tools a
Page 35 and 36: operation, each CLB generated durin
Page 37 and 38: connections, to test adjacent non-F
Page 39 and 40: Toshiba America TC183/180/ Electron
Page 41 and 42: V. Standard Cell and Custom ASICs I
Page 43 and 44: combinations of full custom and sta
Page 45 and 46: functionality of the system (IC) is
Page 47 and 48: Ad hoc methods generally consist of
Page 49 and 50: D C I A B D C I A B L 1 L 1 49 L 2
Page 51 and 52: interpreting commands, a boundary s
Page 53 and 54: industrial applications such as mot
Page 55 and 56: 20 FLEX 8000 Programmable Logic Dev

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