MNEMEE - Electronic Systems - Technische Universiteit Eindhoven

For multimedia application this is often the case, provided that the application can be analyzed and
optimized sufficiently at compile time. Moreover, the cycle cost for the solution on the right can
become even less than the sum of C2a and C2b if the block transfers between the two memories can
be handed over to a DMA controller, which can operate in parallel with the processor.
This is, in effect, the same principle as the one behind hardware caches, except that hardware caches
cannot exploit application knowledge, and energy consumption in caches is typically much higher than
for a simple local memory. By using software controlled local memories and application knowledge,
hardware caches can be beaten both in terms of performance and in terms of energy consumption.
Work flow
Figure 20 - Exploiting the memory hierarchy.
The proposed work flow for identifying the available re-use in an application and for assessing
the potential to exploit this re-use is depicted in
Figure 21.
The coloured blocks suggest different tools used in particular stages. The details of the tools used in
this workflow have been discussed in Section 8.4.
First, the application, specified in C source code, is profiled both for array accesses and cycle counts.
The application source code was produced maintaining CleanC specifications. The Atomium toolset is
used for the profiling. The information is stored in a database, from which reports can be generated.
This allows the designer to identify the most important data-structures and the most important code
sections. The profiling information is further used to quantify the potential gains in the platformspecific
part of the flow.
The re-use analysis identifies potential re-use buffers. These so-called copy-candidates can be depicted
in a graph for inspection by the designer. The information is also passed on to the next stage, where
the most profitable set of copy-candidates is selected for a specific platform. This trade-off between
different solutions is made based on the copy-candidate information, profiling data and the platform
description. For each solution the cost in terms of cycle counts and power consumption can be
estimated. Moreover, a schedule of the data-transfers and data-life-times can be constructed. The MH
tool is used for this analysis.
Finally, once a solution has been selected, the source code can be transformed to include the re-use
buffers and data-transfers.
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