MNEMEE - Electronic Systems - Technische Universiteit Eindhoven

• Read energy: the (average) energy needed for a read access. As for cycles, each access mode
can have a different figure.
• Write energy: the (average) energy needed for a write access. This is similar to the energy
needed for a read access.
• Static power consumption of a single memory module.
• Maximum size of a memory module. If a memory partition of this type has a larger word
depth, it is must consist of multiple modules.
Processor partitions
A processor partition represents a set of processors (possibly only one) with similar characteristics and
that share their connections to the memory partitions.
DMA controllers
The transfers of data between different memory layers (i.e., the loading and storing of copies), can
often be handled very efficiently by a direct memory access (DMA) controller. A DMA controller can
typically perform transfers independently, while the processor is processing other data. Data re-use can
be better exploited such DMA controllers is present in a platform. Only a high-level model of the
controllers is needed. Its specification should include the following properties:
• Possible source and destination memory partitions for transfers
• Maximum number of transfers that can be handled in parallel by the unit.
• Cycle cost of a DMA transfer. The cost can be derived from 4 parameters:
o Processor overhead: the number of cycles it takes for the processor to set up a DMA
transfer, and during which it cannot perform other processing.
o DMA overhead: the number of cycles it takes for the DMA unit to prepare a whole
transfer, after it has received the necessary parameters from the processor.
o Line setup: the number of cycles it takes for the DMA unit to prepare the transfer of a
line of data. A line of data consists of a set of elements that can be transferred at once.
Usually, they are stored in adjacent addresses, but they could be separated by a certain
stride.
o Line gap: the number of cycles it takes for the DMA unit to switch to another line.
Connections
To optimize the allocation and assignment of copy candidates to memory partitions, it should be
known, which transfers the architecture allows. For instance, it needs to be known whether there is a
connection between memory partitions that the DMA controller can use to transfer data. Also, the
memory partitions which are directly accessible by the processor partition need to be known. It is
possible that all accesses to a background memory must pass via an on-chip local memory, for
instance, because the processor has no direct access to the background memory.
Copy selection and assignment
In the assignment phase, a set of copy-candidates is selected and assigned to the memory layers such
that an optimal solution is obtained.
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