CV - Electronic Systems

Curriculum Vitae of Kees Goossens
1 Personal Details
Name: Kees Gerard Willem Goossens.
Nationality: Netherlands.
Last updated January 2, 2013.
Work address:
Electronic Systems group, Faculty of Electrical Engineering
Eindhoven University of Technology (TU/e)
Potentiaal/PT 9.34, Den Dolech 2, 5612 AZ, Eindhoven, The Netherlands.
Tel. +31-40-2473404.
Work email: k.g.w.goossens@tue.nl
Qualifications: BSc (Hons) Wales, PhD (Edinburgh), Professor (Eindhoven).
Contents
1 Personal Details 1
2 Education 2
3 Employment History 2
4 Publications 3
4.1 Thesis and (Edited) Books . . . . . . . . . . . . . . . . . . . . . . . . . 3
4.2 Book Chapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.3 Journal and Magazine Articles . . . . . . . . . . . . . . . . . . . . . . 5
4.4 Peer-Reviewed International Conference Articles . . . . . . . . . . . . 7
4.5 Invited publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6 Special sessions and tutorials . . . . . . . . . . . . . . . . . . . . . . . 17
4.7 Local Conferences, Posters, etc. . . . . . . . . . . . . . . . . . . . . . . 17
4.8 Paper Awards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.9 Press Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.10 Technical Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Patents 24
5.1 Granted patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2 Published pending patents . . . . . . . . . . . . . . . . . . . . . . . . . 25
6 Professional Activities 26
6.1 Research Grants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2 Other Professional Activities . . . . . . . . . . . . . . . . . . . . . . . 27
6.3 Journal & Conference Reviewing . . . . . . . . . . . . . . . . . . . . . 28
6.4 Teaching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.5 Organised Tutorials, Special Sessions, etc. . . . . . . . . . . . . . . . . 31
6.6 Invited Presentations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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6.7 Invited Lectures, Tutorials, etc. . . . . . . . . . . . . . . . . . . . . . . 34
7 Mangement, Promotions, Supervision 35
7.1 Promotor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2 PhD Committees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3 Team Leader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.4 PhD Advisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5 Visiting researchers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.6 PDEng Advisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.7 MSc Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.8 MSc graduation committees . . . . . . . . . . . . . . . . . . . . . . . . 41
7.9 Bachelor Project Supervision . . . . . . . . . . . . . . . . . . . . . . . 42
8 Committees 42
9 Research Interests 42
10 Miscellaneous 43
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2 Education
1978 to 1984
Secondary school: Cobbenhagen College, Brittendreef 5, 5012 AE Tilburg,
The Netherlands. Completing the VWO secondary education (Preparatory
Scientific Education) gives a right of entry to a Dutch university.
October 1984 to June 1986 and October 1987 to June 1988
Undergraduate degree in Computer Science and Pure Mathematics at the
University College of Wales, Aberystwyth. Department of Computer Science,
Penglais, Aberystwyth, SY23 3BZ, Dyfed, Wales.
I received a class II(i) BSc (Hons) degree.
October 1988 to December 1992
27 May 1993 PhD defence (viva). Postgraduate degree (PhD) at the Laboratory
for Foundations of Computer Science, Department of Computer
Science. University of Edinburgh. James Clerk Maxwell Building, The
King’s Buildings, Edinburgh EH9 3JZ, Scotland.
In my thesis, Embedding Hardware Description Languages in Proof Systems,
I gave a static and dynamic operational semantics for a subset of the
ella hardware description language, and embedded this semantics in the
higher-order-logic proof system Lambda, and proved various properties
about the embedded semantics, formal hardware synthesis, and symbolic
simulation. Prof. M. P. Fourman was my promotor.
3 Employment History
4 August 1986 to 24 July 1987
Full-time employment as a software engineer at Praxis Systems Plc. 20
Manvers Street, Bath BA1 1PX, England.
One project involved porting a relational database from a personal computer
to a mini computer, another implementing various parts of a compiler
(Algol68 to C translator).
October 1988 to July 1991
Part-time employment as an undergraduate supervisor (for first-year students)
and tutor (for third-year students) at the Department of Computer
Science, University of Edinburgh, Scotland.
1 July 1991 to 30 August 1992
Part-time (0.5 FTE) appointment as a research associate at the Department
of Computer Science, University of Edinburgh, Scotland on the
SERC-funded project Formal System Design Tools.
1 December 1992 to 31 September 1993
Full-time appointment as a research fellow at the Department of Computer
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Science, University of Edinburgh, Scotland on the SERC-funded project
Formal System Design Tools.
1 October 1993 to 31 March 1994
Full-time appointment as a visiting researcher at the Departamento de
Informatica, Universidade Federal de Pernambuco at Recife, Brazil on the
CNPq-funded project Encoding Relational Semantics in Automated Proof
Systems.
1 May 1994 to 31 May 1995
Full-time appointment as a visiting researcher on the EEC-funded Human
Capital and Mobility project Euroform at the Dipartimento di Scienze
dell’Informazione, Università di Roma “La Sapienza,” Italy and at the
Departimento di Automatica e Informatica, Politecnico di Torino, Italy.
I developed formal operational and observational semantics for VHDL
inspired by process calculi.
16 September 1995 to 31 December 2009
Full-time appointment as senior research scientist, at the Natuurkundig
Laboratorium, Philips Research Laboratories in the Netherlands.
As of 1 March 2004, full-time appointment as principal research scientist.
1 February 2007 to 31 December 2009
Three-year appointment as a part-time (0.2 FTE) full professor (“buitengewoon
hoogleraar”) in VLSI Design at the Computer Engineering (CE)
division within the Electrical Engineering, Mathematics and Computer
Science (EEMCS) faculty of the Delft University of Technology.
1 January 2010 to present
Full-time full professor in Real-Time Embedded Systems in the Electronics
Systems group within the Electrical Engineering faculty of the Eindhoven
University of Technology.
1 January 2012 to present
Part-time consultant with K.G.W. Goossens Consultancy.
4 Publications
4.1 Thesis and (Edited) Books
1. Kees G. W. Goossens. Embedding Hardware Description Languages in
Proof Systems. PhD thesis, Laboratory for Foundations of Computer
Science, Department of Computer Science, University of Edinburgh, May
1993.
2. Kees Goossens and Laure Petrucci, editors. Sixth International Conference
on Applications of Concurrency to System Design (ACSD), Turku,
Finland, June 2006. IEEE.
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3. Koen Bertels, Sorin Cotofana, Georgi N. Gaydadjiev, Kees Goossens, Said
Hamdioui, Arjan van Genderen, and Stephan Wong, editors. The Future
of Computing — Essays in Memory of Stamatis Vassiliadis. September
2007.
4. Andreas Hansson and Kees Goossens. On-Chip Interconnect with aelite:
Composable and Predictable Systems. Embedded Systems Series. Springer,
November 2010.
5. Benny Akesson and Kees Goossens. Memory Controllers for Real-Time
Embedded Systems. Embedded Systems Series. Springer, September 2011.
4.2 Book Chapters
1. Kees Goossens, John Dielissen, Jef van Meerbergen, Peter Poplavko, Andrei
Rădulescu, Edwin Rijpkema, Erwin Waterlander, and Paul Wielage.
Guaranteeing the quality of services in networks on chip. In Axel Jantsch
and Hannu Tenhunen, editors, Networks on Chip, chapter 4, pages 61–82.
Kluwer Academic Publishers, Hingham, MA, USA, 2003.
2. Andrei Rădulescu and Kees Goossens. Communication services for networks
on chip. In Shuvra S. Bhattacharyya, Ed F. Deprettere, and Jürgen
Teich, editors, Domain-Specific Processors: Systems, Architectures, Modeling,
and Simulation, pages 193–213. Marcel Dekker, 2004.
3. Kees Goossens, Om Prakash Gangwal, Jens Röver, and A. P. Niranjan.
Interconnect and memory organization in SOCs for advanced set-top boxes
and TV — Evolution, analysis, and trends. In Jari Nurmi, Hannu Tenhunen,
Jouni Isoaho, and Axel Jantsch, editors, Interconnect-Centric Design
for Advanced SoC and NoC, chapter 15, pages 399–423. Kluwer,
2004.
4. Kees Goossens, Santiago González Pestana, John Dielissen, Om Prakash
Gangwal, Jef van Meerbergen, Andrei Rădulescu, Edwin Rijpkema, and
Paul Wielage. Service-based design of systems on chip and networks
on chip. In Peter van der Stok, editor, Dynamic and Robust Streaming
In And Between Connected Consumer-Electronics Devices, volume 3 of
Philips Research Book Series, chapter 2, pages 37–60. Springer, 2005.
5. Om Prakash Gangwal, Andrei Rădulescu, Kees Goossens, Santiago González Pestana,
and Edwin Rijpkema. Building predictable systems on chip: An
analysis of guaranteed communication in the Æthereal network on chip.
In Peter van der Stok, editor, Dynamic and Robust Streaming In And
Between Connected Consumer-Electronics Devices, volume 3 of Philips
Research Book Series, chapter 1, pages 1–36. Springer, 2005.
6. Israel Cidon and Kees Goossens. Network and transport layers in networks
on chip. In Giovanni De Micheli and Luca Benini, editors, Networks on
Chips: Technology and Tools, The Morgan Kaufmann Series in Systems
on Silicon, chapter 5, pages 147–202. Morgan Kaufmann, July 2006.
7. Arno Moonen, Chris Bartels, Marco Bekooij, René van den Berg, Harpreet
Bhullar, Kees Goossens, Patrick Groeneveld, Jos Huiskens, and Jef van
Meerbergen. Comparison of an Aethereal network on chip and tradi-
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tional interconnects - two case studies. In Giovanni De Micheli, Salvador
Mir, and Ricardo Reis, editors, VLSI-SoC: Research Trends in VLSI and
Systems on Chip, volume 249 of IFIP International Federation for Information
Processing, pages 317–336. Springer, 2007.
8. E. Rijpkema, K. G. W. Goossens, A. Rădulescu, J. Dielissen, J. van Meerbergen,
P. Wielage, and E. Waterlander. Trade offs in the design of a
router with both guaranteed and best-effort services for networks on chip.
In Rudy Lauwereins and Jan Madsen, editors, Design Automation, and
Test in Europe. The Most Influential Papers of 10 Years DATE, Circuits
& Systems, chapter 2 (Networks on Chip). Springer, January 2008.
9. Bart Vermeulen and Kees Goossens. Debugging multi-core systems on
chip. In George Kornaros, editor, Multi-Core Embedded Systems, chapter
5, pages 153–198. CRC Press/Taylor & Francis Group, April 2010.
10. Benny Akesson, Anca Molnos, Andreas Hansson, Jude Ambrose Angelo,
and Kees Goossens. Composability and predictability for independent
application development, verification, and execution. In Michael Hübner
and Jürgen Becker, editors, Multiprocessor System-on-Chip — Hardware
Design and Tool Integration, Circuits and Systems, chapter 2, pages 25–56.
Springer, November 2010.
4.3 Journal and Magazine Articles
1. André Nieuwland, Jeffrey Kang, Om Prakash Gangwal, Ramanathan Sethuraman,
Natalino Busá, Kees Goossens, Rafael Peset Llopis, and Paul Lippens.
C-HEAP: A heterogeneous multi-processor architecture template
and scalable and flexible protocol for the design of embedded signal processing
systems. ACM Transactions on Design Automation for Embedded
Systems, 7(3):233–270, 2002.
2. E. Rijpkema, K. Goossens, A. Rădulescu, J. Dielissen, J. van Meerbergen,
P. Wielage, and E. Waterlander. Trade-offs in the design of a router with
both guaranteed and best-effort services for networks on chip. IEE Proceedings:
Computers and Digital Techniques, 150(5):294–302, September
2003.
3. Bart Vermeulen, John Dielissen, Kees Goossens, and Călin Ciorda¸s. Bringing
communication networks on chip: Test and verification implications.
IEEE Communications Magazine, 41(9):74–81, September 2003.
4. Andrei Rădulescu, John Dielissen, Santiago González Pestana, Om Prakash
Gangwal, Edwin Rijpkema, Paul Wielage, and Kees Goossens. An efficient
on-chip network interface offering guaranteed services, shared-memory abstraction,
and flexible network programming. IEEE Transactions on CAD
of Integrated Circuits and Systems, 24(1):4–17, January 2005.
5. Kees Goossens, John Dielissen, and Andrei Rădulescu. The Æthereal
network on chip: Concepts, architectures, and implementations. IEEE
Design and Test of Computers, 22(5):414–421, Sept-Oct 2005.
6. Călin Ciorda¸s, Twan Basten, Andrei Rădulescu, Kees Goossens, and Jef
van Meerbergen. An event-based monitoring service for networks on
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chip. ACM Transactions on Design Automation of Electronic Systems,
10(4):702–723, October 2005.
7. Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski,
and Fernando Moraes. Wrapper design for the reuse of a bus, networkon-chip,
or ther functional interconnect as test access mechanism. IET
Computers & Digital Techniques, 1(3):197–206, May 2007.
8. Andreas Hansson, Kees Goossens, and Andrei Rădulescu. A unified approach
to mapping and routing on a network on chip for both best-effort
and guaranteed service traffic. VLSI Design, 2007:Article ID 68432, 16
pages, May 2007. Hindawi Publishing Corporation.
9. Andreas Hansson, Kees Goossens, and Andrei Rădulescu. Avoiding
message-dependent deadlock in network-based systems on chip. VLSI
Design, 2007:Article ID 95859, 10 pages, May 2007. Hindawi Publishing
Corporation.
10. Călin Ciorda¸s, Andreas Hansson, Kees Goossens, and Twan Basten. A
monitoring-aware network-on-chip design flow. Journal of Systems Architecture,
54(3–4):397–410, March 2008.
11. Andreas Hansson, Kees Goossens, Marco Bekooij, and Jos Huisken. CoMP-
SoC: A template for composable and predictable multi-processor system
on chips. ACM Transactions on Design Automation of Electronic Systems,
14(1):1–24, 2009.
12. Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, and
Marco Bekooij. Enabling application-level performance guarantees in
network-based systems on chip by applying dataflow analysis. IET Computers
& Digital Techniques, 3(5):398 –412, September 2009.
13. Davide Bertozzi and Kees Goossens. Editorial: Networks on chips. IET
Computers & Digital Techniques, 3(5):395–397, 2009.
14. Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev,
and Kees Goossens. Bandwidth analysis for reusing functional interconnect
as test access mechanism. Journal of Electronic Testing (JETTA),
pages 1–12, July 2010.
15. Andreas Hansson, Marcus Ekerhult, Anca Molnos, Aleksandar Milutinovic,
Andrew Nelson, Jude Ambrose, and Kees Goossens. Design and
implementation of an operating system for composable processor sharing.
Microprocessors and Microsystems (MICPRO), 35(2):246–260, March 2011.
Special issue on Network-on-Chip Architectures and Design Methodologies.
16. Radu Stefan and Kees Goossens. A TDM slot allocation flow based on
multipath routing in NoCs. Microprocessors and Microsystems (MICPRO),
35(2):130–138, March 2011. Elsevier.
17. Andreas Hansson and Kees Goossens. A quantitative evaluation of a
network-based interconnect for multi-core consumer multimedia applications.
Springer Journal of Design Automation for Embedded Systems
(DAEM), 15:159–190, 2011.
18. Kees Goossens and Radu Marculescu. Editorial: Special issue on networkson-chip:
Design flows and case studies. Springer Journal of Design Au-
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tomation for Embedded Systems (DAEM), 15:87–88, 2011.
19. Jae Young Hur, Todor Stefanov, Stephan Wong, and Kees Goossens. Customization
of on-chip network interconnects and experiments in FPGAs.
IET Computers & Digital Techniques, 6(1):56–68, January 2012.
20. Radu Stefan, Anca Molnos, and Kees Goossens. dAElite: A TDM NoC
supporting QoS, multicast, and fast connection set-up. IEEE Transactions
on Computers, 2012.
21. Jae Young Hur, Kees Goossens, Lotfi Mhamdi, and Muhammad Wahlah.
Comparative analysis of soft and hard on-chip interconnects for FPGAs.
IET Computers & Digital Techniques, 6(1):1–10, December 2012.
4.4 Peer-Reviewed International Conference Articles
1. K. G. W. Goossens. Embedding a CHDDL in a proof system. In
P. Prinetto and P. Camurati, editors, Advanced Research Workshop on
Correct Hardware Design Methodologies, pages 359–374. ESPRIT CHARME,
North Holland, June 1991. Also as University of Edinburgh LFCS Report
ECS-LFCS-91-155.
2. K. G. W. Goossens. Operational semantics based formal symbolic simulation.
In Luc Claesen and Michael Gordon, editors, Higher Order Logic
Theorem Proving and Its Applications, pages 487–506. North-Holland/Elsevier,
September 1992. A longer version is available as University of Edinburgh
LFCS Report ECS-LFCS-92-231.
3. K. G. W. Goossens. Structure and behaviour in hardware verification. In
Jeffrey J. Joyce and Carl-Johan H. Seger, editors, Higher Order Logic Theorem
Proving and Its Applications, number 780 in Lecture Notes in Computer
Science (LNCS), pages 75–88, London, UK, August 1993. Springer
Verlag. A longer version is available as University of Edinburgh LFCS
Report ECS-LFCS-93-273.
4. K. G. W. Goossens. The formalisation of a hardware description language
in a proof system: Motivation and applications. In Proceedings of the
XIII Conference of the Brazilian Computer Society, Florianopolis, Brazil,
September 1993.
5. K. G. W. Goossens. Reasoning about VHDL using operational and observational
semantics. In Paolo E. Camurati and Hans Eveking, editors,
Correct Hardware Design Methodologies, volume 987 of Lecture Notes in
Computer Science, pages 311–327, London, UK, October 1995. Springer
Verlag.
6. R. Peset Llopis and K.G.W. Goossens. The Petrol approach to high-level
power estimation. In Proc. Int’l Symposium on Low Power Electronics
and Design (ISLPED), pages 130–132, New York, NY, USA, August 1998.
ACM Press.
7. Lodewijk T. Smit, Gerard J.M. Smit, Paul J.M. Havinga, Jos A. Huisken,
Kees G.W. Goossens, and John T.M.H. Dielissen. Towards a model for
making a trade-off between QoS and costs. In Proceedings of the CTIT
workshop on Mobile Communications in perspective, February 2001.
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8. K. G. W. Goossens. A protocol and memory manager for on-chip communication.
In Proc. Int’l Symposium on Circuits and Systems (ISCAS),
volume 2, pages 225–228, Sydney, May 2001. IEEE Circuits and Systems
Society.
9. K. Goossens, J. van Meerbergen, A. Peeters, and P. Wielage. Networks on
silicon: Combining best-effort and guaranteed services. In Proc. Design,
Automation and Test in Europe Conference and Exhibition (DATE), pages
423–425, Washington, DC, USA, March 2002. IEEE Computer Society.
10. K. G. W. Goossens and O. P. Gangwal. The cost of communication
protocols and coordination languages in embedded systems. In Farhad
Arbab and Carolyn Talcott, editors, Coordination languages and models,
volume 2315 of Lecture notes in computer science, pages 174–190. Springer
Verlag, April 2002.
11. E. Rijpkema, K. G. W. Goossens, A. Rădulescu, J. Dielissen, J. van Meerbergen,
P. Wielage, and E. Waterlander. Trade offs in the design of a
router with both guaranteed and best-effort services for networks on chip.
In Proc. Design, Automation and Test in Europe Conference and Exhibition
(DATE), pages 350–355, Washington, DC, USA, March 2003. IEEE
Computer Society.
12. John Dielissen, Andrei Rădulescu, Kees Goossens, and Edwin Rijpkema.
Concepts and implementation of the Philips network-on-chip. In Workshop
on IP-Based System-on-Chip Design. IFIP workshop, November
2003.
13. Andrei Rădulescu, John Dielissen, Kees Goossens, Edwin Rijpkema, and
Paul Wielage. An efficient on-chip network interface offering guaranteed
services, shared-memory abstraction, and flexible network programming.
In Proc. Design, Automation and Test in Europe Conference and Exhibition
(DATE), volume 2, pages 878–883, Washington, DC, USA, February
2004. IEEE Computer Society.
14. Santiago González Pestana, Edwin Rijpkema, Andrei Rădulescu, Kees
Goossens, and Om Prakash Gangwal. Cost-performance trade-offs in
networks on chip: A simulation-based approach. In Proc. Design, Automation
and Test in Europe Conference and Exhibition (DATE), pages
764–769, Washington, DC, USA, February 2004. IEEE Computer Society.
15. Călin Ciorda¸s, Twan Basten, Andrei Rădulescu, Kees Goossens, and Jef
van Meerbergen. An event-based network-on-chip monitoring service. In
Proc. Workshop on High-Level Design Validation and Test (HLDVT),
pages 149–154, Washington, DC, USA, November 2004. IEEE Computer
Society.
16. Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago González Pestana,
Andrei Rădulescu, and Edwin Rijpkema. A design flow for applicationspecific
networks on chip with guaranteed performance to accelerate SOC
design and verification. In Proc. Design, Automation and Test in Europe
Conference and Exhibition (DATE), pages 1182–1187, Washington, DC,
USA, March 2005. IEEE Computer Society.
17. Kees Goossens. Networks on chip for consumer electronics. In Proc. Int’l
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Summer School on Advanced Computer Architecture and Compilation for
Embedded Systems (ACACES), pages 2272–230, July 2005.
18. Andreas Hansson, Kees Goossens, and Andrei Rădulescu. A unified approach
to constrained mapping and routing on network-on-chip architectures.
In Int’l Conf. on Hardware/Software Codesign and System Synthesis
(CODES+ISSS), pages 75–80. ACM, September 2005.
19. Biniam Gebremichael, Frits Vaandrager, Miaomiao Zhang, Kees Goossens,
Edwin Rijpkema, and Andrei Rădulescu. Deadlock prevention in the
Æthereal protocol. In Dominique Borrione and Wolfgang Paul, editors,
Proc. Working Conference on Correct Hardware Design and Verification
Methods (CHARME), volume 3725 of Lecture Notes in Computer Science
(LNCS), pages 345–348, October 2005.
20. Srinivasan Murali, Martijn Coenen, Andrei Rădulescu, Kees Goossens,
and Giovanni De Micheli. Mapping and configuration methods for multiuse-case
networks on chips. In Proc. Design Automation Conference.
Asia and South Pacific (ASPDAC), pages 146–151, New York, NY, USA,
January 2006. ACM Press.
21. Srinivasan Murali, Martijn Coenen, Andrei Rădulescu, Kees Goossens,
and Giovanni De Micheli. A methodology for mapping multiple usecases
on to networks on chip. In Proc. Design, Automation and Test
in Europe Conference and Exhibition (DATE), pages 118–123, 3001 Leuven,
Belgium, Belgium, March 2006. European Design and Automation
Association.
22. Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, and Rafael
Peset Llopis. Networks on chips for high-end consumer-electronics TV
system architectures. In Proc. Design, Automation and Test in Europe
Conference and Exhibition (DATE), volume 2, pages 148–153, 3001 Leuven,
Belgium, Belgium, March 2006. European Design and Automation
Association.
23. Călin Ciorda¸s, Kees Goossens, Andrei Rădulescu, and Twan Basten. NoC
monitoring: Impact on the design flow. In Proc. Int’l Symposium on
Circuits and Systems (ISCAS), pages 1981–1984, May 2006.
24. Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski,
and Fernando Moraes. Wrapper design for the reuse of networks-on-chip
as test access mechanism. In Proc. European Test Symposium (ETS),
pages 213–218, Washington, DC, USA, May 2006. IEEE Computer Society.
25. Milan Pastrnak, Peter H.N. de With, Călin Ciorda¸s, Jef van Meerbergen,
and Kees Goossens. Mixed adaptation and fixed-reservation QoS for
improving picture quality and resource usage of multimedia (noc) chips.
In Proc. Int’l Symposium on Consumer Electronics (ISCE), pages 1–6,
June 2006.
26. Călin Ciorda¸s, Andreas Hansson, Kees Goossens, and Twan Basten. A
monitoring-aware NoC design flow. In Proc. Euromicro Symposium on
Digital System Design (DSD), pages 97–104, San Jose, CA, USA, August
2006. EDA Consortium.
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27. Lambert Spaanenburg, Benny Akesson, Andreas Hansson, and Kees Goossens.
Design method for unconventional computing. In Int’l Workshop on Cellular
Neural Networks and their Applications (CNNA), pages 1–6. IEEE,
August 2006.
28. Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, and Jef
van Meerbergen. Comparison of an Æthereal network on chip and a
traditional interconnect for a multi-processor DVB-T system on chip. In
Proc. IFIP Int’l Conference on Very Large Scale Integration (VLSI-SoC),
pages 80–85, October 2006.
29. Călin Ciorda¸s, Kees Goossens, Twan Basten, Andrei Rădulescu, and Andre
Boon. Transaction monitoring in networks on chip: The on-chip runtime
perspective. In Proc. Symposium on Industrial Embedded Systems
(IES), pages 1–10, Antibes, France, October 2006. IEEE.
30. Martijn Coenen, Srinivasan Murali, Andrei Rădulescu, Kees Goossens,
and Giovanni De Micheli. A buffer-sizing algorithm for networks on chip
using TDMA and credit-based end-to-end flow control. In Int’l Conf.
on Hardware/Software Codesign and System Synthesis (CODES+ISSS),
pages 130–135, New York, NY, USA, October 2006. ACM Press.
31. Jan Willem van den Brand, Călin Ciorda¸s, Twan Basten, and Kees Goossens.
Congestion-controlled best-effort communication for networks-on-chip. In
Proc. Design, Automation and Test in Europe Conference and Exhibition
(DATE), pages 948–953, San Jose, CA, USA, April 2007. EDA Consortium.
32. Andreas Hansson, Martijn Coenen, and Kees Goossens. Undisrupted
quality-of-service during reconfiguration of multiple applications in networks
on chip. In Proc. Design, Automation and Test in Europe Conference
and Exhibition (DATE), pages 954–959, San Jose, CA, USA, April
2007. EDA Consortium.
33. Kees Goossens, Bart Vermeulen, Remco van Steeden, and Martijn Bennebroek.
Transaction-based communication-centric debug. In Proc. Int’l
Symposium on Networks on Chip (NOCS), pages 95–106, Washington,
DC, USA, May 2007. IEEE Computer Society.
34. Andreas Hansson and Kees Goossens. Trade-offs in the configuration of
a network on chip for multiple use-cases. In Proc. Int’l Symposium on
Networks on Chip (NOCS), pages 233–242, Washington, DC, USA, May
2007. IEEE Computer Society.
35. Bart Vermeulen, Kees Goossens, Remco van Steeden, and Martijn Bennebroek.
Communication-centric SOC debug using transactions. In Proc.
European Test Symposium (ETS), pages 69–76, Washington, DC, USA,
May 2007. IEEE Computer Society.
36. Andreas Hansson, Martijn Coenen, and Kees Goossens. Channel trees:
Reducing latency by sharing time slots in time-multiplexed networks on
chip. In Int’l Conf. on Hardware/Software Codesign and System Synthesis
(CODES+ISSS), pages 149–154, New York, NY, USA, October 2007.
ACM.
37. Benny Akesson, Kees Goossens, and Markus Ringhofer. Predator: A pre-
11

dictable SDRAM memory controller. In Int’l Conf. on Hardware/Software
Codesign and System Synthesis (CODES+ISSS), pages 251–256, New York,
NY, USA, October 2007. ACM.
38. Bart Vermeulen, Kees Goossens, and Siddharth Umrani. Debugging
distributed-shared-memory communication at multiple granularities in networks
on chip. In Proc. Int’l Symposium on Networks on Chip (NOCS),
pages 3–12, Washington, DC, USA, April 2008. IEEE Computer Society.
39. Kees Goossens, Martijn Bennebroek, Jae Young Hur, and Muhammad Aqeel
Wahlah. Hardwired networks on chip in FPGAs to unify data and configuration
interconnects. In Proc. Int’l Symposium on Networks on Chip
(NOCS), pages 45–54, Washington, DC, USA, April 2008. IEEE Computer
Society.
40. Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev,
and Kees Goossens. Bandwidth analysis for reusing functional interconnect
as test access mechanism. In Proc. European Test Symposium
(ETS), pages 21–26, Washington, DC, USA, May 2008. IEEE Computer
Society.
41. Benny Akesson, Liesbeth Steffens, Eelke Strooisma, and Kees Goossens.
Real-time scheduling using credit-controlled static-priority arbitration. In
Proc. Int’l Conference on Embedded and Real-Time Computing Systems
and Applications (RTCSA), pages 3–14, Washington, DC, USA, August
2008. IEEE Computer Society.
42. Jae Young Hur, Kees Goossens, and Lotfi Mhamdi. Performance analysis
of soft and hard single-hop and multi-hop circuit-switched interconnects
for FPGAs. In Proc. IFIP Int’l Conference on Very Large Scale Integration
(VLSI-SoC), October 2008.
43. Aleksandar Milutinović, Kees Goossens, and Gerard Smit. Impact of
power-management granularity on the energy-quality trade-off for soft and
hard real-time applications. In Proc. Int’l Symposium on Systems on Chip
(SoC), pages 1–4, November 2008.
44. Andreas Hansson, Mahesh Subbaraman, and Kees Goossens. aelite: A flitsynchronous
network on chip with composable and predictable services. In
Proc. Design, Automation and Test in Europe Conference and Exhibition
(DATE), pages 250–255, April 2009.
45. Kees Goossens, Bart Vermeulen, and Ashkan Beyranvand Nejad. A highlevel
debug environment for communication-centric debug. In Proc. Design,
Automation and Test in Europe Conference and Exhibition (DATE),
pages 202–207, April 2009.
46. Muhammad Aqeel Wahlah and Kees Goossens. Modeling reconfiguration
in a FPGA with a hardwired network on chip. In Proc. Reconfigurable
Architecture Workshop (RAW), pages 1–8. IEEE Computer Society, May
2009.
47. Kees Goossens, Lotfi Mhamdi, and Iria Varela Senin. Internet-router
buffered crossbars based on networks on chip. In Proc. Euromicro Symposium
on Digital System Design (DSD), pages 365 –374, August 2009.
48. Benny Akesson, Andreas Hansson, and Kees Goossens. Composable re-
12

source sharing based on latency-rate servers. In Proc. Euromicro Symposium
on Digital System Design (DSD), pages 547–555, August 2009.
49. Anca Molnos and Kees Goossens. Conservative dynamic energy management
for real-time dataflow applications mapped on multiple processors.
In Proc. Euromicro Symposium on Digital System Design (DSD), pages
409–418, August 2009.
50. Benny Akesson, Liesbeth Steffens, and Kees Goossens. Efficient service
allocation in hardware using credit-controlled static-priority arbitration.
In Proc. Int’l Conference on Embedded and Real-Time Computing Systems
and Applications (RTCSA), pages 59–68, Washington, DC, USA, August
2009. IEEE Computer Society.
51. Radu Stefan and Kees Goossens. Multi-path routing in time-divisionmultiplexed
networks on chip. In Proc. IFIP Int’l Conference on Very
Large Scale Integration (VLSI-SoC), pages 109–114, October 2009.
52. Aleksandar Milutinović, Kees Goossens, and Gerard Smit. Dynamic workload
peak detection for slack management. In Proc. Int’l Symposium on
Systems on Chip (SoC), pages 1–4, October 2009.
53. Andreas Hansson and Kees Goossens. An on-chip interconnect and protocol
stack for multiple communication paradigms and programming models.
In Int’l Conf. on Hardware/Software Codesign and System Synthesis
(CODES+ISSS), pages 99–108, New York, NY, USA, October 2009.
ACM.
54. Iria Varela Senín, Lotfi Mhamdi, and Kees Goossens. Efficient multicast
support in buffered crossbars using networks on chip. In Proc. Global
Telecommunications Conference (GLOBECOM), pages 5024–5030, Piscataway,
NJ, USA, December 2009. IEEE Press.
55. Muhammad Aqeel Wahlah and Kees Goossens. Composable and persistentstate
application swapping on FPGAs using hardwired network on chip.
In Proc. Int’l Conference on Reconfigurable Computing and FPGAs (Re-
ConFig), pages 380–385, December 2009.
56. Anca Molnos, Aleksandar Milutinovic, Dongrui She, and Kees Goossens.
Composable processor virtualization for embedded systems. In Proc.
Workshop on Computer Architecture and Operating System Co-Design
(CAOS), Lecture Notes in Computer Science (LNCS). Springer, January
2010.
57. Lotfi Mhamdi, Kees Goossens, and Iria Varela Senín. Buffered crossbar
fabrics based on networks on chip. In Proc. Annual Conference on Communication
Networks and Services Research (CNSR), pages 74–79. IEEE
Computer Society, May 2010.
58. Erik Larsson, Bart Vermeulen, and Kees Goossens. Distributed architecture
for checking global properties during post silicon debug. In Proc.
European Test Symposium (ETS), pages 182–187. IEEE, May 2010.
59. Radu Stefan, Jason de Windt, and Kees Goossens. On-chip network
interfaces supporting automatic burst write creation, posted writes and
read prefetch. In Proc. Int’l Conference on Embedded Computer Systems:
Architectures, MOdeling and Simulation (SAMOS), pages 185–192, July
13

2010.
60. Benny Akesson, Williston Hayes Jr., and Kees Goossens. Classification
and analysis of predictable memory patterns. In Proc. Int’l Conference on
Embedded and Real-Time Computing Systems and Applications (RTCSA),
pages 367–376, Washington, DC, USA, August 2010. IEEE Computer
Society.
61. Kees Goossens, Dongrui She, Aleksandar Milutinovic, and Anca Molnos.
Composable dynamic voltage and frequency scaling and power management
for dataflow applications. In Proc. Euromicro Symposium on Digital
System Design (DSD), pages 107–114, Washington, DC, USA, September
2010. IEEE Computer Society.
62. Andrew Nelson, Andreas Hansson, Henk Corporaal, and Kees Goossens.
Conservative application-level performance analysis through simulation of
MPSoCs. In Embedded Systems for Real-Time Multimedia (ESTIMedia),
pages 51–60, October 2010.
63. Erik Larsson, Bart Vermeulen, and Kees Goossens. Checking pipelined
distributed global properties for post-silicon debug. In Proc. Workshop
on RTL and high level testing (WRTLT), December 2010.
64. Radu Stefan and Kees Goossens. An improved algorithm for slot selection
in the Æthereal network-on-chip. In Proc. Interconnection Network
Architecture: On-Chip, Multi-Chip (INA-OCMC), INA-OCMC ’11, pages
7–10, New York, NY, USA, January 2011. ACM.
65. Bart Vermeulen and Kees Goossens. Interactive debugging of systems on
chip with multiple clocks. IEEE Design & Test of Computers, 28(3):44–
51, May/June 2011. Special issue on Transaction-Level Validation of
Multicore Architectures.
66. Ashkan Beyranvand Nejad, Matías Escudero Martínez, and Kees Goossens.
An FPGA bridge preserving traffic quality of service for on-chip networkbased
systems. In Proc. Design, Automation and Test in Europe Conference
and Exhibition (DATE), pages 1–6. IEEE, March 2011.
67. Thijs Schenkelaars, Bart Vermeulen, and Kees Goossens. Optimal scheduling
of switched FlexRay networks. In Proc. Design, Automation and Test
in Europe Conference and Exhibition (DATE), pages 1–6, March 2011.
68. Benny Akesson and Kees Goossens. Architectures and modeling of predictable
memory controllers for improved system integration. In Proc. Design,
Automation and Test in Europe Conference and Exhibition (DATE),
pages 1–6. IEEE, March 2011.
69. Benny Akesson, Williston Hayes Jr., and Kees Goossens. Automatic generation
of efficient predictable memory patterns. In Proc. Int’l Conference
on Embedded and Real-Time Computing Systems and Applications
(RTCSA), volume 1, pages 177–184. IEEE Computer Society, August
2011.
70. Firew Siyoum, Benny Akesson, Sander Stuijk, Kees Goossens, and Henk
Corporaal. Resource-efficient real-time scheduling using credit-controlled
static-priority arbitration. In Proc. Int’l Conference on Embedded and
Real-Time Computing Systems and Applications (RTCSA), volume 1, pages
14

309–318. IEEE Computer Society, August 2011.
71. Karthik Chandrasekar, Benny Akesson, and Kees Goossens. Improved
power modeling of DDR SDRAMs. In Proc. Euromicro Symposium on
Digital System Design (DSD), DSD ’11, pages 99–108, Washington, DC,
USA, August 2011. IEEE Computer Society.
72. Andrew Nelson, Orlando Moreira, Anca Molnos, Sander Stuijk, Ba Thang
Nguyen, and Kees Goossens. Power minimisation for real-time dataflow
applications. In Proc. Euromicro Symposium on Digital System Design
(DSD), DSD ’11, pages 117–124, Washington, DC, USA, August 2011.
IEEE Computer Society.
73. Muhammad Aqeel Wahlah and Kees Goossens. PUMA: Placement unification
with mapping and guaranteed throughput allocation on an FPGA
using a hardwired NoC. In Proc. Euromicro Symposium on Digital System
Design (DSD), pages 88–96. IEEE, August 2011.
74. Muhammad Aqeel Wahlah and Kees Goossens. A non-intrusive online
FPGA test scheme using a hardwired network on chip. In Proc. Euromicro
Symposium on Digital System Design (DSD), DSD ’11, pages 351–359,
Washington, DC, USA, August 2011. IEEE Computer Society.
75. Radu Stefan and Kees Goossens. Enhancing the security of time-divisionmultiplexing
networks-on-chip through the use of multipath routing. In
Proc. Int’l Workshop on Network on Chip Architectures (NOCARC), New
York, NY, USA, December 2011. ACM.
76. Radu Stefan, Ashkan Beyranvand Nejad, and Kees Goossens. Online
allocation for contention-free-routing nocs. In Proc. Interconnection Network
Architecture: On-Chip, Multi-Chip (INA-OCMC), pages 13–16, New
York, NY, USA, 2012. ACM Press.
77. Radu Stefan, Anca Molnos, Angelo Ambrose, and Kees Goossens. A
TDM NoC supporting QoS, multicast, and fast connection set-up. In
Proc. Design, Automation and Test in Europe Conference and Exhibition
(DATE), pages 1283–1288, Dresden, Germany, March 2012. IEEE.
78. Manil Dev Gomony, Christian Weis, Benny Akesson, Norbert Wehn, and
Kees Goossens. DRAM selection and configuration for real-time mobile
systems. In Proc. Design, Automation and Test in Europe Conference
and Exhibition (DATE), pages 51–56, Dresden, Germany, March 2012.
IEEE.
79. Davit Mirzoyan, Benny Akesson, and Kees Goossens. Process-variation
aware mapping of real-time streaming applications to MPSoCs for improved
yield. In Int’l Symposium on Quality Electronic Design (ISQED),
pages 41 –48, Santa Clara, CA USA, March 2012. IEEE.
80. Anca Molnos, Ashkan Beyranvand Nejad, Ba Thang Nguyen, Sorin Cotofana,
and Kees Goossens. Decoupled inter- and intra-application scheduling
for composable and robust embedded MPSoC platforms. In Workshop
on Mapping of Applications to MPSoCs (MAP2MPSOC), pages 13–21,
New York, NY, USA, May 2012. ACM.
81. Karthik Chandrasekar, Benny Akesson, and Kees Goossens. Run-time
power-down strategies for real-time SDRAM memory controllers. In Proc.
15

Design Automation Conference (DAC), pages 988–993, New York, NY,
USA, June 2012. ACM.
82. Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael
Hübner, Jürgen Becker, Sébastien Pillement, Olivier Sentieys, Martijn
Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas
Morgan, and Romain Lemaire. Towards future adaptive multiprocessor
systems-on-chip: an innovative approach for flexible architectures. In
Proc. Int’l Conference on Embedded Computer Systems: Architectures,
MOdeling and Simulation (SAMOS), Samos, Greece, July 2012.
83. Cor Meenderinck, Anca Molnos, and Kees Goossens. Composable virtual
memory for an embedded SoC. In Proc. Euromicro Symposium on Digital
System Design (DSD), Izmir, Turkey, September 2012.
84. Gervin Thomas, Karthik Chandrasekar, Benny Akesson, Ben Juurlink,
and Kees Goossens. A predictor-based power-saving policy for DRAM
memories. In Proc. Euromicro Symposium on Digital System Design
(DSD), Izmir, Turkey, September 2012.
85. Arnaldo Azevedo, Bart Vermeulen, and Kees Goossens. Architecture and
design flow for a debug event distribution interconnect. In Proc. Int’l
Conference on Computer Design (ICCD), Montreal, Canada, September
2012.
86. Andrew Nelson, Anca Molnos, and Kees Goossens. Power versus quality
trade-offs for adaptive real-time applications. In Embedded Systems
for Real-Time Multimedia (ESTIMedia), pages 75–84, Tampere, Finland,
October 2012.
87. Andrew Nelson, Anca Molnos, Ashkan Beyranvand Nejad, Davit Mirzoyan,
Sorin Cotofana, and Kees Goossens. Embedded computer architecture
laboratory: A hands-on experience programming embedded systems
with resource and energy constraints. In Workshop on Embedded Systems
Education (WESE), Tampere, Finland, October 2012.
88. Turhan Karadeniz, Lotfi Mhamdi, Kees Goossens, and J.J. Garcia-Luna-
Aceves. Hardware design and implementation of a network-on-chip based
load balancing switch fabric. In Proc. Int’l Conference on Reconfigurable
Computing and FPGAs (ReConFig), Cancun, Mexico, December 2012.
89. Kees Goossens, Arnaldo Azevedo, Karthik Chandrasekar, Manil Dev Gomony,
Sven Goossens, Martijn Koedam, Yonghui Li, Davit Mirzoyan, Anca Molnos,
Ashkan Beyranvand Nejad, Andrew Nelson, and Shubhendu Sinha.
Virtual execution platforms for mixed-time-criticality applications: The
CompSOC architecture and design flow. In Proc. Workshop on Compositional
Theory and Technology for Real-Time Embedded Systems (CRTS),
San Juan, Puerto Rico, December 2012.
90. Pengcheng Huang, Orlando Moreira, Kees Goossens, and Anca Molnos.
Throughput-constrained voltage and frequency scaling for real-time heterogeneous
multiprocessors. In Proc. Symposium On Applied Computing
(SAC), March 2013.
91. Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn,
and Kees Goossens. System and Circuit Level Power Modeling of Energy-
16

Efficient 3D-Stacked Wide I/O DRAMs. In Proc. Design, Automation
and Test in Europe Conference and Exhibition (DATE), March 2013.
92. Manil Dev Gomony, Benny Akesson, and Kees Goossens. Architecture and
optimal configuration of a real-time multi-channel memory controller. In
Proc. Design, Automation and Test in Europe Conference and Exhibition
(DATE), March 2013.
93. Sven Goossens, Benny Akesson, and Kees Goossens. Conservative openpage
policy for mixed time-criticality memory controllers. In Proc. Design,
Automation and Test in Europe Conference and Exhibition (DATE),
March 2013.
4.5 Invited publications
1. Paul Wielage and Kees Goossens. Networks on silicon: Blessing or nightmare?
In Euromicro Symposium On Digital System Design, pages 196–
200, Washington, DC, USA, September 2002. IEEE Computer Society.
2. Kees Goossens. Formal methods for networks on chips. In Proc. Int’l
Conference on Application of Concurrency to System Design (ACSD),
pages 188–189, Washington, DC, USA, June 2005. IEEE Computer Society.
3. Miron Abramovici, Neal Stollon, Kees Goossens, Bart Vermeulen, Jack
Greenbaum, and Adam Donlin. You can catch more bugs with transaction
level honey. In Int’l Conf. on Hardware/Software Codesign and System
Synthesis (CODES+ISSS), pages 121–124, New York, NY, USA, October
2008. ACM.
4. Bart Vermeulen and Kees Goossens. A network-on-chip monitoring infrastructure
for communication-centric debug of embedded multi-processor
SoCs. In Proc. Int’l Symposium on VLSI Design, Automation and Test
(VLSI-DAT), pages 183–186, April 2009.
5. Anca Molnos, Jude Angelo Ambrose, Andrew Nelson, Radu Stefan, Sorin
Cotofana, and Kees Goossens. A composable, energy-managed, real-time
MPSOC platform. In Proc. Int’l Conference on Optimization of Electrical
and Electronic Equipment (OPTIM), pages 870–876, May 2010.
6. Bart Vermeulen and Kees Goossens. Obtaining consistent global state
dumps to interactively debug systems on chip with multiple clocks. In
Proc. Workshop on High-Level Design Validation and Test (HLDVT),
pages 1–8, June 2010.
7. Kees Goossens and Andreas Hansson. The Aethereal network on chip
after ten years: Goals, evolution, lessons, and future. In Proc. Design
Automation Conference (DAC), pages 306–311, June 2010.
8. Andrew Nelson, Anca Molnos, and Kees Goossens. Composable power
management with energy and power budgets per application. In Proc.
Int’l Conference on Embedded Computer Systems: Architectures, MOdeling
and Simulation (SAMOS), pages 396–403, July 2011.
9. M. Ferger, M. Al Kadi, M. Hübner, M. Koedam, S. Sinha, K. Goossens,
G. Marchesan Almeida, J. Rodrigo Azambuja, and J. Becker. Hardware
17

software virtualization for the reconfigurable multicore platform. In
Proc. Int’l Conference on Embedded and Ubiquitous Computing (EUC),
December 2012. Invited paper.
Almost all of these were peer reviewed.
4.6 Special sessions and tutorials
1. Saddek Bensalem, Kees Goossens, Christoph M. Kirsch, Roman Obermaisser,
Edward A. Lee, and Joseph Sifakis. Time-predictable and composable
architectures for dependable embedded systems. In Proc. ACM
Int’l Conference on Embedded software (EMSOFT), EMSOFT ’11, pages
351–352, New York, NY, USA, October 2011. ACM.
2. Benny Akesson, Po-Chun Huang, Fabien Clermidy, Denis Dutoit, Kees
Goossens, Yuan-Hao Chang, Tei-Wei Kuo, Pascal Vivet, and Drew Wingard.
Memory controllers for high-performance and real-time MPSoCs — Requirements,
architectures, and future trends. In Int’l Conf. on Hardware/Software
Codesign and System Synthesis (CODES+ISSS), pages 3–
12, October 2011.
4.7 Local Conferences, Posters, etc.
1. K. G. W. Goossens. Integrating hardware description languages and proof
systems. In IFIP 12th World Computer Congress, September 1992.
2. Wim Verhaegh, Gertjan Arnoldussen, Kees Goossens, and Marc Heijligers.
Phideo: architectural synthesis for high-throughput digital signal processing.
Philips Research Bulletin on IC Design, (31):9–11, 1997.
3. Edwin Rijpkema, Kees Goossens, and Paul Wielage. A router architecture
for networks on silicon. In Proceedings of Progress 2001, 2nd Workshop
on Embedded Systems, Veldhoven, the Netherlands, October 2001.
4. Xiao Ru, John Dielissen, Christer Svensson, and Kees Goossens. Synchronous
latency-insensitive design in Æthereal NoC. Future Interconnects
and Network on Chip workshop at Design, Automation and Test in
Europe Conference and Exhibition (DATE), March 2006.
5. Kees Goossens. Multiple use-cases for a network-on-chip design flow. Future
Interconnects and Network on Chip workshop at Design, Automation
and Test in Europe Conference and Exhibition (DATE), March 2006.
6. Pengwei Ren, Alexandre M. Amory, Erik Jan Marinissen, Kees Goossens,
Sandeep K. Goel, Georgi N. Gaydadjiev, Marcelo Lubaszewski, and Fernando
Moraes. Test wrapper design that allows a core to be tested via a
network-on-chip or other functional interconnect. Diagnostic Services in
Networks-on-Chips workshop at Design, Automation and Test in Europe
Conference and Exhibition (DATE), April 2007.
7. Aleksandar Milutinović, Kees Goossens, and Gerard J.M. Smit. Slack
exploitation for aggressive dynamic power reduction in SoC. In Proc.
Annual Workshop on Circuits, Systems and Signal Processing (ProRisc),
Veldhoven, The Netherlands, November 2007.
18

8. Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, and
Marco Bekooij. Applying dataflow analysis to dimension buffers for guaranteed
performance in networks on chip. In Proc. Int’l Symposium on
Networks on Chip (NOCS), pages 211–212, April 2008.
9. Muhammad Aqeel Wahlah and Kees Goossens. Hardwired NOC infrastructure
with integrated configuration and functional architectures.
In Proc. Annual Workshop on Circuits, Systems and Signal Processing
(ProRisc), November 2008.
10. R. Benjaminsen, F. Duarte, J. Huisken, and K. Goossens. Gate-level
power analysis of on-chip communication infrastructures for biomedical
applications. In Proc. Annual Workshop on Circuits, Systems and Signal
Processing (ProRisc), November 2009.
11. Aleksandar Milutinović, Anca Molnos, Kees Goossens, and Gerard J.M.
Smit. Dynamic voltage and frequency scaling and adaptive body biasing
for active and leakage power reduction in MPSOC: a literature overview.
In Proc. Annual Workshop on Circuits, Systems and Signal Processing
(ProRisc), Veldhoven, The Netherlands, November 2009.
12. Ashkan Beyranvand Nejad, Kees Goossens, Johan Walters, and Bart Kienhuis.
Mapping KPN models of streaming applications on a network-onchip
platform. In Proc. Annual Workshop on Circuits, Systems and
Signal Processing (ProRisc), November 2009.
13. Radu Stefan and Kees Goossens. NoC security using multipath routing.
In Proc. Annual Workshop on Circuits, Systems and Signal Processing
(ProRisc), November 2009.
14. Muhammad Aqeel Wahlah and Kees Goossens. Run-time FPGA testing
using hardwired network on chip. In Proc. Annual Workshop on Circuits,
Systems and Signal Processing (ProRisc), November 2009.
15. Muhammad Aqeel Wahlah and Kees Goossens. 3-tier reconfiguration
model for FPGAs using hardwired network on chip. In Proc. Int’l Conference
on Field-Programmable Technology (FPT), December 2009.
16. Erik Larsson, Bart Vermeulen, and Kees Goossens. Checking pipelined
distributed global properties at post-silicon debug. In DAC Workshop on
Diagnostic Services in Network-on-Chips (DSNoC), June 2010.
17. Davit Mirzoyan, Benny Akesson, and Kees Goossens. Impact of process
variations on the throughput of real-time applications in multiprocessor
systems-on-chip. In Proc. Annual Workshop on PROGram for Research
on Embedded Systems & Software (Progress), November 2010.
18. Ashkan Beyranvand Nejad, Matias Escudero Martinez, and Kees Goossens.
On-chip interconnect protocol stack exploration for FPGA board-to-board
bridging. In Proc. Annual Workshop on PROGram for Research on Embedded
Systems & Software (Progress), November 2010.
19. Karthik Chandrasekar, Benny Akesson, and Kees Goossens. Modeling
and optimizing power for a real-time SDRAM controller. In Proc. Annual
Workshop on PROGram for Research on Embedded Systems & Software
(Progress), November 2010.
20. Andrew Nelson, Orlando Moreira, Sander Stuijk, Anca Molnos, Kees
19

Goossens, and Thang Nguyen. Ideas on power minimisation for realtime
dataflow applications through voltage & frequency scaling. In Proc.
Annual Workshop on Circuits, Systems and Signal Processing (ProRisc),
Veldhoven, The Netherlands, November 2010.
21. Jude Ambrose, Anca Molnos, Andrew Nelson, Sorin Cotofana, Kees Goossens,
and Ben Juurlink. Composable local memory organisation for streaming
applications on embedded MPSoCs. In Proc. Int’l Conference on Computing
Frontiers (CF), May 2011.
22. Ashkan Beyranvand Nejad, Anca Molnos, and Kees Goossens. A unified
execution model for data-driven applications on a composable MPSoC. In
Proc. Euromicro Symposium on Digital System Design (DSD), August
2011.
23. Arnaldo Azevedo, Bart Vermeulen, and Kees Goossens. Architecture of
the event distribution network for cross-triggering debug. In Proc. Annual
Workshop on PROGram for Research on Embedded Systems & Software
(Progress), November 2011. Abstract & Poster.
24. Ashkan Beyranvand Nejad, Anca Molnos, and Kees Goossens. Enabling
time-triggered scheduling on a composable embedded system. In Proc.
Annual Workshop on PROGram for Research on Embedded Systems &
Software (Progress), November 2011. Abstract & Poster.
25. Karthik Chandrasekar, Benny Akesson, and Kees Goossens. Predictable
power-down policies for SDRAMs. In Proc. Annual Workshop on PRO-
Gram for Research on Embedded Systems & Software (Progress), November
2011. Abstract & Poster.
26. Manil Dev Gomony, Benny Akesson, and Kees Goossens. A parallel-access
method for 3D-stacked DRAMs. In Proc. Annual Workshop on PRO-
Gram for Research on Embedded Systems & Software (Progress), November
2011. Abstract & Poster.
27. Sven Goossens, Benny Akesson, and Kees Goossens. Reconfiguration
of a predictable and composable SDRAM controller with persistent applications.
In Proc. Annual Workshop on PROGram for Research on
Embedded Systems & Software (Progress), November 2011. Abstract &
Poster.
28. Davit Mirzoyan, Benny Akesson, and Kees Goossens. Impact of process
variation on QoS in SRT applications. In Proc. Annual Workshop
on PROGram for Research on Embedded Systems & Software (Progress),
November 2011. Abstract & Poster.
29. Andrew Nelson, Anca Molnos, and Kees Goossens. A design concept for
independent multi-application development. In Proc. Annual Workshop
on PROGram for Research on Embedded Systems & Software (Progress),
November 2011. Abstract & Poster.
30. Radu Stefan and Kees Goossens. Run-time allocation in contention-free
routing NoCs. In Proc. Annual Workshop on PROGram for Research on
Embedded Systems & Software (Progress), November 2011. Abstract &
Poster.
31. Pavel G. Zaykov, Anca M. Molnos, Georgi Kuzmanov, and Kees Goossens.
20

Communication of slack availability with timestamps in multiprocessor
systems. In Proc. Annual Workshop on PROGram for Research on
Embedded Systems & Software (Progress), November 2011. Abstract &
Poster.
32. Sven Goossens, Tim Kouters, Benny Akesson, and Kees Goossens. Memorymap
selection for firm real-time SDRAM controllers. In Proc. Design, Automation
and Test in Europe Conference and Exhibition (DATE), March
2012. Poster.
33. Benny Akesson, Sander Stuijk, Anca Molnos, Martijn Koedam, Radu Stefan,
Andrew Nelson, Ashkan Beyranvand, and Kees Goossens. Virtual
platform for mixed-time criticality applications: The CoMPSoC architecture
and SDF3 design flow. In Quo Vadis, Virtual Platforms? Challenges
and Solutions for Today and Tomorrow (QVVP), March 2012. Abstract
& Poster.
34. Manil Dev Gomony, Christian Weis, Benny Akesson, Norbert Wehn, and
Kees Goossens. DRAM selection and configuration for real-time mobile
systems. In Proc. ICT.OPEN, October 2012. Abstract & Poster.
35. Sven Goossens, Tim Kouters, Benny Akesson, and Kees Goossens. Memorymap
selection for firm real-time SDRAM controllers. In Proc. ICT.OPEN,
October, 2012. Abstract & Poster.
36. Yonghui Li, Benny Akesson, and Kees Goossens. Dynamic command
scheduling for real-time memory controller. In Proc. ICT.OPEN, October
2012. Abstract & Poster.
37. Shubhendu Sinha, Martijn Koedam, Kees Goossens, and Marc Geilen.
Resource manager for TDM network on chips. In Proc. ICT.OPEN,
October 2012. Abstract & Poster.
38. Benny Akesson, Martijn Koedam, Anca Molnos, Ashkan Beyranvand Nejad,
Andrew Nelson, Sander Stuijk, , and Kees Goossens. Virtual execution
platforms for mixed time-criticality applications: Demonstrating the
CompSoC platform and design flow. In Proc. RTSS@Work demo session,
December 2012.
4.8 Paper Awards
• 2003 DATE paper (“Trade offs in the design of a router with both guaranteed
and best-effort services for networks on chip”): selected as one of the
30 most influential papers of 10 years of the DATE conference, published
by Springer in their Circuits & Systems series.
• 2005 CODES+ISSS paper (“A unified approach to constrained mapping
and routing on network-on-chip architectures”): best paper award.
• 2006 IES paper (“Transaction monitoring in networks on chip: The onchip
run-time perspective”): best paper award.
• 2006 ISCE paper (“Combined reservation and adaptation QoS for improving
picture quality and resource usage of multimedia (NoC) chips.”): best
21

paper award (3rd place).
• 2010 Progress poster (“Impact of process variations on the throughput
of real-time applications in multiprocessor systems-on-chip”): best poster
award.
• 2010 DAC paper (“The Aethereal network on chip after ten years: Goals,
evolution, lessons, and future.”) received the HiPEAC Paper Award.
• 2012 DAC paper (“Run-time power-down strategies for real-time SDRAM
memory controllersXS.”) received the HiPEAC Paper Award.
4.9 Press Coverage
Reports on my research, or quoting me.
1. “Networks on Processors Improve On-Chip Communications” by David
Geer. Computer Volume 42, Issue 3, March 2009.
2. “SoC stumbling blocks cataloged at DATE” by Nicolas Mokhoff and Chris
Edwards. EE Times of coverage of “network on chip” hot topic at DATE,
March 2002.
3. “Networking concepts inspire next-gen SoCs” by Richard Goering. EE
Times coverage of MPSOC, 2002.
4. Article on networks on chip, with details on the Æthereal network. In
Japanese by Masahide Kimura, Nikkei Microdevices, pp 21–29, August
2003.
5. “Design View from Japan: ST, Philips Steal Show at DATE 06” by Ikutaro
Kojima. NE Asia online, May 2006. Coverage of our DATE article on
high-end consumer-electronics TV system architectures.
4.10 Technical Notes
1. K. G. W. Goossens. Embedding a CHDDL in a proof system. LFCS Report
Series ECS-LFCS-91-155, LFCS, Department of Computer Science,
University of Edinburgh, May 1991.
2. K. G. W. Goossens. Operational semantics based formal symbolic simulation.
LFCS Report Series ECS-LFCS-92-231, LFCS, Department of
Computer Science, University of Edinburgh, September 1992.
3. K. G. W. Goossens. The formalisation of a hardware description language
in a proof system: Motivation and applications. LFCS Report Series
ECS-LFCS-93-269, LFCS, Department of Computer Science, University
of Edinburgh, June 1993.
4. K. G. W. Goossens. Structure and behaviour in hardware verification.
LFCS Report Series ECS-LFCS-93-273, LFCS, Department of Computer
Science, University of Edinburgh, July 1993.
5. K. G. W. Goossens. Reasoning about VHDL using operational and observational
semantics. Rapporto di Ricerca SI/RR 95/06, Dipartimento di
Scienze dell’Informazione, Università di Roma “La Sapienza”, April 1995.
22

6. P. Lippens, Z. Chamski, B. Kastrup, W. Kloosterhuis, M. Heijligers,
L. Augusteijn, K. Goossens, M. Lindwer, E. van der Horst, and W. Smits.
C-Frontend working group; report on activities. Technical Note 195/98,
Philips Research, May 1998.
7. Kees Goossens, Marc Heijligers, Erwin de Kock, Wido Kruijtzer, and
Frans Theeuwen. Concepts for a system-level design flow. Technical
Note 2001/00440, Philips Research, November 2001.
8. K. Goossens, J. Dielissen, J. van Meerbergen, P. Poplavko, A. Radulescu,
E. Rijpkema, P. Wielage, and E. Waterlander. Networks on chip. IST
newsletter, 2002.
9. M. Edzes, K. Goossens, P. Klapproth, K. Locker, S. Nayak, T. Pontius,
A. Radulescu, and D. Taussig. Amba 3.0 proposal update response.
Technical Note 2003/00064, Philips Research, 2003.
10. K. Goossens, P. Klapproth, K. Locker, A. P. Niranjan, A. Radulescu,
J. Roever, and D. Taussig. OCP 2.0 review report. Technical Note
2003/00063, Philips Research, 2003.
11. Andrei Rădulescu and Kees Goossens. Æthereal services. Technical Note
2003/00577, Philips Research, July 2003.
12. Andrei Rădulescu, John Dielissen, Kees Goossens, Edwin Rijpkema, and
Paul Wielage. Æthereal network interface design. Technical Note 2003/01005,
Philips Research, December 2003.
13. Thomas M. Philipp, Kees Goossens, and Andrei Rădulescu. Modelling of
the Æthereal network on chip using the Aachen NOC Exploration Framework.
Technical Note 2004/00485, Philips Research, September 2004.
14. Tomaz Felicijan, John Dielissen, and Kees Goossens. Asynchronous
TDMA networks on chip. Technical Note 2004/00081, Philips Research,
January 2005.
15. Razvan Dinu, Kees Goossens, and Andrei Rădulescu. Refactoring the
Æthereal network-on-chip design flow: Data model. Technical Note
2005/00129, Philips Research, February 2005.
16. John Dielissen, Andrei Rădulescu, and Kees Goossens. Power measurements
and analysis of a network on chip. Technical Note 2005/00282,
Philips Research, April 2005.
17. Razvan Dinu, Kees Goossens, and Andrei Rădulescu. Æthereal networkon-chip
design flow system architecture. Technical Note 2005/00271,
Philips Research, March 2005.
18. Andreas Hansson, Kees Goossens, and Andrei Rădulescu. UMARS:
A unified approach to mapping and routing on a combined guaranteed
service and best-effort network-on-chip architecture. Technical Report
2005/00340, Philips Research, April 2005.
19. Benny ˚Akesson, Kees Goossens, and Andrei Rădulescu. An analytical
model for a memory controller offering hard-real-time guarantees. Technical
Report 2005/00353, Philips Research, April 2005.
20. Xiao Ru, John Dielissen, Kees Goossens, and Christer Svensson. Synchronous
latency-insensitive design in Æthereal. Technical Note 2005/00352,
Philips Research, August 2005.
23

21. Razvan Dinu, Kees Goossens, Andrei Rădulescu, Peter van den Hamer,
and Ewa Hekstra-Nowacka. Refactoring the aethereal network-on-chip
design flow: Extended data model. Technical Note 2005/00685, Philips
Research, August 2005.
22. Razvan Dinu, Kees Goossens, and Andrei Rădulescu. Analysis and refactoring
of a design flow for application-specific networks on chip. Technical
Note 2005/00686, Philips Research, 2005.
23. Prathiba Sharma, Kees Goossens, Andrei Rădulescu, and Martijn Coenen.
Configuring the æthereal NoC using an ARM processor. Technical Note
2005/00568, Philips Research, July 2005.
24. Santiago González Pestana, Kees Goossens, Andrei Rădulescu, and Rikard
Thid. Framework and performance metric definitions: A first step towards
network-on-chip benchmarking. Technical Note 2006/00003, Philips Research,
January 2006.
25. Andreas Hansson, Kees Goossens, and Andrei Rădulescu. Analysis of
message-dependent deadlock in network-based systems on chip. Technical
Report 2006/00230, Philips Research, March 2006.
26. Markus Ringhofer, Kees Goossens, and Benny ˚Akesson. Design and implementation
of a memory controller for real-time applications. Technical
Note 2006/00500, Philips Research, November 2006.
27. Remco van Steeden, Martijn Bennebroek, Kees Goossens, and Bart Vermeulen.
Communication-centric debug of systems on chip using networks
on chip. Technical Note 2006-00541, Philips Research, October 2006.
28. Pengwei Ren, Erik Jan Marinissen, Kees Goossens, Sandeep Goel, and
Georgi Gaydadjiev. Wrapper design for the reuse of a NOC or other
functional interconnect as test infrastructure. Technical Note NPX-R-TN
2007/00094, NXP Semiconductors Research, May 2007.
29. Benny ˚Akesson, Liesbeth Steffens, Eelke Strooisma, and Kees Goossens.
Real-time scheduling of hybrid systems using credit-controlled static-priority
arbitration. Technical Note NPX-TN 2007/00119, NXP Semiconductors
Research, September 2007.
30. Siddharth Umrani, Kees Goossens, and Bart Vermeulen. Debug infrastructure
for communication-centric debug of systems-on-chip using a
network-on-chip. Technical Note NPX-TN 2007/00132, NXP Semiconductors
Research, December 2007.
31. Radu Stefan, Ioannis Sourdis, Georgi Gaydadjiev, and Kees Goossens.
Comparison of custom topology networks against rigid interconnects. Technical
Report CE-TR-2008-01, Computer Engineering, Delft University of
Technology, February 2008.
32. Eelke Strooisma, Benny ˚Akesson, Kees Goossens, and Ad Siereveld. A predictable
and composable front-end for system on chip memory controllers.
Technical Note NXP-TN-2007-00281, NXP Semiconductors, May 2008.
33. Firew Siyoum, Benny Akesson, Sander Stuijk, Kees Goossens, and Henk
Corporaal. Dataflow model for credit-controlled static-priority arbitration.
Technical Report ESR-2010-03, Electronic Systems, Eindhoven university
of technology, October 2010.
24

5 Patents
5.1 Granted patents
Note that granted patents are often also still pending in other countries (e.g.
EP, US, KR, JR, DE).
1. WO2004034176(A2), EP2003748424 granted 26/9/2007, US7366818
granted 29/5/2008, “Integrated circuit for establishing transactions,”
Andrei Rădulescu, Kees G. W. Goossens
2. WO2004034676(A1), EP2003740945 granted 19/9/2007, US7769893
granted 3/8/2010, “Integrated circuit for establishing transactions,”
Kees G. W. Goossens
3. WO2004099999(A2,A3), US7356669(B2) granted 8/4/2008, KR1020057020935
granted 12/7/2011, “Processing system and method for transmitting
data,” Andrei Rădulescu, Kees G. W. Goossens
4. WO2005091574(A1), US10598795 granted 22/9/2009, EP1728364(A1)
request for examination, JP2007529808(T), CN1934831(A), “Integrated
circuit and method of communication service mapping,” Andrei Rădulescu,
Kees Goossens
5. WO2005093590(A1), US10599201 granted 29/3/2011, EP2005709014
granted 26/5/2010), KR20070003969(A), JP2007534052(T), CN1934550(A),
“Integrated circuit and method for transaction retraction,” Andrei Rădulescu,
Kees Goossens
6. WO2005111823(A1), US11569083 granted 27/12/2011, EP2005739743
granted 21/05/2008, “Integrated circuit and method for buffering to
optimize burst length in networks on chips,” Andrei Rădulescu, Kees
Goossens
7. WO2005122631(A1), EP2005745222 granted 21/11/2007, KR1020067025908
granted 27/10/2011 “Integrated circuit and method for time slot allocation,”
O. P. Gangwal, Andrei Rădulescu, Kees Goossens
8. WO2004100006(A1),KR1020057020935 granted 12/7/2011, EP1623330(A1)
examination in progress, US2006253604(A1) and continuation US 2011/0219155(A1)
granted 8/9/2011, JP2006525587(T), CN100390771(C), CN1784669 (A),
“Processing system and method for transmitting data,” Andrei Rădulescu,
Kees G. W. Goossens
9. WO2006059284(A1), US11720211 granted 8/12/2009, EP1820356(A1),JP2008522306(T),
CN101069434(A), “Data processing system and method for converting and
synchronising data,” Kees Goossens, Andrei Rădulescu and Edwin Rijpkema
10. WO2005093591(A1), US10599215 granted 3/11/2009, EP1735712(A1)
examination in progress, KR20070010127(A), JP2007531101(T), CN1938695(A),
“Integrated circuit and method for transaction abortion,” Andrei Rădulescu,
Kees Goossens
11. WO2008004187, EP2041920 granted 13/4/2011, US7969899 granted
28/6/2011, “Electronic device, system on chip and method of monitoring
data traffic,” Kees Goossens and Calin Ciordas.
25

12. WO2004034590(A2,A3), EP2003807931 granted 12/9/2007, KR1020057005982
granted 30/11/2010, “Integrated circuit and method for sending requests,”
Andrei Rădulescu, Kees G. W. Goossens
13. WO2006123287(A2,A3), US8005097 granted 23/8/2011, JP2008541647(T),
CN101176318(A), “Integrated circuit and method of arbitration in a network
on an integrated circuit,” Rikard Thid, Kees Goossens, and Andrei
Rădulescu.
14. WO2004100005(A1), US7412549(B2) granted 12/8/2008, KR1020057021132
granted 15/7/2011, “Processing system and method for communicating
data,” Andrei Rădulescu, Kees G. W. Goossens
15. WO2004034173(A2,A3), US7373449 granted 13/5/2008, KR1020057005986
granted 29/11/2010, “Integrated circuit and method for exchanging
data,” Andrei Rădulescu, Kees G. W. Goossens
5.2 Published pending patents
Patent applications in various countries at various stages.
1. WO2003034657(A2,A3), JP withdrawn, US20030074389(A1), AU2002329567(A1),
“Scheme for dynamic process network reconfiguration,” I-Chih Kang, Albert
van der Werf, Kees G.W. Goossens
2. WO2004056051(A1), EP1576773(A1) request for examination, US2006077974(A1),
JP2006511115(T), CN1729661(A), AU2003276606 (A1), “Return-path derivation
in packet-switched networks,” Kees G. W. Goossens, Edwin Rijpkema,
and Paul Wielage
3. WO2005103934(A1), EP1743251(A1) examination in progress, US2007234006(A1),
KR20070010152(A), JP2007535057(T), CN1947112(A), “Integrated circuit
and method for issuing transactions,” Andrei Rădulescu, Kees Goossens
4. WO2006018751(A1), EP1779608(A1), US2008123541(A1), JP2008510337(T),
CN101002443(A), “A method for allocating data to at least one packet in
an integrated circuit,” John Dielissen, Kees Goossens, Andrei Rădulescu,
Edwin Rijpkema
5. WO2006051471(A1), EP1813066(A1) published, US2008123666(A1), JP2008520119(T),
CN101053225(A), “Electronic device and method of communication resource
allocation”, Calin Ciordas, Kees Goossens, and Andrei Rădulescu
6. WO2006056904(A2,A3) withdrawn, “Globally Asynchronous Locally Synchronous
Systems,” Kees van Kaam, John Dielissen, Kees Goossens
7. WO2006059277(A2,A3), EP1839183(A2) withdrawn, US2008144670(A1),
P2008522526(T), CN101069174(A), “Data processing system and method
for synchronizing data traffic,” Kees Goossens and Andrei Rădulescu
8. WO2006067709(A1), EP5825568 withdrawn, “Data processing system and
method for configuring a network on an at least one integrated circuit,”
Edwin Rijpkema, John Dielissen, Kees Goossens
9. WO2006092768(A1), EP1859575(A1) withdrawn, US2008215786(A1), JP2008532169(T),
CN101133597(A), “Device and method for arbitrating shared resources,”
Kees Goossens, John Dielissen, Andrei Rădulescu, Edwin Rijpkema, and
Paul Wielage
26

10. WO2006117746(A1), EP0715261(A1) examination in progress, EP1880296,
US2008244135(A1), JP2008541217(T), “Memory controller and method
for controlling access to a memory, as well as system comprising a memory
controller,” Benny Akesson, Andrei Rădulescu, Kees Goossens, Frits
Steenhof
11. WO2007010461(A2,A3), EP1911218 (A2), US2008232387(A1), JP2009502080(T),
CN101223745(A), “Electronic device and method of communication resource
allocation,” Edwin Rijpkema, Andrei Radulescu, Kees Goossens,
and John Dielissen
12. WO2007122547(A2,A3), EP2014032(A2), JP2009507206, “Electronic device
with end-to-end flow control of messages,” Srinivasan Murali, Martijn
Coenen, Andrei Rădulescu, and Kees Goossens
13. WO2008004185, EP2041933, “Electronic device, system on chip and method
for monitoring data traffic,” Kees Goossens, Calin Ciordas, Andrei Rădulescu
14. WO2008004188, EP2041661, “Electronic device, system on chip and method
for monitoring a data flow,” Calin Ciordas, Kees Goossens, Andrei Rădulescu
15. WO2008018017(A2,A3), “System for communication control of integrated
circuits,” Martijn Bennebroek, Kees Goossens, Bart Vermeulen.
16. WO2008035265(A3), “Electronic device and controlling a communication
between processing units,” Kees Goossens and Martijn Coenen.
17. EP2428912, “ System and method for responding to a request received at
an object with an RFID device” Kees Goossens and Lukasz Szostek.
18. WO2009138953(A1),“Power manager and method for managing power”
Artur Burchard, Ger Kersten, Anca Molnos, Aleksandar Milutinovic, Kees
Goossens, Liesbeth Steffens.
19. WO2009125371(A2), “A method and system for power management,” Artur
Burchard, Anca Molnos, Aleksandar Milutinovic, Kees Goossens, Liesbeth
Steffens.
6 Professional Activities
6.1 Research Grants
1. Definition of and principal investigator for Encoding Relational Semantics
in Automated Proof Systems for a visiting researcher grant (1 year) for
CNPq (Brasilian national grant body), 1993-1994.
2. Responsible for the Philips contribution to the Multi-processor work package
in the Medea+ MESA project, 2001-2004.
3. Technical contribution to the Medea+ NEVA project, and responsibility
for the Philips/NXP contribution to the Multi-Level-Networking work (30
person years), 2005-2008.
4. Supervisor of a Marie-Curie Early-Stage-Training fellow of the Sprint
project, 2002-2005.
5. Principal co-investigator for NXP and TUD for the Netherlands Streaming
(NEST) STW project, 2009-2012 (4 years). 1 PhD and 2 PhDs at NXP
27

and TUD, respectively.
6. Principal investigator for NXP, and definition of contributions for NXP
and TUD for the Tera-Scale Multi-Core Processor Architecture (TSAR)
MEDEA+ project, 2008-2011 (3 years). 3 and 4.5 person years at NXP
and TUD, respectively.
7. Principal investigator for NXP, and definition of the NXP and TUD contributions
for the 3D-TSV Integration for Multimedia and Mobile applications
(3DIM3) CATRENE project, 2009-2011. 34 and 18 person years at
NXP and TUD, respectively.
8. Definition of the NXP and TUD contributions for the Communication-
Centric Heterogeneous Multi-Core Architectures (COMCAS) CATRENE
project, 2009-2011 (3 years). 24 and 12.3 person years at NXP and TUD,
respectively.
9. Principal investigator for NXP, and definition of NXP and TUD contributions
for the Scalable Low-Power Embedded Platforms (SCALOPES)
Artemis project, 2009-2010 (2 years). 33 and 9 person years at NXP and
TUD, respectively.
10. Principal investigator for NXP, and definition of the NXP and TUD contributions
for the Industrial Exploitation Of The Genesys Cross-Domain
Architecture (INDEXYS) 2008 Artemis project, 2009-2011 (2 years). 5
and 2.5 person years at NXP and TUD, respectively.
11. Principal co-investigator for TUD, and definition of TUD contributions
for the Computing Fabric for high performance Applications (COBRA)
2009 Catrene project, 2010-2012 (3 years). 15 person years at TUD.
12. Principal investigator for the FP7-ICT-2011-7 project Time-predictable
Multi-Core Architecture for Embedded Systems (T-CREST), grant agreement
number 288008, 2011-2014 (3 years). 5.1 person years.
13. Principal investigator for the FP7-ICT-2011-7 project Self adaptive heterogeneous
manycore based on Flexible Tiles (Flextiles), grant agreement
number 288248. 4.6 person years.
6.2 Other Professional Activities
1. 2007, External project proposal examinator for the System on Chip programme,
Austrian Research Promotion Agency.
2. 2008, Gave a two-day course on networks on chip for the European patent
office (EPO) at Rijswijk.
3. 2009, External project proposal examinator for the Swiss National Science
Foundation.
4. 2009, External project proposal examinator for the Estonian Science Foundation.
5. 2009, Member of assessment committee for professor position, Technical
University of Denmark.
6. 2009, Member of assessment committee (“benoemingsadviescommissie”)
for professor position, Technical University of Delft.
7. 2010, External project proposal examinator for the System on Chip pro-
28

gramme, Austrian Research Promotion Agency.
8. 2011, Consultant for Philips on Network on Chip patent portfolio.
9. 2011, Assessment for professor position, Philadelphia University of Jordania.
10. 2011, Member of assessment committee (“benoemingsadviescommissie”)
for professor position, Technical University of Delft.
11. 2012, Member of habilitation committee for Prof. O. Hammami, Université
Paris Sud.
6.3 Journal & Conference Reviewing
Editorial board:
1. TODAES 2009-2013 Editorial board member for the Association for
Computing Machinery (ACM) Transactions on Design Automation of
Electronic Systems. (I served for the maximum term of 4 years.)
2. DAEM 2006-present Associate editor for the Springer Journal of Design
Automation of Embedded Systems.
3. IJECRTS April 20011 to March 2013 Editorial Review Board of the Resources
Management Association (IRMA) International Journal of Embedded
and Real-Time Communication Systems.
4. CDT 2008 Guest editor for the IET Computers and Digital Techniques
special issue on networks on chip.
5. DAEM 2011 Guest editor for the Springer Journal of Design Automation
of Embedded Systems for the special issue on on Networks on chips: design
flows and case studies.
TPC / conference (co)-chair:
1. ACSD 2006 Programme committee co-chair of Applications of Concurrency
Theory to System Design.
2. DATE 2005-2008 Technical programme committee co-chair for the Multiprocessors
and Networks on Chip track of the Design Automation and Test
in Europe Conference.
3. NOCS 2007-2012 Steering committee member for the International Symposium
on Networks on Chips.
4. NOCS 2008 Programme co-chair for the International Symposium on
Networks on Chips.
5. NOCS 2009 Tutorial chair for the International Symposium on Networks
on Chips.
6. MPSOC 2012-2013 Co-chair for International Seminar on Application-
Specific Multi-Processor Systems on Chip.
TPC member:
1. CODES+ISSS 2006-2012 Technical programme committee member of
the International Conference on Hardware-Software Codesign and System
Synthesis.
2. CRTS 2012, Workshop on Compositional Theory and Technology for
Real-Time Embedded Systems.
29

3. DATE 2004, 2008-2013 Technical programme committee member for the
Multi-processors and Networks on Chip track of the Design Automation
and Test in Europe Conference.
4. DSD 2008 Technical programme commmittee member of the Euromicro
Conference on Digital System Design. 2010-2013, Special session programme
“Multicore Systems: Design And Applications” steering member
and committee member.
5. ECRTS 2013 Technical programme commmittee member of the Euromicro
Conference on Real-Time Systems.
6. FPL 2010-2012, Technical programme commmittee member of the International
Conference on Field Programmable Logic and Applications.
7. ICPP 2011 Programme committee member of the Multi-core and Parallel
Systems track of the International Conference on Parallel Processing.
8. INA-OCMC 2007-2013 Programme committee member of the Interconnection
Network Architectures: On-Chip, Multi-Chip workshop in conjunction
with the HiPEAC Int. Conf. on High Performance Embedded
Architectures & Compilers.
9. MPSOC 2005-2011 Technical programme committee member of the International
Seminar on Application-Specific Multi-Processor Systems on
Chip.
10. NOCS 2007-2013 Technical programme committee member of the International
Symposium on Networks on Chips.
11. OMHI 2012 Technical programme committee member of the International
Workshop on On-chip memory hierarchies and interconnects: organization,
management and implementation.
12. PARMA 2011-2013 Technical programme committee member of the Workshop
on Parallel Programming and Run-time Management Techniques for
Many-core Architectures.
13. QVVP Quo Vadis, Virtual Platforms? Challenges and Solutions for Today
and Tomorrow, Programme committee DATE Friday workshop, 2012.
14. ReConFig 2009 Technical programme committee member of the International
Conference on ReConFigurable Computing and FPGAs.
15. RTAS 2013 Technical programme committee member of the Real-Time
and Embedded Technology and Applications Symposium.
16. SAMOS 2007-2010 Programme committee member of the International
Symposium on Systems, Architectures, MOdeling and Simulation.
17. SDR 2010 Technical programme committee member of the Software Defined
Radio Technical Conference (SDR).
18. SOC 2004-2012 Scientific programme committee member of International
Symposium on System-on-Chip (TUT, Finland).
19. VLSI-SoC 2006 Technical programme committee member of IFIP International
Conference on Very Large Scale Integration.
Reviewing:
1. CSUR 2011 Reviewer for ACM Computing Surveys.
2. CDT 2005-2006 Reviewer for IEE Proceedings Computers & Digital Techniques.
30

3. DAC 2006, 2007, 2011 Reviewer for the Design Automation Conference.
4. DAES 2006 Reviewer for ACM Transactions on Design Automation of
Electronic Systems.
5. DTC 2004-2006,2011 Reviewer for IEEE Design and Test of Computers.
6. ESSCIRC 2009 Reviewer for IEEE European Solid-State Circuits Conference
7. GLSVLSI 2011 Great Lakes Symposium on VLSI.
8. ICPP 2011 International Conference on Parallel Processing.
9. ISCAS 2009,2010,2012 Reviewer for Int’l Symposium on Circuits and
Systems.
10. JCST 2012 Reviewer for Journal of Computer Science and Technology.
11. JPDC 2010 Reviewer for Journal of Parallel and Distributed Computing
12. MICPRO 2010 Reviewer for Elsevier Microprocessors and Microsystems.
13. MR 2011 Reviewer for Elsevier Microelectronics Reliability journal.
14. SAMOS 2011 Reviewer for International Symposium on Systems, Architectures,
MOdeling and Simulation.
15. TACO 2009 Reviewer for ACM Transactions on Architecture and Code
Optimization.
16. TCAS 2009 Reviewer for IEEE Transactions on Circuits and Systems.
17. TCOMP 2007 Reviewer for IEEE Transactions on Computers.
18. TECS 2010-2011 Reviewer for ACM Transactions on Embedded Computing
Systems.
19. TC 2007,2009 Reviewer for IEEE Transactions on Computers.
20. TVLSI 2008, 2010 Reviewer for IEEE Transactions on Very Large scale
Integration Systems.
6.4 Teaching
1. Created and lectured the short MSc course “ Topics in Theorem Proving”
at the Universidade Federal de Pernambuco at Recife, 1994.
2. Created and lectured the final-year elective MSc course “Network on chips”
(ET4361) of 5 ECTS credits at the Delft university of Technology, academic
years 2006/07 - 2008/09.
3. Responsible for, and co-lectured the compulsory MSc course “Embedded
System Lab” (5KK03) of 5 ECTS credits at the TUE, academic years
2010/11 - 2012/2013. Student satisfaction score 8.7 in academic years
2009/10, and 8.35 in 2010/11.
4. Created, lectured, and supervised the course “Design of Complex Systems”
(5JJ30) of 3 ECTS credits at the TUE, academic years 2010/11 (first-year
EE bachelor) and 2012/13 (second-year year EE (Automotive) bachelor).
5. Created and lectured the compulsory PDEng (post-master) course “Design
and modelling of Complex Systems” (5Z028) of 5 ECTS credits at the
TUE, academic years 2011/12, 2012/13.
6. Responsible for, and supervision of PDEng (post-master) students for the
compulsory course “ICT Systems (Group Project)” (5Z045) of 8 ECTS
credits at the TUE, academic years 2011/12, 2012/2013.
31

7. (Partially) created and co-lectured the compulsory BSC Automotive EE
course “Vehicle networking” (5JJ75) of 5 ECTS credits at the TUE, academic
year 2012/13.
In the academic years starting 2008-2012, the CompSOC research platform
has been used in the Embedded Systems Lab, a MSc course that is compulsory
for Embedded Systems students. The number of students has grown from 30
in the first year, to 55 in 2012. The course has always been very popular, and
has consistently received very high ratings from students. The concepts and organisation
of the course have been published in “Multi-Processor Programming
in the Embedded System Curriculum” by Andreas Hansson, Benny kesson, and
Jef van Meerbergen in Workshop on Embedded Systems Education (WESE),
2008.
For two academic years (2010/11, 2011/12), the Embedded Systems Lab
also ran at the Delft University of Technology, with minor modifications. The
course was organised and run by PhD students that I supervised (Stefan, Nelson,
Beyranvand).
In the academic years 2011-2012, the same CompSOC hardware platform
was used, but with different assignments in the TU Delft’s Embedded Computer
Architecture course. The concepts and organisation of this course have been
published in [87].
6.5 Organised Tutorials, Special Sessions, etc.
I (co)-organised the following events:
1. EMSOFT tutorial “Time-Predictable and Composable Architectures for
Dependable Embedded Systems,” October 2011, with Saddek Bensalem.
With participation of Prof. Sifakis, Prof. Obermaisser, Prof. Goossens,
Prof. Lee, and Prof. Kirsch.
2. CODES+ISSS special session “DRAM Controllers for High-Performance
and Real-Time MPSoCs: Requirements, Architectures, and Future Trends,”
October 2011. With participation of Drew Wingard, Sonics Inc., Tei-Wei
Kuo, National university of Taiwan, Denis Dutoit, CEA LETI, Benny
Akesson, Kees Goossens, Eindhoven University of Technology.
3. “Designing Next-Generation Real-Time Streaming Systems” at ESWEEK,
October 2011. With participation of TU Eindhoven, ST Ericsson, and
University of California at Berkeley.
4. CompSOC presentation and demonstration at the University Booth at
Proc. Design, Automation and Test in Europe Conference and Exhibition
(DATE), March 2012.
5. Full-day tutorial on predictability and composability, Eindhoven, January
2012. About 40 attendees, including from KTH, Sweden and KIT, Germany.
6. “Designing Next-Generation Real-Time Streaming Systems” at HiPEAC,
January 2013. With participation of TU Eindhoven, ST Ericsson, and
University of Saarland.
32

7. CompSOC presentation and demonstration at Real-Time Systems Symposium
at Work session (RTSS), December 2012.
6.6 Invited Presentations
1. Hot topic “Network on a Chip,” Design Automation and Test in Europe
Conference, France, March 2002.
2. Invited speaker “Systems on Chip and Networks on chip: bridging the gap
with QoS,” International Seminar on Application-Specific Multi-Processor
Systems on Chip (MPSOC), France, July 2003.
3. Invited speaker “How Networks on Chip can Contribute to Building Predictable
Systems on Chip,” MEDEA+ workshop, Germany, November
2003.
4. Invited speaker “Predictable Systems: Reality, or just an illusion?” for
International Seminar on Application-Specific Multi-Processor Systems on
Chip (MPSOC), France, July 2004.
5. Invited speaker “Predictable Systems: Reality, or just an illusion?” for
Digital Circuits, Multimedia & Implementation track of ProRisc, Netherlands,
November 2004.
6. Invited speaker “Networks on Chip: Science or Science Fiction?” for the
OCP Partnership panel “Networks on Chip: Great Idea, but where are
the Implementations?” DATE Exhibition, March 2005.
7. Invited speaker “Formal methods for system (and network) on chip design,”
for International Conference on Application of Concurrency to System
Design (ACSD), France, June 2005.
8. Invited speaker “Systems on Chips: Personal computers or correct performance?”for
International seminar on application-specific multi-processor
systems on chip (MPSOC), France, July 2005.
9. Invited speaker for panel “Looking Through the On-Chip Channels” of
Future Interconnects and Network on Chip workshop at Design, Automation
and Test in Europe Conference and Exhibition (DATE), Germany,
March 2006.
10. Invited speaker “Quality of Service for an uncertain World” for International
seminar on application-specific multi-processor systems on chip
(MPSOC), Colorado, August 2006.
11. Participation in panel “Networks on Chip: Panacea for IP Integration &
SoC Design?” of the Network on Chip panel at Design, Automation and
Test in Europe Conference and Exhibition (DATE), April 2007.
12. Invited speaker “Impact of diagnostic services on NOC architectures and
design flows,” of the Diagnostic Services in Networks-on-Chips workshop
at Design, Automation and Test in Europe Conference and Exhibition
(DATE), April 2007.
13. Invited speaker “Debug, Test, and Security Services on Networks on Chip”
for International seminar on application-specific multi-processor systems
on chip (MPSOC), Japan, June 2007.
14. Invited speaker in the special session “You can catch more bugs with trans-
33

action level honey” of the International Conference on Hardware/Software
Codesign and System Synthesis (CODES+ISSS), October 2008.
15. Invited speaker “Hardwired Networks on Chip for FPGAs” for the Tubs.City
symposium, at the TU Braunschweig, Germany, July 2009.
16. Invited speaker “Virtualisation in NOCs for enhanced MPSOC robustness
and performance verification” in the work shop “Multiprocessor System
on Chip – Current Trends and the Future” of the Design Automation
Conference (DAC), July 2009.
17. Invited speaker “Hardwired Networks on Chip for FPGAs” for International
seminar on application-specific multi-processor systems on chip
(MPSOC), Georgia, USA, August 2009.
18. Invited speaker “The Aethereal NOC after Ten Years: Goals, Evolution,
lessons, and Future” in the “A Decade of NOC Research - Where Do We
Stand?” special session of the Design Automation Conference (DAC),
June 2010.
19. Invited speaker on the technical panel on “Tackling device degradation
effects in NoCs” on the Workshop on Diagnostic Services in Network-on-
Chips (DSNOC), June 2010.
20. Invited speaker “Virtualised processor power management” for International
seminar on application-specific multi-processor systems on chip (MP-
SOC), Gifu, Japan, July 2010.
21. Invited speaker “Debugging Embedded Systems – From ad hoc to science”
ICES ENEA workshop on debugging, Kista, Sweden, October, 2010.
22. Invited speaker “Debugging heterogeneous manycore systems” on the SOC
design workshop organised by Intel, November 2010.
23. Invited speaker on the panel on “Micro Power Management for Macro
Systems-on-Chip” (µP M 2 SoC) workshop at the DATE, March 2011.
24. Invited speaker “Architectures and modelling of predictable memory controllers
for improved system integration” in the “Predictable System Integration”
special session at DATE, March 2011.
25. Invited speaker “Efficient Real-Time SDRAM performance” for International
seminar on application-specific multi-processor systems on chip
(MPSOC), France, July 2011.
26. Invited speaker “The Aethereal network on chip” Newcastle university,
December 2011.
27. Invited speaker “CompSOC: A Composable and Predictable Execution
Platform” on the “Quo Vadis, Virtual Platforms: Challenges and Solutions
for Today and Tomorrow” (QVVP’12) workshop at the DATE, March
2012.
28. Invited talk about IMEC-NL on networks on chip, in particular low power
aspects, April 2012.
29. Invited speaker “CompSOC: A Mixed-Criticality Multi-MOC Execution
Platform” for International seminar on application-specific multi-processor
systems on chip (MPSOC), Quebec, Canada, July 2012.
30. Invited speaker “CompSOC: A Mixed-Criticality Multi-MOC Execution
Platform” Vienna university, 15 October 2012.
34

31. Invited speaker on the panel on “Timing isolation in commercial-of-theshelf
systems” at the CRTS workshop, Puerto Rico, December 2012.
32. Invited speaker “Something XXXXXXXXX” for International seminar
on application-specific multi-processor systems on chip (MPSOC), Japan,
July 2013.
6.7 Invited Lectures, Tutorials, etc.
1. Presented (part of) the CCT course “Phideo” on high-level behavioural
synthesis a number of times at Philips from 1995-1999.
2. Invited MSc course “Quality of Service in Networks on Chip: the Æthereal
Approach,” KTH, Sweden, May 2003.
3. Tutorial “Assembling an SoC: Communication Architectures and Protocols,”
Design automation conference (DAC), US, June 2003.
4. Tutorial “Predictable Performance in SoC and NoC,” and “Quality of
Service in Networks on Chip,” for the “Multiprocessor Systems on Chip”
Swedish national summer school (INTELECT), Sweden, August 2003.
5. Guest lecture “Predictable Performance in Systems on Chip and Networks
on Chip,” at the TUE, Eindhoven, October 2003.
6. Teaching in the CTT course “Top-Down VLSI Design,” at Philips, 2003.
7. Invited lecture (“Computation Architectures” and “Communication Architectures”)
for ASCI Winterschool on Embedded Systems, March 2004.
8. Invited MSc course “Predictable Performance in SoCs - A Case Study”
and “Quality of Service in On-Chip Interconnects,” KTH, Sweden, March
2004.
9. Guest lecture “Quality of Service in On-Chip Interconnects,” TUE, Eindhoven,
October 2004.
10. Guest lecture “Interconnects for Systems on Chip,” Lund University, Sweden,
October 2005.
11. Guest lecture “Interconnects for Systems on Chip,” TUE, Eindhoven, October
2005.
12. Lecture “Project leadership: Why and how did this happen to me?” for
project leader course (several times).
13. Invited lecture “On-Chip Interconnects: Architectures and Design Flows,”
for ASCI Winterschool on Embedded Systems, March 2006.
14. Tutorial “Quality of service in networks,” at the “NoC at the Age of Six:
Advanced Topics, Current Challenges and Trends” tutorial at the Design,
Automation and Test in Europe Conference and Exhibition (DATE), April
2007.
15. Lecture “Challenges in System on Chip Design” for NXP Semiconductors
course for system architects, December 2007.
16. Guest lecture “Networks on Chip,” at the TUE, Eindhoven, December
2008.
17. Guest lecture “Networks on Chip,” at the TUE, Eindhoven, November
2009.
18. Guest lectures “Swarm Intelligence,” at the TUE, Eindhoven, December
35

2009.
19. Colloquium “MPSOC performance virtualisation for enhanced robustness
and performance verification” at Computer Science, TUE, Eindhoven, December
2011.
20. Invited lecture “CompSOC - A predictable and composable execution platform”
at ASCI Winterschool on Embedded Systems, March 2012.
7 Mangement, Promotions, Supervision
7.1 Promotor
1. Andreas Hansson “A Composable and Predictable On-Chip Interconnect.”
Second promotor, Eindhoven University of Technology, June 2009. Cum
laude thesis, and winner of the Else Kooij Prize.
2. Benny Akesson “Predictable and Composable System-on-Chip Memory
Controllers.” Promotor, Eindhoven University of Technology, February
2010.
3. Jae Young Hur “Customizing and Hardwiring On-Chip Interconnects in
FPGAs.” Promotor, Delft University of Technology, The Netherlands,
January 2011.
4. Radu Stefan “Resource Allocation in Time-Division-Multiplexed Networks
on Chip,” Promotor, Delft University of Technology, The Netherlands,
April 2012.
5. Muhammad Aqeel Wahlah “Field Programmable Gate Arrays with Hardwired
Networks on Chip.” Promotor, Delft University of Technology, The
Netherlands, November 2012.
For the following promotions, I replaced the deceased original promotor Prof.
S. Vassiliadis, and was not actively involved with the research of the promovendus/a.
1. Lotfi Mhamdi “Scheduling in High Performance Buffered Crossbar Switches.”
PhD committee, Delft University of Technology, The Netherlands, October
2007.
2. Iosif Antochi “Suitability of Tile-Based Rendering for Low-Power 3D Graphics
Accelerators.” Co-promotor, Delft University of Technology, The Netherlands,
October 2007.
3. Daniel Ramiro Humberto Calderón Racabado “Arithmetic Soft-Core Accelerators.”
Promotor, Delft University of Technology, The Netherlands,
November 2007.
4. Christoforos Krachis “Reconfigurable Network Processing Platforms.” Promotor,
Delft University of Technology, The Netherlands, December 2007.
5. Ricardo Chaves “Secure Computing on Reconfigurable Systems.” Promotor,
Delft University of Technology, The Netherlands, December 2007.
6. Ioannis Sourdis “Designs & Algorithms for Packet and Content Inspection.”
Co-promotor, Delft University of Technology, The Netherlands,
December 2007.
36

7. Asadollah Shahbahrami “Avoiding Conversion and Rearrangement Overhead
in SIMD Architectures.” Promotor, Delft University of Technology,
The Netherlands, September 2008.
8. Filipa Duarte “A Cache-based Hardware Accelerator for Memory Data
Movements.” Promotor, Delft University of Technology, The Netherlands,
October 2008.
9. Anca Mariana Molnos “Task-Centric Memory Management for an On-
Chip Multiprocessor.” Promotor, Delft University of Technology, The
Netherlands, January 2009.
10. Carlo Galuzzi “Automatically Fused Instructions.” Promotor, Delft University
of Technology, The Netherlands, May 2009.
11. Pepijn de Langen “Energy Reduction Techniques for Caches and Multiprocessors.”
Promotor, Delft University of Technology, The Netherlands,
October 2009.
12. Behnaz Pourebrahimi “An Economic Framework for Resource Allocation
in Ad-hoc Grids.” Promotor, Delft University of Technology, The Netherlands,
November 2009.
13. Cor Meenderinck “Improving the Scalability of Multicore Systems With a
Focus on H.264 Video Decoding.” Promotor, Delft University of Technology,
The Netherlands, July 2010.
7.2 PhD Committees
1. Daniel Wiklund Licentiate defence, Linkoping University, Sweden, 2003.
2. Giuseppe Garcea “Trade offs in Buffer Planning.” PhD committee, TU
Delft, The Netherlands, June 2005.
3. Tobias Bjerregaard “The MANGO Clockless Network-on-Chip: Concepts
and Implementation.” PhD opponent, DTU, Sweden, January 2006.
4. Nikolay Kavaldjiev “A Run-Time Reconfigurable Network-on-Chip for
Streaming DSP Applications.” PhD committee, Technical University Twente,
The Netherlands, January 2006.
5. Zhonghai Lu “Design and Analysis of On-Chip Communication for Networkon-Chip
Platforms.” PhD opponent, KTH, Sweden, March 2007.
6. Elena Moscu Panainte “The Molen Compiler for Reconfigurable Architectures.”
PhD committee, Delft University of Technology, The Netherlands,
June 2007.
7. Théodore Marescaux “Mapping and Management of Communication Services
on MP-SoC Platforms.” PhD committee, Eindhoven University of
Technology, The Netherlands, September 2007.
8. Sander Stuijk “Predictable Mapping of Streaming Applications on Multiprocessors.”
PhD committee, Eindhoven University of Technology, The
Netherlands, October 2007.
9. Petro Poplavko “An accurate Analysis for Guaranteed Performance of
Multiprocessor Streaming Applications.” PhD committee, Eindhoven University
of Technology, The Netherlands, November 2008.
37

10. Claudiu Zissulescu-Ianculescú “Synthesis of a Parallel Data Stream Processor
from Data Flow Process Networks.” PhD committee, Leiden University,
The Netherlands, November 2008.
11. Calin Ciordas “Monitoring-Aware Network-on-Chip Design.” PhD committee,
Eindhoven University of Technology, The Netherlands, December
2008.
12. Pascal T. Wolkotte “Exploration Within the Network-on-Chip Paradigm.”
PhD committee, Technical University Twente, The Netherlands, January
2009.
13. Arno Moonen “Predictable Embedded Multiprocessor Architecture for
Streaming Applications.” PhD committee, Eindhoven University of Technology,
The Netherlands, June 2009.
14. Zhoukun Wang “Design and Multi-Technology Multi-Objective Comparative
Analysis of Families of MPSOC.” PhD examiner, Institute polytechnique
de Grenoble, November 2009.
15. Mahmood Ahmady “High-performance Processing in Networked and Grid
Environments.” PhD committee, Delft University of Technology, The
Netherlands, May 2010.
16. Sahar Foroutan “‘An Analytical Method for Performance Evaluation of
Networks-on-Chip,” PhD committee, CEA/LETI, September 2010.
17. Marius Gligor “Fast Simulation Strategies and Adaptive DVFS Algorithm
for Low Power MPSoCs,” PhD committee, TIMA, Grenoble, france,
September 2010.
18. Claudia Russu “Multi-Level Fault-Tolerance in Networks-on-Chip,” PhD
committee, Institute Polytechnique de Grenoble, France, September 2010.
19. Orlando Moreira “Temporal Analysis and Scheduling of Hard Real-Time
Radios running on a Multi-Processor,” PhD commitee, TU Eindhoven,
January 2012.
20. Ra’Ed Al-Dujaily “Embedded Dynamic Programming Networks for Networks-
On-Chip,” PhD commitee, University of Newcastle, August 2012.
21. Leando Fiorin “High level services for Networks-on-Chip,” PhD commitee,
Universitá della Svizzera Italiana, September 2012.
22. Mikel Azkarate-Askasua “The Transient Tolerant Time-Triggered Systemon-Chip
(4TSoC),” PhD commitee, TU Wien, 2012.
7.3 Team Leader
I guide(d) the following people (post-docs, researchers, technical programmers):
1. Benny ˚Akesson, post-doc
2. Arnaldo Azevedo, post-doc
3. Jude Angelo Ambrose, post-doc
4. Sven Goossens, researcher
5. Martijn Koedam, technical programmer
6. Cor Meenderinck
7. Anca Molnos, post-doc
8. Radu Stefan, post-doc
38

9. Jun Zhu, post-doc
7.4 PhD Advisor
I have (co)-advised the following PhD students, and I was the (co)-promotor for
those marked in italics.
Finished:
1. Benny ˚Akesson PhD, TUE “Predictable and Composable System-on-Chip
Memory Controllers,” 2010
2. Calin Ciordas PhD, TUE “Monitoring-Aware Network-on-Chip Design,”
2008
3. Andreas Hansson PhD, TUE “A Composable and Predictable On-Chip
Interconnect,” 2009
4. Jae Young Hur PhD, TUD, “Customizing and Hardwiring On-Chip Interconnects
in FPGAs,” 2011
5. Radu Stefan PhD, TUD “Resource Allocation in Time-Division-Multiplexed
Networks on Chip,” 2012
6. Muhammad Aqeel Wahlah PhD, TUD, “Field Programmable Gate Arrays
with Hardwired Networks on Chip’,” 2012.
Ongoing:
1. Ashkan Beyranvand Nejad PhD, TUD on SOC debug
2. Karthik Chandrasekar PhD, TUD, on NOCs and low power
3. Manil Dev Gomony PhD, TUE on 3D memories
4. Davit Mirzoyan PhD, TUD, on system-level variability
5. Andrew Nelson PhD, TUD, on energy-performance trade-offs in real-time
multi-processor systems
6. Shubhendu Sinha PhD, TUE, on virtualisation in NOCs
7. Pavel Zaykov PhD, TUD, on hardware-accelerated OS
Abandoned:
1. Shiqi Li PhD, TUD, on MPSOC debug
2. Aleksandar Milutinovic PhD, UT on system-level energy management
3. Santiago Gonzalez Pestana PhD, TUE on network-on-chip metrics and
benchmarking (Marie Curie) (3 years)
7.5 Visiting researchers
1. Alexandre Amory PhD, Universidade de Rio Grande do Sul on using networks
on chip as test access mechanism at NXP (Jan 2005 - Jan 2006).
2. Sahar Foroutan post-doc, TIMA/IMAG at TUE (October 2011 - May
2012).
3. Erik Larsson associate professor, Linkoping University at NXP (October
2008 - May 2010).
4. Srinivasan Murali PhD, Stanford University on NOC synthesis at Philips
(July - September 2005).
5. Rikard Thid PhD KTH on network-on-chip metrics and benchmarking at
Philips (October 2003 - April 2004).
39

7.6 PDEng Advisor
1. Ying Zhang PDEng, TUE on virtualising an RTOS in a partitioned RTOS
(2012, 10 months).
7.7 MSc Supervision
I have (co)-supervised the following MSc and visiting PhD students, and I am
the responsible professor for those marked in italics.
1. Benny ˚Akesson MSc, Lund University “An analytical model for a memory
controller offering hard real-time guarantees” (9 months) at Philips.
2. Ruud Benjaminsen MSc, TUD “Low Power Evaluation for Arbitration
and MPSoC” (2009, 9 months) at IMEC-NL.
3. Ardy van den Berg MSc, TUD “Automation of wrapper design for the
reuse of a bus, network-on-chip, or other functional interconnect as test
access mechanism in a chip” (9 months) at NXP.
4. Ashkan Beyranvand Nejad MSc, KTH “High-Level Debugger Software for
Communication-Centric Transaction-Based Debug Infrastructure of Systems
on Chip (Æthereal Platform)” (9 months) at Philips.
5. Victor Camelo Romero MSc, TUE on multi-cpu mapping of a control
application (7 months) at ASML.
6. Razvan Dinu MSc, TUE on design flow refactoring (9 months) at Philips.
7. Marcus Ekerhult MSc, Lund University “CompOSe: Design and implementation
of a composable and slack-aware operating system targeting
a Multi-Processor System-on-Chip in the signal processing domain” (9
months) at NXP
8. Matias Escudero Martinez MSc, TUD “An Off-Chip Bridge for On-Chip
Network-Based Systems Supporting Traffic Quality of Service” (2010, 12
months).
9. Tomaz Felicijan PhD, Manchester University “Asynchronous TDMA Networks
on Chip” (6 months) at Philips.
10. Om Prakash Gangwal MSc, IIT Delhi on RTL power estimations in combination
with high-level synthesis (9 months)
11. Muhammad Hafijul Islam MSc, KTH on efficient slot table architectures
for routers (2 months)
12. Andreas Hansson MSc, Lund University “UMARS: A Unified Approach
to Mapping and Routing in a Combined Guaranteed Service and Best-
Effort Network-on-Chip Architecture” (9 months) Specification and Environment”
(9 months)
13. Dustin Pinedo Hernandez MSc, TUE on “Selecting hardware for Digital
Control” at ASML (2012, 7 months).
14. Rene de Jong MSc, TUE “System Exploration of Next Generation Flash
Devices”, at ARM Ltd (2012, 7 months).
15. Turhan Karadeniz MSc, TUD “Hardware Design and Implementation of a
Network-on-Chip Based High Performance Crossbar Switch Fabric” (2009,
9 months)
40

16. Peter Klerks MSc, TUE at on graphics acceleration with Axon (2012, 3
months pre-project).
17. Anand Khot MSc, TUD, “Performance estimation technique for optimizing
and integrating IPs in MPSoCs” (2010, 9 months)
18. Tim Kouters MSc, TUE, “Exploiting Memory Maps and predictable Open-
Page Policy in SDRAM for mixed Time-Criticality Systems” (2010, 9
months)
19. Jasper Kuijsten MSc, TUE, “DRAM memory controller architecture”
(2012, 9 months)
20. Aster Leegwater MSc, TUD, “Scheduling Streaming Applications on a
Composable Multi-Processor System” (2010, 9 months)
21. Tali Milea MSc, TUE “Conservative and compositional modeling in the
CompSOC platform” (2012, 7 months).
22. Orhan Mert PDEng, TUE on on-chip solar cell, at Moog (2012)
23. Ghazaleh Nazarian MSc, TUD “On-line Testing of Routers in Networkson-Chips”
(11 months).
24. Ba Thang Nguyen MSc, TUD “Task Scheduling Methods for Composable
and Predictable MPSoC” platform (9 months).
25. Douwe van Nijnatten MSc, TUE on multi-resource power management
(2013, 7 months)
26. Thomas Philipp MSc, Aachen University “Modelling of the Æthereal Network
on Chip using the Aachen NOC Exploration Framework” (February
- June 2004) at NXP.
27. Alexandru Ionut Pustianu MSc, TUE on automotive networking (2012, 9
months) at NXP
28. Sjoerd te Pas MSc, TUE “Quality versus energy trade-off for real-time
applications on a composable MPSoC” (2011, 7 months).
29. Pengwei Ren MSc, TUD “Wrapper design for the reuse of a NoC or other
functional interconnect as test infrastructure” (9 months) at Philips.
30. Markus Ringhofer MSc, Lund University “Design and Implementation of
a Memory Controller for Real-Time Applications” (9 months) at Philips.
31. Victor Camelo Romero MSc, TUE “Multi-core CPU Exploration for CARM
Host in ASML Technology” at ASML (2012, 7 months).
32. Thijs Schenkelaars MSc, TUE “Optimal scheduling of switched FlexRay
networks” (2009, 9 months) at NXP.
33. Simon Schliecker MSc, University of Braunschweig on data flow modelling
of systems (6 months) at Philips.
34. Pratibha Sharma MSc, IIRT Delhi “Configuring the Æthereal NoC using
an ARM processor” (9 months) at Philips.
35. Dongrui She MSc, TUE “FPGA Platform for Emulation of Composable
and Predictable MPSoC Power Management” (9 months) at NXP.
36. Winston Siauw MSc, TUD “3D Architecture Exploration for Multimedia
Applications” (2009, 9 months) at NXP.
37. Gabriel Squillace PDEng, TUE, “Design of Telemetry update for Reaction
Wheel Unit” (2011) at Bradford Engineering.
41

38. Remco van Steeden MSc, University of Twente “Communication-Centric
Debug of Systems-on-Chip using Networks-on-Chip” (6 months) at Philips.
39. Williston Sterchi Hayes MSc, TUE “Memory Pattern Generation based
on Specification and Environment” (9 months) at NXP.
40. Eelke Strooisma MSc, TUD “A predictable and composable front-end for
system on chip memory controllers” (12 months) at NXP.
41. Mahesh Balaji Subburaman MSc, Linkoping “Flit Synchronous Aelite Network
on Chip” (9 months) at NXP.
42. Getachew Teshome Woldegebreal MSc, TUD “Front-end for Composable
Resource Sharing Using Latency-Rate Servers” (9 months) at NXP.
43. Siddhart Umrani MSc, TUD “Communication-centric Debugging of Systems
on Chip using Networks on Chip” (9 months) at NXP.
44. Iria Varela Senin MSc, TUD “Design of a High-Performance Buffered
Crossbar Switch Fabric Using Network on Chip” (9 months).
45. Eugenia Eunice Valdez Solorzano MSc, TUD “Monitoring of Traffic Generators
for Networks on Chip using the Æthereal Platform”
46. Bert Visser PhD, UT on transformations from process-based application
specifications to input for high-level synthesis tools (3 years) at Philips.
47. Rob van Wijk MSc, TUE dynamic reconfiguration in CompSOC (2012, 9
months).
48. Jason de Windt MSc, TUD “Protocol conversions for the Æthereal Networkson-Chip”
(9 months).
49. Uri Wiener MSc, TUE, “Modeling and Analysis of a Cache Coherent
Interconnect” at ARM Ltd (2011, 7 months).
7.8 MSc graduation committees
(Excluding students listed above.)
1. K. Chandrasekar “Performance Validation of Networks on Chip,” TUD,
2009.
2. Z. Lu, “MPSoC Platform Design and Simulation for Power Performance
Estimation,” TUE, 2010.
3. J. Cai, “Budget-scheduling for a Real-time Software-Defined Multi-Radio
on a Heterogeneous Multiprocessor System,” TUE, 2010.
4. M. Verschoor, “Design of a crypto core for securing intra system-on-chip
communication,” TUD, 2010.
5. G. Schmitz, “Video Camera based Photoplethysmography using Ambient
Light,” TUE, 2011.
6. K. Hoogendoorn, “Inter-cluster Communication on Clustered SIMD Architectures”
TUE, 2011.
7. Gowri Sankar Ramachandran “Integrating enhanced slot-shifting in µC/OS-
II” TUE, 2011.
8. Johan Splinter “Tile-Based rasterization on an embedded Tile-based MP-
SoC” TUD, 2011.
9. Pieter Custers “Algorithmic Species: Classifying Program Code for Parallel
Computing”, TUE, 2012.
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10. Wouter Loeffen “Automated Generation of IP Core Wrappers for Faster
SoC Integration using High Level Synthesis”, TUE, 2012.
11. Adriaan van Buuren “Dynamic loading and task migration for streaming
applications on a composable system on chip” TUD, 2012. r
7.9 Bachelor Project Supervision
I have (co)-supervised the following BSc students for their bachelor end projects.
1. Ruud Bauhaus, TUE, on implementing H263 video encoding on Comp-
SOC, 2011.
2. Marco Rompen, TUE, on implementing a real-time control algorithm on
CompSOC, 2012.
8 Committees
• Examination committee embedded systems 1 October 2010 - 30 September
2014.
• Education committee electrical engineering faculty as of 1 December 2010.
• Advisory committee (Benoemingsadviescommissie) for the TU Delft “Computer
Engineering” Chair Professor position, 2009.
• Advisory committee for a Assistant/Associate Professor System-on-Chip
position at the Danish Technical University (DTU), 2009.
• Advisory committee (Benoemingsadviescommissie) for the TU Delft “Computer
Engineering” Chair Professor position, 2011.
9 Research Interests
Having worked in varied research fields is, I believe, one of my strengths. In
academia, I started with software engineering and pure mathematics, and then
moved to formal hardware verification using logics and proof systems. After joining
Philips, after working on hardware synthesis and associated high-throughput
hardware architectures, I shifted to system-level design methods and on-chip
communication protocols. Many of these diverse interests are combined in my
current networks-on-chip research.
The focus of the Æthereal research effort has been on defining a network
on chip with communication services with predictable performance to enable a
design flow that reduces the effort to design and program SOCs. As of 2004,
memory controllers with guaranteed performance have been an additional topic
of interest, to enlarge the scope of predictable communication to include predictable
storage. My long-term goal is to be be able to construct SOCs (including
software) with predictable performance, based on compositional performance
(quality of service) models that are enabled by appropriate hardware and
software concepts and architectures.
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10 Miscellaneous
I am fluent user of both Dutch and English. The English Language Test, as
set by The British Council (University of Cambridge) rated me as a “very good
user” in 1987. In 2012 the Eindhoven university of technology gave me the
maximum score (C2) on all categories (spoken fluency, grammar, vocabulary,
phonological control, exchanging information, coherence and cohesion). I speak
Italian well enough for good day-to-day use.
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